#ifndef XPARAMETERS_H   /* prevent circular inclusions */
#define XPARAMETERS_H   /* by using protection macros */

#define XPAR_XCANFD_NUM_INSTANCES 1

/* Definitions for peripheral CAN1 */
#define XPAR_CAN1_COMPATIBLE xlnx,canfd-2.0
#define XPAR_CAN1_BASEADDR 0xff070000
#define XPAR_CAN1_HIGHADDR 0xff075fff
#define XPAR_CAN1_RX_MODE 0x0
#define XPAR_CAN1_RX_FIFO_DEPTH 0x40
#define XPAR_CAN1_TX_MAILBOX_COUNT 0x20
#define XPAR_CAN1_INTERRUPTS 0x4015

/* Canonical definitions for peripheral CAN1 */
#define XPAR_XCANFD_0_BASEADDR 0xff070000
#define XPAR_XCANFD_0_HIGHADDR 0xff075fff
#define XPAR_XCANFD_0_COMPATIBLE xlnx,canfd-2.0
#define XPAR_XCANFD_0_INTERRUPTS 0x4015
#define XPAR_XCANFD_0_RX_MODE 0x0
#define XPAR_XCANFD_0_RX_FIFO_DEPTH 0x40
#define XPAR_XCANFD_0_TX_MAILBOX_COUNT 0x20

#define XPAR_XCFRAME_NUM_INSTANCES 1

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_0_COMPATIBLE xlnx,psv-pmc-cfi-cframe-1.0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_0_BASEADDR 0xf12d0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_0_HIGHADDR 0xf12d0fff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_0 */
#define XPAR_XCFRAME_0_BASEADDR 0xf12d0000
#define XPAR_XCFRAME_0_HIGHADDR 0xf12d0fff
#define XPAR_XCFRAME_0_COMPATIBLE xlnx,psv-pmc-cfi-cframe-1.0

#define XPAR_XCFUPMC_NUM_INSTANCES 1

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_CFU_APB_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_CFU_APB_0_COMPATIBLE xlnx,psv-pmc-cfu-apb-1.0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_CFU_APB_0_BASEADDR 0xf12b0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_CFU_APB_0_HIGHADDR 0xf12bffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_CFU_APB_0 */
#define XPAR_XCFUPMC_0_BASEADDR 0xf12b0000
#define XPAR_XCFUPMC_0_HIGHADDR 0xf12bffff
#define XPAR_XCFUPMC_0_COMPATIBLE xlnx,psv-pmc-cfu-apb-1.0

#define XPAR_XCORESIGHTPS_DCC_NUM_INSTANCES 1

/* Definitions for peripheral CORESIGHT */
#define XPAR_CORESIGHT_COMPATIBLE xlnx,coresight-1.0
#define XPAR_CORESIGHT_BASEADDR 0xf0800000
#define XPAR_CORESIGHT_HIGHADDR 0xf080ffff

/* Canonical definitions for peripheral CORESIGHT */
#define XPAR_XCORESIGHTPS_DCC_0_BASEADDR 0xf0800000
#define XPAR_XCORESIGHTPS_DCC_0_HIGHADDR 0xf080ffff
#define XPAR_XCORESIGHTPS_DCC_0_COMPATIBLE xlnx,coresight-1.0

#define XPAR_XCSUDMA_NUM_INSTANCES 2

/* Definitions for peripheral DMA0 */
#define XPAR_DMA0_COMPATIBLE xlnx,zynqmp-csudma-1.0
#define XPAR_DMA0_BASEADDR 0xf11c0000
#define XPAR_DMA0_HIGHADDR 0xf11fffff
#define XPAR_DMA0_DMA_TYPE 0x1
#define XPAR_DMA0_INTERRUPTS 0x4083

/* Canonical definitions for peripheral DMA0 */
#define XPAR_XCSUDMA_0_BASEADDR 0xf11c0000
#define XPAR_XCSUDMA_0_HIGHADDR 0xf11fffff
#define XPAR_XCSUDMA_0_COMPATIBLE xlnx,zynqmp-csudma-1.0
#define XPAR_XCSUDMA_0_DMA_TYPE 0x1
#define XPAR_XCSUDMA_0_INTERRUPTS 0x4083

/* Definitions for peripheral DMA1 */
#define XPAR_DMA1_COMPATIBLE xlnx,zynqmp-csudma-1.0
#define XPAR_DMA1_BASEADDR 0xf11d0000
#define XPAR_DMA1_HIGHADDR 0xf120ffff
#define XPAR_DMA1_DMA_TYPE 0x2
#define XPAR_DMA1_INTERRUPTS 0x4084

/* Canonical definitions for peripheral DMA1 */
#define XPAR_XCSUDMA_1_BASEADDR 0xf11d0000
#define XPAR_XCSUDMA_1_HIGHADDR 0xf120ffff
#define XPAR_XCSUDMA_1_COMPATIBLE xlnx,zynqmp-csudma-1.0
#define XPAR_XCSUDMA_1_DMA_TYPE 0x2
#define XPAR_XCSUDMA_1_INTERRUPTS 0x4084

#define XPAR_XEMACPS_NUM_INSTANCES 2

/* Definitions for peripheral GEM0 */
#define XPAR_GEM0_COMPATIBLE xlnx,versal-gem
#define XPAR_GEM0_BASEADDR 0xff0c0000
#define XPAR_GEM0_HIGHADDR 0xff0c0fff
#define XPAR_GEM0_DMA_COHERENT 0x0
#define XPAR_GEM0_INTERRUPTS 0x4038
#define XPAR_GEM0_REF_CLK 0x0

/* Canonical definitions for peripheral GEM0 */
#define XPAR_XEMACPS_0_BASEADDR 0xff0c0000
#define XPAR_XEMACPS_0_HIGHADDR 0xff0c0fff
#define XPAR_XEMACPS_0_COMPATIBLE xlnx,versal-gem
#define XPAR_XEMACPS_0_DMA_COHERENT 0x0
#define XPAR_XEMACPS_0_INTERRUPTS 0x4038
#define XPAR_XEMACPS_0_REF_CLK 0x0

/* Definitions for peripheral GEM1 */
#define XPAR_GEM1_COMPATIBLE xlnx,versal-gem
#define XPAR_GEM1_BASEADDR 0xff0d0000
#define XPAR_GEM1_HIGHADDR 0xff0d0fff
#define XPAR_GEM1_DMA_COHERENT 0x0
#define XPAR_GEM1_INTERRUPTS 0x403a
#define XPAR_GEM1_REF_CLK 0x0

/* Canonical definitions for peripheral GEM1 */
#define XPAR_XEMACPS_1_BASEADDR 0xff0d0000
#define XPAR_XEMACPS_1_HIGHADDR 0xff0d0fff
#define XPAR_XEMACPS_1_COMPATIBLE xlnx,versal-gem
#define XPAR_XEMACPS_1_DMA_COHERENT 0x0
#define XPAR_XEMACPS_1_INTERRUPTS 0x403a
#define XPAR_XEMACPS_1_REF_CLK 0x0

#define XPAR_XIICPS_NUM_INSTANCES 2

/* Definitions for peripheral I2C0 */
#define XPAR_I2C0_COMPATIBLE cdns,i2c-r1p14
#define XPAR_I2C0_BASEADDR 0xff020000
#define XPAR_I2C0_HIGHADDR 0xff020fff
#define XPAR_I2C0_CLOCK_FREQ 0x5f5e09d
#define XPAR_I2C0_INTERRUPTS 0x400e
#define XPAR_I2C0_REF_CLK 0x0

/* Canonical definitions for peripheral I2C0 */
#define XPAR_XIICPS_0_BASEADDR 0xff020000
#define XPAR_XIICPS_0_HIGHADDR 0xff020fff
#define XPAR_XIICPS_0_COMPATIBLE cdns,i2c-r1p14
#define XPAR_XIICPS_0_CLOCK_FREQ 0x5f5e09d
#define XPAR_XIICPS_0_INTERRUPTS 0x400e
#define XPAR_XIICPS_0_REF_CLK 0x0

/* Definitions for peripheral I2C1 */
#define XPAR_I2C1_COMPATIBLE cdns,i2c-r1p14
#define XPAR_I2C1_BASEADDR 0xff030000
#define XPAR_I2C1_HIGHADDR 0xff030fff
#define XPAR_I2C1_CLOCK_FREQ 0x5f5e09d
#define XPAR_I2C1_INTERRUPTS 0x400f
#define XPAR_I2C1_REF_CLK 0x0

/* Canonical definitions for peripheral I2C1 */
#define XPAR_XIICPS_1_BASEADDR 0xff030000
#define XPAR_XIICPS_1_HIGHADDR 0xff030fff
#define XPAR_XIICPS_1_COMPATIBLE cdns,i2c-r1p14
#define XPAR_XIICPS_1_CLOCK_FREQ 0x5f5e09d
#define XPAR_XIICPS_1_INTERRUPTS 0x400f
#define XPAR_XIICPS_1_REF_CLK 0x0

#define XPAR_XIOMODULE_NUM_INSTANCES 1

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_COMPATIBLE xlnx,iomodule-1.0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_BASEADDR 0xffc80000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_HIGHADDR 0xffc87fff
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_INTC_HAS_FAST 0x0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_INTC_BASE_VECTORS 0xffc00000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_INTC_ADDR_WIDTH 0x20
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_INTC_LEVEL_EDGE 0x7fff
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_OPTIONS 0x1
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_CLOCK_FREQ 0x5f5e100
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_UART_BAUDRATE 0x1c200
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_USED_0 1
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_USED_1 1
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_USED_2 1
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_USED_3 1
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_SIZE_0 32
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_SIZE_1 32
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_SIZE_2 32
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_SIZE_3 32
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_MASK_0 4294967295
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_MASK_1 4294967295
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_MASK_2 4294967295
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_MASK_3 4294967295
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_PRESCALER_0 9
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_PRESCALER_1 0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_PRESCALER_2 9
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_PRESCALER_3 0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_READABLE_0 1
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_READABLE_1 1
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_READABLE_2 1
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_PIT_READABLE_3 1
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_GPO_INIT_0 0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_GPO_INIT_1 0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_GPO_INIT_2 0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_GPO_INIT_3 0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0_HANDLER_TABLE 0x0

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PSM_IOMODULE_0 */
#define XPAR_XIOMODULE_0_BASEADDR 0xffc80000
#define XPAR_XIOMODULE_0_HIGHADDR 0xffc87fff
#define XPAR_XIOMODULE_0_HANDLER_TABLE 0x0
#define XPAR_XIOMODULE_0_COMPATIBLE xlnx,iomodule-1.0
#define XPAR_XIOMODULE_0_CLOCK_FREQ 0x5f5e100
#define XPAR_XIOMODULE_0_GPO_INIT_0 0
#define XPAR_XIOMODULE_0_GPO_INIT_1 0
#define XPAR_XIOMODULE_0_GPO_INIT_2 0
#define XPAR_XIOMODULE_0_GPO_INIT_3 0
#define XPAR_XIOMODULE_0_INTC_HAS_FAST 0x0
#define XPAR_XIOMODULE_0_INTC_BASE_VECTORS 0xffc00000
#define XPAR_XIOMODULE_0_INTC_ADDR_WIDTH 0x20
#define XPAR_XIOMODULE_0_INTC_LEVEL_EDGE 0x7fff
#define XPAR_XIOMODULE_0_OPTIONS 0x1
#define XPAR_XIOMODULE_0_PIT_USED_0 1
#define XPAR_XIOMODULE_0_PIT_USED_1 1
#define XPAR_XIOMODULE_0_PIT_USED_2 1
#define XPAR_XIOMODULE_0_PIT_USED_3 1
#define XPAR_XIOMODULE_0_PIT_SIZE_0 32
#define XPAR_XIOMODULE_0_PIT_SIZE_1 32
#define XPAR_XIOMODULE_0_PIT_SIZE_2 32
#define XPAR_XIOMODULE_0_PIT_SIZE_3 32
#define XPAR_XIOMODULE_0_PIT_MASK_0 4294967295
#define XPAR_XIOMODULE_0_PIT_MASK_1 4294967295
#define XPAR_XIOMODULE_0_PIT_MASK_2 4294967295
#define XPAR_XIOMODULE_0_PIT_MASK_3 4294967295
#define XPAR_XIOMODULE_0_PIT_PRESCALER_0 9
#define XPAR_XIOMODULE_0_PIT_PRESCALER_1 0
#define XPAR_XIOMODULE_0_PIT_PRESCALER_2 9
#define XPAR_XIOMODULE_0_PIT_PRESCALER_3 0
#define XPAR_XIOMODULE_0_PIT_READABLE_0 1
#define XPAR_XIOMODULE_0_PIT_READABLE_1 1
#define XPAR_XIOMODULE_0_PIT_READABLE_2 1
#define XPAR_XIOMODULE_0_PIT_READABLE_3 1
#define XPAR_XIOMODULE_0_UART_BAUDRATE 0x1c200

#define XPAR_XIPIPSU_NUM_INSTANCES 1

/* Definitions for peripheral IPI2 */
#define XPAR_IPI2_COMPATIBLE xlnx,zynqmp-ipi-mailbox
#define XPAR_IPI2_BASEADDR 0xff310000
#define XPAR_IPI2_HIGHADDR 0xff31001f
#define XPAR_IPI2_IPI_BITMASK 0x1
#define XPAR_IPI2_IPI_BUF_INDEX 0x0
#define XPAR_IPI2_INTERRUPTS 0x401d
#define XPAR_IPI2_IPI_TARGET_COUNT 0xa
#define XPAR_IPI2_0_IPI_BITMASK 0x4
#define XPAR_IPI2_0_IPI_BUF_INDEX 0x2
#define XPAR_IPI2_1_IPI_BITMASK 0x8
#define XPAR_IPI2_1_IPI_BUF_INDEX 0x3
#define XPAR_IPI2_2_IPI_BITMASK 0x10
#define XPAR_IPI2_2_IPI_BUF_INDEX 0x4
#define XPAR_IPI2_3_IPI_BITMASK 0x20
#define XPAR_IPI2_3_IPI_BUF_INDEX 0x5
#define XPAR_IPI2_4_IPI_BITMASK 0x40
#define XPAR_IPI2_4_IPI_BUF_INDEX 0x6
#define XPAR_IPI2_5_IPI_BITMASK 0x80
#define XPAR_IPI2_5_IPI_BUF_INDEX 0x7
#define XPAR_IPI2_6_IPI_BITMASK 0x200
#define XPAR_IPI2_6_IPI_BUF_INDEX 0xffff
#define XPAR_IPI2_7_IPI_BITMASK 0x2
#define XPAR_IPI2_7_IPI_BUF_INDEX 0x1
#define XPAR_IPI2_8_IPI_BITMASK 0x100
#define XPAR_IPI2_8_IPI_BUF_INDEX 0xffff
#define XPAR_IPI2_9_IPI_BITMASK 0x1
#define XPAR_IPI2_9_IPI_BUF_INDEX 0x0

/* Canonical definitions for peripheral IPI2 */
#define XPAR_XIPIPSU_0_BASEADDR 0xff310000
#define XPAR_XIPIPSU_0_HIGHADDR 0xff31001f
#define XPAR_XIPIPSU_0_COMPATIBLE xlnx,zynqmp-ipi-mailbox
#define XPAR_XIPIPSU_0_IPI_BITMASK 0x1
#define XPAR_XIPIPSU_0_IPI_BUF_INDEX 0x0
#define XPAR_XIPIPSU_0_INTERRUPTS 0x401d
#define XPAR_XIPIPSU_0_IPI_TARGET_COUNT 0xa

#define XPAR_XQSPIPSU_NUM_INSTANCES 1

/* Definitions for peripheral QSPI */
#define XPAR_QSPI_COMPATIBLE xlnx,versal-qspi-1.0
#define XPAR_QSPI_BASEADDR 0xf1030000
#define XPAR_QSPI_HIGHADDR 0xf1030fff
#define XPAR_QSPI_CLOCK_FREQ 0x11a20dce
#define XPAR_QSPI_CONNECTION_MODE 0x2
#define XPAR_QSPI_BUS_WIDTH 0x2
#define XPAR_QSPI_DMA_COHERENT 0x0
#define XPAR_QSPI_INTERRUPTS 0x407d
#define XPAR_QSPI_REF_CLK 0x0

/* Canonical definitions for peripheral QSPI */
#define XPAR_XQSPIPSU_0_BASEADDR 0xf1030000
#define XPAR_XQSPIPSU_0_HIGHADDR 0xf1030fff
#define XPAR_XQSPIPSU_0_BUS_WIDTH 0x2
#define XPAR_XQSPIPSU_0_COMPATIBLE xlnx,versal-qspi-1.0
#define XPAR_XQSPIPSU_0_CLOCK_FREQ 0x11a20dce
#define XPAR_XQSPIPSU_0_CONNECTION_MODE 0x2
#define XPAR_XQSPIPSU_0_DMA_COHERENT 0x0
#define XPAR_XQSPIPSU_0_INTERRUPTS 0x407d
#define XPAR_XQSPIPSU_0_REF_CLK 0x0

#define XPAR_XRTCPSU_NUM_INSTANCES 1

/* Definitions for peripheral RTC */
#define XPAR_RTC_COMPATIBLE xlnx,zynqmp-rtc
#define XPAR_RTC_BASEADDR 0xf12a0000
#define XPAR_RTC_HIGHADDR 0xf12a00ff
#define XPAR_RTC_INTERRUPTS 0x408e
#define XPAR_RTC_INTERRUPTS_1 0x408f

/* Canonical definitions for peripheral RTC */
#define XPAR_XRTCPSU_0_BASEADDR 0xf12a0000
#define XPAR_XRTCPSU_0_HIGHADDR 0xf12a00ff
#define XPAR_XRTCPSU_0_COMPATIBLE xlnx,zynqmp-rtc
#define XPAR_XRTCPSU_0_INTERRUPTS 0x408e

#define XPAR_XSDPS_NUM_INSTANCES 1

/* Definitions for peripheral SDHCI1 */
#define XPAR_SDHCI1_COMPATIBLE xlnx,versal-8.9a
#define XPAR_SDHCI1_BASEADDR 0xf1050000
#define XPAR_SDHCI1_HIGHADDR 0xf105ffff
#define XPAR_SDHCI1_SDIO_CLK_FREQ_HZ 0xbebc13a
#define XPAR_SDHCI1_HAS_CD 0x1
#define XPAR_SDHCI1_HAS_WP 0x0
#define XPAR_SDHCI1_BUS_WIDTH 0x8
#define XPAR_SDHCI1_MIO_BANK 0x1
#define XPAR_SDHCI1_HAS_EMIO 0x0
#define XPAR_SDHCI1_SLOT_TYPE 0x3
#define XPAR_SDHCI1_IS_CACHE_COHERENT 0x0
#define XPAR_SDHCI1_CLOCKS 0x3c

/* Canonical definitions for peripheral SDHCI1 */
#define XPAR_XSDPS_0_BASEADDR 0xf1050000
#define XPAR_XSDPS_0_HIGHADDR 0xf105ffff
#define XPAR_XSDPS_0_BUS_WIDTH 0x8
#define XPAR_XSDPS_0_COMPATIBLE xlnx,versal-8.9a
#define XPAR_XSDPS_0_CLOCKS 0x3c
#define XPAR_XSDPS_0_HAS_CD 0x1
#define XPAR_XSDPS_0_HAS_WP 0x0
#define XPAR_XSDPS_0_HAS_EMIO 0x0
#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0x0
#define XPAR_XSDPS_0_MIO_BANK 0x1
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 0xbebc13a
#define XPAR_XSDPS_0_SLOT_TYPE 0x3

#define XPAR_XSYSMONPSV_NUM_INSTANCES 1

/* Definitions for peripheral SYSMON0 */
#define XPAR_SYSMON0_BASEADDR 0xf1270000
#define XPAR_SYSMON0_HIGHADDR 0xf1273fff
#define XPAR_SYSMON0_INTERRUPTS 0x4090

/* Canonical definitions for peripheral SYSMON0 */
#define XPAR_XSYSMONPSV_0_BASEADDR 0xf1270000
#define XPAR_XSYSMONPSV_0_HIGHADDR 0xf1273fff
#define XPAR_XSYSMONPSV_0_INTERRUPTS 0x4090

#define XPAR_XTMR_INJECT_NUM_INSTANCES 1

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_INJECT_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_INJECT_0_COMPATIBLE xlnx,tmr-inject-1.0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_INJECT_0_BASEADDR 0xffcd0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_INJECT_0_HIGHADDR 0xffcdffff
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_INJECT_0_CPU_ID 0x1
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_INJECT_0_LMB_AWIDTH 0x20

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_INJECT_0 */
#define XPAR_XTMR_INJECT_0_BASEADDR 0xffcd0000
#define XPAR_XTMR_INJECT_0_HIGHADDR 0xffcdffff
#define XPAR_XTMR_INJECT_0_COMPATIBLE xlnx,tmr-inject-1.0
#define XPAR_XTMR_INJECT_0_CPU_ID 0x1
#define XPAR_XTMR_INJECT_0_LMB_AWIDTH 0x20

#define XPAR_XTMR_MANAGER_NUM_INSTANCES 1

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_COMPATIBLE xlnx,tmr-manager-1.0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_BASEADDR 0xffcc0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_HIGHADDR 0xffccffff
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_BRK_DELAY_RST_VALUE 0x0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_MASK_RST_VALUE_0 4294967295
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_MASK_RST_VALUE_1 4294967295
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_MAGIC1 0x0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_MAGIC2 0x0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_UE_IS_FATAL 0x0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_UE_WIDTH 0x3
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_NO_OF_COMPARATORS 0x1
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_COMPARATORS_MASK 0x0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_WATCHDOG 0x0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_WATCHDOG_WIDTH 0x1e
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_SEM_INTERFACE 0x0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_SEM_HEARTBEAT_WATCHDOG 0x0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_SEM_HEARTBEAT_WATCHDOG_WIDTH 0xa
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_BRK_DELAY_WIDTH 0x0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_TMR 0x1
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_TEST_COMPARATOR 0x0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_STRICT_MISCOMPARE 0x0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_USE_DEBUG_DISABLE 0x0
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0_USE_TMR_DISABLE 0x0

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PSM_TMR_MANAGER_0 */
#define XPAR_XTMR_MANAGER_0_BASEADDR 0xffcc0000
#define XPAR_XTMR_MANAGER_0_HIGHADDR 0xffccffff
#define XPAR_XTMR_MANAGER_0_BRK_DELAY_RST_VALUE 0x0
#define XPAR_XTMR_MANAGER_0_BRK_DELAY_WIDTH 0x0
#define XPAR_XTMR_MANAGER_0_COMPATIBLE xlnx,tmr-manager-1.0
#define XPAR_XTMR_MANAGER_0_COMPARATORS_MASK 0x0
#define XPAR_XTMR_MANAGER_0_MASK_RST_VALUE_0 4294967295
#define XPAR_XTMR_MANAGER_0_MASK_RST_VALUE_1 4294967295
#define XPAR_XTMR_MANAGER_0_MAGIC1 0x0
#define XPAR_XTMR_MANAGER_0_MAGIC2 0x0
#define XPAR_XTMR_MANAGER_0_NO_OF_COMPARATORS 0x1
#define XPAR_XTMR_MANAGER_0_SEM_INTERFACE 0x0
#define XPAR_XTMR_MANAGER_0_SEM_HEARTBEAT_WATCHDOG 0x0
#define XPAR_XTMR_MANAGER_0_SEM_HEARTBEAT_WATCHDOG_WIDTH 0xa
#define XPAR_XTMR_MANAGER_0_STRICT_MISCOMPARE 0x0
#define XPAR_XTMR_MANAGER_0_TMR 0x1
#define XPAR_XTMR_MANAGER_0_TEST_COMPARATOR 0x0
#define XPAR_XTMR_MANAGER_0_UE_IS_FATAL 0x0
#define XPAR_XTMR_MANAGER_0_UE_WIDTH 0x3
#define XPAR_XTMR_MANAGER_0_USE_DEBUG_DISABLE 0x0
#define XPAR_XTMR_MANAGER_0_USE_TMR_DISABLE 0x0
#define XPAR_XTMR_MANAGER_0_WATCHDOG 0x0
#define XPAR_XTMR_MANAGER_0_WATCHDOG_WIDTH 0x1e

#define XPAR_XTTCPS_NUM_INSTANCES 4

/* Definitions for peripheral TTC0 */
#define XPAR_TTC0_COMPATIBLE cdns,ttc
#define XPAR_TTC0_BASEADDR 0xff0e0000
#define XPAR_TTC0_HIGHADDR 0xff0e0fff
#define XPAR_TTC0_CLOCK_FREQ 0x8f0d0f7
#define XPAR_TTC0_INTERRUPTS 0x4025
#define XPAR_TTC0_INTERRUPTS_1 0x4026
#define XPAR_TTC0_INTERRUPTS_2 0x4027

/* Canonical definitions for peripheral TTC0 */
#define XPAR_XTTCPS_0_BASEADDR 0xff0e0000
#define XPAR_XTTCPS_0_HIGHADDR 0xff0e0fff
#define XPAR_XTTCPS_0_COMPATIBLE cdns,ttc
#define XPAR_XTTCPS_0_CLOCK_FREQ 0x8f0d0f7
#define XPAR_XTTCPS_0_INTERRUPTS 0x4025

/* Definitions for peripheral TTC1 */
#define XPAR_TTC1_COMPATIBLE cdns,ttc
#define XPAR_TTC1_BASEADDR 0xff0f0000
#define XPAR_TTC1_HIGHADDR 0xff0f0fff
#define XPAR_TTC1_CLOCK_FREQ 0x8f0d0f7
#define XPAR_TTC1_INTERRUPTS 0x4028
#define XPAR_TTC1_INTERRUPTS_1 0x4029
#define XPAR_TTC1_INTERRUPTS_2 0x402a

/* Canonical definitions for peripheral TTC1 */
#define XPAR_XTTCPS_1_BASEADDR 0xff0f0000
#define XPAR_XTTCPS_1_HIGHADDR 0xff0f0fff
#define XPAR_XTTCPS_1_COMPATIBLE cdns,ttc
#define XPAR_XTTCPS_1_CLOCK_FREQ 0x8f0d0f7
#define XPAR_XTTCPS_1_INTERRUPTS 0x4028

/* Definitions for peripheral TTC2 */
#define XPAR_TTC2_COMPATIBLE cdns,ttc
#define XPAR_TTC2_BASEADDR 0xff100000
#define XPAR_TTC2_HIGHADDR 0xff100fff
#define XPAR_TTC2_CLOCK_FREQ 0x8f0d0f7
#define XPAR_TTC2_INTERRUPTS 0x402b
#define XPAR_TTC2_INTERRUPTS_1 0x402c
#define XPAR_TTC2_INTERRUPTS_2 0x402d

/* Canonical definitions for peripheral TTC2 */
#define XPAR_XTTCPS_2_BASEADDR 0xff100000
#define XPAR_XTTCPS_2_HIGHADDR 0xff100fff
#define XPAR_XTTCPS_2_COMPATIBLE cdns,ttc
#define XPAR_XTTCPS_2_CLOCK_FREQ 0x8f0d0f7
#define XPAR_XTTCPS_2_INTERRUPTS 0x402b

/* Definitions for peripheral TTC3 */
#define XPAR_TTC3_COMPATIBLE cdns,ttc
#define XPAR_TTC3_BASEADDR 0xff110000
#define XPAR_TTC3_HIGHADDR 0xff110fff
#define XPAR_TTC3_CLOCK_FREQ 0x8f0d0f7
#define XPAR_TTC3_INTERRUPTS 0x402e
#define XPAR_TTC3_INTERRUPTS_1 0x402f
#define XPAR_TTC3_INTERRUPTS_2 0x4030

/* Canonical definitions for peripheral TTC3 */
#define XPAR_XTTCPS_3_BASEADDR 0xff110000
#define XPAR_XTTCPS_3_HIGHADDR 0xff110fff
#define XPAR_XTTCPS_3_COMPATIBLE cdns,ttc
#define XPAR_XTTCPS_3_CLOCK_FREQ 0x8f0d0f7
#define XPAR_XTTCPS_3_INTERRUPTS 0x402e

#define XPAR_XUARTPSV_NUM_INSTANCES 1

/* Definitions for peripheral SERIAL0 */
#define XPAR_SERIAL0_COMPATIBLE arm,pl011
#define XPAR_SERIAL0_BASEADDR 0xff000000
#define XPAR_SERIAL0_HIGHADDR 0xff000fff
#define XPAR_SERIAL0_CLOCK_FREQ 0x5f5e09d
#define XPAR_SERIAL0_MODEMPINSCONNECTED 0x0
#define XPAR_SERIAL0_BAUDRATE 0x1c200
#define XPAR_SERIAL0_INTERRUPTS 0x4012

/* Canonical definitions for peripheral SERIAL0 */
#define XPAR_XUARTPSV_0_BASEADDR 0xff000000
#define XPAR_XUARTPSV_0_HIGHADDR 0xff000fff
#define XPAR_XUARTPSV_0_MODEMPINSCONNECTED 0x0
#define XPAR_XUARTPSV_0_BAUDRATE 0x1c200
#define XPAR_XUARTPSV_0_COMPATIBLE arm,pl011
#define XPAR_XUARTPSV_0_CLOCK_FREQ 0x5f5e09d
#define XPAR_XUARTPSV_0_INTERRUPTS 0x4012

#define XPAR_XUSBPSU_NUM_INSTANCES 1

/* Definitions for peripheral DWC3_0 */
#define XPAR_DWC3_0_COMPATIBLE snps,dwc3
#define XPAR_DWC3_0_BASEADDR 0xfe200000
#define XPAR_DWC3_0_HIGHADDR 0xfe20ffff
#define XPAR_DWC3_0_DMA_COHERENT 0x0
#define XPAR_DWC3_0_ENABLE_SUPERSPEED 0x0
#define XPAR_DWC3_0_INTERRUPTS 0x4016
#define XPAR_DWC3_0_INTERRUPTS_1 0x401a
#define XPAR_DWC3_0_INTERRUPTS_2 0x404a

/* Canonical definitions for peripheral DWC3_0 */
#define XPAR_XUSBPSU_0_BASEADDR 0xfe200000
#define XPAR_XUSBPSU_0_HIGHADDR 0xfe20ffff
#define XPAR_XUSBPSU_0_COMPATIBLE snps,dwc3
#define XPAR_XUSBPSU_0_DMA_COHERENT 0x0
#define XPAR_XUSBPSU_0_ENABLE_SUPERSPEED 0x0
#define XPAR_XUSBPSU_0_INTERRUPTS 0x4016

#define XPAR_XWDTTB_NUM_INSTANCES 1

/* Definitions for peripheral WATCHDOG1 */
#define XPAR_WATCHDOG1_COMPATIBLE xlnx,versal-wwdt-1.0
#define XPAR_WATCHDOG1_BASEADDR 0xff120000
#define XPAR_WATCHDOG1_HIGHADDR 0xff12ffff
#define XPAR_WATCHDOG1_ENABLE_WINDOW_WDT 0x0
#define XPAR_WATCHDOG1_WDT_CLK_FREQ_HZ 0x5f5e100
#define XPAR_WATCHDOG1_INTERRUPTS 0x1031
#define XPAR_WATCHDOG1_INTERRUPTS_1 0x1045
#define XPAR_WATCHDOG1_INTERRUPTS_2 0x4046
#define XPAR_WATCHDOG1_INTERRUPTS_3 0x4047

/* Canonical definitions for peripheral WATCHDOG1 */
#define XPAR_XWDTTB_0_BASEADDR 0xff120000
#define XPAR_XWDTTB_0_HIGHADDR 0xff12ffff
#define XPAR_XWDTTB_0_COMPATIBLE xlnx,versal-wwdt-1.0
#define XPAR_XWDTTB_0_ENABLE_WINDOW_WDT 0x0
#define XPAR_XWDTTB_0_INTERRUPTS 0x1031
#define XPAR_XWDTTB_0_WDT_CLK_FREQ_HZ 0x5f5e100

#define XPAR_XZDMA_NUM_INSTANCES 8

/* Definitions for peripheral LPD_DMA_CHAN0 */
#define XPAR_LPD_DMA_CHAN0_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_LPD_DMA_CHAN0_BASEADDR 0xffa80000
#define XPAR_LPD_DMA_CHAN0_HIGHADDR 0xffa80fff
#define XPAR_LPD_DMA_CHAN0_DMA_TYPE 0x1
#define XPAR_LPD_DMA_CHAN0_DMA_COHERENT 0x0
#define XPAR_LPD_DMA_CHAN0_INTERRUPTS 0x403c

/* Canonical definitions for peripheral LPD_DMA_CHAN0 */
#define XPAR_XZDMA_0_BASEADDR 0xffa80000
#define XPAR_XZDMA_0_HIGHADDR 0xffa80fff
#define XPAR_XZDMA_0_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_XZDMA_0_DMA_TYPE 0x1
#define XPAR_XZDMA_0_DMA_COHERENT 0x0
#define XPAR_XZDMA_0_INTERRUPTS 0x403c

/* Definitions for peripheral LPD_DMA_CHAN1 */
#define XPAR_LPD_DMA_CHAN1_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_LPD_DMA_CHAN1_BASEADDR 0xffa90000
#define XPAR_LPD_DMA_CHAN1_HIGHADDR 0xffa90fff
#define XPAR_LPD_DMA_CHAN1_DMA_TYPE 0x1
#define XPAR_LPD_DMA_CHAN1_DMA_COHERENT 0x0
#define XPAR_LPD_DMA_CHAN1_INTERRUPTS 0x403d

/* Canonical definitions for peripheral LPD_DMA_CHAN1 */
#define XPAR_XZDMA_1_BASEADDR 0xffa90000
#define XPAR_XZDMA_1_HIGHADDR 0xffa90fff
#define XPAR_XZDMA_1_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_XZDMA_1_DMA_TYPE 0x1
#define XPAR_XZDMA_1_DMA_COHERENT 0x0
#define XPAR_XZDMA_1_INTERRUPTS 0x403d

/* Definitions for peripheral LPD_DMA_CHAN2 */
#define XPAR_LPD_DMA_CHAN2_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_LPD_DMA_CHAN2_BASEADDR 0xffaa0000
#define XPAR_LPD_DMA_CHAN2_HIGHADDR 0xffaa0fff
#define XPAR_LPD_DMA_CHAN2_DMA_TYPE 0x1
#define XPAR_LPD_DMA_CHAN2_DMA_COHERENT 0x0
#define XPAR_LPD_DMA_CHAN2_INTERRUPTS 0x403e

/* Canonical definitions for peripheral LPD_DMA_CHAN2 */
#define XPAR_XZDMA_2_BASEADDR 0xffaa0000
#define XPAR_XZDMA_2_HIGHADDR 0xffaa0fff
#define XPAR_XZDMA_2_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_XZDMA_2_DMA_TYPE 0x1
#define XPAR_XZDMA_2_DMA_COHERENT 0x0
#define XPAR_XZDMA_2_INTERRUPTS 0x403e

/* Definitions for peripheral LPD_DMA_CHAN3 */
#define XPAR_LPD_DMA_CHAN3_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_LPD_DMA_CHAN3_BASEADDR 0xffab0000
#define XPAR_LPD_DMA_CHAN3_HIGHADDR 0xffab0fff
#define XPAR_LPD_DMA_CHAN3_DMA_TYPE 0x1
#define XPAR_LPD_DMA_CHAN3_DMA_COHERENT 0x0
#define XPAR_LPD_DMA_CHAN3_INTERRUPTS 0x403f

/* Canonical definitions for peripheral LPD_DMA_CHAN3 */
#define XPAR_XZDMA_3_BASEADDR 0xffab0000
#define XPAR_XZDMA_3_HIGHADDR 0xffab0fff
#define XPAR_XZDMA_3_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_XZDMA_3_DMA_TYPE 0x1
#define XPAR_XZDMA_3_DMA_COHERENT 0x0
#define XPAR_XZDMA_3_INTERRUPTS 0x403f

/* Definitions for peripheral LPD_DMA_CHAN4 */
#define XPAR_LPD_DMA_CHAN4_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_LPD_DMA_CHAN4_BASEADDR 0xffac0000
#define XPAR_LPD_DMA_CHAN4_HIGHADDR 0xffac0fff
#define XPAR_LPD_DMA_CHAN4_DMA_TYPE 0x1
#define XPAR_LPD_DMA_CHAN4_DMA_COHERENT 0x0
#define XPAR_LPD_DMA_CHAN4_INTERRUPTS 0x4040

/* Canonical definitions for peripheral LPD_DMA_CHAN4 */
#define XPAR_XZDMA_4_BASEADDR 0xffac0000
#define XPAR_XZDMA_4_HIGHADDR 0xffac0fff
#define XPAR_XZDMA_4_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_XZDMA_4_DMA_TYPE 0x1
#define XPAR_XZDMA_4_DMA_COHERENT 0x0
#define XPAR_XZDMA_4_INTERRUPTS 0x4040

/* Definitions for peripheral LPD_DMA_CHAN5 */
#define XPAR_LPD_DMA_CHAN5_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_LPD_DMA_CHAN5_BASEADDR 0xffad0000
#define XPAR_LPD_DMA_CHAN5_HIGHADDR 0xffad0fff
#define XPAR_LPD_DMA_CHAN5_DMA_TYPE 0x1
#define XPAR_LPD_DMA_CHAN5_DMA_COHERENT 0x0
#define XPAR_LPD_DMA_CHAN5_INTERRUPTS 0x4041

/* Canonical definitions for peripheral LPD_DMA_CHAN5 */
#define XPAR_XZDMA_5_BASEADDR 0xffad0000
#define XPAR_XZDMA_5_HIGHADDR 0xffad0fff
#define XPAR_XZDMA_5_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_XZDMA_5_DMA_TYPE 0x1
#define XPAR_XZDMA_5_DMA_COHERENT 0x0
#define XPAR_XZDMA_5_INTERRUPTS 0x4041

/* Definitions for peripheral LPD_DMA_CHAN6 */
#define XPAR_LPD_DMA_CHAN6_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_LPD_DMA_CHAN6_BASEADDR 0xffae0000
#define XPAR_LPD_DMA_CHAN6_HIGHADDR 0xffae0fff
#define XPAR_LPD_DMA_CHAN6_DMA_TYPE 0x1
#define XPAR_LPD_DMA_CHAN6_DMA_COHERENT 0x0
#define XPAR_LPD_DMA_CHAN6_INTERRUPTS 0x4042

/* Canonical definitions for peripheral LPD_DMA_CHAN6 */
#define XPAR_XZDMA_6_BASEADDR 0xffae0000
#define XPAR_XZDMA_6_HIGHADDR 0xffae0fff
#define XPAR_XZDMA_6_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_XZDMA_6_DMA_TYPE 0x1
#define XPAR_XZDMA_6_DMA_COHERENT 0x0
#define XPAR_XZDMA_6_INTERRUPTS 0x4042

/* Definitions for peripheral LPD_DMA_CHAN7 */
#define XPAR_LPD_DMA_CHAN7_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_LPD_DMA_CHAN7_BASEADDR 0xffaf0000
#define XPAR_LPD_DMA_CHAN7_HIGHADDR 0xffaf0fff
#define XPAR_LPD_DMA_CHAN7_DMA_TYPE 0x1
#define XPAR_LPD_DMA_CHAN7_DMA_COHERENT 0x0
#define XPAR_LPD_DMA_CHAN7_INTERRUPTS 0x4043

/* Canonical definitions for peripheral LPD_DMA_CHAN7 */
#define XPAR_XZDMA_7_BASEADDR 0xffaf0000
#define XPAR_XZDMA_7_HIGHADDR 0xffaf0fff
#define XPAR_XZDMA_7_COMPATIBLE xlnx,zynqmp-dma-1.0
#define XPAR_XZDMA_7_DMA_TYPE 0x1
#define XPAR_XZDMA_7_DMA_COHERENT 0x0
#define XPAR_XZDMA_7_INTERRUPTS 0x4043

/* Definitions for peripheral GPIO1 */
#define XPAR_GPIO1_BASEADDR 0xf1020000
#define XPAR_GPIO1_HIGHADDR 0xf1020fff

/* Canonical definitions for peripheral GPIO1 */
#define XPAR_GPIO_0_BASEADDR 0xf1020000
#define XPAR_GPIO_0_HIGHADDR 0xf1020fff

/* Definitions for peripheral SMMU */
#define XPAR_SMMU_BASEADDR 0xfd800000
#define XPAR_SMMU_HIGHADDR 0xfd83ffff

/* Definitions for peripheral USB0 */
#define XPAR_USB0_BASEADDR 0xff9d0000
#define XPAR_USB0_HIGHADDR 0xff9d00ff

/* Canonical definitions for peripheral USB0 */
#define XPAR_USB_0_BASEADDR 0xff9d0000
#define XPAR_USB_0_HIGHADDR 0xff9d00ff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_CTI */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_CTI_BASEADDR 0xf0d10000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_CTI_HIGHADDR 0xf0d1ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_CTI */
#define XPAR_PSV_CORESIGHT_A720_CTI_0_BASEADDR 0xf0d10000
#define XPAR_PSV_CORESIGHT_A720_CTI_0_HIGHADDR 0xf0d1ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_DBG */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_DBG_BASEADDR 0xf0d00000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_DBG_HIGHADDR 0xf0d0ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_DBG */
#define XPAR_PSV_CORESIGHT_A720_DBG_0_BASEADDR 0xf0d00000
#define XPAR_PSV_CORESIGHT_A720_DBG_0_HIGHADDR 0xf0d0ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_ETM */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_ETM_BASEADDR 0xf0d30000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_ETM_HIGHADDR 0xf0d3ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_ETM */
#define XPAR_PSV_CORESIGHT_A720_ETM_0_BASEADDR 0xf0d30000
#define XPAR_PSV_CORESIGHT_A720_ETM_0_HIGHADDR 0xf0d3ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_PMU */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_PMU_BASEADDR 0xf0d20000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_PMU_HIGHADDR 0xf0d2ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A720_PMU */
#define XPAR_PSV_CORESIGHT_A720_PMU_0_BASEADDR 0xf0d20000
#define XPAR_PSV_CORESIGHT_A720_PMU_0_HIGHADDR 0xf0d2ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_CTI */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_CTI_BASEADDR 0xf0d50000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_CTI_HIGHADDR 0xf0d5ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_CTI */
#define XPAR_PSV_CORESIGHT_A721_CTI_0_BASEADDR 0xf0d50000
#define XPAR_PSV_CORESIGHT_A721_CTI_0_HIGHADDR 0xf0d5ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_DBG */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_DBG_BASEADDR 0xf0d40000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_DBG_HIGHADDR 0xf0d4ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_DBG */
#define XPAR_PSV_CORESIGHT_A721_DBG_0_BASEADDR 0xf0d40000
#define XPAR_PSV_CORESIGHT_A721_DBG_0_HIGHADDR 0xf0d4ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_ETM */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_ETM_BASEADDR 0xf0d70000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_ETM_HIGHADDR 0xf0d7ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_ETM */
#define XPAR_PSV_CORESIGHT_A721_ETM_0_BASEADDR 0xf0d70000
#define XPAR_PSV_CORESIGHT_A721_ETM_0_HIGHADDR 0xf0d7ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_PMU */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_PMU_BASEADDR 0xf0d60000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_PMU_HIGHADDR 0xf0d6ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_A721_PMU */
#define XPAR_PSV_CORESIGHT_A721_PMU_0_BASEADDR 0xf0d60000
#define XPAR_PSV_CORESIGHT_A721_PMU_0_HIGHADDR 0xf0d6ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_CTI */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_CTI_BASEADDR 0xf0ca0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_CTI_HIGHADDR 0xf0caffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_CTI */
#define XPAR_PSV_CORESIGHT_APU_CTI_0_BASEADDR 0xf0ca0000
#define XPAR_PSV_CORESIGHT_APU_CTI_0_HIGHADDR 0xf0caffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_ELA */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_ELA_BASEADDR 0xf0c60000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_ELA_HIGHADDR 0xf0c6ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_ELA */
#define XPAR_PSV_CORESIGHT_APU_ELA_0_BASEADDR 0xf0c60000
#define XPAR_PSV_CORESIGHT_APU_ELA_0_HIGHADDR 0xf0c6ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_ETF */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_ETF_BASEADDR 0xf0c30000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_ETF_HIGHADDR 0xf0c3ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_ETF */
#define XPAR_PSV_CORESIGHT_APU_ETF_0_BASEADDR 0xf0c30000
#define XPAR_PSV_CORESIGHT_APU_ETF_0_HIGHADDR 0xf0c3ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_FUN */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_FUN_BASEADDR 0xf0c20000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_FUN_HIGHADDR 0xf0c2ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_APU_FUN */
#define XPAR_PSV_CORESIGHT_APU_FUN_0_BASEADDR 0xf0c20000
#define XPAR_PSV_CORESIGHT_APU_FUN_0_HIGHADDR 0xf0c2ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ATM */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ATM_BASEADDR 0xf0f80000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ATM_HIGHADDR 0xf0f8ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ATM */
#define XPAR_PSV_CORESIGHT_CPM_ATM_0_BASEADDR 0xf0f80000
#define XPAR_PSV_CORESIGHT_CPM_ATM_0_HIGHADDR 0xf0f8ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_CTI2A */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_CTI2A_BASEADDR 0xf0fa0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_CTI2A_HIGHADDR 0xf0faffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_CTI2A */
#define XPAR_PSV_CORESIGHT_CPM_CTI2A_0_BASEADDR 0xf0fa0000
#define XPAR_PSV_CORESIGHT_CPM_CTI2A_0_HIGHADDR 0xf0faffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_CTI2D */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_CTI2D_BASEADDR 0xf0fd0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_CTI2D_HIGHADDR 0xf0fdffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_CTI2D */
#define XPAR_PSV_CORESIGHT_CPM_CTI2D_0_BASEADDR 0xf0fd0000
#define XPAR_PSV_CORESIGHT_CPM_CTI2D_0_HIGHADDR 0xf0fdffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2A */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2A_BASEADDR 0xf0f40000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2A_HIGHADDR 0xf0f4ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2A */
#define XPAR_PSV_CORESIGHT_CPM_ELA2A_0_BASEADDR 0xf0f40000
#define XPAR_PSV_CORESIGHT_CPM_ELA2A_0_HIGHADDR 0xf0f4ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2B */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2B_BASEADDR 0xf0f50000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2B_HIGHADDR 0xf0f5ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2B */
#define XPAR_PSV_CORESIGHT_CPM_ELA2B_0_BASEADDR 0xf0f50000
#define XPAR_PSV_CORESIGHT_CPM_ELA2B_0_HIGHADDR 0xf0f5ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2C */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2C_BASEADDR 0xf0f60000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2C_HIGHADDR 0xf0f6ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2C */
#define XPAR_PSV_CORESIGHT_CPM_ELA2C_0_BASEADDR 0xf0f60000
#define XPAR_PSV_CORESIGHT_CPM_ELA2C_0_HIGHADDR 0xf0f6ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2D */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2D_BASEADDR 0xf0f70000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2D_HIGHADDR 0xf0f7ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ELA2D */
#define XPAR_PSV_CORESIGHT_CPM_ELA2D_0_BASEADDR 0xf0f70000
#define XPAR_PSV_CORESIGHT_CPM_ELA2D_0_HIGHADDR 0xf0f7ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_FUN */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_FUN_BASEADDR 0xf0f20000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_FUN_HIGHADDR 0xf0f2ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_FUN */
#define XPAR_PSV_CORESIGHT_CPM_FUN_0_BASEADDR 0xf0f20000
#define XPAR_PSV_CORESIGHT_CPM_FUN_0_HIGHADDR 0xf0f2ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ROM */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ROM_BASEADDR 0xf0f00000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ROM_HIGHADDR 0xf0f0ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_CPM_ROM */
#define XPAR_PSV_CORESIGHT_CPM_ROM_0_BASEADDR 0xf0f00000
#define XPAR_PSV_CORESIGHT_CPM_ROM_0_HIGHADDR 0xf0f0ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_FPD_ATM */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_FPD_ATM_BASEADDR 0xf0b80000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_FPD_ATM_HIGHADDR 0xf0b8ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_FPD_ATM */
#define XPAR_PSV_CORESIGHT_FPD_ATM_0_BASEADDR 0xf0b80000
#define XPAR_PSV_CORESIGHT_FPD_ATM_0_HIGHADDR 0xf0b8ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_FPD_STM */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_FPD_STM_BASEADDR 0xf0b70000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_FPD_STM_HIGHADDR 0xf0b7ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_FPD_STM */
#define XPAR_PSV_CORESIGHT_FPD_STM_0_BASEADDR 0xf0b70000
#define XPAR_PSV_CORESIGHT_FPD_STM_0_HIGHADDR 0xf0b7ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_LPD_ATM */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_LPD_ATM_BASEADDR 0xf0980000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_LPD_ATM_HIGHADDR 0xf098ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CORESIGHT_LPD_ATM */
#define XPAR_PSV_CORESIGHT_LPD_ATM_0_BASEADDR 0xf0980000
#define XPAR_PSV_CORESIGHT_LPD_ATM_0_HIGHADDR 0xf098ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CRF_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CRF_0_BASEADDR 0xfd1a0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CRF_0_HIGHADDR 0xfd2dffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CRF_0 */
#define XPAR_PSV_CRF_0_BASEADDR 0xfd1a0000
#define XPAR_PSV_CRF_0_HIGHADDR 0xfd2dffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CRL_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CRL_0_BASEADDR 0xff5e0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CRL_0_HIGHADDR 0xff8dffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CRL_0 */
#define XPAR_PSV_CRL_0_BASEADDR 0xff5e0000
#define XPAR_PSV_CRL_0_HIGHADDR 0xff8dffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CRP_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CRP_0_BASEADDR 0xf1260000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_CRP_0_HIGHADDR 0xf126ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_CRP_0 */
#define XPAR_PSV_CRP_0_BASEADDR 0xf1260000
#define XPAR_PSV_CRP_0_HIGHADDR 0xf126ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_AFI_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_AFI_0_BASEADDR 0xfd360000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_AFI_0_HIGHADDR 0xfd36ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_AFI_0 */
#define XPAR_PSV_FPD_AFI_0_BASEADDR 0xfd360000
#define XPAR_PSV_FPD_AFI_0_HIGHADDR 0xfd36ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_AFI_2 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_AFI_2_BASEADDR 0xfd380000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_AFI_2_HIGHADDR 0xfd38ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_AFI_2 */
#define XPAR_PSV_FPD_AFI_1_BASEADDR 0xfd380000
#define XPAR_PSV_FPD_AFI_1_HIGHADDR 0xfd38ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_CCI_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_CCI_0_BASEADDR 0xfd5e0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_CCI_0_HIGHADDR 0xfd5effff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_CCI_0 */
#define XPAR_PSV_FPD_CCI_0_BASEADDR 0xfd5e0000
#define XPAR_PSV_FPD_CCI_0_HIGHADDR 0xfd5effff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_GPV_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_GPV_0_BASEADDR 0xfd700000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_GPV_0_HIGHADDR 0xfd7fffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_GPV_0 */
#define XPAR_PSV_FPD_GPV_0_BASEADDR 0xfd700000
#define XPAR_PSV_FPD_GPV_0_HIGHADDR 0xfd7fffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_MAINCCI_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_MAINCCI_0_BASEADDR 0xfd000000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_MAINCCI_0_HIGHADDR 0xfd0fffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_MAINCCI_0 */
#define XPAR_PSV_FPD_MAINCCI_0_BASEADDR 0xfd000000
#define XPAR_PSV_FPD_MAINCCI_0_HIGHADDR 0xfd0fffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_SLCR_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_SLCR_0_BASEADDR 0xfd610000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_SLCR_0_HIGHADDR 0xfd61ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_SLCR_0 */
#define XPAR_PSV_FPD_SLCR_0_BASEADDR 0xfd610000
#define XPAR_PSV_FPD_SLCR_0_HIGHADDR 0xfd61ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_SLCR_SECURE_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_SLCR_SECURE_0_BASEADDR 0xfd690000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_SLCR_SECURE_0_HIGHADDR 0xfd69ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_SLCR_SECURE_0 */
#define XPAR_PSV_FPD_SLCR_SECURE_0_BASEADDR 0xfd690000
#define XPAR_PSV_FPD_SLCR_SECURE_0_HIGHADDR 0xfd69ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_SMMU_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_SMMU_0_BASEADDR 0xfd5f0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_FPD_SMMU_0_HIGHADDR 0xfd5fffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_FPD_SMMU_0 */
#define XPAR_PSV_FPD_SMMU_0_BASEADDR 0xfd5f0000
#define XPAR_PSV_FPD_SMMU_0_HIGHADDR 0xfd5fffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_LPD_AFI_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_LPD_AFI_0_BASEADDR 0xff9b0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_LPD_AFI_0_HIGHADDR 0xff9bffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_LPD_AFI_0 */
#define XPAR_PSV_LPD_AFI_0_BASEADDR 0xff9b0000
#define XPAR_PSV_LPD_AFI_0_HIGHADDR 0xff9bffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_LPD_IOU_SECURE_SLCR_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_LPD_IOU_SECURE_SLCR_0_BASEADDR 0xff0a0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_LPD_IOU_SECURE_SLCR_0_HIGHADDR 0xff0affff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_LPD_IOU_SECURE_SLCR_0 */
#define XPAR_PSV_LPD_IOU_SECURE_SLCR_0_BASEADDR 0xff0a0000
#define XPAR_PSV_LPD_IOU_SECURE_SLCR_0_HIGHADDR 0xff0affff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_LPD_IOU_SLCR_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_LPD_IOU_SLCR_0_BASEADDR 0xff080000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_LPD_IOU_SLCR_0_HIGHADDR 0xff09ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_LPD_IOU_SLCR_0 */
#define XPAR_PSV_LPD_IOU_SLCR_0_BASEADDR 0xff080000
#define XPAR_PSV_LPD_IOU_SLCR_0_HIGHADDR 0xff09ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_LPD_SLCR_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_LPD_SLCR_0_BASEADDR 0xff410000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_LPD_SLCR_0_HIGHADDR 0xff50ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_LPD_SLCR_0 */
#define XPAR_PSV_LPD_SLCR_0_BASEADDR 0xff410000
#define XPAR_PSV_LPD_SLCR_0_HIGHADDR 0xff50ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_LPD_SLCR_SECURE_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_LPD_SLCR_SECURE_0_BASEADDR 0xff510000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_LPD_SLCR_SECURE_0_HIGHADDR 0xff54ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_LPD_SLCR_SECURE_0 */
#define XPAR_PSV_LPD_SLCR_SECURE_0_BASEADDR 0xff510000
#define XPAR_PSV_LPD_SLCR_SECURE_0_HIGHADDR 0xff54ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_OCM_CTRL */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_OCM_CTRL_BASEADDR 0xff960000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_OCM_CTRL_HIGHADDR 0xff96ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_OCM_CTRL */
#define XPAR_PSV_OCM_0_BASEADDR 0xff960000
#define XPAR_PSV_OCM_0_HIGHADDR 0xff96ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_AES */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_AES_BASEADDR 0xf11e0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_AES_HIGHADDR 0xf11effff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_AES */
#define XPAR_PSV_PMC_AES_0_BASEADDR 0xf11e0000
#define XPAR_PSV_PMC_AES_0_HIGHADDR 0xf11effff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_BBRAM_CTRL */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_BBRAM_CTRL_BASEADDR 0xf11f0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_BBRAM_CTRL_HIGHADDR 0xf11fffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_BBRAM_CTRL */
#define XPAR_PSV_PMC_BBRAM_CTRL_0_BASEADDR 0xf11f0000
#define XPAR_PSV_PMC_BBRAM_CTRL_0_HIGHADDR 0xf11fffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_EFUSE_CACHE */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_EFUSE_CACHE_BASEADDR 0xf1250000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_EFUSE_CACHE_HIGHADDR 0xf125ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_EFUSE_CACHE */
#define XPAR_PSV_PMC_EFUSE_CACHE_0_BASEADDR 0xf1250000
#define XPAR_PSV_PMC_EFUSE_CACHE_0_HIGHADDR 0xf125ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_EFUSE_CTRL */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_EFUSE_CTRL_BASEADDR 0xf1240000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_EFUSE_CTRL_HIGHADDR 0xf124ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_EFUSE_CTRL */
#define XPAR_PSV_PMC_EFUSE_CTRL_0_BASEADDR 0xf1240000
#define XPAR_PSV_PMC_EFUSE_CTRL_0_HIGHADDR 0xf124ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_GLOBAL_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_GLOBAL_0_BASEADDR 0xf1110000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_GLOBAL_0_HIGHADDR 0xf115ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_GLOBAL_0 */
#define XPAR_PSV_PMC_GLOBAL_0_BASEADDR 0xf1110000
#define XPAR_PSV_PMC_GLOBAL_0_HIGHADDR 0xf115ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_PPU1_MDM_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_PPU1_MDM_0_BASEADDR 0xf0310000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_PPU1_MDM_0_HIGHADDR 0xf0317fff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_PPU1_MDM_0 */
#define XPAR_PSV_PMC_PPU1_MDM_0_BASEADDR 0xf0310000
#define XPAR_PSV_PMC_PPU1_MDM_0_HIGHADDR 0xf0317fff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_RAM_NPI */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_RAM_NPI_BASEADDR 0xf6000000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_RAM_NPI_HIGHADDR 0xf7ffffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_RAM_NPI */
#define XPAR_PSV_PMC_RAM_NPI_0_BASEADDR 0xf6000000
#define XPAR_PSV_PMC_RAM_NPI_0_HIGHADDR 0xf7ffffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_RSA */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_RSA_BASEADDR 0xf1200000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_RSA_HIGHADDR 0xf120ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_RSA */
#define XPAR_PSV_PMC_RSA_0_BASEADDR 0xf1200000
#define XPAR_PSV_PMC_RSA_0_HIGHADDR 0xf120ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SHA */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SHA_BASEADDR 0xf1210000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SHA_HIGHADDR 0xf121ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SHA */
#define XPAR_PSV_PMC_SHA_0_BASEADDR 0xf1210000
#define XPAR_PSV_PMC_SHA_0_HIGHADDR 0xf121ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SLAVE_BOOT */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SLAVE_BOOT_BASEADDR 0xf1220000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SLAVE_BOOT_HIGHADDR 0xf122ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SLAVE_BOOT */
#define XPAR_PSV_PMC_SLAVE_BOOT_0_BASEADDR 0xf1220000
#define XPAR_PSV_PMC_SLAVE_BOOT_0_HIGHADDR 0xf122ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SLAVE_BOOT_STREAM */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SLAVE_BOOT_STREAM_BASEADDR 0xf2100000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SLAVE_BOOT_STREAM_HIGHADDR 0xf210ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SLAVE_BOOT_STREAM */
#define XPAR_PSV_PMC_SLAVE_BOOT_STREAM_0_BASEADDR 0xf2100000
#define XPAR_PSV_PMC_SLAVE_BOOT_STREAM_0_HIGHADDR 0xf210ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_TRNG */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_TRNG_BASEADDR 0xf1230000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_TRNG_HIGHADDR 0xf123ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PMC_TRNG */
#define XPAR_PSV_PMC_TRNG_0_BASEADDR 0xf1230000
#define XPAR_PSV_PMC_TRNG_0_HIGHADDR 0xf123ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PSM_GLOBAL_REG */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_GLOBAL_REG_BASEADDR 0xffc90000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_GLOBAL_REG_HIGHADDR 0xffc9efff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PSM_GLOBAL_REG */
#define XPAR_PSV_PSM_GLOBAL_REG_0_BASEADDR 0xffc90000
#define XPAR_PSV_PSM_GLOBAL_REG_0_HIGHADDR 0xffc9efff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PSM_RAM_DATA_CNTLR */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_RAM_DATA_CNTLR_BASEADDR 0xffc20000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_RAM_DATA_CNTLR_HIGHADDR 0xffc3ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PSM_RAM_DATA_CNTLR */
#define XPAR_PSM_PPU_0_BASEADDR 0xffc20000
#define XPAR_PSM_PPU_0_HIGHADDR 0xffc3ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PSM_RAM_INSTR_CNTLR */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_RAM_INSTR_CNTLR_BASEADDR 0xffc00000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PSM_RAM_INSTR_CNTLR_HIGHADDR 0xffc1ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_PSM_RAM_INSTR_CNTLR */
#define XPAR_RAM_INSTR_CNTLR_0_BASEADDR 0xffc00000
#define XPAR_RAM_INSTR_CNTLR_0_HIGHADDR 0xffc1ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_R5_1_ATCM_GLOBAL */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_R5_1_ATCM_GLOBAL_BASEADDR 0xffe90000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_R5_1_ATCM_GLOBAL_HIGHADDR 0xffe9ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_R5_1_ATCM_GLOBAL */
#define XPAR_PSV_TCM_GLOBAL_0_BASEADDR 0xffe90000
#define XPAR_PSV_TCM_GLOBAL_0_HIGHADDR 0xffe9ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_R5_1_BTCM_GLOBAL */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_R5_1_BTCM_GLOBAL_BASEADDR 0xffeb0000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_R5_1_BTCM_GLOBAL_HIGHADDR 0xffebffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_R5_1_BTCM_GLOBAL */
#define XPAR_PSV_TCM_GLOBAL_1_BASEADDR 0xffeb0000
#define XPAR_PSV_TCM_GLOBAL_1_HIGHADDR 0xffebffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_R5_TCM_RAM_GLOBAL */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_R5_TCM_RAM_GLOBAL_BASEADDR 0xffe00000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_R5_TCM_RAM_GLOBAL_HIGHADDR 0xffe3ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_R5_TCM_RAM_GLOBAL */
#define XPAR_PSV_R5_TCM_0_BASEADDR 0xffe00000
#define XPAR_PSV_R5_TCM_0_HIGHADDR 0xffe3ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_SCNTR_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_SCNTR_0_BASEADDR 0xff130000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_SCNTR_0_HIGHADDR 0xff13ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_SCNTR_0 */
#define XPAR_PSV_SCNTR_0_BASEADDR 0xff130000
#define XPAR_PSV_SCNTR_0_HIGHADDR 0xff13ffff

/* Definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_SCNTRS_0 */
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_SCNTRS_0_BASEADDR 0xff140000
#define XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_SCNTRS_0_HIGHADDR 0xff14ffff

/* Canonical definitions for peripheral VERSAL_CIPS_0_PSPMC_0_PSV_SCNTRS_0 */
#define XPAR_PSV_SCNTRS_0_BASEADDR 0xff140000
#define XPAR_PSV_SCNTRS_0_HIGHADDR 0xff14ffff

/* Definitions for peripheral LPD_XPPU */
#define XPAR_LPD_XPPU_BASEADDR 0xff990000
#define XPAR_LPD_XPPU_HIGHADDR 0xff991fff

/* Canonical definitions for peripheral LPD_XPPU */
#define XPAR_XPPU_0_BASEADDR 0xff990000
#define XPAR_XPPU_0_HIGHADDR 0xff991fff

/* Definitions for peripheral PMC_XPPU */
#define XPAR_PMC_XPPU_BASEADDR 0xf1310000
#define XPAR_PMC_XPPU_HIGHADDR 0xf1311fff

/* Canonical definitions for peripheral PMC_XPPU */
#define XPAR_XPPU_1_BASEADDR 0xf1310000
#define XPAR_XPPU_1_HIGHADDR 0xf1311fff

/* Definitions for peripheral PMC_XPPU_NPI */
#define XPAR_PMC_XPPU_NPI_BASEADDR 0xf1300000
#define XPAR_PMC_XPPU_NPI_HIGHADDR 0xf1301fff

/* Canonical definitions for peripheral PMC_XPPU_NPI */
#define XPAR_XPPU_2_BASEADDR 0xf1300000
#define XPAR_XPPU_2_HIGHADDR 0xf1301fff

/* Definitions for peripheral FPD_XMPU */
#define XPAR_FPD_XMPU_BASEADDR 0xfd390000
#define XPAR_FPD_XMPU_HIGHADDR 0xfd390fff

/* Canonical definitions for peripheral FPD_XMPU */
#define XPAR_XMPU_0_BASEADDR 0xfd390000
#define XPAR_XMPU_0_HIGHADDR 0xfd390fff

/* Definitions for peripheral PMC_XMPU */
#define XPAR_PMC_XMPU_BASEADDR 0xf12f0000
#define XPAR_PMC_XMPU_HIGHADDR 0xf12f0fff

/* Canonical definitions for peripheral PMC_XMPU */
#define XPAR_XMPU_1_BASEADDR 0xf12f0000
#define XPAR_XMPU_1_HIGHADDR 0xf12f0fff

/* Definitions for peripheral OCM_XMPU */
#define XPAR_OCM_XMPU_BASEADDR 0xff980000
#define XPAR_OCM_XMPU_HIGHADDR 0xff980fff

/* Canonical definitions for peripheral OCM_XMPU */
#define XPAR_XMPU_2_BASEADDR 0xff980000
#define XPAR_XMPU_2_HIGHADDR 0xff980fff

#define XPAR_AXI_NOC_0_BASEADDRESS 0x0
#define XPAR_AXI_NOC_0_HIGHADDRESS 0x80000000
#define XPAR_PSV_OCM_0_BASEADDRESS 0xfffc0000
#define XPAR_PSV_OCM_0_HIGHADDRESS 0x100000000
#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 100000000

#define STDOUT_BASEADDRESS 0xff000000
#define STDIN_BASEADDRESS 0xff000000

/* Number of SLRs */
#define NUMBER_OF_SLRS 0x1

#endif  /* end of protection macro */