/******************************************************************************
* Copyright (C) 2019 - 2022 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/


/*****************************************************************************/
/**
*
* @file xaiemlgbl_params.h
* @{
*
* This file contains the macro definitions for the AIE registers, generated from
* regdb headers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver   Who     Date     Changes
* ----- ------  -------- -----------------------------------------------------
* 1.0   Tejus   07/25/2019  Initial creation
* 1.1   Tejus   07/31/2019  Update register defn to r0p6  
* 1.2   Dishita 09/17/2020  Update register defn to r0p14
* 1.3   Dishita 09/17/2020  Replace XAIEMLGBL with XAIEMLGBL
* </pre>
*
******************************************************************************/
#ifndef XAIEMLGBL_PARAMS_H
#define XAIEMLGBL_PARAMS_H

/* AIE-ML core module register definitions */
#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY                             0x00020000
#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY_A_LSB                     0
#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY_A_WIDTH                   128
#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY_A_MASK                    0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY_A_DEFVAL                  0x0

#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY_ERROR_INJECTION             0x00024000
#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY_ERROR_INJECTION_WIDTH       128
#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY_ERROR_INJECTION_MASK        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY_ERROR_INJECTION_A_LSB     0
#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY_ERROR_INJECTION_A_WIDTH   128
#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY_ERROR_INJECTION_A_MASK    0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PROGRAM_MEMORY_ERROR_INJECTION_A_DEFVAL  0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART1                           0x00030000
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART2                           0x00030010
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL0_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART1                           0x00030020
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART2                           0x00030030
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH0_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART1                           0x00030040
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART2                           0x00030050
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL0_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART1                           0x00030060
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART2                           0x00030070
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH0_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART1                           0x00030080
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART2                           0x00030090
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL1_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART1                           0x000300A0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART2                           0x000300B0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH1_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART1                           0x000300C0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART2                           0x000300D0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL1_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART1                           0x000300E0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART2                           0x000300F0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH1_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART1                           0x00030100
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART2                           0x00030110
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL2_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART1                           0x00030120
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART2                           0x00030130
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH2_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART1                           0x00030140
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART2                           0x00030150
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL2_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART1                           0x00030160
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART2                           0x00030170
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH2_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART1                           0x00030180
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART2                           0x00030190
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL3_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART1                           0x000301A0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART2                           0x000301B0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH3_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART1                           0x000301C0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART2                           0x000301D0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL3_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART1                           0x000301E0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART2                           0x000301F0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH3_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART1                           0x00030200
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART2                           0x00030210
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL4_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART1                           0x00030220
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART2                           0x00030230
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH4_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART1                           0x00030240
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART2                           0x00030250
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL4_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART1                           0x00030260
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART2                           0x00030270
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH4_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART1                           0x00030280
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART2                           0x00030290
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL5_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART1                           0x000302A0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART2                           0x000302B0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH5_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART1                           0x000302C0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART2                           0x000302D0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL5_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART1                           0x000302E0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART2                           0x000302F0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH5_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART1                           0x00030300
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART2                           0x00030310
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL6_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART1                           0x00030320
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART2                           0x00030330
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH6_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART1                           0x00030340
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART2                           0x00030350
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL6_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART1                           0x00030360
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART2                           0x00030370
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH6_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART1                           0x00030380
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART2                           0x00030390
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL7_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART1                           0x000303A0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART2                           0x000303B0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH7_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART1                           0x000303C0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART2                           0x000303D0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL7_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART1                           0x000303E0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART2                           0x000303F0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH7_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART1                           0x00030400
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART2                           0x00030410
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLL8_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART1                           0x00030420
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART2                           0x00030430
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMLH8_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART1                           0x00030440
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART2                           0x00030450
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHL8_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART1                           0x00030460
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART1_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART1_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART1_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART1_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART1_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART1_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART2                           0x00030470
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART2_WIDTH                     128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART2_MASK                      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART2_REGISTER_VALUE_LSB      0
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART2_REGISTER_VALUE_WIDTH    128
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART2_REGISTER_VALUE_MASK     0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_AMHH8_PART2_REGISTER_VALUE_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_RESERVED0                                  0x00030480
#define XAIEMLGBL_CORE_MODULE_RESERVED0_WIDTH                            128
#define XAIEMLGBL_CORE_MODULE_RESERVED0_MASK                             0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED1                                  0x00030490
#define XAIEMLGBL_CORE_MODULE_RESERVED1_WIDTH                            128
#define XAIEMLGBL_CORE_MODULE_RESERVED1_MASK                             0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED2                                  0x000304A0
#define XAIEMLGBL_CORE_MODULE_RESERVED2_WIDTH                            128
#define XAIEMLGBL_CORE_MODULE_RESERVED2_MASK                             0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED3                                  0x000304B0
#define XAIEMLGBL_CORE_MODULE_RESERVED3_WIDTH                            128
#define XAIEMLGBL_CORE_MODULE_RESERVED3_MASK                             0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED4                                  0x000304C0
#define XAIEMLGBL_CORE_MODULE_RESERVED4_WIDTH                            128
#define XAIEMLGBL_CORE_MODULE_RESERVED4_MASK                             0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED5                                  0x000304D0
#define XAIEMLGBL_CORE_MODULE_RESERVED5_WIDTH                            128
#define XAIEMLGBL_CORE_MODULE_RESERVED5_MASK                             0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED6                                  0x000304E0
#define XAIEMLGBL_CORE_MODULE_RESERVED6_WIDTH                            128
#define XAIEMLGBL_CORE_MODULE_RESERVED6_MASK                             0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED7                                  0x000304F0
#define XAIEMLGBL_CORE_MODULE_RESERVED7_WIDTH                            128
#define XAIEMLGBL_CORE_MODULE_RESERVED7_MASK                             0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED8                                  0x00030500
#define XAIEMLGBL_CORE_MODULE_RESERVED8_WIDTH                            128
#define XAIEMLGBL_CORE_MODULE_RESERVED8_MASK                             0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED9                                  0x00030510
#define XAIEMLGBL_CORE_MODULE_RESERVED9_WIDTH                            128
#define XAIEMLGBL_CORE_MODULE_RESERVED9_MASK                             0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED10                                 0x00030520
#define XAIEMLGBL_CORE_MODULE_RESERVED10_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED10_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED11                                 0x00030530
#define XAIEMLGBL_CORE_MODULE_RESERVED11_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED11_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED12                                 0x00030540
#define XAIEMLGBL_CORE_MODULE_RESERVED12_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED12_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED13                                 0x00030550
#define XAIEMLGBL_CORE_MODULE_RESERVED13_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED13_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED14                                 0x00030560
#define XAIEMLGBL_CORE_MODULE_RESERVED14_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED14_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED15                                 0x00030570
#define XAIEMLGBL_CORE_MODULE_RESERVED15_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED15_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED16                                 0x00030580
#define XAIEMLGBL_CORE_MODULE_RESERVED16_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED16_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED17                                 0x00030590
#define XAIEMLGBL_CORE_MODULE_RESERVED17_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED17_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED18                                 0x000305A0
#define XAIEMLGBL_CORE_MODULE_RESERVED18_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED18_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED19                                 0x000305B0
#define XAIEMLGBL_CORE_MODULE_RESERVED19_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED19_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED20                                 0x000305C0
#define XAIEMLGBL_CORE_MODULE_RESERVED20_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED20_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED21                                 0x000305D0
#define XAIEMLGBL_CORE_MODULE_RESERVED21_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED21_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED22                                 0x000305E0
#define XAIEMLGBL_CORE_MODULE_RESERVED22_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED22_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED23                                 0x000305F0
#define XAIEMLGBL_CORE_MODULE_RESERVED23_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED23_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED24                                 0x00030600
#define XAIEMLGBL_CORE_MODULE_RESERVED24_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED24_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED25                                 0x00030610
#define XAIEMLGBL_CORE_MODULE_RESERVED25_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED25_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED26                                 0x00030620
#define XAIEMLGBL_CORE_MODULE_RESERVED26_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED26_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED27                                 0x00030630
#define XAIEMLGBL_CORE_MODULE_RESERVED27_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED27_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED28                                 0x00030640
#define XAIEMLGBL_CORE_MODULE_RESERVED28_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED28_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED29                                 0x00030650
#define XAIEMLGBL_CORE_MODULE_RESERVED29_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED29_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED30                                 0x00030660
#define XAIEMLGBL_CORE_MODULE_RESERVED30_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED30_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED31                                 0x00030670
#define XAIEMLGBL_CORE_MODULE_RESERVED31_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED31_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED32                                 0x00030680
#define XAIEMLGBL_CORE_MODULE_RESERVED32_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED32_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED33                                 0x00030690
#define XAIEMLGBL_CORE_MODULE_RESERVED33_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED33_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED34                                 0x000306A0
#define XAIEMLGBL_CORE_MODULE_RESERVED34_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED34_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED35                                 0x000306B0
#define XAIEMLGBL_CORE_MODULE_RESERVED35_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED35_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED36                                 0x000306C0
#define XAIEMLGBL_CORE_MODULE_RESERVED36_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED36_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED37                                 0x000306D0
#define XAIEMLGBL_CORE_MODULE_RESERVED37_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED37_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED38                                 0x000306E0
#define XAIEMLGBL_CORE_MODULE_RESERVED38_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED38_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED39                                 0x000306F0
#define XAIEMLGBL_CORE_MODULE_RESERVED39_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED39_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED40                                 0x00030700
#define XAIEMLGBL_CORE_MODULE_RESERVED40_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED40_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED41                                 0x00030710
#define XAIEMLGBL_CORE_MODULE_RESERVED41_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED41_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED42                                 0x00030720
#define XAIEMLGBL_CORE_MODULE_RESERVED42_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED42_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED43                                 0x00030730
#define XAIEMLGBL_CORE_MODULE_RESERVED43_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED43_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED44                                 0x00030740
#define XAIEMLGBL_CORE_MODULE_RESERVED44_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED44_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED45                                 0x00030750
#define XAIEMLGBL_CORE_MODULE_RESERVED45_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED45_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED46                                 0x00030760
#define XAIEMLGBL_CORE_MODULE_RESERVED46_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED46_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED47                                 0x00030770
#define XAIEMLGBL_CORE_MODULE_RESERVED47_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED47_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED48                                 0x00030780
#define XAIEMLGBL_CORE_MODULE_RESERVED48_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED48_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED49                                 0x00030790
#define XAIEMLGBL_CORE_MODULE_RESERVED49_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED49_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED50                                 0x000307A0
#define XAIEMLGBL_CORE_MODULE_RESERVED50_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED50_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED51                                 0x000307B0
#define XAIEMLGBL_CORE_MODULE_RESERVED51_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED51_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED52                                 0x000307C0
#define XAIEMLGBL_CORE_MODULE_RESERVED52_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED52_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED53                                 0x000307D0
#define XAIEMLGBL_CORE_MODULE_RESERVED53_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED53_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED54                                 0x000307E0
#define XAIEMLGBL_CORE_MODULE_RESERVED54_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED54_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED55                                 0x000307F0
#define XAIEMLGBL_CORE_MODULE_RESERVED55_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED55_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART1                             0x00030800
#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART2                             0x00030810
#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL0_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART1                             0x00030820
#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART2                             0x00030830
#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH0_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART1                             0x00030840
#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART2                             0x00030850
#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL1_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART1                             0x00030860
#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART2                             0x00030870
#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH1_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART1                             0x00030880
#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART2                             0x00030890
#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL2_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART1                             0x000308A0
#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART2                             0x000308B0
#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH2_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART1                             0x000308C0
#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART2                             0x000308D0
#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL3_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART1                             0x000308E0
#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART2                             0x000308F0
#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH3_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART1                             0x00030900
#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART2                             0x00030910
#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL4_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART1                             0x00030920
#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART2                             0x00030930
#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH4_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART1                             0x00030940
#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART2                             0x00030950
#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL5_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART1                             0x00030960
#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART2                             0x00030970
#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH5_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART1                             0x00030980
#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART2                             0x00030990
#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL6_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART1                             0x000309A0
#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART2                             0x000309B0
#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH6_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART1                             0x000309C0
#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART2                             0x000309D0
#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL7_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART1                             0x000309E0
#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART2                             0x000309F0
#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH7_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART1                             0x00030A00
#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART2                             0x00030A10
#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL8_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART1                             0x00030A20
#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART2                             0x00030A30
#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH8_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART1                             0x00030A40
#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART2                             0x00030A50
#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL9_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART1                             0x00030A60
#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART1_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART1_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART1_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART1_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART1_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART1_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART2                             0x00030A70
#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART2_WIDTH                       128
#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART2_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART2_REGISTER_VALUE_LSB        0
#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART2_REGISTER_VALUE_WIDTH      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART2_REGISTER_VALUE_MASK       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH9_PART2_REGISTER_VALUE_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART1                            0x00030A80
#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART1_WIDTH                      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART1_MASK                       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART1_REGISTER_VALUE_LSB       0
#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART1_REGISTER_VALUE_WIDTH     128
#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART1_REGISTER_VALUE_MASK      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART1_REGISTER_VALUE_DEFVAL    0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART2                            0x00030A90
#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART2_WIDTH                      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART2_MASK                       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART2_REGISTER_VALUE_LSB       0
#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART2_REGISTER_VALUE_WIDTH     128
#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART2_REGISTER_VALUE_MASK      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL10_PART2_REGISTER_VALUE_DEFVAL    0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART1                            0x00030AA0
#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART1_WIDTH                      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART1_MASK                       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART1_REGISTER_VALUE_LSB       0
#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART1_REGISTER_VALUE_WIDTH     128
#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART1_REGISTER_VALUE_MASK      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART1_REGISTER_VALUE_DEFVAL    0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART2                            0x00030AB0
#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART2_WIDTH                      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART2_MASK                       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART2_REGISTER_VALUE_LSB       0
#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART2_REGISTER_VALUE_WIDTH     128
#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART2_REGISTER_VALUE_MASK      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH10_PART2_REGISTER_VALUE_DEFVAL    0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART1                            0x00030AC0
#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART1_WIDTH                      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART1_MASK                       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART1_REGISTER_VALUE_LSB       0
#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART1_REGISTER_VALUE_WIDTH     128
#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART1_REGISTER_VALUE_MASK      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART1_REGISTER_VALUE_DEFVAL    0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART2                            0x00030AD0
#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART2_WIDTH                      128
#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART2_MASK                       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART2_REGISTER_VALUE_LSB       0
#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART2_REGISTER_VALUE_WIDTH     128
#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART2_REGISTER_VALUE_MASK      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WL11_PART2_REGISTER_VALUE_DEFVAL    0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART1                            0x00030AE0
#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART1_WIDTH                      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART1_MASK                       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART1_REGISTER_VALUE_LSB       0
#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART1_REGISTER_VALUE_WIDTH     128
#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART1_REGISTER_VALUE_MASK      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART1_REGISTER_VALUE_DEFVAL    0x0

#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART2                            0x00030AF0
#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART2_WIDTH                      128
#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART2_MASK                       0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART2_REGISTER_VALUE_LSB       0
#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART2_REGISTER_VALUE_WIDTH     128
#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART2_REGISTER_VALUE_MASK      0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_WH11_PART2_REGISTER_VALUE_DEFVAL    0x0

#define XAIEMLGBL_CORE_MODULE_RESERVED56                                 0x00030B00
#define XAIEMLGBL_CORE_MODULE_RESERVED56_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED56_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED57                                 0x00030B10
#define XAIEMLGBL_CORE_MODULE_RESERVED57_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED57_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED58                                 0x00030B20
#define XAIEMLGBL_CORE_MODULE_RESERVED58_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED58_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED59                                 0x00030B30
#define XAIEMLGBL_CORE_MODULE_RESERVED59_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED59_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED60                                 0x00030B40
#define XAIEMLGBL_CORE_MODULE_RESERVED60_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED60_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED61                                 0x00030B50
#define XAIEMLGBL_CORE_MODULE_RESERVED61_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED61_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED62                                 0x00030B60
#define XAIEMLGBL_CORE_MODULE_RESERVED62_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED62_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED63                                 0x00030B70
#define XAIEMLGBL_CORE_MODULE_RESERVED63_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED63_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED64                                 0x00030B80
#define XAIEMLGBL_CORE_MODULE_RESERVED64_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED64_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED65                                 0x00030B90
#define XAIEMLGBL_CORE_MODULE_RESERVED65_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED65_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED66                                 0x00030BA0
#define XAIEMLGBL_CORE_MODULE_RESERVED66_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED66_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED67                                 0x00030BB0
#define XAIEMLGBL_CORE_MODULE_RESERVED67_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED67_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED68                                 0x00030BC0
#define XAIEMLGBL_CORE_MODULE_RESERVED68_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED68_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED69                                 0x00030BD0
#define XAIEMLGBL_CORE_MODULE_RESERVED69_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED69_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED70                                 0x00030BE0
#define XAIEMLGBL_CORE_MODULE_RESERVED70_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED70_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED71                                 0x00030BF0
#define XAIEMLGBL_CORE_MODULE_RESERVED71_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED71_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_CORE_R0                                    0x00030C00
#define XAIEMLGBL_CORE_MODULE_CORE_R0_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_R0_MASK                               0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R0_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_R0_REGISTER_VALUE_WIDTH             32
#define XAIEMLGBL_CORE_MODULE_CORE_R0_REGISTER_VALUE_MASK              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R0_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R1                                    0x00030C10
#define XAIEMLGBL_CORE_MODULE_CORE_R1_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_R1_MASK                               0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R1_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_R1_REGISTER_VALUE_WIDTH             32
#define XAIEMLGBL_CORE_MODULE_CORE_R1_REGISTER_VALUE_MASK              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R1_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R2                                    0x00030C20
#define XAIEMLGBL_CORE_MODULE_CORE_R2_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_R2_MASK                               0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R2_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_R2_REGISTER_VALUE_WIDTH             32
#define XAIEMLGBL_CORE_MODULE_CORE_R2_REGISTER_VALUE_MASK              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R2_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R3                                    0x00030C30
#define XAIEMLGBL_CORE_MODULE_CORE_R3_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_R3_MASK                               0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R3_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_R3_REGISTER_VALUE_WIDTH             32
#define XAIEMLGBL_CORE_MODULE_CORE_R3_REGISTER_VALUE_MASK              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R3_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R4                                    0x00030C40
#define XAIEMLGBL_CORE_MODULE_CORE_R4_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_R4_MASK                               0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R4_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_R4_REGISTER_VALUE_WIDTH             32
#define XAIEMLGBL_CORE_MODULE_CORE_R4_REGISTER_VALUE_MASK              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R4_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R5                                    0x00030C50
#define XAIEMLGBL_CORE_MODULE_CORE_R5_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_R5_MASK                               0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R5_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_R5_REGISTER_VALUE_WIDTH             32
#define XAIEMLGBL_CORE_MODULE_CORE_R5_REGISTER_VALUE_MASK              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R5_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R6                                    0x00030C60
#define XAIEMLGBL_CORE_MODULE_CORE_R6_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_R6_MASK                               0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R6_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_R6_REGISTER_VALUE_WIDTH             32
#define XAIEMLGBL_CORE_MODULE_CORE_R6_REGISTER_VALUE_MASK              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R6_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R7                                    0x00030C70
#define XAIEMLGBL_CORE_MODULE_CORE_R7_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_R7_MASK                               0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R7_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_R7_REGISTER_VALUE_WIDTH             32
#define XAIEMLGBL_CORE_MODULE_CORE_R7_REGISTER_VALUE_MASK              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R7_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R8                                    0x00030C80
#define XAIEMLGBL_CORE_MODULE_CORE_R8_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_R8_MASK                               0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R8_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_R8_REGISTER_VALUE_WIDTH             32
#define XAIEMLGBL_CORE_MODULE_CORE_R8_REGISTER_VALUE_MASK              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R8_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R9                                    0x00030C90
#define XAIEMLGBL_CORE_MODULE_CORE_R9_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_R9_MASK                               0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R9_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_R9_REGISTER_VALUE_WIDTH             32
#define XAIEMLGBL_CORE_MODULE_CORE_R9_REGISTER_VALUE_MASK              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R9_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R10                                   0x00030CA0
#define XAIEMLGBL_CORE_MODULE_CORE_R10_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R10_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R10_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R10_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R10_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R10_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R11                                   0x00030CB0
#define XAIEMLGBL_CORE_MODULE_CORE_R11_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R11_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R11_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R11_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R11_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R11_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R12                                   0x00030CC0
#define XAIEMLGBL_CORE_MODULE_CORE_R12_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R12_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R12_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R12_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R12_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R12_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R13                                   0x00030CD0
#define XAIEMLGBL_CORE_MODULE_CORE_R13_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R13_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R13_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R13_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R13_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R13_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R14                                   0x00030CE0
#define XAIEMLGBL_CORE_MODULE_CORE_R14_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R14_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R14_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R14_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R14_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R14_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R15                                   0x00030CF0
#define XAIEMLGBL_CORE_MODULE_CORE_R15_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R15_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R15_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R15_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R15_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R15_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R16                                   0x00030D00
#define XAIEMLGBL_CORE_MODULE_CORE_R16_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R16_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R16_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R16_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R16_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R16_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R17                                   0x00030D10
#define XAIEMLGBL_CORE_MODULE_CORE_R17_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R17_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R17_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R17_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R17_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R17_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R18                                   0x00030D20
#define XAIEMLGBL_CORE_MODULE_CORE_R18_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R18_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R18_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R18_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R18_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R18_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R19                                   0x00030D30
#define XAIEMLGBL_CORE_MODULE_CORE_R19_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R19_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R19_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R19_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R19_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R19_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R20                                   0x00030D40
#define XAIEMLGBL_CORE_MODULE_CORE_R20_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R20_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R20_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R20_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R20_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R20_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R21                                   0x00030D50
#define XAIEMLGBL_CORE_MODULE_CORE_R21_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R21_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R21_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R21_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R21_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R21_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R22                                   0x00030D60
#define XAIEMLGBL_CORE_MODULE_CORE_R22_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R22_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R22_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R22_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R22_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R22_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R23                                   0x00030D70
#define XAIEMLGBL_CORE_MODULE_CORE_R23_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R23_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R23_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R23_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R23_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R23_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R24                                   0x00030D80
#define XAIEMLGBL_CORE_MODULE_CORE_R24_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R24_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R24_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R24_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R24_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R24_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R25                                   0x00030D90
#define XAIEMLGBL_CORE_MODULE_CORE_R25_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R25_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R25_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R25_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R25_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R25_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R26                                   0x00030DA0
#define XAIEMLGBL_CORE_MODULE_CORE_R26_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R26_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R26_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R26_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R26_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R26_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R27                                   0x00030DB0
#define XAIEMLGBL_CORE_MODULE_CORE_R27_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R27_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R27_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R27_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R27_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R27_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R28                                   0x00030DC0
#define XAIEMLGBL_CORE_MODULE_CORE_R28_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R28_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R28_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R28_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R28_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R28_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R29                                   0x00030DD0
#define XAIEMLGBL_CORE_MODULE_CORE_R29_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R29_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R29_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R29_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R29_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R29_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R30                                   0x00030DE0
#define XAIEMLGBL_CORE_MODULE_CORE_R30_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R30_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R30_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R30_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R30_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R30_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_R31                                   0x00030DF0
#define XAIEMLGBL_CORE_MODULE_CORE_R31_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_R31_MASK                              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R31_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_R31_REGISTER_VALUE_WIDTH            32
#define XAIEMLGBL_CORE_MODULE_CORE_R31_REGISTER_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_R31_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_M0                                    0x00030E00
#define XAIEMLGBL_CORE_MODULE_CORE_M0_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_M0_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M0_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_M0_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_M0_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M0_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_M1                                    0x00030E10
#define XAIEMLGBL_CORE_MODULE_CORE_M1_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_M1_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M1_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_M1_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_M1_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M1_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_M2                                    0x00030E20
#define XAIEMLGBL_CORE_MODULE_CORE_M2_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_M2_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M2_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_M2_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_M2_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M2_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_M3                                    0x00030E30
#define XAIEMLGBL_CORE_MODULE_CORE_M3_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_M3_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M3_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_M3_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_M3_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M3_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_M4                                    0x00030E40
#define XAIEMLGBL_CORE_MODULE_CORE_M4_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_M4_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M4_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_M4_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_M4_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M4_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_M5                                    0x00030E50
#define XAIEMLGBL_CORE_MODULE_CORE_M5_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_M5_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M5_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_M5_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_M5_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M5_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_M6                                    0x00030E60
#define XAIEMLGBL_CORE_MODULE_CORE_M6_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_M6_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M6_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_M6_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_M6_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M6_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_M7                                    0x00030E70
#define XAIEMLGBL_CORE_MODULE_CORE_M7_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_M7_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M7_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_M7_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_M7_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_M7_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DN0                                   0x00030E80
#define XAIEMLGBL_CORE_MODULE_CORE_DN0_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DN0_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN0_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DN0_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DN0_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN0_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DN1                                   0x00030E90
#define XAIEMLGBL_CORE_MODULE_CORE_DN1_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DN1_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN1_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DN1_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DN1_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN1_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DN2                                   0x00030EA0
#define XAIEMLGBL_CORE_MODULE_CORE_DN2_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DN2_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN2_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DN2_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DN2_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN2_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DN3                                   0x00030EB0
#define XAIEMLGBL_CORE_MODULE_CORE_DN3_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DN3_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN3_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DN3_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DN3_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN3_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DN4                                   0x00030EC0
#define XAIEMLGBL_CORE_MODULE_CORE_DN4_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DN4_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN4_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DN4_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DN4_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN4_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DN5                                   0x00030ED0
#define XAIEMLGBL_CORE_MODULE_CORE_DN5_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DN5_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN5_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DN5_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DN5_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN5_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DN6                                   0x00030EE0
#define XAIEMLGBL_CORE_MODULE_CORE_DN6_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DN6_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN6_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DN6_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DN6_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN6_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DN7                                   0x00030EF0
#define XAIEMLGBL_CORE_MODULE_CORE_DN7_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DN7_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN7_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DN7_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DN7_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DN7_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DJ0                                   0x00030F00
#define XAIEMLGBL_CORE_MODULE_CORE_DJ0_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DJ0_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ0_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DJ0_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DJ0_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ0_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DJ1                                   0x00030F10
#define XAIEMLGBL_CORE_MODULE_CORE_DJ1_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DJ1_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ1_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DJ1_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DJ1_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ1_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DJ2                                   0x00030F20
#define XAIEMLGBL_CORE_MODULE_CORE_DJ2_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DJ2_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ2_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DJ2_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DJ2_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ2_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DJ3                                   0x00030F30
#define XAIEMLGBL_CORE_MODULE_CORE_DJ3_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DJ3_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ3_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DJ3_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DJ3_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ3_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DJ4                                   0x00030F40
#define XAIEMLGBL_CORE_MODULE_CORE_DJ4_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DJ4_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ4_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DJ4_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DJ4_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ4_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DJ5                                   0x00030F50
#define XAIEMLGBL_CORE_MODULE_CORE_DJ5_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DJ5_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ5_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DJ5_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DJ5_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ5_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DJ6                                   0x00030F60
#define XAIEMLGBL_CORE_MODULE_CORE_DJ6_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DJ6_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ6_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DJ6_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DJ6_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ6_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DJ7                                   0x00030F70
#define XAIEMLGBL_CORE_MODULE_CORE_DJ7_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DJ7_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ7_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DJ7_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DJ7_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DJ7_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DC0                                   0x00030F80
#define XAIEMLGBL_CORE_MODULE_CORE_DC0_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DC0_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC0_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DC0_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DC0_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC0_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DC1                                   0x00030F90
#define XAIEMLGBL_CORE_MODULE_CORE_DC1_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DC1_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC1_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DC1_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DC1_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC1_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DC2                                   0x00030FA0
#define XAIEMLGBL_CORE_MODULE_CORE_DC2_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DC2_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC2_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DC2_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DC2_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC2_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DC3                                   0x00030FB0
#define XAIEMLGBL_CORE_MODULE_CORE_DC3_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DC3_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC3_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DC3_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DC3_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC3_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DC4                                   0x00030FC0
#define XAIEMLGBL_CORE_MODULE_CORE_DC4_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DC4_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC4_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DC4_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DC4_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC4_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DC5                                   0x00030FD0
#define XAIEMLGBL_CORE_MODULE_CORE_DC5_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DC5_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC5_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DC5_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DC5_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC5_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DC6                                   0x00030FE0
#define XAIEMLGBL_CORE_MODULE_CORE_DC6_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DC6_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC6_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DC6_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DC6_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC6_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DC7                                   0x00030FF0
#define XAIEMLGBL_CORE_MODULE_CORE_DC7_WIDTH                             32
#define XAIEMLGBL_CORE_MODULE_CORE_DC7_MASK                              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC7_REGISTER_VALUE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_DC7_REGISTER_VALUE_WIDTH            20
#define XAIEMLGBL_CORE_MODULE_CORE_DC7_REGISTER_VALUE_MASK             0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DC7_REGISTER_VALUE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_P0                                    0x00031000
#define XAIEMLGBL_CORE_MODULE_CORE_P0_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_P0_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P0_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_P0_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_P0_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P0_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_P1                                    0x00031010
#define XAIEMLGBL_CORE_MODULE_CORE_P1_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_P1_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P1_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_P1_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_P1_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P1_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_P2                                    0x00031020
#define XAIEMLGBL_CORE_MODULE_CORE_P2_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_P2_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P2_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_P2_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_P2_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P2_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_P3                                    0x00031030
#define XAIEMLGBL_CORE_MODULE_CORE_P3_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_P3_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P3_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_P3_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_P3_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P3_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_P4                                    0x00031040
#define XAIEMLGBL_CORE_MODULE_CORE_P4_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_P4_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P4_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_P4_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_P4_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P4_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_P5                                    0x00031050
#define XAIEMLGBL_CORE_MODULE_CORE_P5_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_P5_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P5_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_P5_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_P5_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P5_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_P6                                    0x00031060
#define XAIEMLGBL_CORE_MODULE_CORE_P6_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_P6_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P6_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_P6_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_P6_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P6_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_P7                                    0x00031070
#define XAIEMLGBL_CORE_MODULE_CORE_P7_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_P7_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P7_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_P7_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_P7_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_P7_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_S0                                    0x00031080
#define XAIEMLGBL_CORE_MODULE_CORE_S0_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_S0_MASK                               0x0000003F
#define XAIEMLGBL_CORE_MODULE_CORE_S0_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_S0_REGISTER_VALUE_WIDTH             6
#define XAIEMLGBL_CORE_MODULE_CORE_S0_REGISTER_VALUE_MASK              0x0000003F
#define XAIEMLGBL_CORE_MODULE_CORE_S0_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_S1                                    0x00031090
#define XAIEMLGBL_CORE_MODULE_CORE_S1_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_S1_MASK                               0x0000003F
#define XAIEMLGBL_CORE_MODULE_CORE_S1_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_S1_REGISTER_VALUE_WIDTH             6
#define XAIEMLGBL_CORE_MODULE_CORE_S1_REGISTER_VALUE_MASK              0x0000003F
#define XAIEMLGBL_CORE_MODULE_CORE_S1_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_S2                                    0x000310A0
#define XAIEMLGBL_CORE_MODULE_CORE_S2_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_S2_MASK                               0x0000003F
#define XAIEMLGBL_CORE_MODULE_CORE_S2_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_S2_REGISTER_VALUE_WIDTH             6
#define XAIEMLGBL_CORE_MODULE_CORE_S2_REGISTER_VALUE_MASK              0x0000003F
#define XAIEMLGBL_CORE_MODULE_CORE_S2_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_S3                                    0x000310B0
#define XAIEMLGBL_CORE_MODULE_CORE_S3_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_S3_MASK                               0x0000003F
#define XAIEMLGBL_CORE_MODULE_CORE_S3_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_S3_REGISTER_VALUE_WIDTH             6
#define XAIEMLGBL_CORE_MODULE_CORE_S3_REGISTER_VALUE_MASK              0x0000003F
#define XAIEMLGBL_CORE_MODULE_CORE_S3_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_RESERVED72                                 0x000310C0
#define XAIEMLGBL_CORE_MODULE_RESERVED72_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED72_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED73                                 0x000310D0
#define XAIEMLGBL_CORE_MODULE_RESERVED73_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED73_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED74                                 0x000310E0
#define XAIEMLGBL_CORE_MODULE_RESERVED74_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED74_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_RESERVED75                                 0x000310F0
#define XAIEMLGBL_CORE_MODULE_RESERVED75_WIDTH                           128
#define XAIEMLGBL_CORE_MODULE_RESERVED75_MASK                            0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_CORE_PC                                    0x00031100
#define XAIEMLGBL_CORE_MODULE_CORE_PC_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_PC_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_PC_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_PC_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_PC_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_PC_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_FC                                    0x00031110
#define XAIEMLGBL_CORE_MODULE_CORE_FC_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_FC_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_FC_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_FC_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_FC_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_FC_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_SP                                    0x00031120
#define XAIEMLGBL_CORE_MODULE_CORE_SP_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_SP_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_SP_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_SP_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_SP_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_SP_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_LR                                    0x00031130
#define XAIEMLGBL_CORE_MODULE_CORE_LR_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_LR_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_LR_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_LR_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_LR_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_LR_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_LS                                    0x00031140
#define XAIEMLGBL_CORE_MODULE_CORE_LS_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_LS_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_LS_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_LS_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_LS_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_LS_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_LE                                    0x00031150
#define XAIEMLGBL_CORE_MODULE_CORE_LE_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_LE_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_LE_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_LE_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_LE_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_LE_REGISTER_VALUE_DEFVAL            0xFFFFF

#define XAIEMLGBL_CORE_MODULE_CORE_LC                                    0x00031160
#define XAIEMLGBL_CORE_MODULE_CORE_LC_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_LC_MASK                               0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_LC_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_LC_REGISTER_VALUE_WIDTH             32
#define XAIEMLGBL_CORE_MODULE_CORE_LC_REGISTER_VALUE_MASK              0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_LC_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_CR                                    0x00031170
#define XAIEMLGBL_CORE_MODULE_CORE_CR_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_CR_MASK                               0x0FFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_HUGE_MASK_LSB    27
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_HUGE_MASK_WIDTH  1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_HUGE_MASK_MASK   0x08000000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_HUGE_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_TINY_MASK_LSB    26
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_TINY_MASK_WIDTH  1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_TINY_MASK_MASK   0x04000000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_TINY_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_INVALID_MASK_LSB 25
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_INVALID_MASK_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_INVALID_MASK_MASK 0x02000000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_INVALID_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_INFINITY_MASK_LSB 24
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_INFINITY_MASK_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_INFINITY_MASK_MASK 0x01000000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_INFINITY_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_ZERO_MASK_LSB    23
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_ZERO_MASK_WIDTH  1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_ZERO_MASK_MASK   0x00800000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_TO_BFLOAT_ZERO_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_HUGE_MASK_LSB      22
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_HUGE_MASK_WIDTH    1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_HUGE_MASK_MASK     0x00400000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_HUGE_MASK_DEFVAL   0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_TINY_MASK_LSB      21
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_TINY_MASK_WIDTH    1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_TINY_MASK_MASK     0x00200000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_TINY_MASK_DEFVAL   0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_INVALID_MASK_LSB   20
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_INVALID_MASK_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_INVALID_MASK_MASK  0x00100000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_INVALID_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_ZERO_MASK_LSB      18
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_ZERO_MASK_WIDTH    1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_ZERO_MASK_MASK     0x00040000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_BFLOAT_TO_INT_ZERO_MASK_DEFVAL   0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_SRS_SIGN_LSB                     17
#define XAIEMLGBL_CORE_MODULE_CORE_CR_SRS_SIGN_WIDTH                   1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_SRS_SIGN_MASK                    0x00020000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_SRS_SIGN_DEFVAL                  0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_UPS_SIGN_LSB                     16
#define XAIEMLGBL_CORE_MODULE_CORE_CR_UPS_SIGN_WIDTH                   1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_UPS_SIGN_MASK                    0x00010000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_UPS_SIGN_DEFVAL                  0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_PACK_SIGN_LSB                    15
#define XAIEMLGBL_CORE_MODULE_CORE_CR_PACK_SIGN_WIDTH                  1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_PACK_SIGN_MASK                   0x00008000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_PACK_SIGN_DEFVAL                 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_UNPACK_SIGN_LSB                  14
#define XAIEMLGBL_CORE_MODULE_CORE_CR_UNPACK_SIGN_WIDTH                1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_UNPACK_SIGN_MASK                 0x00004000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_UNPACK_SIGN_DEFVAL               0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_VADD_SIGN_LSB                    13
#define XAIEMLGBL_CORE_MODULE_CORE_CR_VADD_SIGN_WIDTH                  1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_VADD_SIGN_MASK                   0x00002000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_VADD_SIGN_DEFVAL                 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_SCD_ENABLE_LSB                   12
#define XAIEMLGBL_CORE_MODULE_CORE_CR_SCD_ENABLE_WIDTH                 1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_SCD_ENABLE_MASK                  0x00001000
#define XAIEMLGBL_CORE_MODULE_CORE_CR_SCD_ENABLE_DEFVAL                0x1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_MCD_ENABLE_LSB                   11
#define XAIEMLGBL_CORE_MODULE_CORE_CR_MCD_ENABLE_WIDTH                 1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_MCD_ENABLE_MASK                  0x00000800
#define XAIEMLGBL_CORE_MODULE_CORE_CR_MCD_ENABLE_DEFVAL                0x1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_HUGE_MASK_LSB          10
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_HUGE_MASK_WIDTH        1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_HUGE_MASK_MASK         0x00000400
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_HUGE_MASK_DEFVAL       0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_TINY_MASK_LSB          9
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_TINY_MASK_WIDTH        1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_TINY_MASK_MASK         0x00000200
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_TINY_MASK_DEFVAL       0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_INVALID_MASK_LSB       8
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_INVALID_MASK_WIDTH     1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_INVALID_MASK_MASK      0x00000100
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_INVALID_MASK_DEFVAL    0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_INFINITY_MASK_LSB      7
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_INFINITY_MASK_WIDTH    1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_INFINITY_MASK_MASK     0x00000080
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_INFINITY_MASK_DEFVAL   0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_ZERO_MASK_LSB          6
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_ZERO_MASK_WIDTH        1
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_ZERO_MASK_MASK         0x00000040
#define XAIEMLGBL_CORE_MODULE_CORE_CR_FLOAT_MAC_ZERO_MASK_DEFVAL       0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_ROUND_MODE_LSB                   2
#define XAIEMLGBL_CORE_MODULE_CORE_CR_ROUND_MODE_WIDTH                 4
#define XAIEMLGBL_CORE_MODULE_CORE_CR_ROUND_MODE_MASK                  0x0000003C
#define XAIEMLGBL_CORE_MODULE_CORE_CR_ROUND_MODE_DEFVAL                0x0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_SATURATION_MODE_LSB              0
#define XAIEMLGBL_CORE_MODULE_CORE_CR_SATURATION_MODE_WIDTH            2
#define XAIEMLGBL_CORE_MODULE_CORE_CR_SATURATION_MODE_MASK             0x00000003
#define XAIEMLGBL_CORE_MODULE_CORE_CR_SATURATION_MODE_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_CORE_SR                                    0x00031180
#define XAIEMLGBL_CORE_MODULE_CORE_SR_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_SR_MASK                               0x007FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SPARSE_OVERFLOW_LSB              22
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SPARSE_OVERFLOW_WIDTH            1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SPARSE_OVERFLOW_MASK             0x00400000
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SPARSE_OVERFLOW_DEFVAL           0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_HUGE_FLAG_LSB    21
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_HUGE_FLAG_WIDTH  1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_HUGE_FLAG_MASK   0x00200000
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_HUGE_FLAG_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_TINY_FLAG_LSB    20
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_TINY_FLAG_WIDTH  1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_TINY_FLAG_MASK   0x00100000
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_TINY_FLAG_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_INVALID_FLAG_LSB 19
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_INVALID_FLAG_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_INVALID_FLAG_MASK 0x00080000
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_INVALID_FLAG_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_INFINITY_FLAG_LSB 18
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_INFINITY_FLAG_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_INFINITY_FLAG_MASK 0x00040000
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_INFINITY_FLAG_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_ZERO_FLAG_LSB    17
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_ZERO_FLAG_WIDTH  1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_ZERO_FLAG_MASK   0x00020000
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_TO_BFLOAT_ZERO_FLAG_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_HUGE_FLAG_LSB      16
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_HUGE_FLAG_WIDTH    1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_HUGE_FLAG_MASK     0x00010000
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_HUGE_FLAG_DEFVAL   0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_TINY_FLAG_LSB      15
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_TINY_FLAG_WIDTH    1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_TINY_FLAG_MASK     0x00008000
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_TINY_FLAG_DEFVAL   0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_INVALID_FLAG_LSB   14
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_INVALID_FLAG_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_INVALID_FLAG_MASK  0x00004000
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_INVALID_FLAG_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_ZERO_FLAG_LSB      12
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_ZERO_FLAG_WIDTH    1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_ZERO_FLAG_MASK     0x00001000
#define XAIEMLGBL_CORE_MODULE_CORE_SR_BFLOAT_TO_INT_ZERO_FLAG_DEFVAL   0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_HUGE_FLAG_LSB          11
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_HUGE_FLAG_WIDTH        1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_HUGE_FLAG_MASK         0x00000800
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_HUGE_FLAG_DEFVAL       0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_TINY_FLAG_LSB          10
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_TINY_FLAG_WIDTH        1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_TINY_FLAG_MASK         0x00000400
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_TINY_FLAG_DEFVAL       0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_INVALID_FLAG_LSB       9
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_INVALID_FLAG_WIDTH     1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_INVALID_FLAG_MASK      0x00000200
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_INVALID_FLAG_DEFVAL    0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_INFINITY_FLAG_LSB      8
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_INFINITY_FLAG_WIDTH    1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_INFINITY_FLAG_MASK     0x00000100
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_INFINITY_FLAG_DEFVAL   0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_ZERO_FLAG_LSB          7
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_ZERO_FLAG_WIDTH        1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_ZERO_FLAG_MASK         0x00000080
#define XAIEMLGBL_CORE_MODULE_CORE_SR_FLOAT_MAC_ZERO_FLAG_DEFVAL       0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_COMPRESSION_UNDERFLOW_LSB        6
#define XAIEMLGBL_CORE_MODULE_CORE_SR_COMPRESSION_UNDERFLOW_WIDTH      1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_COMPRESSION_UNDERFLOW_MASK       0x00000040
#define XAIEMLGBL_CORE_MODULE_CORE_SR_COMPRESSION_UNDERFLOW_DEFVAL     0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_UPS_OVERFLOW_LSB                 5
#define XAIEMLGBL_CORE_MODULE_CORE_SR_UPS_OVERFLOW_WIDTH               1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_UPS_OVERFLOW_MASK                0x00000020
#define XAIEMLGBL_CORE_MODULE_CORE_SR_UPS_OVERFLOW_DEFVAL              0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SRS_OVERFLOW_LSB                 4
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SRS_OVERFLOW_WIDTH               1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SRS_OVERFLOW_MASK                0x00000010
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SRS_OVERFLOW_DEFVAL              0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_MS0_SUCCESS_LSB                  3
#define XAIEMLGBL_CORE_MODULE_CORE_SR_MS0_SUCCESS_WIDTH                1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_MS0_SUCCESS_MASK                 0x00000008
#define XAIEMLGBL_CORE_MODULE_CORE_SR_MS0_SUCCESS_DEFVAL               0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SS0_TLAST_LSB                    2
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SS0_TLAST_WIDTH                  1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SS0_TLAST_MASK                   0x00000004
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SS0_TLAST_DEFVAL                 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SS0_SUCCESS_LSB                  1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SS0_SUCCESS_WIDTH                1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SS0_SUCCESS_MASK                 0x00000002
#define XAIEMLGBL_CORE_MODULE_CORE_SR_SS0_SUCCESS_DEFVAL               0x0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_CARRY_LSB                        0
#define XAIEMLGBL_CORE_MODULE_CORE_SR_CARRY_WIDTH                      1
#define XAIEMLGBL_CORE_MODULE_CORE_SR_CARRY_MASK                       0x00000001
#define XAIEMLGBL_CORE_MODULE_CORE_SR_CARRY_DEFVAL                     0x0

#define XAIEMLGBL_CORE_MODULE_CORE_DP                                    0x00031190
#define XAIEMLGBL_CORE_MODULE_CORE_DP_WIDTH                              32
#define XAIEMLGBL_CORE_MODULE_CORE_DP_MASK                               0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DP_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_DP_REGISTER_VALUE_WIDTH             20
#define XAIEMLGBL_CORE_MODULE_CORE_DP_REGISTER_VALUE_MASK              0x000FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_DP_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_Q0                                    0x00031200
#define XAIEMLGBL_CORE_MODULE_CORE_Q0_WIDTH                              128
#define XAIEMLGBL_CORE_MODULE_CORE_Q0_MASK                               0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_Q0_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_Q0_REGISTER_VALUE_WIDTH             128
#define XAIEMLGBL_CORE_MODULE_CORE_Q0_REGISTER_VALUE_MASK              0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_Q0_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_Q1                                    0x00031210
#define XAIEMLGBL_CORE_MODULE_CORE_Q1_WIDTH                              128
#define XAIEMLGBL_CORE_MODULE_CORE_Q1_MASK                               0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_Q1_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_Q1_REGISTER_VALUE_WIDTH             128
#define XAIEMLGBL_CORE_MODULE_CORE_Q1_REGISTER_VALUE_MASK              0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_Q1_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_Q2                                    0x00031220
#define XAIEMLGBL_CORE_MODULE_CORE_Q2_WIDTH                              128
#define XAIEMLGBL_CORE_MODULE_CORE_Q2_MASK                               0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_Q2_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_Q2_REGISTER_VALUE_WIDTH             128
#define XAIEMLGBL_CORE_MODULE_CORE_Q2_REGISTER_VALUE_MASK              0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_Q2_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_CORE_Q3                                    0x00031230
#define XAIEMLGBL_CORE_MODULE_CORE_Q3_WIDTH                              128
#define XAIEMLGBL_CORE_MODULE_CORE_Q3_MASK                               0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_Q3_REGISTER_VALUE_LSB               0
#define XAIEMLGBL_CORE_MODULE_CORE_Q3_REGISTER_VALUE_WIDTH             128
#define XAIEMLGBL_CORE_MODULE_CORE_Q3_REGISTER_VALUE_MASK              0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_Q3_REGISTER_VALUE_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0                       0x00031500
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_WIDTH                 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_MASK                  0x7F7F7F7F
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT1_STOP_EVENT_LSB 24
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT1_STOP_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT1_STOP_EVENT_MASK 0x7F000000
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT1_STOP_EVENT_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT1_START_EVENT_LSB 16
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT1_START_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT1_START_EVENT_MASK 0x007F0000
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT1_START_EVENT_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT0_STOP_EVENT_LSB 8
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT0_STOP_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT0_STOP_EVENT_MASK 0x00007F00
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT0_STOP_EVENT_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT0_START_EVENT_LSB 0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT0_START_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT0_START_EVENT_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL0_CNT0_START_EVENT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1                       0x00031504
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_WIDTH                 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_MASK                  0x7F7F7F7F
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT3_STOP_EVENT_LSB 24
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT3_STOP_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT3_STOP_EVENT_MASK 0x7F000000
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT3_STOP_EVENT_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT3_START_EVENT_LSB 16
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT3_START_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT3_START_EVENT_MASK 0x007F0000
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT3_START_EVENT_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT2_STOP_EVENT_LSB 8
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT2_STOP_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT2_STOP_EVENT_MASK 0x00007F00
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT2_STOP_EVENT_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT2_START_EVENT_LSB 0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT2_START_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT2_START_EVENT_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL1_CNT2_START_EVENT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2                       0x00031508
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_WIDTH                 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_MASK                  0x7F7F7F7F
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT3_RESET_EVENT_LSB 24
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT3_RESET_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT3_RESET_EVENT_MASK 0x7F000000
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT3_RESET_EVENT_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT2_RESET_EVENT_LSB 16
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT2_RESET_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT2_RESET_EVENT_MASK 0x007F0000
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT2_RESET_EVENT_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT1_RESET_EVENT_LSB 8
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT1_RESET_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT1_RESET_EVENT_MASK 0x00007F00
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT1_RESET_EVENT_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT0_RESET_EVENT_LSB 0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT0_RESET_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT0_RESET_EVENT_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_CONTROL2_CNT0_RESET_EVENT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0                       0x00031520
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0_WIDTH                 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0_MASK                  0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_LSB  0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1                       0x00031524
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1_WIDTH                 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1_MASK                  0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1_COUNTER0_VALUE_LSB  0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1_COUNTER0_VALUE_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1_COUNTER0_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1_COUNTER0_VALUE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2                       0x00031528
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2_WIDTH                 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2_MASK                  0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2_COUNTER0_VALUE_LSB  0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2_COUNTER0_VALUE_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2_COUNTER0_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2_COUNTER0_VALUE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3                       0x0003152C
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3_WIDTH                 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3_MASK                  0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3_COUNTER0_VALUE_LSB  0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3_COUNTER0_VALUE_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3_COUNTER0_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3_COUNTER0_VALUE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE           0x00031580
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_MASK      0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER_EVENT_VALUE_LSB 0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER_EVENT_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER_EVENT_VALUE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE           0x00031584
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_MASK      0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER_EVENT_VALUE_LSB 0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER_EVENT_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER_EVENT_VALUE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE           0x00031588
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE_MASK      0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE_COUNTER_EVENT_VALUE_LSB 0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE_COUNTER_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE_COUNTER_EVENT_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE_COUNTER_EVENT_VALUE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE           0x0003158C
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE_MASK      0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE_COUNTER_EVENT_VALUE_LSB 0
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE_COUNTER_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE_COUNTER_EVENT_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE_COUNTER_EVENT_VALUE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_CORE_CONTROL                               0x00032000
#define XAIEMLGBL_CORE_MODULE_CORE_CONTROL_WIDTH                         32
#define XAIEMLGBL_CORE_MODULE_CORE_CONTROL_MASK                          0x00000003
#define XAIEMLGBL_CORE_MODULE_CORE_CONTROL_RESET_LSB                   1
#define XAIEMLGBL_CORE_MODULE_CORE_CONTROL_RESET_WIDTH                 1
#define XAIEMLGBL_CORE_MODULE_CORE_CONTROL_RESET_MASK                  0x00000002
#define XAIEMLGBL_CORE_MODULE_CORE_CONTROL_RESET_DEFVAL                0x1
#define XAIEMLGBL_CORE_MODULE_CORE_CONTROL_ENABLE_LSB                  0
#define XAIEMLGBL_CORE_MODULE_CORE_CONTROL_ENABLE_WIDTH                1
#define XAIEMLGBL_CORE_MODULE_CORE_CONTROL_ENABLE_MASK                 0x00000001
#define XAIEMLGBL_CORE_MODULE_CORE_CONTROL_ENABLE_DEFVAL               0x0

#define XAIEMLGBL_CORE_MODULE_CORE_STATUS                                0x00032004
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_WIDTH                          32
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MASK                           0x003FFFFF
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CORE_PROCESSOR_BUS_STALL_LSB 21
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CORE_PROCESSOR_BUS_STALL_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CORE_PROCESSOR_BUS_STALL_MASK 0x00200000
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CORE_PROCESSOR_BUS_STALL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CORE_DONE_LSB                20
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CORE_DONE_WIDTH              1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CORE_DONE_MASK               0x00100000
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CORE_DONE_DEFVAL             0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ERROR_HALT_LSB               19
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ERROR_HALT_WIDTH             1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ERROR_HALT_MASK              0x00080000
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ERROR_HALT_DEFVAL            0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ECC_SCRUBBING_STALL_LSB      18
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ECC_SCRUBBING_STALL_WIDTH    1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ECC_SCRUBBING_STALL_MASK     0x00040000
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ECC_SCRUBBING_STALL_DEFVAL   0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ECC_ERROR_STALL_LSB          17
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ECC_ERROR_STALL_WIDTH        1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ECC_ERROR_STALL_MASK         0x00020000
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ECC_ERROR_STALL_DEFVAL       0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_DEBUG_HALT_LSB               16
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_DEBUG_HALT_WIDTH             1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_DEBUG_HALT_MASK              0x00010000
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_DEBUG_HALT_DEFVAL            0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CASCADE_STALL_MCD_LSB        15
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CASCADE_STALL_MCD_WIDTH      1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CASCADE_STALL_MCD_MASK       0x00008000
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CASCADE_STALL_MCD_DEFVAL     0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CASCADE_STALL_SCD_LSB        14
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CASCADE_STALL_SCD_WIDTH      1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CASCADE_STALL_SCD_MASK       0x00004000
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_CASCADE_STALL_SCD_DEFVAL     0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_STREAM_STALL_MS0_LSB         12
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_STREAM_STALL_MS0_WIDTH       1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_STREAM_STALL_MS0_MASK        0x00001000
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_STREAM_STALL_MS0_DEFVAL      0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_STREAM_STALL_SS0_LSB         10
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_STREAM_STALL_SS0_WIDTH       1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_STREAM_STALL_SS0_MASK        0x00000400
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_STREAM_STALL_SS0_DEFVAL      0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_E_LSB             9
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_E_WIDTH           1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_E_MASK            0x00000200
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_E_DEFVAL          0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_N_LSB             8
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_N_WIDTH           1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_N_MASK            0x00000100
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_N_DEFVAL          0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_W_LSB             7
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_W_WIDTH           1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_W_MASK            0x00000080
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_W_DEFVAL          0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_S_LSB             6
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_S_WIDTH           1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_S_MASK            0x00000040
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_LOCK_STALL_S_DEFVAL          0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_E_LSB           5
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_E_WIDTH         1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_E_MASK          0x00000020
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_E_DEFVAL        0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_N_LSB           4
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_N_WIDTH         1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_N_MASK          0x00000010
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_N_DEFVAL        0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_W_LSB           3
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_W_WIDTH         1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_W_MASK          0x00000008
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_W_DEFVAL        0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_S_LSB           2
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_S_WIDTH         1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_S_MASK          0x00000004
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_MEMORY_STALL_S_DEFVAL        0x0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_RESET_LSB                    1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_RESET_WIDTH                  1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_RESET_MASK                   0x00000002
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_RESET_DEFVAL                 0x1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ENABLE_LSB                   0
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ENABLE_WIDTH                 1
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ENABLE_MASK                  0x00000001
#define XAIEMLGBL_CORE_MODULE_CORE_STATUS_ENABLE_DEFVAL                0x0

#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS                              0x00032008
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_WIDTH                        32
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_MASK                         0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_DISABLE_EVENT_OCCURRED_LSB 15
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_DISABLE_EVENT_OCCURRED_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_DISABLE_EVENT_OCCURRED_MASK 0x00008000
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_DISABLE_EVENT_OCCURRED_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_DISABLE_EVENT_LSB          8
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_DISABLE_EVENT_WIDTH        7
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_DISABLE_EVENT_MASK         0x00007F00
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_DISABLE_EVENT_DEFVAL       0x0
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_ENABLE_EVENT_OCCURRED_LSB  7
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_ENABLE_EVENT_OCCURRED_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_ENABLE_EVENT_OCCURRED_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_ENABLE_EVENT_OCCURRED_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_ENABLE_EVENT_LSB           0
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_ENABLE_EVENT_WIDTH         7
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_ENABLE_EVENT_MASK          0x0000007F
#define XAIEMLGBL_CORE_MODULE_ENABLE_EVENTS_ENABLE_EVENT_DEFVAL        0x0

#define XAIEMLGBL_CORE_MODULE_RESET_EVENT                                0x0003200C
#define XAIEMLGBL_CORE_MODULE_RESET_EVENT_WIDTH                          32
#define XAIEMLGBL_CORE_MODULE_RESET_EVENT_MASK                           0x0000007F
#define XAIEMLGBL_CORE_MODULE_RESET_EVENT_RESET_EVENT_LSB              0
#define XAIEMLGBL_CORE_MODULE_RESET_EVENT_RESET_EVENT_WIDTH            7
#define XAIEMLGBL_CORE_MODULE_RESET_EVENT_RESET_EVENT_MASK             0x0000007F
#define XAIEMLGBL_CORE_MODULE_RESET_EVENT_RESET_EVENT_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL0                             0x00032010
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL0_WIDTH                       32
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL0_MASK                        0x0000003D
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL0_SINGLE_STEP_COUNT_LSB     2
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL0_SINGLE_STEP_COUNT_WIDTH   4
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL0_SINGLE_STEP_COUNT_MASK    0x0000003C
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL0_SINGLE_STEP_COUNT_DEFVAL  0x0
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL0_DEBUG_HALT_BIT_LSB        0
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL0_DEBUG_HALT_BIT_WIDTH      1
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL0_DEBUG_HALT_BIT_MASK       0x00000001
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL0_DEBUG_HALT_BIT_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1                             0x00032014
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_WIDTH                       32
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_MASK                        0x7F7F7F7F
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_HALT_CORE_EVENT1_LSB 24
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_HALT_CORE_EVENT1_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_HALT_CORE_EVENT1_MASK 0x7F000000
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_HALT_CORE_EVENT1_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_HALT_CORE_EVENT0_LSB 16
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_HALT_CORE_EVENT0_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_HALT_CORE_EVENT0_MASK 0x007F0000
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_HALT_CORE_EVENT0_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_SINGLESTEP_CORE_EVENT_LSB 8
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_SINGLESTEP_CORE_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_SINGLESTEP_CORE_EVENT_MASK 0x00007F00
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_SINGLESTEP_CORE_EVENT_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_RESUME_CORE_EVENT_LSB 0
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_RESUME_CORE_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_RESUME_CORE_EVENT_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL1_DEBUG_RESUME_CORE_EVENT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2                             0x00032018
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_WIDTH                       32
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_MASK                        0x0000000F
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_STREAM_STALL_HALT_LSB     3
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_STREAM_STALL_HALT_WIDTH   1
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_STREAM_STALL_HALT_MASK    0x00000008
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_STREAM_STALL_HALT_DEFVAL  0x0
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_LOCK_STALL_HALT_LSB       2
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_LOCK_STALL_HALT_WIDTH     1
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_LOCK_STALL_HALT_MASK      0x00000004
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_LOCK_STALL_HALT_DEFVAL    0x0
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_MEMORY_STALL_HALT_LSB     1
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_MEMORY_STALL_HALT_WIDTH   1
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_MEMORY_STALL_HALT_MASK    0x00000002
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_MEMORY_STALL_HALT_DEFVAL  0x0
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_PC_EVENT_HALT_LSB         0
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_PC_EVENT_HALT_WIDTH       1
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_PC_EVENT_HALT_MASK        0x00000001
#define XAIEMLGBL_CORE_MODULE_DEBUG_CONTROL2_PC_EVENT_HALT_DEFVAL      0x0

#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS                               0x0003201C
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_WIDTH                         32
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_MASK                          0x0000007F
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_DEBUG_EVENT1_HALTED_LSB     6
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_DEBUG_EVENT1_HALTED_WIDTH   1
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_DEBUG_EVENT1_HALTED_MASK    0x00000040
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_DEBUG_EVENT1_HALTED_DEFVAL  0x0
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_DEBUG_EVENT0_HALTED_LSB     5
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_DEBUG_EVENT0_HALTED_WIDTH   1
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_DEBUG_EVENT0_HALTED_MASK    0x00000020
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_DEBUG_EVENT0_HALTED_DEFVAL  0x0
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_STREAM_STALL_HALTED_LSB     4
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_STREAM_STALL_HALTED_WIDTH   1
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_STREAM_STALL_HALTED_MASK    0x00000010
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_STREAM_STALL_HALTED_DEFVAL  0x0
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_LOCK_STALL_HALTED_LSB       3
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_LOCK_STALL_HALTED_WIDTH     1
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_LOCK_STALL_HALTED_MASK      0x00000008
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_LOCK_STALL_HALTED_DEFVAL    0x0
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_MEMORY_STALL_HALTED_LSB     2
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_MEMORY_STALL_HALTED_WIDTH   1
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_MEMORY_STALL_HALTED_MASK    0x00000004
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_MEMORY_STALL_HALTED_DEFVAL  0x0
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_PC_EVENT_HALTED_LSB         1
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_PC_EVENT_HALTED_WIDTH       1
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_PC_EVENT_HALTED_MASK        0x00000002
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_PC_EVENT_HALTED_DEFVAL      0x0
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_DEBUG_HALTED_LSB            0
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_DEBUG_HALTED_WIDTH          1
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_DEBUG_HALTED_MASK           0x00000001
#define XAIEMLGBL_CORE_MODULE_DEBUG_STATUS_DEBUG_HALTED_DEFVAL         0x0

#define XAIEMLGBL_CORE_MODULE_PC_EVENT0                                  0x00032020
#define XAIEMLGBL_CORE_MODULE_PC_EVENT0_WIDTH                            32
#define XAIEMLGBL_CORE_MODULE_PC_EVENT0_MASK                             0x80003FFF
#define XAIEMLGBL_CORE_MODULE_PC_EVENT0_VALID_LSB                      31
#define XAIEMLGBL_CORE_MODULE_PC_EVENT0_VALID_WIDTH                    1
#define XAIEMLGBL_CORE_MODULE_PC_EVENT0_VALID_MASK                     0x80000000
#define XAIEMLGBL_CORE_MODULE_PC_EVENT0_VALID_DEFVAL                   0x0
#define XAIEMLGBL_CORE_MODULE_PC_EVENT0_PC_ADDRESS_LSB                 0
#define XAIEMLGBL_CORE_MODULE_PC_EVENT0_PC_ADDRESS_WIDTH               14
#define XAIEMLGBL_CORE_MODULE_PC_EVENT0_PC_ADDRESS_MASK                0x00003FFF
#define XAIEMLGBL_CORE_MODULE_PC_EVENT0_PC_ADDRESS_DEFVAL              0x0

#define XAIEMLGBL_CORE_MODULE_PC_EVENT1                                  0x00032024
#define XAIEMLGBL_CORE_MODULE_PC_EVENT1_WIDTH                            32
#define XAIEMLGBL_CORE_MODULE_PC_EVENT1_MASK                             0x80003FFF
#define XAIEMLGBL_CORE_MODULE_PC_EVENT1_VALID_LSB                      31
#define XAIEMLGBL_CORE_MODULE_PC_EVENT1_VALID_WIDTH                    1
#define XAIEMLGBL_CORE_MODULE_PC_EVENT1_VALID_MASK                     0x80000000
#define XAIEMLGBL_CORE_MODULE_PC_EVENT1_VALID_DEFVAL                   0x0
#define XAIEMLGBL_CORE_MODULE_PC_EVENT1_PC_ADDRESS_LSB                 0
#define XAIEMLGBL_CORE_MODULE_PC_EVENT1_PC_ADDRESS_WIDTH               14
#define XAIEMLGBL_CORE_MODULE_PC_EVENT1_PC_ADDRESS_MASK                0x00003FFF
#define XAIEMLGBL_CORE_MODULE_PC_EVENT1_PC_ADDRESS_DEFVAL              0x0

#define XAIEMLGBL_CORE_MODULE_PC_EVENT2                                  0x00032028
#define XAIEMLGBL_CORE_MODULE_PC_EVENT2_WIDTH                            32
#define XAIEMLGBL_CORE_MODULE_PC_EVENT2_MASK                             0x80003FFF
#define XAIEMLGBL_CORE_MODULE_PC_EVENT2_VALID_LSB                      31
#define XAIEMLGBL_CORE_MODULE_PC_EVENT2_VALID_WIDTH                    1
#define XAIEMLGBL_CORE_MODULE_PC_EVENT2_VALID_MASK                     0x80000000
#define XAIEMLGBL_CORE_MODULE_PC_EVENT2_VALID_DEFVAL                   0x0
#define XAIEMLGBL_CORE_MODULE_PC_EVENT2_PC_ADDRESS_LSB                 0
#define XAIEMLGBL_CORE_MODULE_PC_EVENT2_PC_ADDRESS_WIDTH               14
#define XAIEMLGBL_CORE_MODULE_PC_EVENT2_PC_ADDRESS_MASK                0x00003FFF
#define XAIEMLGBL_CORE_MODULE_PC_EVENT2_PC_ADDRESS_DEFVAL              0x0

#define XAIEMLGBL_CORE_MODULE_PC_EVENT3                                  0x0003202C
#define XAIEMLGBL_CORE_MODULE_PC_EVENT3_WIDTH                            32
#define XAIEMLGBL_CORE_MODULE_PC_EVENT3_MASK                             0x80003FFF
#define XAIEMLGBL_CORE_MODULE_PC_EVENT3_VALID_LSB                      31
#define XAIEMLGBL_CORE_MODULE_PC_EVENT3_VALID_WIDTH                    1
#define XAIEMLGBL_CORE_MODULE_PC_EVENT3_VALID_MASK                     0x80000000
#define XAIEMLGBL_CORE_MODULE_PC_EVENT3_VALID_DEFVAL                   0x0
#define XAIEMLGBL_CORE_MODULE_PC_EVENT3_PC_ADDRESS_LSB                 0
#define XAIEMLGBL_CORE_MODULE_PC_EVENT3_PC_ADDRESS_WIDTH               14
#define XAIEMLGBL_CORE_MODULE_PC_EVENT3_PC_ADDRESS_MASK                0x00003FFF
#define XAIEMLGBL_CORE_MODULE_PC_EVENT3_PC_ADDRESS_DEFVAL              0x0

#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_CONTROL                         0x00032030
#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_CONTROL_WIDTH                   32
#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_CONTROL_MASK                    0x00000001
#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_CONTROL_ERROR_HALT_LSB        0
#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_CONTROL_ERROR_HALT_WIDTH      1
#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_CONTROL_ERROR_HALT_MASK       0x00000001
#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_CONTROL_ERROR_HALT_DEFVAL     0x0

#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_EVENT                           0x00032034
#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_EVENT_WIDTH                     32
#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_EVENT_MASK                      0x0000007F
#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_EVENT_ERROR_HALT_CORE_EVENT_LSB 0
#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_EVENT_ERROR_HALT_CORE_EVENT_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_EVENT_ERROR_HALT_CORE_EVENT_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_ERROR_HALT_EVENT_ERROR_HALT_CORE_EVENT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_CORE_PROCESSOR_BUS                         0x00032038
#define XAIEMLGBL_CORE_MODULE_CORE_PROCESSOR_BUS_WIDTH                   32
#define XAIEMLGBL_CORE_MODULE_CORE_PROCESSOR_BUS_MASK                    0x00000005
#define XAIEMLGBL_CORE_MODULE_CORE_PROCESSOR_BUS_SLVERR_ON_ACCESS_LSB  2
#define XAIEMLGBL_CORE_MODULE_CORE_PROCESSOR_BUS_SLVERR_ON_ACCESS_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_CORE_PROCESSOR_BUS_SLVERR_ON_ACCESS_MASK 0x00000004
#define XAIEMLGBL_CORE_MODULE_CORE_PROCESSOR_BUS_SLVERR_ON_ACCESS_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_CORE_PROCESSOR_BUS_ENABLE_LSB            0
#define XAIEMLGBL_CORE_MODULE_CORE_PROCESSOR_BUS_ENABLE_WIDTH          1
#define XAIEMLGBL_CORE_MODULE_CORE_PROCESSOR_BUS_ENABLE_MASK           0x00000001
#define XAIEMLGBL_CORE_MODULE_CORE_PROCESSOR_BUS_ENABLE_DEFVAL         0x0

#define XAIEMLGBL_CORE_MODULE_ECC_CONTROL                                0x00032100
#define XAIEMLGBL_CORE_MODULE_ECC_CONTROL_WIDTH                          32
#define XAIEMLGBL_CORE_MODULE_ECC_CONTROL_MASK                           0x00000003
#define XAIEMLGBL_CORE_MODULE_ECC_CONTROL_UNSTALL_CORE_LSB             1
#define XAIEMLGBL_CORE_MODULE_ECC_CONTROL_UNSTALL_CORE_WIDTH           1
#define XAIEMLGBL_CORE_MODULE_ECC_CONTROL_UNSTALL_CORE_MASK            0x00000002
#define XAIEMLGBL_CORE_MODULE_ECC_CONTROL_UNSTALL_CORE_DEFVAL          0x0
#define XAIEMLGBL_CORE_MODULE_ECC_CONTROL_STALL_CORE_CONTROL_LSB       0
#define XAIEMLGBL_CORE_MODULE_ECC_CONTROL_STALL_CORE_CONTROL_WIDTH     1
#define XAIEMLGBL_CORE_MODULE_ECC_CONTROL_STALL_CORE_CONTROL_MASK      0x00000001
#define XAIEMLGBL_CORE_MODULE_ECC_CONTROL_STALL_CORE_CONTROL_DEFVAL    0x0

#define XAIEMLGBL_CORE_MODULE_ECC_SCRUBBING_EVENT                        0x00032110
#define XAIEMLGBL_CORE_MODULE_ECC_SCRUBBING_EVENT_WIDTH                  32
#define XAIEMLGBL_CORE_MODULE_ECC_SCRUBBING_EVENT_MASK                   0x0000007F
#define XAIEMLGBL_CORE_MODULE_ECC_SCRUBBING_EVENT_SCRUBBING_EVENT_NUMBER_LSB 0
#define XAIEMLGBL_CORE_MODULE_ECC_SCRUBBING_EVENT_SCRUBBING_EVENT_NUMBER_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_ECC_SCRUBBING_EVENT_SCRUBBING_EVENT_NUMBER_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_ECC_SCRUBBING_EVENT_SCRUBBING_EVENT_NUMBER_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS                        0x00032120
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_WIDTH                  32
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_MASK                   0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_CLEAR_FAILING_ADDRESS_LSB 15
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_CLEAR_FAILING_ADDRESS_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_CLEAR_FAILING_ADDRESS_MASK 0x00008000
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_CLEAR_FAILING_ADDRESS_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_ACCESS_TYPE_LSB      14
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_ACCESS_TYPE_WIDTH    1
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_ACCESS_TYPE_MASK     0x00004000
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_ACCESS_TYPE_DEFVAL   0x0
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_ECC_ERROR_DETECTION_ADDRESS_LSB 0
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_ECC_ERROR_DETECTION_ADDRESS_WIDTH 14
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_ECC_ERROR_DETECTION_ADDRESS_MASK 0x00003FFF
#define XAIEMLGBL_CORE_MODULE_ECC_FAILING_ADDRESS_ECC_ERROR_DETECTION_ADDRESS_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_TIMER_CONTROL                              0x00034000
#define XAIEMLGBL_CORE_MODULE_TIMER_CONTROL_WIDTH                        32
#define XAIEMLGBL_CORE_MODULE_TIMER_CONTROL_MASK                         0x80007F00
#define XAIEMLGBL_CORE_MODULE_TIMER_CONTROL_RESET_LSB                  31
#define XAIEMLGBL_CORE_MODULE_TIMER_CONTROL_RESET_WIDTH                1
#define XAIEMLGBL_CORE_MODULE_TIMER_CONTROL_RESET_MASK                 0x80000000
#define XAIEMLGBL_CORE_MODULE_TIMER_CONTROL_RESET_DEFVAL               0x0
#define XAIEMLGBL_CORE_MODULE_TIMER_CONTROL_RESET_EVENT_LSB            8
#define XAIEMLGBL_CORE_MODULE_TIMER_CONTROL_RESET_EVENT_WIDTH          7
#define XAIEMLGBL_CORE_MODULE_TIMER_CONTROL_RESET_EVENT_MASK           0x00007F00
#define XAIEMLGBL_CORE_MODULE_TIMER_CONTROL_RESET_EVENT_DEFVAL         0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_GENERATE                             0x00034008
#define XAIEMLGBL_CORE_MODULE_EVENT_GENERATE_WIDTH                       32
#define XAIEMLGBL_CORE_MODULE_EVENT_GENERATE_MASK                        0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_GENERATE_EVENT_LSB                 0
#define XAIEMLGBL_CORE_MODULE_EVENT_GENERATE_EVENT_WIDTH               7
#define XAIEMLGBL_CORE_MODULE_EVENT_GENERATE_EVENT_MASK                0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_GENERATE_EVENT_DEFVAL              0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST0                           0x00034010
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST0_WIDTH                     32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST0_MASK                      0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST0_EVENT_LSB               0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST0_EVENT_WIDTH             7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST0_EVENT_MASK              0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST0_EVENT_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST1                           0x00034014
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST1_WIDTH                     32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST1_MASK                      0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST1_EVENT_LSB               0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST1_EVENT_WIDTH             7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST1_EVENT_MASK              0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST1_EVENT_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST2                           0x00034018
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST2_WIDTH                     32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST2_MASK                      0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST2_EVENT_LSB               0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST2_EVENT_WIDTH             7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST2_EVENT_MASK              0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST2_EVENT_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST3                           0x0003401C
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST3_WIDTH                     32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST3_MASK                      0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST3_EVENT_LSB               0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST3_EVENT_WIDTH             7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST3_EVENT_MASK              0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST3_EVENT_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST4                           0x00034020
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST4_WIDTH                     32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST4_MASK                      0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST4_EVENT_LSB               0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST4_EVENT_WIDTH             7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST4_EVENT_MASK              0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST4_EVENT_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST5                           0x00034024
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST5_WIDTH                     32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST5_MASK                      0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST5_EVENT_LSB               0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST5_EVENT_WIDTH             7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST5_EVENT_MASK              0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST5_EVENT_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST6                           0x00034028
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST6_WIDTH                     32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST6_MASK                      0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST6_EVENT_LSB               0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST6_EVENT_WIDTH             7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST6_EVENT_MASK              0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST6_EVENT_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST7                           0x0003402C
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST7_WIDTH                     32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST7_MASK                      0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST7_EVENT_LSB               0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST7_EVENT_WIDTH             7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST7_EVENT_MASK              0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST7_EVENT_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST8                           0x00034030
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST8_WIDTH                     32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST8_MASK                      0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST8_EVENT_LSB               0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST8_EVENT_WIDTH             7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST8_EVENT_MASK              0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST8_EVENT_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST9                           0x00034034
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST9_WIDTH                     32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST9_MASK                      0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST9_EVENT_LSB               0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST9_EVENT_WIDTH             7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST9_EVENT_MASK              0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST9_EVENT_DEFVAL            0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST10                          0x00034038
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST10_WIDTH                    32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST10_MASK                     0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST10_EVENT_LSB              0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST10_EVENT_WIDTH            7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST10_EVENT_MASK             0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST10_EVENT_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST11                          0x0003403C
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST11_WIDTH                    32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST11_MASK                     0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST11_EVENT_LSB              0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST11_EVENT_WIDTH            7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST11_EVENT_MASK             0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST11_EVENT_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST12                          0x00034040
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST12_WIDTH                    32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST12_MASK                     0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST12_EVENT_LSB              0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST12_EVENT_WIDTH            7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST12_EVENT_MASK             0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST12_EVENT_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST13                          0x00034044
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST13_WIDTH                    32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST13_MASK                     0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST13_EVENT_LSB              0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST13_EVENT_WIDTH            7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST13_EVENT_MASK             0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST13_EVENT_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST14                          0x00034048
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST14_WIDTH                    32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST14_MASK                     0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST14_EVENT_LSB              0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST14_EVENT_WIDTH            7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST14_EVENT_MASK             0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST14_EVENT_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST15                          0x0003404C
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST15_WIDTH                    32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST15_MASK                     0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST15_EVENT_LSB              0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST15_EVENT_WIDTH            7
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST15_EVENT_MASK             0x0000007F
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST15_EVENT_DEFVAL           0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET            0x00034050
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET_WIDTH      32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET_MASK       0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET_SET_LSB  0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET_SET_WIDTH 16
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR            0x00034054
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR_WIDTH      32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR_MASK       0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR_CLEAR_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE          0x00034058
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE_MASK     0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE_VALUE_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET             0x00034060
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET_WIDTH       32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET_MASK        0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET_SET_LSB   0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET_SET_WIDTH 16
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET_SET_MASK  0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR             0x00034064
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR_WIDTH       32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR_MASK        0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR_CLEAR_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE           0x00034068
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE_MASK      0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE_VALUE_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET            0x00034070
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET_WIDTH      32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET_MASK       0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET_SET_LSB  0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET_SET_WIDTH 16
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR            0x00034074
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR_WIDTH      32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR_MASK       0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR_CLEAR_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE          0x00034078
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE_MASK     0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE_VALUE_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET             0x00034080
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET_WIDTH       32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET_MASK        0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET_SET_LSB   0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET_SET_WIDTH 16
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET_SET_MASK  0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR             0x00034084
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR_WIDTH       32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR_MASK        0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR_CLEAR_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE           0x00034088
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE_MASK      0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE_VALUE_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0                             0x000340D0
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_WIDTH                       32
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_MASK                        0x7F7F0003
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_LSB      24
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_WIDTH    7
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_MASK     0x7F000000
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_DEFVAL   0x0
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_LSB     16
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_WIDTH   7
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_MASK    0x007F0000
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_DEFVAL  0x0
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_MODE_LSB                  0
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_MODE_WIDTH                2
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_MODE_MASK                 0x00000003
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL0_MODE_DEFVAL               0x0

#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL1                             0x000340D4
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL1_WIDTH                       32
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL1_MASK                        0x0000701F
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL1_PACKET_TYPE_LSB           12
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL1_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL1_PACKET_TYPE_MASK          0x00007000
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL1_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL1_ID_LSB                    0
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL1_ID_WIDTH                  5
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL1_ID_MASK                   0x0000001F
#define XAIEMLGBL_CORE_MODULE_TRACE_CONTROL1_ID_DEFVAL                 0x0

#define XAIEMLGBL_CORE_MODULE_TRACE_STATUS                               0x000340D8
#define XAIEMLGBL_CORE_MODULE_TRACE_STATUS_WIDTH                         32
#define XAIEMLGBL_CORE_MODULE_TRACE_STATUS_MASK                          0x00000307
#define XAIEMLGBL_CORE_MODULE_TRACE_STATUS_STATE_LSB                   8
#define XAIEMLGBL_CORE_MODULE_TRACE_STATUS_STATE_WIDTH                 2
#define XAIEMLGBL_CORE_MODULE_TRACE_STATUS_STATE_MASK                  0x00000300
#define XAIEMLGBL_CORE_MODULE_TRACE_STATUS_STATE_DEFVAL                0x0
#define XAIEMLGBL_CORE_MODULE_TRACE_STATUS_MODE_LSB                    0
#define XAIEMLGBL_CORE_MODULE_TRACE_STATUS_MODE_WIDTH                  3
#define XAIEMLGBL_CORE_MODULE_TRACE_STATUS_MODE_MASK                   0x00000007
#define XAIEMLGBL_CORE_MODULE_TRACE_STATUS_MODE_DEFVAL                 0x0

#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0                               0x000340E0
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_WIDTH                         32
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_MASK                          0x7F7F7F7F
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT3_LSB            24
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT3_WIDTH          7
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT3_MASK           0x7F000000
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT3_DEFVAL         0x0
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT2_LSB            16
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT2_WIDTH          7
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT2_MASK           0x007F0000
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT2_DEFVAL         0x0
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT1_LSB            8
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT1_WIDTH          7
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT1_MASK           0x00007F00
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT1_DEFVAL         0x0
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT0_LSB            0
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT0_WIDTH          7
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT0_MASK           0x0000007F
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT0_TRACE_EVENT0_DEFVAL         0x0

#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1                               0x000340E4
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_WIDTH                         32
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_MASK                          0x7F7F7F7F
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT7_LSB            24
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT7_WIDTH          7
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT7_MASK           0x7F000000
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT7_DEFVAL         0x0
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT6_LSB            16
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT6_WIDTH          7
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT6_MASK           0x007F0000
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT6_DEFVAL         0x0
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT5_LSB            8
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT5_WIDTH          7
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT5_MASK           0x00007F00
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT5_DEFVAL         0x0
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT4_LSB            0
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT4_WIDTH          7
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT4_MASK           0x0000007F
#define XAIEMLGBL_CORE_MODULE_TRACE_EVENT1_TRACE_EVENT4_DEFVAL         0x0

#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE                 0x000340F0
#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_WIDTH           32
#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_MASK            0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_LSB 0
#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_MASK 0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_DEFVAL 0xFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE                0x000340F4
#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_WIDTH          32
#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_MASK           0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_LSB 0
#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_MASK 0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_DEFVAL 0xFFFFFFFF

#define XAIEMLGBL_CORE_MODULE_TIMER_LOW                                  0x000340F8
#define XAIEMLGBL_CORE_MODULE_TIMER_LOW_WIDTH                            32
#define XAIEMLGBL_CORE_MODULE_TIMER_LOW_MASK                             0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_TIMER_LOW_TIMERLOW_LSB                   0
#define XAIEMLGBL_CORE_MODULE_TIMER_LOW_TIMERLOW_WIDTH                 32
#define XAIEMLGBL_CORE_MODULE_TIMER_LOW_TIMERLOW_MASK                  0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_TIMER_LOW_TIMERLOW_DEFVAL                0x0

#define XAIEMLGBL_CORE_MODULE_TIMER_HIGH                                 0x000340FC
#define XAIEMLGBL_CORE_MODULE_TIMER_HIGH_WIDTH                           32
#define XAIEMLGBL_CORE_MODULE_TIMER_HIGH_MASK                            0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_TIMER_HIGH_TIMERHIGH_LSB                 0
#define XAIEMLGBL_CORE_MODULE_TIMER_HIGH_TIMERHIGH_WIDTH               32
#define XAIEMLGBL_CORE_MODULE_TIMER_HIGH_TIMERHIGH_MASK                0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_TIMER_HIGH_TIMERHIGH_DEFVAL              0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS0                              0x00034200
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS0_WIDTH                        32
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS0_MASK                         0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_LSB      0
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_MASK     0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_DEFVAL   0x2

#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS1                              0x00034204
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS1_WIDTH                        32
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS1_MASK                         0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_LSB     0
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_MASK    0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_DEFVAL  0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS2                              0x00034208
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS2_WIDTH                        32
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS2_MASK                         0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_LSB     0
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_MASK    0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_DEFVAL  0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS3                              0x0003420C
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS3_WIDTH                        32
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS3_MASK                         0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_LSB    0
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_MASK   0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS                         0x00034400
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_WIDTH                   32
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_MASK                    0x7F7F7F7F
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTD_LSB            24
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTD_WIDTH          7
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTD_MASK           0x7F000000
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTD_DEFVAL         0x0
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTC_LSB            16
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTC_WIDTH          7
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTC_MASK           0x007F0000
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTC_DEFVAL         0x0
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTB_LSB            8
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTB_WIDTH          7
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTB_MASK           0x00007F00
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTB_DEFVAL         0x0
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTA_LSB            0
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTA_WIDTH          7
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTA_MASK           0x0000007F
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_INPUTS_EVENTA_DEFVAL         0x0

#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL                        0x00034404
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_WIDTH                  32
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_MASK                   0x00030303
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_COMBO2_LSB           16
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_COMBO2_WIDTH         2
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_COMBO2_MASK          0x00030000
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_COMBO2_DEFVAL        0x0
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_COMBO1_LSB           8
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_COMBO1_WIDTH         2
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_COMBO1_MASK          0x00000300
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_COMBO1_DEFVAL        0x0
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_COMBO0_LSB           0
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_COMBO0_WIDTH         2
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_COMBO0_MASK          0x00000003
#define XAIEMLGBL_CORE_MODULE_COMBO_EVENT_CONTROL_COMBO0_DEFVAL        0x0

#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL               0x00034408
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_WIDTH         32
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_MASK          0x067F067F
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_LSB 26
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_MASK 0x04000000
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_LSB 25
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_MASK 0x02000000
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_LSB 16
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_MASK 0x007F0000
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_LSB 10
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_MASK 0x00000400
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_LSB 9
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_MASK 0x00000200
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_LSB 0
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE                       0x00034500
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_WIDTH                 32
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_MASK                  0x00000FFF
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_LSB 11
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_MASK 0x00000800
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_LSB 10
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_MASK 0x00000400
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_LSB   9
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_MASK  0x00000200
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_LSB   8
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_MASK  0x00000100
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_LSB   7
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_MASK  0x00000080
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_LSB   6
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_MASK  0x00000040
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT3_LSB       5
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT3_WIDTH     1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT3_MASK      0x00000020
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT3_DEFVAL    0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT2_LSB       4
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT2_WIDTH     1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT2_MASK      0x00000010
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT2_DEFVAL    0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_LSB       3
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_WIDTH     1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_MASK      0x00000008
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_DEFVAL    0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_LSB       2
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_WIDTH     1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_MASK      0x00000004
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_DEFVAL    0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_LSB 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_MASK 0x00000002
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_LSB      0
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_WIDTH    1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_MASK     0x00000001
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_DEFVAL   0x1

#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE                      0x00034504
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_WIDTH                32
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_MASK                 0x0000003F
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_RANGE_2_3_LSB   5
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_RANGE_2_3_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_RANGE_2_3_MASK  0x00000020
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_RANGE_2_3_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_RANGE_0_1_LSB   4
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_RANGE_0_1_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_RANGE_0_1_MASK  0x00000010
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_RANGE_0_1_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_3_LSB           3
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_3_WIDTH         1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_3_MASK          0x00000008
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_3_DEFVAL        0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_2_LSB           2
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_2_WIDTH         1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_2_MASK          0x00000004
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_2_DEFVAL        0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_1_LSB           1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_1_WIDTH         1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_1_MASK          0x00000002
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_1_DEFVAL        0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_0_LSB           0
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_0_WIDTH         1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_0_MASK          0x00000001
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_PC_ENABLE_PC_0_DEFVAL        0x1

#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE              0x00034508
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_WIDTH        32
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_MASK         0x000001FF
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_ECC_ERROR_STALL_LSB 8
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_ECC_ERROR_STALL_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_ECC_ERROR_STALL_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_ECC_ERROR_STALL_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_ECC_SCRUBBING_STALL_LSB 7
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_ECC_SCRUBBING_STALL_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_ECC_SCRUBBING_STALL_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_ECC_SCRUBBING_STALL_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_DISABLE_LSB 6
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_DISABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_DISABLE_MASK 0x00000040
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_DISABLE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_ACTIVE_LSB 5
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_ACTIVE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_ACTIVE_MASK 0x00000020
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_ACTIVE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_DEBUG_LSB  4
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_DEBUG_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_DEBUG_MASK 0x00000010
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_DEBUG_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_LOCK_STALL_LSB 3
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_LOCK_STALL_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_LOCK_STALL_MASK 0x00000008
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_LOCK_STALL_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_CASCADE_STALL_LSB 2
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_CASCADE_STALL_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_CASCADE_STALL_MASK 0x00000004
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_CASCADE_STALL_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_STREAM_STALL_LSB 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_STREAM_STALL_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_STREAM_STALL_MASK 0x00000002
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_STREAM_STALL_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_MEMORY_STALL_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_MEMORY_STALL_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_MEMORY_STALL_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_STALL_ENABLE_MEMORY_STALL_DEFVAL 0x1

#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE       0x0003450C
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_MASK  0x00001FFF
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_LOCK_RELEASE_REQ_LSB 12
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_LOCK_RELEASE_REQ_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_LOCK_RELEASE_REQ_MASK 0x00001000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_LOCK_RELEASE_REQ_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_LOCK_ACQUIRE_REQ_LSB 11
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_LOCK_ACQUIRE_REQ_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_LOCK_ACQUIRE_REQ_MASK 0x00000800
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_LOCK_ACQUIRE_REQ_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_CASCADE_PUT_LSB 10
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_CASCADE_PUT_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_CASCADE_PUT_MASK 0x00000400
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_CASCADE_PUT_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_CASCADE_GET_LSB 9
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_CASCADE_GET_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_CASCADE_GET_MASK 0x00000200
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_CASCADE_GET_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_STREAM_PUT_LSB 8
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_STREAM_PUT_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_STREAM_PUT_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_STREAM_PUT_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_STREAM_GET_LSB 7
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_STREAM_GET_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_STREAM_GET_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_STREAM_GET_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_STORE_LSB 6
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_STORE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_STORE_MASK 0x00000040
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_STORE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_LOAD_LSB 5
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_LOAD_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_LOAD_MASK 0x00000020
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_LOAD_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_VECTOR_LSB 4
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_VECTOR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_VECTOR_MASK 0x00000010
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_VECTOR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_RETURN_LSB 3
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_RETURN_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_RETURN_MASK 0x00000008
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_RETURN_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_CALL_LSB 2
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_CALL_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_CALL_MASK 0x00000004
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_CALL_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_EVENT_1_LSB 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_EVENT_1_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_EVENT_1_MASK 0x00000002
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_EVENT_1_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_EVENT_0_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_EVENT_0_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_EVENT_0_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_CORE_PROGRAM_FLOW_ENABLE_INSTR_EVENT_0_DEFVAL 0x1

#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE                 0x00034510
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_WIDTH           32
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_MASK            0x01FFFFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PROCESSOR_BUS_ERROR_LSB 24
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PROCESSOR_BUS_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PROCESSOR_BUS_ERROR_MASK 0x01000000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PROCESSOR_BUS_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_LSB 23
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_MASK 0x00800000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_DECOMPRESSION_UNDERFLOW_LSB 22
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_DECOMPRESSION_UNDERFLOW_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_DECOMPRESSION_UNDERFLOW_MASK 0x00400000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_DECOMPRESSION_UNDERFLOW_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INSTR_ERROR_LSB 21
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INSTR_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INSTR_ERROR_MASK 0x00200000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INSTR_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INSTR_WARNING_LSB 20
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INSTR_WARNING_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INSTR_WARNING_MASK 0x00100000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INSTR_WARNING_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_LOCK_ACCESS_TO_UNAVAILABLE_LSB 19
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00080000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_DM_ACCESS_TO_UNAVAILABLE_LSB 18
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00040000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ADDRESS_OUT_OF_RANGE_LSB 17
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ADDRESS_OUT_OF_RANGE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ADDRESS_OUT_OF_RANGE_MASK 0x00020000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ADDRESS_OUT_OF_RANGE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_2BIT_LSB 16
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_2BIT_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_2BIT_MASK 0x00010000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_2BIT_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_1BIT_LSB 15
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_1BIT_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_1BIT_MASK 0x00008000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_1BIT_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_SCRUB_2BIT_LSB 14
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_SCRUB_2BIT_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_SCRUB_2BIT_MASK 0x00004000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_SCRUB_2BIT_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_SCRUB_CORRECTED_LSB 13
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_SCRUB_CORRECTED_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_SCRUB_CORRECTED_MASK 0x00002000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_ECC_ERROR_SCRUB_CORRECTED_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_DM_ADDRESS_OUT_OF_RANGE_LSB 12
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_DM_ADDRESS_OUT_OF_RANGE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_DM_ADDRESS_OUT_OF_RANGE_MASK 0x00001000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_DM_ADDRESS_OUT_OF_RANGE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INSTRUCTION_DECOMPRESSION_ERROR_LSB 11
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INSTRUCTION_DECOMPRESSION_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INSTRUCTION_DECOMPRESSION_ERROR_MASK 0x00000800
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INSTRUCTION_DECOMPRESSION_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_AXI_MM_SLAVE_ERROR_LSB 10
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_AXI_MM_SLAVE_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_AXI_MM_SLAVE_ERROR_MASK 0x00000400
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_AXI_MM_SLAVE_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_CONTROL_PKT_ERROR_LSB 9
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_CONTROL_PKT_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_CONTROL_PKT_ERROR_MASK 0x00000200
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_CONTROL_PKT_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_STREAM_PKT_PARITY_ERROR_LSB 8
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_STREAM_PKT_PARITY_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_STREAM_PKT_PARITY_ERROR_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_STREAM_PKT_PARITY_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_REG_ACCESS_FAILURE_LSB 7
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_REG_ACCESS_FAILURE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_REG_ACCESS_FAILURE_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_PM_REG_ACCESS_FAILURE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_FP_INF_LSB    5
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_FP_INF_WIDTH  1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_FP_INF_MASK   0x00000020
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_FP_INF_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_FP_INVALID_LSB 4
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_FP_INVALID_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_FP_INVALID_MASK 0x00000010
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_FP_INVALID_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INT_FP_ZERO_LSB 3
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INT_FP_ZERO_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INT_FP_ZERO_MASK 0x00000008
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_INT_FP_ZERO_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_FP_HUGE_LSB   2
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_FP_HUGE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_FP_HUGE_MASK  0x00000004
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_FP_HUGE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_UPS_OVERFLOW_LSB 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_UPS_OVERFLOW_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_UPS_OVERFLOW_MASK 0x00000002
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_UPS_OVERFLOW_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_SRS_OVERFLOW_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_SRS_OVERFLOW_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_SRS_OVERFLOW_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS0_ENABLE_SRS_OVERFLOW_DEFVAL 0x1

#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE                 0x00034514
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_WIDTH           32
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_MASK            0x01FFFFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PROCESSOR_BUS_ERROR_LSB 24
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PROCESSOR_BUS_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PROCESSOR_BUS_ERROR_MASK 0x01000000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PROCESSOR_BUS_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_LSB 23
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_MASK 0x00800000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_DECOMPRESSION_UNDERFLOW_LSB 22
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_DECOMPRESSION_UNDERFLOW_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_DECOMPRESSION_UNDERFLOW_MASK 0x00400000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_DECOMPRESSION_UNDERFLOW_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INSTR_ERROR_LSB 21
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INSTR_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INSTR_ERROR_MASK 0x00200000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INSTR_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INSTR_WARNING_LSB 20
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INSTR_WARNING_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INSTR_WARNING_MASK 0x00100000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INSTR_WARNING_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_LOCK_ACCESS_TO_UNAVAILABLE_LSB 19
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00080000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_DM_ACCESS_TO_UNAVAILABLE_LSB 18
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00040000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ADDRESS_OUT_OF_RANGE_LSB 17
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ADDRESS_OUT_OF_RANGE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ADDRESS_OUT_OF_RANGE_MASK 0x00020000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ADDRESS_OUT_OF_RANGE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_2BIT_LSB 16
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_2BIT_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_2BIT_MASK 0x00010000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_2BIT_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_1BIT_LSB 15
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_1BIT_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_1BIT_MASK 0x00008000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_1BIT_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_SCRUB_2BIT_LSB 14
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_SCRUB_2BIT_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_SCRUB_2BIT_MASK 0x00004000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_SCRUB_2BIT_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_SCRUB_CORRECTED_LSB 13
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_SCRUB_CORRECTED_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_SCRUB_CORRECTED_MASK 0x00002000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_ECC_ERROR_SCRUB_CORRECTED_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_DM_ADDRESS_OUT_OF_RANGE_LSB 12
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_DM_ADDRESS_OUT_OF_RANGE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_DM_ADDRESS_OUT_OF_RANGE_MASK 0x00001000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_DM_ADDRESS_OUT_OF_RANGE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INSTRUCTION_DECOMPRESSION_ERROR_LSB 11
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INSTRUCTION_DECOMPRESSION_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INSTRUCTION_DECOMPRESSION_ERROR_MASK 0x00000800
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INSTRUCTION_DECOMPRESSION_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_AXI_MM_SLAVE_ERROR_LSB 10
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_AXI_MM_SLAVE_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_AXI_MM_SLAVE_ERROR_MASK 0x00000400
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_AXI_MM_SLAVE_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_CONTROL_PKT_ERROR_LSB 9
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_CONTROL_PKT_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_CONTROL_PKT_ERROR_MASK 0x00000200
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_CONTROL_PKT_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_STREAM_PKT_PARITY_ERROR_LSB 8
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_STREAM_PKT_PARITY_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_STREAM_PKT_PARITY_ERROR_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_STREAM_PKT_PARITY_ERROR_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_REG_ACCESS_FAILURE_LSB 7
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_REG_ACCESS_FAILURE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_REG_ACCESS_FAILURE_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_PM_REG_ACCESS_FAILURE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_FP_INF_LSB    5
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_FP_INF_WIDTH  1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_FP_INF_MASK   0x00000020
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_FP_INF_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_FP_INVALID_LSB 4
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_FP_INVALID_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_FP_INVALID_MASK 0x00000010
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_FP_INVALID_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INT_FP_ZERO_LSB 3
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INT_FP_ZERO_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INT_FP_ZERO_MASK 0x00000008
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_INT_FP_ZERO_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_FP_HUGE_LSB   2
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_FP_HUGE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_FP_HUGE_MASK  0x00000004
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_FP_HUGE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_UPS_OVERFLOW_LSB 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_UPS_OVERFLOW_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_UPS_OVERFLOW_MASK 0x00000002
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_UPS_OVERFLOW_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_SRS_OVERFLOW_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_SRS_OVERFLOW_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_SRS_OVERFLOW_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_ERRORS1_ENABLE_SRS_OVERFLOW_DEFVAL 0x1

#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE           0x00034518
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_MASK      0xFFFFFFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_7_LSB 31
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_7_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_7_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_7_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_7_LSB 30
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_7_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_7_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_7_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_7_LSB 29
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_7_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_7_MASK 0x20000000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_7_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_7_LSB 28
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_7_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_7_MASK 0x10000000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_7_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_6_LSB 27
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_6_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_6_MASK 0x08000000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_6_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_6_LSB 26
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_6_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_6_MASK 0x04000000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_6_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_6_LSB 25
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_6_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_6_MASK 0x02000000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_6_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_6_LSB 24
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_6_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_6_MASK 0x01000000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_6_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_5_LSB 23
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_5_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_5_MASK 0x00800000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_5_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_5_LSB 22
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_5_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_5_MASK 0x00400000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_5_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_5_LSB 21
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_5_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_5_MASK 0x00200000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_5_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_5_LSB 20
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_5_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_5_MASK 0x00100000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_5_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_4_LSB 19
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_4_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_4_MASK 0x00080000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_4_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_4_LSB 18
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_4_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_4_MASK 0x00040000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_4_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_4_LSB 17
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_4_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_4_MASK 0x00020000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_4_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_4_LSB 16
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_4_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_4_MASK 0x00010000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_4_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_3_LSB 15
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_3_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_3_MASK 0x00008000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_3_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_3_LSB 14
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_3_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_3_MASK 0x00004000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_3_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_3_LSB 13
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_3_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_3_MASK 0x00002000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_3_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_3_LSB 12
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_3_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_3_MASK 0x00001000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_3_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_2_LSB 11
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_2_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_2_MASK 0x00000800
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_2_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_2_LSB 10
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_2_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_2_MASK 0x00000400
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_2_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_2_LSB 9
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_2_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_2_MASK 0x00000200
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_2_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_2_LSB 8
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_2_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_2_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_2_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_1_LSB 7
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_1_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_1_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_1_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_1_LSB 6
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_1_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_1_MASK 0x00000040
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_1_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_1_LSB 5
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_1_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_1_MASK 0x00000020
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_1_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_1_LSB 4
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_1_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_1_MASK 0x00000010
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_1_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_0_LSB 3
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_0_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_0_MASK 0x00000008
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_0_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_0_LSB 2
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_0_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_0_MASK 0x00000004
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_0_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_0_LSB 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_0_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_0_MASK 0x00000002
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_0_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_0_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_0_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_0_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_0_DEFVAL 0x1

#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE               0x0003451C
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_WIDTH         32
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_MASK          0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_15_LSB 15
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_15_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_15_MASK 0x00008000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_15_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_14_LSB 14
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_14_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_14_MASK 0x00004000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_14_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_13_LSB 13
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_13_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_13_MASK 0x00002000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_13_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_12_LSB 12
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_12_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_12_MASK 0x00001000
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_12_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_11_LSB 11
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_11_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_11_MASK 0x00000800
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_11_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_10_LSB 10
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_10_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_10_MASK 0x00000400
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_10_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_9_LSB 9
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_9_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_9_MASK 0x00000200
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_9_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_8_LSB 8
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_8_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_8_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_8_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_7_LSB 7
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_7_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_7_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_7_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_6_LSB 6
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_6_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_6_MASK 0x00000040
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_6_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_5_LSB 5
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_5_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_5_MASK 0x00000020
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_5_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_4_LSB 4
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_4_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_4_MASK 0x00000010
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_4_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_3_LSB 3
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_3_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_3_MASK 0x00000008
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_3_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_2_LSB 2
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_2_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_2_MASK 0x00000004
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_2_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_1_LSB 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_1_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_1_MASK 0x00000002
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_1_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_0_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_0_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_0_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_0_DEFVAL 0x1

#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE              0x00034520
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_WIDTH        32
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_MASK         0x0000000F
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_3_LSB 3
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_3_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_3_MASK 0x00000008
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_3_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_2_LSB 2
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_2_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_2_MASK 0x00000004
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_2_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_1_LSB 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_1_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_1_MASK 0x00000002
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_1_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_0_LSB 0
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_0_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_0_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_0_DEFVAL 0x1

#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL                               0x00036030
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_WIDTH                         32
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_MASK                          0x0000000F
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_EAST_LSB       3
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_EAST_WIDTH     1
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_EAST_MASK      0x00000008
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_EAST_DEFVAL    0x0
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_NORTH_LSB      2
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_NORTH_WIDTH    1
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_NORTH_MASK     0x00000004
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_NORTH_DEFVAL   0x0
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_WEST_LSB       1
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_WEST_WIDTH     1
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_WEST_MASK      0x00000002
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_WEST_DEFVAL    0x0
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_SOUTH_LSB      0
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_SOUTH_WIDTH    1
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_SOUTH_MASK     0x00000001
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_ISOLATE_FROM_SOUTH_DEFVAL   0x0

#define XAIEMLGBL_CORE_MODULE_CSSD_TRIGGER                               0x00036040
#define XAIEMLGBL_CORE_MODULE_CSSD_TRIGGER_WIDTH                         32
#define XAIEMLGBL_CORE_MODULE_CSSD_TRIGGER_MASK                          0x00000001
#define XAIEMLGBL_CORE_MODULE_CSSD_TRIGGER_TRIGGER_LSB                 0
#define XAIEMLGBL_CORE_MODULE_CSSD_TRIGGER_TRIGGER_WIDTH               1
#define XAIEMLGBL_CORE_MODULE_CSSD_TRIGGER_TRIGGER_MASK                0x00000001
#define XAIEMLGBL_CORE_MODULE_CSSD_TRIGGER_TRIGGER_DEFVAL              0x0

#define XAIEMLGBL_CORE_MODULE_SPARE_REG                                  0x00036050
#define XAIEMLGBL_CORE_MODULE_SPARE_REG_WIDTH                            32
#define XAIEMLGBL_CORE_MODULE_SPARE_REG_MASK                             0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_SPARE_REG_SPARE_REG_LSB                  0
#define XAIEMLGBL_CORE_MODULE_SPARE_REG_SPARE_REG_WIDTH                16
#define XAIEMLGBL_CORE_MODULE_SPARE_REG_SPARE_REG_MASK                 0x0000FFFF
#define XAIEMLGBL_CORE_MODULE_SPARE_REG_SPARE_REG_DEFVAL               0x0

#define XAIEMLGBL_CORE_MODULE_ACCUMULATOR_CONTROL                        0x00036060
#define XAIEMLGBL_CORE_MODULE_ACCUMULATOR_CONTROL_WIDTH                  32
#define XAIEMLGBL_CORE_MODULE_ACCUMULATOR_CONTROL_MASK                   0x00000003
#define XAIEMLGBL_CORE_MODULE_ACCUMULATOR_CONTROL_OUTPUT_LSB           1
#define XAIEMLGBL_CORE_MODULE_ACCUMULATOR_CONTROL_OUTPUT_WIDTH         1
#define XAIEMLGBL_CORE_MODULE_ACCUMULATOR_CONTROL_OUTPUT_MASK          0x00000002
#define XAIEMLGBL_CORE_MODULE_ACCUMULATOR_CONTROL_OUTPUT_DEFVAL        0x0
#define XAIEMLGBL_CORE_MODULE_ACCUMULATOR_CONTROL_INPUT_LSB            0
#define XAIEMLGBL_CORE_MODULE_ACCUMULATOR_CONTROL_INPUT_WIDTH          1
#define XAIEMLGBL_CORE_MODULE_ACCUMULATOR_CONTROL_INPUT_MASK           0x00000001
#define XAIEMLGBL_CORE_MODULE_ACCUMULATOR_CONTROL_INPUT_DEFVAL         0x0

#define XAIEMLGBL_CORE_MODULE_MEMORY_CONTROL                             0x00036070
#define XAIEMLGBL_CORE_MODULE_MEMORY_CONTROL_WIDTH                       32
#define XAIEMLGBL_CORE_MODULE_MEMORY_CONTROL_MASK                        0x00000001
#define XAIEMLGBL_CORE_MODULE_MEMORY_CONTROL_MEMORY_ZEROISATION_LSB    0
#define XAIEMLGBL_CORE_MODULE_MEMORY_CONTROL_MEMORY_ZEROISATION_WIDTH  1
#define XAIEMLGBL_CORE_MODULE_MEMORY_CONTROL_MEMORY_ZEROISATION_MASK   0x00000001
#define XAIEMLGBL_CORE_MODULE_MEMORY_CONTROL_MEMORY_ZEROISATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0      0x0003F000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_MASK 0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_AIE_CORE0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0           0x0003F004
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_MASK      0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1           0x0003F008
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_MASK      0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL      0x0003F00C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASK 0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0          0x0003F010
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_MASK     0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0         0x0003F014
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASK    0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1         0x0003F018
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASK    0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2         0x0003F01C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASK    0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3         0x0003F020
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASK    0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0          0x0003F024
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_MASK     0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1          0x0003F028
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_MASK     0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2          0x0003F02C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_MASK     0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3          0x0003F030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_MASK     0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0         0x0003F034
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASK    0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1         0x0003F038
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASK    0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2         0x0003F03C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASK    0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3         0x0003F040
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASK    0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4         0x0003F044
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASK    0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5         0x0003F048
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASK    0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0          0x0003F04C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_MASK     0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1          0x0003F050
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_MASK     0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2          0x0003F054
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_MASK     0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3          0x0003F058
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_MASK     0xC00000FF
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_DROP_HEADER_LSB 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_CONFIGURATION_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_CORE0       0x0003F100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_CORE0_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_CORE0_MASK  0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_CORE0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_CORE0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_CORE0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_CORE0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_CORE0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_CORE0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_CORE0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_CORE0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0           0x0003F104
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_MASK      0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1           0x0003F108
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_MASK      0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL       0x0003F10C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_MASK  0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0          0x0003F110
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_MASK     0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0         0x0003F114
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_MASK    0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1         0x0003F118
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_MASK    0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2         0x0003F11C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_MASK    0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3         0x0003F120
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_MASK    0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4         0x0003F124
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_MASK    0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5         0x0003F128
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_MASK    0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0          0x0003F12C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_MASK     0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1          0x0003F130
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_MASK     0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2          0x0003F134
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_MASK     0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3          0x0003F138
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_MASK     0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0         0x0003F13C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_MASK    0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1         0x0003F140
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_MASK    0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2         0x0003F144
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_MASK    0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3         0x0003F148
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_MASK    0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0          0x0003F14C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_MASK     0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1          0x0003F150
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_MASK     0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2          0x0003F154
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_MASK     0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3          0x0003F158
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_MASK     0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_TRACE       0x0003F15C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_TRACE_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_TRACE_MASK  0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_TRACE_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_TRACE_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_TRACE_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_TRACE_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_TRACE_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_TRACE_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_TRACE_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_AIE_TRACE_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_MEM_TRACE       0x0003F160
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_MEM_TRACE_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_MEM_TRACE_MASK  0xC0000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_MEM_TRACE_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_MEM_TRACE_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_MEM_TRACE_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_MEM_TRACE_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_MEM_TRACE_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_MEM_TRACE_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_MEM_TRACE_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_MEM_TRACE_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0        0x0003F200
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1        0x0003F204
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2        0x0003F208
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3        0x0003F20C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_CORE0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0            0x0003F210
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_WIDTH      32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ID_LSB   24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1            0x0003F214
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_WIDTH      32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ID_LSB   24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2            0x0003F218
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_WIDTH      32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ID_LSB   24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3            0x0003F21C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_WIDTH      32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ID_LSB   24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0            0x0003F220
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_WIDTH      32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ID_LSB   24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1            0x0003F224
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_WIDTH      32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ID_LSB   24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2            0x0003F228
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_WIDTH      32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ID_LSB   24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3            0x0003F22C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_WIDTH      32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ID_LSB   24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0        0x0003F230
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1        0x0003F234
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2        0x0003F238
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3        0x0003F23C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0           0x0003F240
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1           0x0003F244
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2           0x0003F248
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3           0x0003F24C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0          0x0003F250
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1          0x0003F254
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2          0x0003F258
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3          0x0003F25C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0          0x0003F260
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1          0x0003F264
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2          0x0003F268
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3          0x0003F26C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0          0x0003F270
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1          0x0003F274
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2          0x0003F278
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3          0x0003F27C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0          0x0003F280
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1          0x0003F284
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2          0x0003F288
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3          0x0003F28C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0          0x0003F290
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1          0x0003F294
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2          0x0003F298
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3          0x0003F29C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0          0x0003F2A0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1          0x0003F2A4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2          0x0003F2A8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3          0x0003F2AC
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0           0x0003F2B0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1           0x0003F2B4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2           0x0003F2B8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3           0x0003F2BC
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0           0x0003F2C0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1           0x0003F2C4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2           0x0003F2C8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3           0x0003F2CC
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0           0x0003F2D0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1           0x0003F2D4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2           0x0003F2D8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3           0x0003F2DC
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0           0x0003F2E0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1           0x0003F2E4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2           0x0003F2E8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3           0x0003F2EC
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0          0x0003F2F0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1          0x0003F2F4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2          0x0003F2F8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3          0x0003F2FC
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0          0x0003F300
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1          0x0003F304
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2          0x0003F308
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3          0x0003F30C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0          0x0003F310
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1          0x0003F314
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2          0x0003F318
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3          0x0003F31C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0          0x0003F320
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1          0x0003F324
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2          0x0003F328
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3          0x0003F32C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_WIDTH    32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK     0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0           0x0003F330
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1           0x0003F334
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2           0x0003F338
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3           0x0003F33C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0           0x0003F340
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1           0x0003F344
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2           0x0003F348
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3           0x0003F34C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0           0x0003F350
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1           0x0003F354
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2           0x0003F358
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3           0x0003F35C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0           0x0003F360
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1           0x0003F364
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2           0x0003F368
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3           0x0003F36C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_WIDTH     32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MASK      0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ID_LSB  24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0        0x0003F370
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1        0x0003F374
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2        0x0003F378
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3        0x0003F37C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_AIE_TRACE_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0        0x0003F380
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1        0x0003F384
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2        0x0003F388
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3        0x0003F38C
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_WIDTH  32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_MASK   0x1F1F0137
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_MASK_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_SLAVE_MEM_TRACE_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1 0x0003F800
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_MASK 0x3F1F3F1F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_1_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_1_WIDTH 6
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_1_MASK 0x3F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_1_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_1_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_1_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_1_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_1_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_0_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_0_WIDTH 6
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_0_MASK 0x00003F00
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_0_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_0_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_0_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_0_MASK 0x0000001F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_0_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3 0x0003F804
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_MASK 0x3F1F3F1F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_3_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_3_WIDTH 6
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_3_MASK 0x3F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_3_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_3_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_3_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_3_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_3_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_2_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_2_WIDTH 6
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_2_MASK 0x00003F00
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_2_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_2_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_2_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_2_MASK 0x0000001F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_2_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL 0x0003F808
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_ENABLE_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_ENABLE_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1 0x0003F810
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_MASK 0x3F1F3F1F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_1_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_1_WIDTH 6
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_1_MASK 0x3F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_1_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_1_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_1_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_1_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_1_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_0_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_0_WIDTH 6
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_0_MASK 0x00003F00
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_0_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_0_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_0_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_0_MASK 0x0000001F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_0_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3 0x0003F814
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_MASK 0x3F1F3F1F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_3_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_3_WIDTH 6
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_3_MASK 0x3F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_3_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_3_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_3_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_3_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_3_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_2_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_2_WIDTH 6
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_2_MASK 0x00003F00
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_2_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_2_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_2_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_2_MASK 0x0000001F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_2_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL 0x0003F818
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_ENABLE_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_ENABLE_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0       0x0003FF00
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_MASK  0x3F3F3F3F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_MASTER_SLAVE_LSB 29
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_MASTER_SLAVE_MASK 0x20000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_MASTER_SLAVE_LSB 21
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_MASTER_SLAVE_MASK 0x00200000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_ID_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_ID_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_MASTER_SLAVE_LSB 13
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_MASTER_SLAVE_MASK 0x00002000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_ID_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_ID_MASK 0x00001F00
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_MASTER_SLAVE_LSB 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_MASTER_SLAVE_MASK 0x00000020
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_ID_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_ID_MASK 0x0000001F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_ID_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1       0x0003FF04
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_MASK  0x3F3F3F3F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_MASTER_SLAVE_LSB 29
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_MASTER_SLAVE_MASK 0x20000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_ID_LSB 24
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_ID_MASK 0x1F000000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_MASTER_SLAVE_LSB 21
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_MASTER_SLAVE_MASK 0x00200000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_ID_LSB 16
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_ID_MASK 0x001F0000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_MASTER_SLAVE_LSB 13
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_MASTER_SLAVE_MASK 0x00002000
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_ID_LSB 8
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_ID_MASK 0x00001F00
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_ID_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_MASTER_SLAVE_LSB 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_MASTER_SLAVE_MASK 0x00000020
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_ID_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_ID_WIDTH 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_ID_MASK 0x0000001F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_ID_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS                0x0003FF10
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_WIDTH          32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_MASK           0x0000000F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_TILE_CONTROL_LSB 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_TILE_CONTROL_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_TILE_CONTROL_MASK 0x00000008
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_TILE_CONTROL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_1_LSB    2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_1_WIDTH  1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_1_MASK   0x00000004
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_1_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_0_LSB    1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_0_WIDTH  1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_0_MASK   0x00000002
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_0_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_CORE_LSB     0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_CORE_WIDTH   1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_CORE_MASK    0x00000001
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_STATUS_CORE_DEFVAL  0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION             0x0003FF20
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_WIDTH       32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_MASK        0x0000003F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_MEM_TRACE_LSB 5
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_MEM_TRACE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_MEM_TRACE_MASK 0x00000020
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_MEM_TRACE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_AIE_TRACE_LSB 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_AIE_TRACE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_AIE_TRACE_MASK 0x00000010
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_AIE_TRACE_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_TILE_CONTROL_LSB 3
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_TILE_CONTROL_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_TILE_CONTROL_MASK 0x00000008
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_TILE_CONTROL_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_1_LSB 2
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_1_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_1_MASK 0x00000004
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_1_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_0_LSB 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_0_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_0_MASK 0x00000002
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_0_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_CORE_LSB  0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_CORE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_CORE_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_PARITY_INJECTION_CORE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS         0x0003FF30
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_WIDTH   32
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_MASK    0x0000000F
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_TLAST_ERROR_LSB 3
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_TLAST_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_TLAST_ERROR_MASK 0x00000008
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_TLAST_ERROR_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SLVERR_ON_ACCESS_LSB 2
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SLVERR_ON_ACCESS_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SLVERR_ON_ACCESS_MASK 0x00000004
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SLVERR_ON_ACCESS_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SECOND_HEADER_PARITY_ERROR_LSB 1
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SECOND_HEADER_PARITY_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SECOND_HEADER_PARITY_ERROR_MASK 0x00000002
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SECOND_HEADER_PARITY_ERROR_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_FIRST_HEADER_PARITY_ERROR_LSB 0
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_FIRST_HEADER_PARITY_ERROR_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_FIRST_HEADER_PARITY_ERROR_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_FIRST_HEADER_PARITY_ERROR_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS   0x0003FF34
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_ACTIVE_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_ACTIVE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_ACTIVE_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_ACTIVE_DEFVAL 0x0

#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD 0x0003FF38
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_WIDTH 32
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_MASK 0x0000000F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_ABORT_PERIOD_LSB 0
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_ABORT_PERIOD_WIDTH 4
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_ABORT_PERIOD_MASK 0x0000000F
#define XAIEMLGBL_CORE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_ABORT_PERIOD_DEFVAL 0x7

#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL                       0x00060000
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_WIDTH                 32
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_MASK                  0x00000037
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_DMA_ADAPTIVE_CLOCK_GATE_LSB 5
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_DMA_ADAPTIVE_CLOCK_GATE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_DMA_ADAPTIVE_CLOCK_GATE_MASK 0x00000020
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_DMA_ADAPTIVE_CLOCK_GATE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_LSB 4
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_MASK 0x00000010
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_CORE_MODULE_CLOCK_ENABLE_LSB 2
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_CORE_MODULE_CLOCK_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_CORE_MODULE_CLOCK_ENABLE_MASK 0x00000004
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_CORE_MODULE_CLOCK_ENABLE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_MEMORY_MODULE_CLOCK_ENABLE_LSB 1
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_MEMORY_MODULE_CLOCK_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_MEMORY_MODULE_CLOCK_ENABLE_MASK 0x00000002
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_MEMORY_MODULE_CLOCK_ENABLE_DEFVAL 0x1
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_CLOCK_ENABLE_LSB 0
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_CLOCK_ENABLE_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_CLOCK_ENABLE_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_CLOCK_ENABLE_DEFVAL 0x1

#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL                       0x00060010
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_WIDTH                 32
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_MASK                  0x00000007
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_CORE_MODULE_RESET_LSB 2
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_CORE_MODULE_RESET_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_CORE_MODULE_RESET_MASK 0x00000004
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_CORE_MODULE_RESET_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_MEMORY_MODULE_RESET_LSB 1
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_MEMORY_MODULE_RESET_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_MEMORY_MODULE_RESET_MASK 0x00000002
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_MEMORY_MODULE_RESET_DEFVAL 0x0
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_STREAM_SWITCH_RESET_LSB 0
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_STREAM_SWITCH_RESET_WIDTH 1
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_STREAM_SWITCH_RESET_MASK 0x00000001
#define XAIEMLGBL_CORE_MODULE_MODULE_RESET_CONTROL_STREAM_SWITCH_RESET_DEFVAL 0x0

/* AIE-ML memory module register definitions */
#define XAIEMLGBL_MEMORY_MODULE_DATAMEMORY                               0x00000000
#define XAIEMLGBL_MEMORY_MODULE_DATAMEMORY_WIDTH                         128
#define XAIEMLGBL_MEMORY_MODULE_DATAMEMORY_MASK                          0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DATAMEMORY_DATA_LSB                    0
#define XAIEMLGBL_MEMORY_MODULE_DATAMEMORY_DATA_WIDTH                  128
#define XAIEMLGBL_MEMORY_MODULE_DATAMEMORY_DATA_MASK                   0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DATAMEMORY_DATA_DEFVAL                 0x0

#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0                     0x00011000
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_WIDTH               32
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_MASK                0x7F7F7F7F
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT1_STOP_EVENT_LSB 24
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT1_STOP_EVENT_WIDTH 7
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT1_STOP_EVENT_MASK 0x7F000000
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT1_STOP_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT1_START_EVENT_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT1_START_EVENT_WIDTH 7
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT1_START_EVENT_MASK 0x007F0000
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT1_START_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT0_STOP_EVENT_LSB 8
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT0_STOP_EVENT_WIDTH 7
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT0_STOP_EVENT_MASK 0x00007F00
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT0_STOP_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT0_START_EVENT_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT0_START_EVENT_WIDTH 7
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT0_START_EVENT_MASK 0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL0_CNT0_START_EVENT_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL1                     0x00011008
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL1_WIDTH               32
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL1_MASK                0x00007F7F
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL1_CNT1_RESET_EVENT_LSB 8
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL1_CNT1_RESET_EVENT_WIDTH 7
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL1_CNT1_RESET_EVENT_MASK 0x00007F00
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL1_CNT1_RESET_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL1_CNT0_RESET_EVENT_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL1_CNT0_RESET_EVENT_WIDTH 7
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL1_CNT0_RESET_EVENT_MASK 0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_CONTROL1_CNT0_RESET_EVENT_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0                     0x00011020
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0_WIDTH               32
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0_MASK                0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_WIDTH 32
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1                     0x00011024
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1_WIDTH               32
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1_MASK                0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1_COUNTER1_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1_COUNTER1_VALUE_WIDTH 32
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1_COUNTER1_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1_COUNTER1_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE         0x00011080
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_WIDTH   32
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_MASK    0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER0_EVENT_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER0_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER0_EVENT_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER0_EVENT_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE         0x00011084
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_WIDTH   32
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_MASK    0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER1_EVENT_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER1_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER1_EVENT_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER1_EVENT_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION                0x00012000
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_WIDTH          32
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_MASK           0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE3_LSB    3
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE3_WIDTH  1
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE3_MASK   0x00000008
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE3_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE2_LSB    2
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE2_WIDTH  1
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE2_MASK   0x00000004
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE2_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE1_LSB    1
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE1_WIDTH  1
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE1_MASK   0x00000002
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE1_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE0_LSB    0
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE0_WIDTH  1
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE0_MASK   0x00000001
#define XAIEMLGBL_MEMORY_MODULE_CHECKBIT_ERROR_GENERATION_LANE0_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_ECC_SCRUBBING_EVENT                      0x00012110
#define XAIEMLGBL_MEMORY_MODULE_ECC_SCRUBBING_EVENT_WIDTH                32
#define XAIEMLGBL_MEMORY_MODULE_ECC_SCRUBBING_EVENT_MASK                 0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_ECC_SCRUBBING_EVENT_SCRUBBING_EVENT_NUMBER_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_ECC_SCRUBBING_EVENT_SCRUBBING_EVENT_NUMBER_WIDTH 7
#define XAIEMLGBL_MEMORY_MODULE_ECC_SCRUBBING_EVENT_SCRUBBING_EVENT_NUMBER_MASK 0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_ECC_SCRUBBING_EVENT_SCRUBBING_EVENT_NUMBER_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_ECC_FAILING_ADDRESS                      0x00012120
#define XAIEMLGBL_MEMORY_MODULE_ECC_FAILING_ADDRESS_WIDTH                32
#define XAIEMLGBL_MEMORY_MODULE_ECC_FAILING_ADDRESS_MASK                 0x0000BFFF
#define XAIEMLGBL_MEMORY_MODULE_ECC_FAILING_ADDRESS_VALID_LSB          15
#define XAIEMLGBL_MEMORY_MODULE_ECC_FAILING_ADDRESS_VALID_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_ECC_FAILING_ADDRESS_VALID_MASK         0x00008000
#define XAIEMLGBL_MEMORY_MODULE_ECC_FAILING_ADDRESS_VALID_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_ECC_FAILING_ADDRESS_ECC_ERROR_DETECTION_ADDRESS_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_ECC_FAILING_ADDRESS_ECC_ERROR_DETECTION_ADDRESS_WIDTH 14
#define XAIEMLGBL_MEMORY_MODULE_ECC_FAILING_ADDRESS_ECC_ERROR_DETECTION_ADDRESS_MASK 0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_ECC_FAILING_ADDRESS_ECC_ERROR_DETECTION_ADDRESS_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_PARITY_FAILING_ADDRESS                   0x00012124
#define XAIEMLGBL_MEMORY_MODULE_PARITY_FAILING_ADDRESS_WIDTH             32
#define XAIEMLGBL_MEMORY_MODULE_PARITY_FAILING_ADDRESS_MASK              0x0001FFFF
#define XAIEMLGBL_MEMORY_MODULE_PARITY_FAILING_ADDRESS_VALID_LSB       16
#define XAIEMLGBL_MEMORY_MODULE_PARITY_FAILING_ADDRESS_VALID_WIDTH     1
#define XAIEMLGBL_MEMORY_MODULE_PARITY_FAILING_ADDRESS_VALID_MASK      0x00010000
#define XAIEMLGBL_MEMORY_MODULE_PARITY_FAILING_ADDRESS_VALID_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_PARITY_FAILING_ADDRESS_PARITY_ERROR_DETECTION_ADDRESS_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_PARITY_FAILING_ADDRESS_PARITY_ERROR_DETECTION_ADDRESS_WIDTH 16
#define XAIEMLGBL_MEMORY_MODULE_PARITY_FAILING_ADDRESS_PARITY_ERROR_DETECTION_ADDRESS_MASK 0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_PARITY_FAILING_ADDRESS_PARITY_ERROR_DETECTION_ADDRESS_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_TIMER_CONTROL                            0x00014000
#define XAIEMLGBL_MEMORY_MODULE_TIMER_CONTROL_WIDTH                      32
#define XAIEMLGBL_MEMORY_MODULE_TIMER_CONTROL_MASK                       0x80007F00
#define XAIEMLGBL_MEMORY_MODULE_TIMER_CONTROL_RESET_LSB                31
#define XAIEMLGBL_MEMORY_MODULE_TIMER_CONTROL_RESET_WIDTH              1
#define XAIEMLGBL_MEMORY_MODULE_TIMER_CONTROL_RESET_MASK               0x80000000
#define XAIEMLGBL_MEMORY_MODULE_TIMER_CONTROL_RESET_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_TIMER_CONTROL_RESET_EVENT_LSB          8
#define XAIEMLGBL_MEMORY_MODULE_TIMER_CONTROL_RESET_EVENT_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_TIMER_CONTROL_RESET_EVENT_MASK         0x00007F00
#define XAIEMLGBL_MEMORY_MODULE_TIMER_CONTROL_RESET_EVENT_DEFVAL       0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_GENERATE                           0x00014008
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GENERATE_WIDTH                     32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GENERATE_MASK                      0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GENERATE_EVENT_LSB               0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GENERATE_EVENT_WIDTH             7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GENERATE_EVENT_MASK              0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GENERATE_EVENT_DEFVAL            0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST0                         0x00014010
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST0_WIDTH                   32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST0_MASK                    0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST0_EVENT_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST0_EVENT_WIDTH           7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST0_EVENT_MASK            0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST0_EVENT_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST1                         0x00014014
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST1_WIDTH                   32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST1_MASK                    0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST1_EVENT_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST1_EVENT_WIDTH           7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST1_EVENT_MASK            0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST1_EVENT_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST2                         0x00014018
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST2_WIDTH                   32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST2_MASK                    0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST2_EVENT_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST2_EVENT_WIDTH           7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST2_EVENT_MASK            0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST2_EVENT_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST3                         0x0001401C
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST3_WIDTH                   32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST3_MASK                    0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST3_EVENT_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST3_EVENT_WIDTH           7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST3_EVENT_MASK            0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST3_EVENT_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST4                         0x00014020
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST4_WIDTH                   32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST4_MASK                    0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST4_EVENT_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST4_EVENT_WIDTH           7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST4_EVENT_MASK            0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST4_EVENT_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST5                         0x00014024
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST5_WIDTH                   32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST5_MASK                    0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST5_EVENT_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST5_EVENT_WIDTH           7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST5_EVENT_MASK            0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST5_EVENT_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST6                         0x00014028
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST6_WIDTH                   32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST6_MASK                    0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST6_EVENT_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST6_EVENT_WIDTH           7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST6_EVENT_MASK            0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST6_EVENT_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST7                         0x0001402C
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST7_WIDTH                   32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST7_MASK                    0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST7_EVENT_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST7_EVENT_WIDTH           7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST7_EVENT_MASK            0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST7_EVENT_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST8                         0x00014030
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST8_WIDTH                   32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST8_MASK                    0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST8_EVENT_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST8_EVENT_WIDTH           7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST8_EVENT_MASK            0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST8_EVENT_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST9                         0x00014034
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST9_WIDTH                   32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST9_MASK                    0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST9_EVENT_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST9_EVENT_WIDTH           7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST9_EVENT_MASK            0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST9_EVENT_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST10                        0x00014038
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST10_WIDTH                  32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST10_MASK                   0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST10_EVENT_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST10_EVENT_WIDTH          7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST10_EVENT_MASK           0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST10_EVENT_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST11                        0x0001403C
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST11_WIDTH                  32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST11_MASK                   0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST11_EVENT_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST11_EVENT_WIDTH          7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST11_EVENT_MASK           0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST11_EVENT_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST12                        0x00014040
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST12_WIDTH                  32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST12_MASK                   0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST12_EVENT_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST12_EVENT_WIDTH          7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST12_EVENT_MASK           0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST12_EVENT_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST13                        0x00014044
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST13_WIDTH                  32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST13_MASK                   0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST13_EVENT_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST13_EVENT_WIDTH          7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST13_EVENT_MASK           0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST13_EVENT_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST14                        0x00014048
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST14_WIDTH                  32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST14_MASK                   0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST14_EVENT_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST14_EVENT_WIDTH          7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST14_EVENT_MASK           0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST14_EVENT_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST15                        0x0001404C
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST15_WIDTH                  32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST15_MASK                   0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST15_EVENT_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST15_EVENT_WIDTH          7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST15_EVENT_MASK           0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST15_EVENT_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET          0x00014050
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET_WIDTH    32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET_MASK     0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET_SET_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET_SET_WIDTH 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR          0x00014054
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR_WIDTH    32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR_MASK     0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR_CLEAR_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE        0x00014058
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE_WIDTH  32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE_MASK   0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_SOUTH_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET           0x00014060
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET_WIDTH     32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET_MASK      0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET_SET_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET_SET_WIDTH 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR           0x00014064
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR_WIDTH     32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR_MASK      0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR_CLEAR_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE         0x00014068
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE_WIDTH   32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE_MASK    0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_WEST_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET          0x00014070
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET_WIDTH    32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET_MASK     0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET_SET_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET_SET_WIDTH 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR          0x00014074
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR_WIDTH    32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR_MASK     0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR_CLEAR_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE        0x00014078
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE_WIDTH  32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE_MASK   0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_NORTH_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET           0x00014080
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET_WIDTH     32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET_MASK      0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET_SET_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET_SET_WIDTH 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR           0x00014084
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR_WIDTH     32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR_MASK      0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR_CLEAR_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE         0x00014088
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE_WIDTH   32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE_MASK    0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_BROADCAST_BLOCK_EAST_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL0                           0x000140D0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL0_WIDTH                     32
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL0_MASK                      0x7F7F0000
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_LSB    24
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_WIDTH  7
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_MASK   0x7F000000
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_LSB   16
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_WIDTH 7
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_MASK  0x007F0000
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL1                           0x000140D4
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL1_WIDTH                     32
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL1_MASK                      0x0000701F
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL1_PACKET_TYPE_LSB         12
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL1_PACKET_TYPE_WIDTH       3
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL1_PACKET_TYPE_MASK        0x00007000
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL1_PACKET_TYPE_DEFVAL      0x0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL1_ID_LSB                  0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL1_ID_WIDTH                5
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL1_ID_MASK                 0x0000001F
#define XAIEMLGBL_MEMORY_MODULE_TRACE_CONTROL1_ID_DEFVAL               0x0

#define XAIEMLGBL_MEMORY_MODULE_TRACE_STATUS                             0x000140D8
#define XAIEMLGBL_MEMORY_MODULE_TRACE_STATUS_WIDTH                       32
#define XAIEMLGBL_MEMORY_MODULE_TRACE_STATUS_MASK                        0x00000307
#define XAIEMLGBL_MEMORY_MODULE_TRACE_STATUS_STATE_LSB                 8
#define XAIEMLGBL_MEMORY_MODULE_TRACE_STATUS_STATE_WIDTH               2
#define XAIEMLGBL_MEMORY_MODULE_TRACE_STATUS_STATE_MASK                0x00000300
#define XAIEMLGBL_MEMORY_MODULE_TRACE_STATUS_STATE_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_STATUS_MODE_LSB                  0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_STATUS_MODE_WIDTH                3
#define XAIEMLGBL_MEMORY_MODULE_TRACE_STATUS_MODE_MASK                 0x00000007
#define XAIEMLGBL_MEMORY_MODULE_TRACE_STATUS_MODE_DEFVAL               0x0

#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0                             0x000140E0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_WIDTH                       32
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_MASK                        0x7F7F7F7F
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT3_LSB          24
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT3_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT3_MASK         0x7F000000
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT3_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT2_LSB          16
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT2_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT2_MASK         0x007F0000
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT2_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT1_LSB          8
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT1_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT1_MASK         0x00007F00
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT1_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT0_LSB          0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT0_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT0_MASK         0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT0_TRACE_EVENT0_DEFVAL       0x0

#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1                             0x000140E4
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_WIDTH                       32
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_MASK                        0x7F7F7F7F
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT7_LSB          24
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT7_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT7_MASK         0x7F000000
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT7_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT6_LSB          16
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT6_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT6_MASK         0x007F0000
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT6_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT5_LSB          8
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT5_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT5_MASK         0x00007F00
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT5_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT4_LSB          0
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT4_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT4_MASK         0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_TRACE_EVENT1_TRACE_EVENT4_DEFVAL       0x0

#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_LOW_VALUE               0x000140F0
#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_WIDTH         32
#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_MASK          0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_WIDTH 32
#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_DEFVAL 0xFFFFFFFF

#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE              0x000140F4
#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_WIDTH        32
#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_MASK         0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_WIDTH 32
#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_DEFVAL 0xFFFFFFFF

#define XAIEMLGBL_MEMORY_MODULE_TIMER_LOW                                0x000140F8
#define XAIEMLGBL_MEMORY_MODULE_TIMER_LOW_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_TIMER_LOW_MASK                           0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_TIMER_LOW_TIMERLOW_LSB                 0
#define XAIEMLGBL_MEMORY_MODULE_TIMER_LOW_TIMERLOW_WIDTH               32
#define XAIEMLGBL_MEMORY_MODULE_TIMER_LOW_TIMERLOW_MASK                0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_TIMER_LOW_TIMERLOW_DEFVAL              0x0

#define XAIEMLGBL_MEMORY_MODULE_TIMER_HIGH                               0x000140FC
#define XAIEMLGBL_MEMORY_MODULE_TIMER_HIGH_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_TIMER_HIGH_MASK                          0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_TIMER_HIGH_TIMERHIGH_LSB               0
#define XAIEMLGBL_MEMORY_MODULE_TIMER_HIGH_TIMERHIGH_WIDTH             32
#define XAIEMLGBL_MEMORY_MODULE_TIMER_HIGH_TIMERHIGH_MASK              0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_TIMER_HIGH_TIMERHIGH_DEFVAL            0x0

#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0                              0x00014100
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_WIDTH                        32
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_MASK                         0xFFF0FFF0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_READ_ACCESS_LSB            31
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_READ_ACCESS_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_READ_ACCESS_MASK           0x80000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_READ_ACCESS_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_WRITE_ACCESS_LSB           30
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_WRITE_ACCESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_WRITE_ACCESS_MASK          0x40000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_WRITE_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_AXI_ACCESS_LSB             29
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_AXI_ACCESS_WIDTH           1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_AXI_ACCESS_MASK            0x20000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_AXI_ACCESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_DMA_ACCESS_LSB             28
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_DMA_ACCESS_WIDTH           1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_DMA_ACCESS_MASK            0x10000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_DMA_ACCESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_EAST_ACCESS_LSB            27
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_EAST_ACCESS_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_EAST_ACCESS_MASK           0x08000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_EAST_ACCESS_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_NORTH_ACCESS_LSB           26
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_NORTH_ACCESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_NORTH_ACCESS_MASK          0x04000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_NORTH_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_WEST_ACCESS_LSB            25
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_WEST_ACCESS_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_WEST_ACCESS_MASK           0x02000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_WEST_ACCESS_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_SOUTH_ACCESS_LSB           24
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_SOUTH_ACCESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_SOUTH_ACCESS_MASK          0x01000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_SOUTH_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_WRITESTROBES_LSB           20
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_WRITESTROBES_WIDTH         4
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_WRITESTROBES_MASK          0x00F00000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_WRITESTROBES_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_ADDRESS_LSB                4
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_ADDRESS_WIDTH              12
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_ADDRESS_MASK               0x0000FFF0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT0_ADDRESS_DEFVAL             0x0

#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1                              0x00014104
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_WIDTH                        32
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_MASK                         0xFFF0FFF0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_READ_ACCESS_LSB            31
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_READ_ACCESS_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_READ_ACCESS_MASK           0x80000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_READ_ACCESS_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_WRITE_ACCESS_LSB           30
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_WRITE_ACCESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_WRITE_ACCESS_MASK          0x40000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_WRITE_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_AXI_ACCESS_LSB             29
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_AXI_ACCESS_WIDTH           1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_AXI_ACCESS_MASK            0x20000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_AXI_ACCESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_DMA_ACCESS_LSB             28
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_DMA_ACCESS_WIDTH           1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_DMA_ACCESS_MASK            0x10000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_DMA_ACCESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_EAST_ACCESS_LSB            27
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_EAST_ACCESS_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_EAST_ACCESS_MASK           0x08000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_EAST_ACCESS_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_NORTH_ACCESS_LSB           26
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_NORTH_ACCESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_NORTH_ACCESS_MASK          0x04000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_NORTH_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_WEST_ACCESS_LSB            25
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_WEST_ACCESS_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_WEST_ACCESS_MASK           0x02000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_WEST_ACCESS_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_SOUTH_ACCESS_LSB           24
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_SOUTH_ACCESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_SOUTH_ACCESS_MASK          0x01000000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_SOUTH_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_WRITESTROBES_LSB           20
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_WRITESTROBES_WIDTH         4
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_WRITESTROBES_MASK          0x00F00000
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_WRITESTROBES_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_ADDRESS_LSB                4
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_ADDRESS_WIDTH              12
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_ADDRESS_MASK               0x0000FFF0
#define XAIEMLGBL_MEMORY_MODULE_WATCHPOINT1_ADDRESS_DEFVAL             0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS0                            0x00014200
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS0_WIDTH                      32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS0_MASK                       0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_LSB    0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_WIDTH  32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_MASK   0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_DEFVAL 0x2

#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS1                            0x00014204
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS1_WIDTH                      32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS1_MASK                       0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_LSB   0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_WIDTH 32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_MASK  0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS2                            0x00014208
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS2_WIDTH                      32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS2_MASK                       0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_LSB   0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_WIDTH 32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_MASK  0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS3                            0x0001420C
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS3_WIDTH                      32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS3_MASK                       0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_LSB  0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_WIDTH 32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_RESERVED0                                0x00014210
#define XAIEMLGBL_MEMORY_MODULE_RESERVED0_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_RESERVED0_MASK                           0xFFFFFFFF

#define XAIEMLGBL_MEMORY_MODULE_RESERVED1                                0x00014214
#define XAIEMLGBL_MEMORY_MODULE_RESERVED1_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_RESERVED1_MASK                           0xFFFFFFFF

#define XAIEMLGBL_MEMORY_MODULE_RESERVED2                                0x00014218
#define XAIEMLGBL_MEMORY_MODULE_RESERVED2_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_RESERVED2_MASK                           0xFFFFFFFF

#define XAIEMLGBL_MEMORY_MODULE_RESERVED3                                0x0001421C
#define XAIEMLGBL_MEMORY_MODULE_RESERVED3_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_RESERVED3_MASK                           0xFFFFFFFF

#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS                       0x00014400
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_WIDTH                 32
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_MASK                  0x7F7F7F7F
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTD_LSB          24
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTD_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTD_MASK         0x7F000000
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTD_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTC_LSB          16
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTC_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTC_MASK         0x007F0000
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTC_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTB_LSB          8
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTB_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTB_MASK         0x00007F00
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTB_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTA_LSB          0
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTA_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTA_MASK         0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_INPUTS_EVENTA_DEFVAL       0x0

#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL                      0x00014404
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_WIDTH                32
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_MASK                 0x00030303
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_COMBO2_LSB         16
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_COMBO2_WIDTH       2
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_COMBO2_MASK        0x00030000
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_COMBO2_DEFVAL      0x0
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_COMBO1_LSB         8
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_COMBO1_WIDTH       2
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_COMBO1_MASK        0x00000300
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_COMBO1_DEFVAL      0x0
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_COMBO0_LSB         0
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_COMBO0_WIDTH       2
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_COMBO0_MASK        0x00000003
#define XAIEMLGBL_MEMORY_MODULE_COMBO_EVENT_CONTROL_COMBO0_DEFVAL      0x0

#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL             0x00014408
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_WIDTH       32
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_MASK        0x067F067F
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_LSB 26
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_MASK 0x04000000
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_LSB 25
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_MASK 0x02000000
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_WIDTH 7
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_MASK 0x007F0000
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_LSB 10
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_MASK 0x00000400
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_LSB 9
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_MASK 0x00000200
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_WIDTH 7
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_MASK 0x0000007F
#define XAIEMLGBL_MEMORY_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE                     0x00014500
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_WIDTH               32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_MASK                0x000003FF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_LSB 9
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_MASK 0x00000200
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_LSB 8
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_MASK 0x00000100
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_LSB 7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_MASK 0x00000080
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_LSB 6
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_MASK 0x00000040
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_LSB 5
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_MASK 0x00000020
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_EVENT_LSB 3
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_EVENT_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_EVENT_MASK 0x00000008
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_EVENT_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_EVENT_LSB 2
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_EVENT_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_EVENT_MASK 0x00000004
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_EVENT_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_LSB 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_MASK 0x00000002
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_LSB    0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_WIDTH  1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_MASK   0x00000001
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_DEFVAL 0x1

#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE            0x00014504
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WIDTH      32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_MASK       0x00000003
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_1_LSB 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_1_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_1_MASK 0x00000002
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_1_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_0_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_0_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_0_MASK 0x00000001
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_0_DEFVAL 0x1

#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE                   0x00014508
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_WIDTH             32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_MASK              0x00FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_MEMORY_STARVATION_LSB 23
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_MEMORY_STARVATION_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_MEMORY_STARVATION_MASK 0x00800000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_MEMORY_STARVATION_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_MEMORY_STARVATION_LSB 22
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_MEMORY_STARVATION_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_MEMORY_STARVATION_MASK 0x00400000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_MEMORY_STARVATION_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_STREAM_BACKPRESSURE_LSB 21
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_STREAM_BACKPRESSURE_MASK 0x00200000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_STREAM_BACKPRESSURE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_STREAM_BACKPRESSURE_LSB 20
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_STREAM_BACKPRESSURE_MASK 0x00100000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_STREAM_BACKPRESSURE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_MEMORY_BACKPRESSURE_LSB 19
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_MEMORY_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_MEMORY_BACKPRESSURE_MASK 0x00080000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_MEMORY_BACKPRESSURE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_MEMORY_BACKPRESSURE_LSB 18
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_MEMORY_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_MEMORY_BACKPRESSURE_MASK 0x00040000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_MEMORY_BACKPRESSURE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_STREAM_STARVATION_LSB 17
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_STREAM_STARVATION_MASK 0x00020000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_STREAM_STARVATION_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_STREAM_STARVATION_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_STREAM_STARVATION_MASK 0x00010000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_STREAM_STARVATION_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_STALLED_LOCK_ACQUIRE_LSB 15
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_STALLED_LOCK_ACQUIRE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_STALLED_LOCK_ACQUIRE_MASK 0x00008000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_STALLED_LOCK_ACQUIRE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_STALLED_LOCK_ACQUIRE_LSB 14
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_STALLED_LOCK_ACQUIRE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_STALLED_LOCK_ACQUIRE_MASK 0x00004000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_STALLED_LOCK_ACQUIRE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_STALLED_LOCK_ACQUIRE_LSB 13
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_STALLED_LOCK_ACQUIRE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_STALLED_LOCK_ACQUIRE_MASK 0x00002000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_STALLED_LOCK_ACQUIRE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_STALLED_LOCK_ACQUIRE_LSB 12
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_STALLED_LOCK_ACQUIRE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_STALLED_LOCK_ACQUIRE_MASK 0x00001000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_STALLED_LOCK_ACQUIRE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_FINISHED_TASK_LSB 11
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_FINISHED_TASK_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_FINISHED_TASK_MASK 0x00000800
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_FINISHED_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_FINISHED_TASK_LSB 10
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_FINISHED_TASK_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_FINISHED_TASK_MASK 0x00000400
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_FINISHED_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_FINISHED_TASK_LSB 9
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_FINISHED_TASK_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_FINISHED_TASK_MASK 0x00000200
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_FINISHED_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_FINISHED_TASK_LSB 8
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_FINISHED_TASK_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_FINISHED_TASK_MASK 0x00000100
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_FINISHED_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_FINISHED_BD_LSB 7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_FINISHED_BD_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_FINISHED_BD_MASK 0x00000080
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_FINISHED_BD_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_FINISHED_BD_LSB 6
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_FINISHED_BD_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_FINISHED_BD_MASK 0x00000040
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_FINISHED_BD_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_FINISHED_BD_LSB 5
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_FINISHED_BD_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_FINISHED_BD_MASK 0x00000020
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_FINISHED_BD_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_FINISHED_BD_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_FINISHED_BD_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_FINISHED_BD_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_FINISHED_BD_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_START_TASK_LSB 3
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_START_TASK_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_START_TASK_MASK 0x00000008
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_1_START_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_START_TASK_LSB 2
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_START_TASK_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_START_TASK_MASK 0x00000004
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_0_START_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_START_TASK_LSB 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_START_TASK_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_START_TASK_MASK 0x00000002
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_1_START_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_START_TASK_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_START_TASK_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_START_TASK_MASK 0x00000001
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_0_START_TASK_DEFVAL 0x1

#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE                  0x0001450C
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_WIDTH            32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_MASK             0xFFFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_EQUAL_TO_VALUE_LSB 31
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_EQUAL_TO_VALUE_MASK 0x80000000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_REL_LSB 30
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_REL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_REL_MASK 0x40000000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_REL_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_GE_LSB 29
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_GE_MASK 0x20000000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_EQ_LSB 28
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_EQ_MASK 0x10000000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_EQUAL_TO_VALUE_LSB 27
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_EQUAL_TO_VALUE_MASK 0x08000000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_REL_LSB 26
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_REL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_REL_MASK 0x04000000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_REL_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_GE_LSB 25
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_GE_MASK 0x02000000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_EQ_LSB 24
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_EQ_MASK 0x01000000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_EQUAL_TO_VALUE_LSB 23
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_EQUAL_TO_VALUE_MASK 0x00800000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_REL_LSB 22
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_REL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_REL_MASK 0x00400000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_REL_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_GE_LSB 21
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_GE_MASK 0x00200000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_EQ_LSB 20
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_EQ_MASK 0x00100000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_EQUAL_TO_VALUE_LSB 19
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_EQUAL_TO_VALUE_MASK 0x00080000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_REL_LSB 18
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_REL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_REL_MASK 0x00040000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_REL_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_GE_LSB 17
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_GE_MASK 0x00020000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_EQ_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_EQ_MASK 0x00010000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_EQUAL_TO_VALUE_LSB 15
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_EQUAL_TO_VALUE_MASK 0x00008000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_REL_LSB 14
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_REL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_REL_MASK 0x00004000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_REL_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_GE_LSB 13
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_GE_MASK 0x00002000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_EQ_LSB 12
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_EQ_MASK 0x00001000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_EQUAL_TO_VALUE_LSB 11
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_EQUAL_TO_VALUE_MASK 0x00000800
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_REL_LSB 10
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_REL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_REL_MASK 0x00000400
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_REL_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_GE_LSB 9
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_GE_MASK 0x00000200
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_EQ_LSB 8
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_EQ_MASK 0x00000100
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_EQUAL_TO_VALUE_LSB 7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_EQUAL_TO_VALUE_MASK 0x00000080
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_REL_LSB 6
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_REL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_REL_MASK 0x00000040
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_REL_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_GE_LSB 5
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_GE_MASK 0x00000020
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_EQ_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_EQ_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_EQUAL_TO_VALUE_LSB 3
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_EQUAL_TO_VALUE_MASK 0x00000008
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_REL_LSB 2
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_REL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_REL_MASK 0x00000004
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_REL_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_GE_LSB 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_GE_MASK 0x00000002
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_EQ_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_EQ_MASK 0x00000001
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_EQ_DEFVAL 0x1

#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE       0x00014510
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_WIDTH 32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_MASK  0x000000FF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_7_LSB 7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_7_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_7_MASK 0x00000080
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_7_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_6_LSB 6
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_6_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_6_MASK 0x00000040
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_6_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_5_LSB 5
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_5_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_5_MASK 0x00000020
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_5_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_4_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_4_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_4_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_4_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_3_LSB 3
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_3_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_3_MASK 0x00000008
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_3_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_2_LSB 2
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_2_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_2_MASK 0x00000004
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_2_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_1_LSB 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_1_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_1_MASK 0x00000002
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_1_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_0_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_0_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_0_MASK 0x00000001
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_0_DEFVAL 0x1

#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE                 0x00014514
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_WIDTH           32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_MASK            0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_TASK_TOKEN_STALL_LSB 15
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_TASK_TOKEN_STALL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_TASK_TOKEN_STALL_MASK 0x00008000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_TASK_TOKEN_STALL_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_LOCK_ERROR_LSB 14
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_LOCK_ERROR_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_LOCK_ERROR_MASK 0x00004000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_LOCK_ERROR_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_MM2S_1_ERROR_LSB 13
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_MM2S_1_ERROR_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_MM2S_1_ERROR_MASK 0x00002000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_MM2S_1_ERROR_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_MM2S_0_ERROR_LSB 12
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_MM2S_0_ERROR_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_MM2S_0_ERROR_MASK 0x00001000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_MM2S_0_ERROR_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_S2MM_1_ERROR_LSB 11
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_S2MM_1_ERROR_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_S2MM_1_ERROR_MASK 0x00000800
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_S2MM_1_ERROR_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_S2MM_0_ERROR_LSB 10
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_S2MM_0_ERROR_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_S2MM_0_ERROR_MASK 0x00000400
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_S2MM_0_ERROR_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_7_LSB 9
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_7_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_7_MASK 0x00000200
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_7_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_6_LSB 8
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_6_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_6_MASK 0x00000100
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_6_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_5_LSB 7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_5_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_5_MASK 0x00000080
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_5_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_4_LSB 6
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_4_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_4_MASK 0x00000040
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_4_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_3_LSB 5
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_3_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_3_MASK 0x00000020
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_3_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_2_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_2_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_2_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_PARITY_ERROR_BANK_2_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_2BIT_LSB 3
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_2BIT_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_2BIT_MASK 0x00000008
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_2BIT_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_1BIT_LSB 2
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_1BIT_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_1BIT_MASK 0x00000004
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_1BIT_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_2BIT_LSB 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_2BIT_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_2BIT_MASK 0x00000002
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_2BIT_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_CORRECTED_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_CORRECTED_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_CORRECTED_MASK 0x00000001
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_CORRECTED_DEFVAL 0x1

#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE             0x00014518
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_WIDTH       32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_MASK        0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_15_LSB 15
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_15_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_15_MASK 0x00008000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_15_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_14_LSB 14
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_14_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_14_MASK 0x00004000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_14_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_13_LSB 13
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_13_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_13_MASK 0x00002000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_13_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_12_LSB 12
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_12_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_12_MASK 0x00001000
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_12_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_11_LSB 11
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_11_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_11_MASK 0x00000800
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_11_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_10_LSB 10
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_10_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_10_MASK 0x00000400
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_10_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_9_LSB 9
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_9_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_9_MASK 0x00000200
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_9_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_8_LSB 8
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_8_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_8_MASK 0x00000100
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_8_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_7_LSB 7
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_7_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_7_MASK 0x00000080
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_7_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_6_LSB 6
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_6_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_6_MASK 0x00000040
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_6_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_5_LSB 5
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_5_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_5_MASK 0x00000020
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_5_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_4_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_4_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_4_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_4_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_3_LSB 3
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_3_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_3_MASK 0x00000008
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_3_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_2_LSB 2
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_2_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_2_MASK 0x00000004
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_2_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_1_LSB 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_1_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_1_MASK 0x00000002
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_1_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_0_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_0_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_0_MASK 0x00000001
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_0_DEFVAL 0x1

#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE            0x0001451C
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_WIDTH      32
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_MASK       0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_3_LSB 3
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_3_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_3_MASK 0x00000008
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_3_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_2_LSB 2
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_2_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_2_MASK 0x00000004
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_2_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_1_LSB 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_1_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_1_MASK 0x00000002
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_1_DEFVAL 0x1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_0_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_0_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_0_MASK 0x00000001
#define XAIEMLGBL_MEMORY_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_0_DEFVAL 0x1

#define XAIEMLGBL_MEMORY_MODULE_SPARE_REG                                0x00016000
#define XAIEMLGBL_MEMORY_MODULE_SPARE_REG_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_SPARE_REG_MASK                           0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_SPARE_REG_SPARE_REG_LSB                0
#define XAIEMLGBL_MEMORY_MODULE_SPARE_REG_SPARE_REG_WIDTH              16
#define XAIEMLGBL_MEMORY_MODULE_SPARE_REG_SPARE_REG_MASK               0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_SPARE_REG_SPARE_REG_DEFVAL             0x0

#define XAIEMLGBL_MEMORY_MODULE_MEMORY_CONTROL                           0x00016010
#define XAIEMLGBL_MEMORY_MODULE_MEMORY_CONTROL_WIDTH                     32
#define XAIEMLGBL_MEMORY_MODULE_MEMORY_CONTROL_MASK                      0x00000001
#define XAIEMLGBL_MEMORY_MODULE_MEMORY_CONTROL_MEMORY_ZEROISATION_LSB  0
#define XAIEMLGBL_MEMORY_MODULE_MEMORY_CONTROL_MEMORY_ZEROISATION_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_MEMORY_CONTROL_MEMORY_ZEROISATION_MASK 0x00000001
#define XAIEMLGBL_MEMORY_MODULE_MEMORY_CONTROL_MEMORY_ZEROISATION_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_0                                0x0001D000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_0_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_0_MASK                           0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_0_BASE_ADDRESS_LSB             14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_0_BASE_ADDRESS_WIDTH           14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_0_BASE_ADDRESS_MASK            0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_0_BASE_ADDRESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_0_BUFFER_LENGTH_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_0_BUFFER_LENGTH_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_0_BUFFER_LENGTH_MASK           0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_0_BUFFER_LENGTH_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1                                0x0001D004
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_MASK                           0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_ENABLE_COMPRESSION_LSB       31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_ENABLE_COMPRESSION_WIDTH     1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_ENABLE_COMPRESSION_MASK      0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_ENABLE_COMPRESSION_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_ENABLE_PACKET_LSB            30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_ENABLE_PACKET_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_ENABLE_PACKET_MASK           0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_ENABLE_PACKET_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_OUT_OF_ORDER_BD_ID_LSB       24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_OUT_OF_ORDER_BD_ID_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_OUT_OF_ORDER_BD_ID_MASK      0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_OUT_OF_ORDER_BD_ID_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_PACKET_ID_LSB                19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_PACKET_ID_WIDTH              5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_PACKET_ID_MASK               0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_PACKET_ID_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_PACKET_TYPE_LSB              16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_PACKET_TYPE_WIDTH            3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_PACKET_TYPE_MASK             0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_1_PACKET_TYPE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_2                                0x0001D008
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_2_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_2_MASK                           0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_2_D1_STEPSIZE_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_2_D1_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_2_D1_STEPSIZE_MASK             0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_2_D1_STEPSIZE_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_2_D0_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_2_D0_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_2_D0_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_2_D0_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3                                0x0001D00C
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_MASK                           0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_D1_WRAP_LSB                  21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_D1_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_D1_WRAP_MASK                 0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_D1_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_D0_WRAP_LSB                  13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_D0_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_D0_WRAP_MASK                 0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_D0_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_D2_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_D2_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_D2_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_3_D2_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4                                0x0001D010
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_MASK                           0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_ITERATION_CURRENT_LSB        19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_ITERATION_CURRENT_WIDTH      6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_ITERATION_CURRENT_MASK       0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_ITERATION_CURRENT_DEFVAL     0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_ITERATION_WRAP_LSB           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_ITERATION_WRAP_WIDTH         6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_ITERATION_WRAP_MASK          0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_ITERATION_WRAP_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_ITERATION_STEPSIZE_LSB       0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_ITERATION_STEPSIZE_WIDTH     13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_ITERATION_STEPSIZE_MASK      0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_4_ITERATION_STEPSIZE_DEFVAL    0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5                                0x0001D014
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_MASK                           0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_TLAST_SUPPRESS_LSB           31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_TLAST_SUPPRESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_TLAST_SUPPRESS_MASK          0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_TLAST_SUPPRESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_NEXT_BD_LSB                  27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_NEXT_BD_WIDTH                4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_NEXT_BD_MASK                 0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_NEXT_BD_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_USE_NEXT_BD_LSB              26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_USE_NEXT_BD_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_USE_NEXT_BD_MASK             0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_USE_NEXT_BD_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_VALID_BD_LSB                 25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_VALID_BD_WIDTH               1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_VALID_BD_MASK                0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_VALID_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_REL_VALUE_LSB           18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_REL_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_REL_VALUE_MASK          0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_REL_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_REL_ID_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_REL_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_REL_ID_MASK             0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_REL_ID_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_ACQ_ENABLE_LSB          12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_ACQ_ENABLE_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_ACQ_ENABLE_MASK         0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_ACQ_ENABLE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_ACQ_VALUE_LSB           5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_ACQ_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_ACQ_VALUE_MASK          0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_ACQ_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_ACQ_ID_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_ACQ_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_ACQ_ID_MASK             0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD0_5_LOCK_ACQ_ID_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_0                                0x0001D020
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_0_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_0_MASK                           0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_0_BASE_ADDRESS_LSB             14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_0_BASE_ADDRESS_WIDTH           14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_0_BASE_ADDRESS_MASK            0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_0_BASE_ADDRESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_0_BUFFER_LENGTH_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_0_BUFFER_LENGTH_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_0_BUFFER_LENGTH_MASK           0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_0_BUFFER_LENGTH_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1                                0x0001D024
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_MASK                           0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_ENABLE_COMPRESSION_LSB       31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_ENABLE_COMPRESSION_WIDTH     1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_ENABLE_COMPRESSION_MASK      0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_ENABLE_COMPRESSION_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_ENABLE_PACKET_LSB            30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_ENABLE_PACKET_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_ENABLE_PACKET_MASK           0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_ENABLE_PACKET_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_OUT_OF_ORDER_BD_ID_LSB       24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_OUT_OF_ORDER_BD_ID_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_OUT_OF_ORDER_BD_ID_MASK      0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_OUT_OF_ORDER_BD_ID_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_PACKET_ID_LSB                19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_PACKET_ID_WIDTH              5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_PACKET_ID_MASK               0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_PACKET_ID_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_PACKET_TYPE_LSB              16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_PACKET_TYPE_WIDTH            3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_PACKET_TYPE_MASK             0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_1_PACKET_TYPE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_2                                0x0001D028
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_2_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_2_MASK                           0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_2_D1_STEPSIZE_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_2_D1_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_2_D1_STEPSIZE_MASK             0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_2_D1_STEPSIZE_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_2_D0_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_2_D0_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_2_D0_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_2_D0_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3                                0x0001D02C
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_MASK                           0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_D1_WRAP_LSB                  21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_D1_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_D1_WRAP_MASK                 0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_D1_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_D0_WRAP_LSB                  13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_D0_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_D0_WRAP_MASK                 0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_D0_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_D2_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_D2_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_D2_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_3_D2_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4                                0x0001D030
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_MASK                           0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_ITERATION_CURRENT_LSB        19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_ITERATION_CURRENT_WIDTH      6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_ITERATION_CURRENT_MASK       0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_ITERATION_CURRENT_DEFVAL     0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_ITERATION_WRAP_LSB           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_ITERATION_WRAP_WIDTH         6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_ITERATION_WRAP_MASK          0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_ITERATION_WRAP_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_ITERATION_STEPSIZE_LSB       0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_ITERATION_STEPSIZE_WIDTH     13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_ITERATION_STEPSIZE_MASK      0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_4_ITERATION_STEPSIZE_DEFVAL    0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5                                0x0001D034
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_MASK                           0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_TLAST_SUPPRESS_LSB           31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_TLAST_SUPPRESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_TLAST_SUPPRESS_MASK          0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_TLAST_SUPPRESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_NEXT_BD_LSB                  27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_NEXT_BD_WIDTH                4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_NEXT_BD_MASK                 0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_NEXT_BD_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_USE_NEXT_BD_LSB              26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_USE_NEXT_BD_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_USE_NEXT_BD_MASK             0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_USE_NEXT_BD_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_VALID_BD_LSB                 25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_VALID_BD_WIDTH               1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_VALID_BD_MASK                0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_VALID_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_REL_VALUE_LSB           18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_REL_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_REL_VALUE_MASK          0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_REL_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_REL_ID_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_REL_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_REL_ID_MASK             0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_REL_ID_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_ACQ_ENABLE_LSB          12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_ACQ_ENABLE_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_ACQ_ENABLE_MASK         0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_ACQ_ENABLE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_ACQ_VALUE_LSB           5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_ACQ_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_ACQ_VALUE_MASK          0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_ACQ_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_ACQ_ID_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_ACQ_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_ACQ_ID_MASK             0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD1_5_LOCK_ACQ_ID_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_0                                0x0001D040
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_0_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_0_MASK                           0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_0_BASE_ADDRESS_LSB             14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_0_BASE_ADDRESS_WIDTH           14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_0_BASE_ADDRESS_MASK            0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_0_BASE_ADDRESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_0_BUFFER_LENGTH_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_0_BUFFER_LENGTH_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_0_BUFFER_LENGTH_MASK           0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_0_BUFFER_LENGTH_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1                                0x0001D044
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_MASK                           0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_ENABLE_COMPRESSION_LSB       31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_ENABLE_COMPRESSION_WIDTH     1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_ENABLE_COMPRESSION_MASK      0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_ENABLE_COMPRESSION_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_ENABLE_PACKET_LSB            30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_ENABLE_PACKET_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_ENABLE_PACKET_MASK           0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_ENABLE_PACKET_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_OUT_OF_ORDER_BD_ID_LSB       24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_OUT_OF_ORDER_BD_ID_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_OUT_OF_ORDER_BD_ID_MASK      0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_OUT_OF_ORDER_BD_ID_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_PACKET_ID_LSB                19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_PACKET_ID_WIDTH              5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_PACKET_ID_MASK               0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_PACKET_ID_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_PACKET_TYPE_LSB              16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_PACKET_TYPE_WIDTH            3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_PACKET_TYPE_MASK             0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_1_PACKET_TYPE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_2                                0x0001D048
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_2_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_2_MASK                           0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_2_D1_STEPSIZE_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_2_D1_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_2_D1_STEPSIZE_MASK             0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_2_D1_STEPSIZE_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_2_D0_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_2_D0_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_2_D0_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_2_D0_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3                                0x0001D04C
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_MASK                           0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_D1_WRAP_LSB                  21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_D1_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_D1_WRAP_MASK                 0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_D1_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_D0_WRAP_LSB                  13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_D0_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_D0_WRAP_MASK                 0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_D0_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_D2_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_D2_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_D2_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_3_D2_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4                                0x0001D050
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_MASK                           0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_ITERATION_CURRENT_LSB        19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_ITERATION_CURRENT_WIDTH      6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_ITERATION_CURRENT_MASK       0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_ITERATION_CURRENT_DEFVAL     0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_ITERATION_WRAP_LSB           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_ITERATION_WRAP_WIDTH         6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_ITERATION_WRAP_MASK          0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_ITERATION_WRAP_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_ITERATION_STEPSIZE_LSB       0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_ITERATION_STEPSIZE_WIDTH     13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_ITERATION_STEPSIZE_MASK      0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_4_ITERATION_STEPSIZE_DEFVAL    0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5                                0x0001D054
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_MASK                           0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_TLAST_SUPPRESS_LSB           31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_TLAST_SUPPRESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_TLAST_SUPPRESS_MASK          0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_TLAST_SUPPRESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_NEXT_BD_LSB                  27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_NEXT_BD_WIDTH                4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_NEXT_BD_MASK                 0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_NEXT_BD_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_USE_NEXT_BD_LSB              26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_USE_NEXT_BD_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_USE_NEXT_BD_MASK             0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_USE_NEXT_BD_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_VALID_BD_LSB                 25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_VALID_BD_WIDTH               1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_VALID_BD_MASK                0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_VALID_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_REL_VALUE_LSB           18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_REL_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_REL_VALUE_MASK          0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_REL_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_REL_ID_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_REL_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_REL_ID_MASK             0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_REL_ID_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_ACQ_ENABLE_LSB          12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_ACQ_ENABLE_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_ACQ_ENABLE_MASK         0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_ACQ_ENABLE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_ACQ_VALUE_LSB           5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_ACQ_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_ACQ_VALUE_MASK          0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_ACQ_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_ACQ_ID_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_ACQ_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_ACQ_ID_MASK             0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD2_5_LOCK_ACQ_ID_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_0                                0x0001D060
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_0_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_0_MASK                           0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_0_BASE_ADDRESS_LSB             14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_0_BASE_ADDRESS_WIDTH           14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_0_BASE_ADDRESS_MASK            0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_0_BASE_ADDRESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_0_BUFFER_LENGTH_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_0_BUFFER_LENGTH_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_0_BUFFER_LENGTH_MASK           0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_0_BUFFER_LENGTH_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1                                0x0001D064
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_MASK                           0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_ENABLE_COMPRESSION_LSB       31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_ENABLE_COMPRESSION_WIDTH     1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_ENABLE_COMPRESSION_MASK      0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_ENABLE_COMPRESSION_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_ENABLE_PACKET_LSB            30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_ENABLE_PACKET_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_ENABLE_PACKET_MASK           0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_ENABLE_PACKET_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_OUT_OF_ORDER_BD_ID_LSB       24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_OUT_OF_ORDER_BD_ID_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_OUT_OF_ORDER_BD_ID_MASK      0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_OUT_OF_ORDER_BD_ID_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_PACKET_ID_LSB                19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_PACKET_ID_WIDTH              5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_PACKET_ID_MASK               0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_PACKET_ID_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_PACKET_TYPE_LSB              16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_PACKET_TYPE_WIDTH            3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_PACKET_TYPE_MASK             0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_1_PACKET_TYPE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_2                                0x0001D068
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_2_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_2_MASK                           0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_2_D1_STEPSIZE_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_2_D1_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_2_D1_STEPSIZE_MASK             0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_2_D1_STEPSIZE_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_2_D0_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_2_D0_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_2_D0_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_2_D0_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3                                0x0001D06C
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_MASK                           0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_D1_WRAP_LSB                  21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_D1_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_D1_WRAP_MASK                 0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_D1_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_D0_WRAP_LSB                  13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_D0_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_D0_WRAP_MASK                 0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_D0_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_D2_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_D2_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_D2_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_3_D2_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4                                0x0001D070
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_MASK                           0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_ITERATION_CURRENT_LSB        19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_ITERATION_CURRENT_WIDTH      6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_ITERATION_CURRENT_MASK       0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_ITERATION_CURRENT_DEFVAL     0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_ITERATION_WRAP_LSB           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_ITERATION_WRAP_WIDTH         6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_ITERATION_WRAP_MASK          0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_ITERATION_WRAP_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_ITERATION_STEPSIZE_LSB       0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_ITERATION_STEPSIZE_WIDTH     13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_ITERATION_STEPSIZE_MASK      0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_4_ITERATION_STEPSIZE_DEFVAL    0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5                                0x0001D074
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_MASK                           0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_TLAST_SUPPRESS_LSB           31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_TLAST_SUPPRESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_TLAST_SUPPRESS_MASK          0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_TLAST_SUPPRESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_NEXT_BD_LSB                  27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_NEXT_BD_WIDTH                4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_NEXT_BD_MASK                 0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_NEXT_BD_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_USE_NEXT_BD_LSB              26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_USE_NEXT_BD_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_USE_NEXT_BD_MASK             0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_USE_NEXT_BD_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_VALID_BD_LSB                 25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_VALID_BD_WIDTH               1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_VALID_BD_MASK                0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_VALID_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_REL_VALUE_LSB           18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_REL_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_REL_VALUE_MASK          0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_REL_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_REL_ID_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_REL_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_REL_ID_MASK             0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_REL_ID_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_ACQ_ENABLE_LSB          12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_ACQ_ENABLE_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_ACQ_ENABLE_MASK         0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_ACQ_ENABLE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_ACQ_VALUE_LSB           5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_ACQ_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_ACQ_VALUE_MASK          0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_ACQ_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_ACQ_ID_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_ACQ_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_ACQ_ID_MASK             0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD3_5_LOCK_ACQ_ID_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_0                                0x0001D080
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_0_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_0_MASK                           0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_0_BASE_ADDRESS_LSB             14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_0_BASE_ADDRESS_WIDTH           14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_0_BASE_ADDRESS_MASK            0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_0_BASE_ADDRESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_0_BUFFER_LENGTH_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_0_BUFFER_LENGTH_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_0_BUFFER_LENGTH_MASK           0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_0_BUFFER_LENGTH_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1                                0x0001D084
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_MASK                           0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_ENABLE_COMPRESSION_LSB       31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_ENABLE_COMPRESSION_WIDTH     1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_ENABLE_COMPRESSION_MASK      0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_ENABLE_COMPRESSION_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_ENABLE_PACKET_LSB            30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_ENABLE_PACKET_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_ENABLE_PACKET_MASK           0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_ENABLE_PACKET_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_OUT_OF_ORDER_BD_ID_LSB       24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_OUT_OF_ORDER_BD_ID_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_OUT_OF_ORDER_BD_ID_MASK      0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_OUT_OF_ORDER_BD_ID_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_PACKET_ID_LSB                19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_PACKET_ID_WIDTH              5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_PACKET_ID_MASK               0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_PACKET_ID_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_PACKET_TYPE_LSB              16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_PACKET_TYPE_WIDTH            3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_PACKET_TYPE_MASK             0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_1_PACKET_TYPE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_2                                0x0001D088
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_2_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_2_MASK                           0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_2_D1_STEPSIZE_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_2_D1_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_2_D1_STEPSIZE_MASK             0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_2_D1_STEPSIZE_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_2_D0_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_2_D0_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_2_D0_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_2_D0_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3                                0x0001D08C
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_MASK                           0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_D1_WRAP_LSB                  21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_D1_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_D1_WRAP_MASK                 0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_D1_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_D0_WRAP_LSB                  13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_D0_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_D0_WRAP_MASK                 0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_D0_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_D2_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_D2_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_D2_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_3_D2_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4                                0x0001D090
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_MASK                           0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_ITERATION_CURRENT_LSB        19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_ITERATION_CURRENT_WIDTH      6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_ITERATION_CURRENT_MASK       0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_ITERATION_CURRENT_DEFVAL     0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_ITERATION_WRAP_LSB           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_ITERATION_WRAP_WIDTH         6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_ITERATION_WRAP_MASK          0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_ITERATION_WRAP_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_ITERATION_STEPSIZE_LSB       0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_ITERATION_STEPSIZE_WIDTH     13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_ITERATION_STEPSIZE_MASK      0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_4_ITERATION_STEPSIZE_DEFVAL    0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5                                0x0001D094
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_MASK                           0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_TLAST_SUPPRESS_LSB           31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_TLAST_SUPPRESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_TLAST_SUPPRESS_MASK          0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_TLAST_SUPPRESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_NEXT_BD_LSB                  27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_NEXT_BD_WIDTH                4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_NEXT_BD_MASK                 0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_NEXT_BD_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_USE_NEXT_BD_LSB              26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_USE_NEXT_BD_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_USE_NEXT_BD_MASK             0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_USE_NEXT_BD_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_VALID_BD_LSB                 25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_VALID_BD_WIDTH               1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_VALID_BD_MASK                0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_VALID_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_REL_VALUE_LSB           18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_REL_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_REL_VALUE_MASK          0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_REL_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_REL_ID_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_REL_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_REL_ID_MASK             0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_REL_ID_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_ACQ_ENABLE_LSB          12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_ACQ_ENABLE_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_ACQ_ENABLE_MASK         0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_ACQ_ENABLE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_ACQ_VALUE_LSB           5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_ACQ_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_ACQ_VALUE_MASK          0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_ACQ_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_ACQ_ID_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_ACQ_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_ACQ_ID_MASK             0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD4_5_LOCK_ACQ_ID_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_0                                0x0001D0A0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_0_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_0_MASK                           0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_0_BASE_ADDRESS_LSB             14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_0_BASE_ADDRESS_WIDTH           14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_0_BASE_ADDRESS_MASK            0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_0_BASE_ADDRESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_0_BUFFER_LENGTH_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_0_BUFFER_LENGTH_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_0_BUFFER_LENGTH_MASK           0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_0_BUFFER_LENGTH_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1                                0x0001D0A4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_MASK                           0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_ENABLE_COMPRESSION_LSB       31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_ENABLE_COMPRESSION_WIDTH     1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_ENABLE_COMPRESSION_MASK      0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_ENABLE_COMPRESSION_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_ENABLE_PACKET_LSB            30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_ENABLE_PACKET_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_ENABLE_PACKET_MASK           0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_ENABLE_PACKET_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_OUT_OF_ORDER_BD_ID_LSB       24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_OUT_OF_ORDER_BD_ID_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_OUT_OF_ORDER_BD_ID_MASK      0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_OUT_OF_ORDER_BD_ID_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_PACKET_ID_LSB                19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_PACKET_ID_WIDTH              5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_PACKET_ID_MASK               0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_PACKET_ID_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_PACKET_TYPE_LSB              16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_PACKET_TYPE_WIDTH            3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_PACKET_TYPE_MASK             0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_1_PACKET_TYPE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_2                                0x0001D0A8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_2_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_2_MASK                           0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_2_D1_STEPSIZE_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_2_D1_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_2_D1_STEPSIZE_MASK             0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_2_D1_STEPSIZE_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_2_D0_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_2_D0_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_2_D0_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_2_D0_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3                                0x0001D0AC
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_MASK                           0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_D1_WRAP_LSB                  21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_D1_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_D1_WRAP_MASK                 0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_D1_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_D0_WRAP_LSB                  13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_D0_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_D0_WRAP_MASK                 0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_D0_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_D2_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_D2_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_D2_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_3_D2_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4                                0x0001D0B0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_MASK                           0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_ITERATION_CURRENT_LSB        19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_ITERATION_CURRENT_WIDTH      6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_ITERATION_CURRENT_MASK       0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_ITERATION_CURRENT_DEFVAL     0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_ITERATION_WRAP_LSB           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_ITERATION_WRAP_WIDTH         6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_ITERATION_WRAP_MASK          0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_ITERATION_WRAP_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_ITERATION_STEPSIZE_LSB       0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_ITERATION_STEPSIZE_WIDTH     13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_ITERATION_STEPSIZE_MASK      0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_4_ITERATION_STEPSIZE_DEFVAL    0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5                                0x0001D0B4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_MASK                           0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_TLAST_SUPPRESS_LSB           31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_TLAST_SUPPRESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_TLAST_SUPPRESS_MASK          0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_TLAST_SUPPRESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_NEXT_BD_LSB                  27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_NEXT_BD_WIDTH                4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_NEXT_BD_MASK                 0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_NEXT_BD_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_USE_NEXT_BD_LSB              26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_USE_NEXT_BD_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_USE_NEXT_BD_MASK             0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_USE_NEXT_BD_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_VALID_BD_LSB                 25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_VALID_BD_WIDTH               1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_VALID_BD_MASK                0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_VALID_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_REL_VALUE_LSB           18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_REL_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_REL_VALUE_MASK          0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_REL_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_REL_ID_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_REL_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_REL_ID_MASK             0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_REL_ID_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_ACQ_ENABLE_LSB          12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_ACQ_ENABLE_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_ACQ_ENABLE_MASK         0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_ACQ_ENABLE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_ACQ_VALUE_LSB           5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_ACQ_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_ACQ_VALUE_MASK          0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_ACQ_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_ACQ_ID_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_ACQ_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_ACQ_ID_MASK             0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD5_5_LOCK_ACQ_ID_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_0                                0x0001D0C0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_0_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_0_MASK                           0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_0_BASE_ADDRESS_LSB             14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_0_BASE_ADDRESS_WIDTH           14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_0_BASE_ADDRESS_MASK            0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_0_BASE_ADDRESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_0_BUFFER_LENGTH_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_0_BUFFER_LENGTH_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_0_BUFFER_LENGTH_MASK           0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_0_BUFFER_LENGTH_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1                                0x0001D0C4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_MASK                           0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_ENABLE_COMPRESSION_LSB       31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_ENABLE_COMPRESSION_WIDTH     1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_ENABLE_COMPRESSION_MASK      0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_ENABLE_COMPRESSION_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_ENABLE_PACKET_LSB            30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_ENABLE_PACKET_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_ENABLE_PACKET_MASK           0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_ENABLE_PACKET_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_OUT_OF_ORDER_BD_ID_LSB       24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_OUT_OF_ORDER_BD_ID_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_OUT_OF_ORDER_BD_ID_MASK      0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_OUT_OF_ORDER_BD_ID_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_PACKET_ID_LSB                19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_PACKET_ID_WIDTH              5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_PACKET_ID_MASK               0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_PACKET_ID_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_PACKET_TYPE_LSB              16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_PACKET_TYPE_WIDTH            3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_PACKET_TYPE_MASK             0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_1_PACKET_TYPE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_2                                0x0001D0C8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_2_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_2_MASK                           0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_2_D1_STEPSIZE_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_2_D1_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_2_D1_STEPSIZE_MASK             0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_2_D1_STEPSIZE_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_2_D0_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_2_D0_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_2_D0_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_2_D0_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3                                0x0001D0CC
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_MASK                           0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_D1_WRAP_LSB                  21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_D1_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_D1_WRAP_MASK                 0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_D1_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_D0_WRAP_LSB                  13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_D0_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_D0_WRAP_MASK                 0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_D0_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_D2_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_D2_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_D2_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_3_D2_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4                                0x0001D0D0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_MASK                           0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_ITERATION_CURRENT_LSB        19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_ITERATION_CURRENT_WIDTH      6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_ITERATION_CURRENT_MASK       0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_ITERATION_CURRENT_DEFVAL     0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_ITERATION_WRAP_LSB           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_ITERATION_WRAP_WIDTH         6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_ITERATION_WRAP_MASK          0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_ITERATION_WRAP_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_ITERATION_STEPSIZE_LSB       0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_ITERATION_STEPSIZE_WIDTH     13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_ITERATION_STEPSIZE_MASK      0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_4_ITERATION_STEPSIZE_DEFVAL    0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5                                0x0001D0D4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_MASK                           0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_TLAST_SUPPRESS_LSB           31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_TLAST_SUPPRESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_TLAST_SUPPRESS_MASK          0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_TLAST_SUPPRESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_NEXT_BD_LSB                  27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_NEXT_BD_WIDTH                4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_NEXT_BD_MASK                 0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_NEXT_BD_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_USE_NEXT_BD_LSB              26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_USE_NEXT_BD_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_USE_NEXT_BD_MASK             0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_USE_NEXT_BD_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_VALID_BD_LSB                 25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_VALID_BD_WIDTH               1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_VALID_BD_MASK                0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_VALID_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_REL_VALUE_LSB           18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_REL_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_REL_VALUE_MASK          0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_REL_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_REL_ID_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_REL_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_REL_ID_MASK             0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_REL_ID_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_ACQ_ENABLE_LSB          12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_ACQ_ENABLE_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_ACQ_ENABLE_MASK         0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_ACQ_ENABLE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_ACQ_VALUE_LSB           5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_ACQ_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_ACQ_VALUE_MASK          0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_ACQ_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_ACQ_ID_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_ACQ_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_ACQ_ID_MASK             0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD6_5_LOCK_ACQ_ID_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_0                                0x0001D0E0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_0_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_0_MASK                           0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_0_BASE_ADDRESS_LSB             14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_0_BASE_ADDRESS_WIDTH           14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_0_BASE_ADDRESS_MASK            0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_0_BASE_ADDRESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_0_BUFFER_LENGTH_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_0_BUFFER_LENGTH_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_0_BUFFER_LENGTH_MASK           0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_0_BUFFER_LENGTH_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1                                0x0001D0E4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_MASK                           0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_ENABLE_COMPRESSION_LSB       31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_ENABLE_COMPRESSION_WIDTH     1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_ENABLE_COMPRESSION_MASK      0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_ENABLE_COMPRESSION_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_ENABLE_PACKET_LSB            30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_ENABLE_PACKET_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_ENABLE_PACKET_MASK           0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_ENABLE_PACKET_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_OUT_OF_ORDER_BD_ID_LSB       24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_OUT_OF_ORDER_BD_ID_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_OUT_OF_ORDER_BD_ID_MASK      0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_OUT_OF_ORDER_BD_ID_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_PACKET_ID_LSB                19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_PACKET_ID_WIDTH              5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_PACKET_ID_MASK               0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_PACKET_ID_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_PACKET_TYPE_LSB              16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_PACKET_TYPE_WIDTH            3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_PACKET_TYPE_MASK             0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_1_PACKET_TYPE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_2                                0x0001D0E8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_2_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_2_MASK                           0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_2_D1_STEPSIZE_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_2_D1_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_2_D1_STEPSIZE_MASK             0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_2_D1_STEPSIZE_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_2_D0_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_2_D0_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_2_D0_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_2_D0_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3                                0x0001D0EC
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_MASK                           0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_D1_WRAP_LSB                  21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_D1_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_D1_WRAP_MASK                 0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_D1_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_D0_WRAP_LSB                  13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_D0_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_D0_WRAP_MASK                 0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_D0_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_D2_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_D2_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_D2_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_3_D2_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4                                0x0001D0F0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_MASK                           0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_ITERATION_CURRENT_LSB        19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_ITERATION_CURRENT_WIDTH      6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_ITERATION_CURRENT_MASK       0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_ITERATION_CURRENT_DEFVAL     0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_ITERATION_WRAP_LSB           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_ITERATION_WRAP_WIDTH         6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_ITERATION_WRAP_MASK          0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_ITERATION_WRAP_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_ITERATION_STEPSIZE_LSB       0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_ITERATION_STEPSIZE_WIDTH     13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_ITERATION_STEPSIZE_MASK      0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_4_ITERATION_STEPSIZE_DEFVAL    0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5                                0x0001D0F4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_MASK                           0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_TLAST_SUPPRESS_LSB           31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_TLAST_SUPPRESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_TLAST_SUPPRESS_MASK          0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_TLAST_SUPPRESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_NEXT_BD_LSB                  27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_NEXT_BD_WIDTH                4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_NEXT_BD_MASK                 0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_NEXT_BD_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_USE_NEXT_BD_LSB              26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_USE_NEXT_BD_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_USE_NEXT_BD_MASK             0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_USE_NEXT_BD_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_VALID_BD_LSB                 25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_VALID_BD_WIDTH               1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_VALID_BD_MASK                0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_VALID_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_REL_VALUE_LSB           18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_REL_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_REL_VALUE_MASK          0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_REL_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_REL_ID_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_REL_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_REL_ID_MASK             0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_REL_ID_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_ACQ_ENABLE_LSB          12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_ACQ_ENABLE_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_ACQ_ENABLE_MASK         0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_ACQ_ENABLE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_ACQ_VALUE_LSB           5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_ACQ_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_ACQ_VALUE_MASK          0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_ACQ_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_ACQ_ID_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_ACQ_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_ACQ_ID_MASK             0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD7_5_LOCK_ACQ_ID_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_0                                0x0001D100
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_0_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_0_MASK                           0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_0_BASE_ADDRESS_LSB             14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_0_BASE_ADDRESS_WIDTH           14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_0_BASE_ADDRESS_MASK            0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_0_BASE_ADDRESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_0_BUFFER_LENGTH_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_0_BUFFER_LENGTH_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_0_BUFFER_LENGTH_MASK           0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_0_BUFFER_LENGTH_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1                                0x0001D104
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_MASK                           0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_ENABLE_COMPRESSION_LSB       31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_ENABLE_COMPRESSION_WIDTH     1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_ENABLE_COMPRESSION_MASK      0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_ENABLE_COMPRESSION_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_ENABLE_PACKET_LSB            30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_ENABLE_PACKET_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_ENABLE_PACKET_MASK           0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_ENABLE_PACKET_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_OUT_OF_ORDER_BD_ID_LSB       24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_OUT_OF_ORDER_BD_ID_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_OUT_OF_ORDER_BD_ID_MASK      0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_OUT_OF_ORDER_BD_ID_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_PACKET_ID_LSB                19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_PACKET_ID_WIDTH              5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_PACKET_ID_MASK               0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_PACKET_ID_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_PACKET_TYPE_LSB              16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_PACKET_TYPE_WIDTH            3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_PACKET_TYPE_MASK             0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_1_PACKET_TYPE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_2                                0x0001D108
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_2_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_2_MASK                           0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_2_D1_STEPSIZE_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_2_D1_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_2_D1_STEPSIZE_MASK             0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_2_D1_STEPSIZE_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_2_D0_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_2_D0_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_2_D0_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_2_D0_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3                                0x0001D10C
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_MASK                           0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_D1_WRAP_LSB                  21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_D1_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_D1_WRAP_MASK                 0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_D1_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_D0_WRAP_LSB                  13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_D0_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_D0_WRAP_MASK                 0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_D0_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_D2_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_D2_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_D2_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_3_D2_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4                                0x0001D110
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_MASK                           0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_ITERATION_CURRENT_LSB        19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_ITERATION_CURRENT_WIDTH      6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_ITERATION_CURRENT_MASK       0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_ITERATION_CURRENT_DEFVAL     0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_ITERATION_WRAP_LSB           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_ITERATION_WRAP_WIDTH         6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_ITERATION_WRAP_MASK          0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_ITERATION_WRAP_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_ITERATION_STEPSIZE_LSB       0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_ITERATION_STEPSIZE_WIDTH     13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_ITERATION_STEPSIZE_MASK      0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_4_ITERATION_STEPSIZE_DEFVAL    0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5                                0x0001D114
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_MASK                           0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_TLAST_SUPPRESS_LSB           31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_TLAST_SUPPRESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_TLAST_SUPPRESS_MASK          0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_TLAST_SUPPRESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_NEXT_BD_LSB                  27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_NEXT_BD_WIDTH                4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_NEXT_BD_MASK                 0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_NEXT_BD_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_USE_NEXT_BD_LSB              26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_USE_NEXT_BD_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_USE_NEXT_BD_MASK             0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_USE_NEXT_BD_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_VALID_BD_LSB                 25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_VALID_BD_WIDTH               1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_VALID_BD_MASK                0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_VALID_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_REL_VALUE_LSB           18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_REL_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_REL_VALUE_MASK          0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_REL_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_REL_ID_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_REL_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_REL_ID_MASK             0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_REL_ID_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_ACQ_ENABLE_LSB          12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_ACQ_ENABLE_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_ACQ_ENABLE_MASK         0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_ACQ_ENABLE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_ACQ_VALUE_LSB           5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_ACQ_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_ACQ_VALUE_MASK          0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_ACQ_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_ACQ_ID_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_ACQ_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_ACQ_ID_MASK             0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD8_5_LOCK_ACQ_ID_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_0                                0x0001D120
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_0_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_0_MASK                           0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_0_BASE_ADDRESS_LSB             14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_0_BASE_ADDRESS_WIDTH           14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_0_BASE_ADDRESS_MASK            0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_0_BASE_ADDRESS_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_0_BUFFER_LENGTH_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_0_BUFFER_LENGTH_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_0_BUFFER_LENGTH_MASK           0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_0_BUFFER_LENGTH_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1                                0x0001D124
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_MASK                           0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_ENABLE_COMPRESSION_LSB       31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_ENABLE_COMPRESSION_WIDTH     1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_ENABLE_COMPRESSION_MASK      0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_ENABLE_COMPRESSION_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_ENABLE_PACKET_LSB            30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_ENABLE_PACKET_WIDTH          1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_ENABLE_PACKET_MASK           0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_ENABLE_PACKET_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_OUT_OF_ORDER_BD_ID_LSB       24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_OUT_OF_ORDER_BD_ID_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_OUT_OF_ORDER_BD_ID_MASK      0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_OUT_OF_ORDER_BD_ID_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_PACKET_ID_LSB                19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_PACKET_ID_WIDTH              5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_PACKET_ID_MASK               0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_PACKET_ID_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_PACKET_TYPE_LSB              16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_PACKET_TYPE_WIDTH            3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_PACKET_TYPE_MASK             0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_1_PACKET_TYPE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_2                                0x0001D128
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_2_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_2_MASK                           0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_2_D1_STEPSIZE_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_2_D1_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_2_D1_STEPSIZE_MASK             0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_2_D1_STEPSIZE_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_2_D0_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_2_D0_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_2_D0_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_2_D0_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3                                0x0001D12C
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_MASK                           0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_D1_WRAP_LSB                  21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_D1_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_D1_WRAP_MASK                 0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_D1_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_D0_WRAP_LSB                  13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_D0_WRAP_WIDTH                8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_D0_WRAP_MASK                 0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_D0_WRAP_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_D2_STEPSIZE_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_D2_STEPSIZE_WIDTH            13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_D2_STEPSIZE_MASK             0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_3_D2_STEPSIZE_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4                                0x0001D130
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_MASK                           0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_ITERATION_CURRENT_LSB        19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_ITERATION_CURRENT_WIDTH      6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_ITERATION_CURRENT_MASK       0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_ITERATION_CURRENT_DEFVAL     0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_ITERATION_WRAP_LSB           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_ITERATION_WRAP_WIDTH         6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_ITERATION_WRAP_MASK          0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_ITERATION_WRAP_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_ITERATION_STEPSIZE_LSB       0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_ITERATION_STEPSIZE_WIDTH     13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_ITERATION_STEPSIZE_MASK      0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_4_ITERATION_STEPSIZE_DEFVAL    0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5                                0x0001D134
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_WIDTH                          32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_MASK                           0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_TLAST_SUPPRESS_LSB           31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_TLAST_SUPPRESS_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_TLAST_SUPPRESS_MASK          0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_TLAST_SUPPRESS_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_NEXT_BD_LSB                  27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_NEXT_BD_WIDTH                4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_NEXT_BD_MASK                 0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_NEXT_BD_DEFVAL               0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_USE_NEXT_BD_LSB              26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_USE_NEXT_BD_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_USE_NEXT_BD_MASK             0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_USE_NEXT_BD_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_VALID_BD_LSB                 25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_VALID_BD_WIDTH               1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_VALID_BD_MASK                0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_VALID_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_REL_VALUE_LSB           18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_REL_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_REL_VALUE_MASK          0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_REL_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_REL_ID_LSB              13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_REL_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_REL_ID_MASK             0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_REL_ID_DEFVAL           0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_ACQ_ENABLE_LSB          12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_ACQ_ENABLE_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_ACQ_ENABLE_MASK         0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_ACQ_ENABLE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_ACQ_VALUE_LSB           5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_ACQ_VALUE_WIDTH         7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_ACQ_VALUE_MASK          0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_ACQ_VALUE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_ACQ_ID_LSB              0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_ACQ_ID_WIDTH            4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_ACQ_ID_MASK             0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD9_5_LOCK_ACQ_ID_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_0                               0x0001D140
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_0_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_0_MASK                          0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_0_BASE_ADDRESS_LSB            14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_0_BASE_ADDRESS_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_0_BASE_ADDRESS_MASK           0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_0_BASE_ADDRESS_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_0_BUFFER_LENGTH_LSB           0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_0_BUFFER_LENGTH_WIDTH         14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_0_BUFFER_LENGTH_MASK          0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_0_BUFFER_LENGTH_DEFVAL        0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1                               0x0001D144
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_MASK                          0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_ENABLE_COMPRESSION_LSB      31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_ENABLE_COMPRESSION_WIDTH    1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_ENABLE_COMPRESSION_MASK     0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_ENABLE_COMPRESSION_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_ENABLE_PACKET_LSB           30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_ENABLE_PACKET_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_ENABLE_PACKET_MASK          0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_ENABLE_PACKET_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_OUT_OF_ORDER_BD_ID_LSB      24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_OUT_OF_ORDER_BD_ID_WIDTH    6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_OUT_OF_ORDER_BD_ID_MASK     0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_OUT_OF_ORDER_BD_ID_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_PACKET_ID_LSB               19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_PACKET_ID_WIDTH             5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_PACKET_ID_MASK              0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_PACKET_ID_DEFVAL            0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_PACKET_TYPE_LSB             16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_PACKET_TYPE_WIDTH           3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_PACKET_TYPE_MASK            0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_1_PACKET_TYPE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_2                               0x0001D148
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_2_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_2_MASK                          0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_2_D1_STEPSIZE_LSB             13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_2_D1_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_2_D1_STEPSIZE_MASK            0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_2_D1_STEPSIZE_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_2_D0_STEPSIZE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_2_D0_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_2_D0_STEPSIZE_MASK            0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_2_D0_STEPSIZE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3                               0x0001D14C
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_MASK                          0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_D1_WRAP_LSB                 21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_D1_WRAP_WIDTH               8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_D1_WRAP_MASK                0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_D1_WRAP_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_D0_WRAP_LSB                 13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_D0_WRAP_WIDTH               8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_D0_WRAP_MASK                0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_D0_WRAP_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_D2_STEPSIZE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_D2_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_D2_STEPSIZE_MASK            0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_3_D2_STEPSIZE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4                               0x0001D150
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_MASK                          0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_ITERATION_CURRENT_LSB       19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_ITERATION_CURRENT_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_ITERATION_CURRENT_MASK      0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_ITERATION_CURRENT_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_ITERATION_WRAP_LSB          13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_ITERATION_WRAP_WIDTH        6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_ITERATION_WRAP_MASK         0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_ITERATION_WRAP_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_ITERATION_STEPSIZE_LSB      0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_ITERATION_STEPSIZE_WIDTH    13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_ITERATION_STEPSIZE_MASK     0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_4_ITERATION_STEPSIZE_DEFVAL   0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5                               0x0001D154
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_MASK                          0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_TLAST_SUPPRESS_LSB          31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_TLAST_SUPPRESS_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_TLAST_SUPPRESS_MASK         0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_TLAST_SUPPRESS_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_NEXT_BD_LSB                 27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_NEXT_BD_WIDTH               4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_NEXT_BD_MASK                0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_USE_NEXT_BD_LSB             26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_USE_NEXT_BD_WIDTH           1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_USE_NEXT_BD_MASK            0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_USE_NEXT_BD_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_VALID_BD_LSB                25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_VALID_BD_WIDTH              1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_VALID_BD_MASK               0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_VALID_BD_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_REL_VALUE_LSB          18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_REL_VALUE_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_REL_VALUE_MASK         0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_REL_VALUE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_REL_ID_LSB             13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_REL_ID_WIDTH           4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_REL_ID_MASK            0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_REL_ID_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_ACQ_ENABLE_LSB         12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_ACQ_ENABLE_WIDTH       1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_ACQ_ENABLE_MASK        0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_ACQ_ENABLE_DEFVAL      0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_ACQ_VALUE_LSB          5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_ACQ_VALUE_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_ACQ_VALUE_MASK         0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_ACQ_VALUE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_ACQ_ID_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_ACQ_ID_WIDTH           4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_ACQ_ID_MASK            0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD10_5_LOCK_ACQ_ID_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_0                               0x0001D160
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_0_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_0_MASK                          0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_0_BASE_ADDRESS_LSB            14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_0_BASE_ADDRESS_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_0_BASE_ADDRESS_MASK           0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_0_BASE_ADDRESS_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_0_BUFFER_LENGTH_LSB           0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_0_BUFFER_LENGTH_WIDTH         14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_0_BUFFER_LENGTH_MASK          0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_0_BUFFER_LENGTH_DEFVAL        0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1                               0x0001D164
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_MASK                          0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_ENABLE_COMPRESSION_LSB      31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_ENABLE_COMPRESSION_WIDTH    1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_ENABLE_COMPRESSION_MASK     0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_ENABLE_COMPRESSION_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_ENABLE_PACKET_LSB           30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_ENABLE_PACKET_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_ENABLE_PACKET_MASK          0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_ENABLE_PACKET_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_OUT_OF_ORDER_BD_ID_LSB      24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_OUT_OF_ORDER_BD_ID_WIDTH    6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_OUT_OF_ORDER_BD_ID_MASK     0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_OUT_OF_ORDER_BD_ID_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_PACKET_ID_LSB               19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_PACKET_ID_WIDTH             5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_PACKET_ID_MASK              0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_PACKET_ID_DEFVAL            0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_PACKET_TYPE_LSB             16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_PACKET_TYPE_WIDTH           3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_PACKET_TYPE_MASK            0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_1_PACKET_TYPE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_2                               0x0001D168
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_2_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_2_MASK                          0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_2_D1_STEPSIZE_LSB             13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_2_D1_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_2_D1_STEPSIZE_MASK            0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_2_D1_STEPSIZE_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_2_D0_STEPSIZE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_2_D0_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_2_D0_STEPSIZE_MASK            0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_2_D0_STEPSIZE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3                               0x0001D16C
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_MASK                          0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_D1_WRAP_LSB                 21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_D1_WRAP_WIDTH               8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_D1_WRAP_MASK                0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_D1_WRAP_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_D0_WRAP_LSB                 13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_D0_WRAP_WIDTH               8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_D0_WRAP_MASK                0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_D0_WRAP_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_D2_STEPSIZE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_D2_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_D2_STEPSIZE_MASK            0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_3_D2_STEPSIZE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4                               0x0001D170
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_MASK                          0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_ITERATION_CURRENT_LSB       19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_ITERATION_CURRENT_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_ITERATION_CURRENT_MASK      0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_ITERATION_CURRENT_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_ITERATION_WRAP_LSB          13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_ITERATION_WRAP_WIDTH        6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_ITERATION_WRAP_MASK         0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_ITERATION_WRAP_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_ITERATION_STEPSIZE_LSB      0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_ITERATION_STEPSIZE_WIDTH    13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_ITERATION_STEPSIZE_MASK     0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_4_ITERATION_STEPSIZE_DEFVAL   0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5                               0x0001D174
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_MASK                          0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_TLAST_SUPPRESS_LSB          31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_TLAST_SUPPRESS_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_TLAST_SUPPRESS_MASK         0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_TLAST_SUPPRESS_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_NEXT_BD_LSB                 27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_NEXT_BD_WIDTH               4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_NEXT_BD_MASK                0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_USE_NEXT_BD_LSB             26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_USE_NEXT_BD_WIDTH           1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_USE_NEXT_BD_MASK            0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_USE_NEXT_BD_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_VALID_BD_LSB                25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_VALID_BD_WIDTH              1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_VALID_BD_MASK               0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_VALID_BD_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_REL_VALUE_LSB          18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_REL_VALUE_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_REL_VALUE_MASK         0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_REL_VALUE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_REL_ID_LSB             13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_REL_ID_WIDTH           4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_REL_ID_MASK            0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_REL_ID_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_ACQ_ENABLE_LSB         12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_ACQ_ENABLE_WIDTH       1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_ACQ_ENABLE_MASK        0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_ACQ_ENABLE_DEFVAL      0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_ACQ_VALUE_LSB          5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_ACQ_VALUE_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_ACQ_VALUE_MASK         0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_ACQ_VALUE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_ACQ_ID_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_ACQ_ID_WIDTH           4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_ACQ_ID_MASK            0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD11_5_LOCK_ACQ_ID_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_0                               0x0001D180
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_0_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_0_MASK                          0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_0_BASE_ADDRESS_LSB            14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_0_BASE_ADDRESS_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_0_BASE_ADDRESS_MASK           0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_0_BASE_ADDRESS_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_0_BUFFER_LENGTH_LSB           0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_0_BUFFER_LENGTH_WIDTH         14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_0_BUFFER_LENGTH_MASK          0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_0_BUFFER_LENGTH_DEFVAL        0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1                               0x0001D184
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_MASK                          0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_ENABLE_COMPRESSION_LSB      31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_ENABLE_COMPRESSION_WIDTH    1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_ENABLE_COMPRESSION_MASK     0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_ENABLE_COMPRESSION_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_ENABLE_PACKET_LSB           30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_ENABLE_PACKET_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_ENABLE_PACKET_MASK          0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_ENABLE_PACKET_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_OUT_OF_ORDER_BD_ID_LSB      24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_OUT_OF_ORDER_BD_ID_WIDTH    6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_OUT_OF_ORDER_BD_ID_MASK     0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_OUT_OF_ORDER_BD_ID_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_PACKET_ID_LSB               19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_PACKET_ID_WIDTH             5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_PACKET_ID_MASK              0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_PACKET_ID_DEFVAL            0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_PACKET_TYPE_LSB             16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_PACKET_TYPE_WIDTH           3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_PACKET_TYPE_MASK            0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_1_PACKET_TYPE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_2                               0x0001D188
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_2_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_2_MASK                          0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_2_D1_STEPSIZE_LSB             13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_2_D1_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_2_D1_STEPSIZE_MASK            0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_2_D1_STEPSIZE_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_2_D0_STEPSIZE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_2_D0_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_2_D0_STEPSIZE_MASK            0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_2_D0_STEPSIZE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3                               0x0001D18C
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_MASK                          0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_D1_WRAP_LSB                 21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_D1_WRAP_WIDTH               8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_D1_WRAP_MASK                0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_D1_WRAP_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_D0_WRAP_LSB                 13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_D0_WRAP_WIDTH               8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_D0_WRAP_MASK                0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_D0_WRAP_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_D2_STEPSIZE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_D2_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_D2_STEPSIZE_MASK            0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_3_D2_STEPSIZE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4                               0x0001D190
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_MASK                          0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_ITERATION_CURRENT_LSB       19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_ITERATION_CURRENT_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_ITERATION_CURRENT_MASK      0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_ITERATION_CURRENT_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_ITERATION_WRAP_LSB          13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_ITERATION_WRAP_WIDTH        6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_ITERATION_WRAP_MASK         0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_ITERATION_WRAP_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_ITERATION_STEPSIZE_LSB      0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_ITERATION_STEPSIZE_WIDTH    13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_ITERATION_STEPSIZE_MASK     0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_4_ITERATION_STEPSIZE_DEFVAL   0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5                               0x0001D194
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_MASK                          0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_TLAST_SUPPRESS_LSB          31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_TLAST_SUPPRESS_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_TLAST_SUPPRESS_MASK         0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_TLAST_SUPPRESS_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_NEXT_BD_LSB                 27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_NEXT_BD_WIDTH               4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_NEXT_BD_MASK                0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_USE_NEXT_BD_LSB             26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_USE_NEXT_BD_WIDTH           1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_USE_NEXT_BD_MASK            0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_USE_NEXT_BD_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_VALID_BD_LSB                25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_VALID_BD_WIDTH              1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_VALID_BD_MASK               0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_VALID_BD_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_REL_VALUE_LSB          18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_REL_VALUE_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_REL_VALUE_MASK         0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_REL_VALUE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_REL_ID_LSB             13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_REL_ID_WIDTH           4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_REL_ID_MASK            0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_REL_ID_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_ACQ_ENABLE_LSB         12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_ACQ_ENABLE_WIDTH       1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_ACQ_ENABLE_MASK        0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_ACQ_ENABLE_DEFVAL      0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_ACQ_VALUE_LSB          5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_ACQ_VALUE_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_ACQ_VALUE_MASK         0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_ACQ_VALUE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_ACQ_ID_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_ACQ_ID_WIDTH           4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_ACQ_ID_MASK            0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD12_5_LOCK_ACQ_ID_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_0                               0x0001D1A0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_0_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_0_MASK                          0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_0_BASE_ADDRESS_LSB            14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_0_BASE_ADDRESS_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_0_BASE_ADDRESS_MASK           0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_0_BASE_ADDRESS_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_0_BUFFER_LENGTH_LSB           0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_0_BUFFER_LENGTH_WIDTH         14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_0_BUFFER_LENGTH_MASK          0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_0_BUFFER_LENGTH_DEFVAL        0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1                               0x0001D1A4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_MASK                          0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_ENABLE_COMPRESSION_LSB      31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_ENABLE_COMPRESSION_WIDTH    1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_ENABLE_COMPRESSION_MASK     0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_ENABLE_COMPRESSION_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_ENABLE_PACKET_LSB           30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_ENABLE_PACKET_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_ENABLE_PACKET_MASK          0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_ENABLE_PACKET_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_OUT_OF_ORDER_BD_ID_LSB      24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_OUT_OF_ORDER_BD_ID_WIDTH    6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_OUT_OF_ORDER_BD_ID_MASK     0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_OUT_OF_ORDER_BD_ID_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_PACKET_ID_LSB               19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_PACKET_ID_WIDTH             5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_PACKET_ID_MASK              0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_PACKET_ID_DEFVAL            0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_PACKET_TYPE_LSB             16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_PACKET_TYPE_WIDTH           3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_PACKET_TYPE_MASK            0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_1_PACKET_TYPE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_2                               0x0001D1A8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_2_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_2_MASK                          0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_2_D1_STEPSIZE_LSB             13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_2_D1_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_2_D1_STEPSIZE_MASK            0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_2_D1_STEPSIZE_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_2_D0_STEPSIZE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_2_D0_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_2_D0_STEPSIZE_MASK            0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_2_D0_STEPSIZE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3                               0x0001D1AC
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_MASK                          0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_D1_WRAP_LSB                 21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_D1_WRAP_WIDTH               8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_D1_WRAP_MASK                0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_D1_WRAP_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_D0_WRAP_LSB                 13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_D0_WRAP_WIDTH               8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_D0_WRAP_MASK                0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_D0_WRAP_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_D2_STEPSIZE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_D2_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_D2_STEPSIZE_MASK            0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_3_D2_STEPSIZE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4                               0x0001D1B0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_MASK                          0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_ITERATION_CURRENT_LSB       19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_ITERATION_CURRENT_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_ITERATION_CURRENT_MASK      0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_ITERATION_CURRENT_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_ITERATION_WRAP_LSB          13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_ITERATION_WRAP_WIDTH        6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_ITERATION_WRAP_MASK         0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_ITERATION_WRAP_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_ITERATION_STEPSIZE_LSB      0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_ITERATION_STEPSIZE_WIDTH    13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_ITERATION_STEPSIZE_MASK     0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_4_ITERATION_STEPSIZE_DEFVAL   0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5                               0x0001D1B4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_MASK                          0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_TLAST_SUPPRESS_LSB          31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_TLAST_SUPPRESS_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_TLAST_SUPPRESS_MASK         0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_TLAST_SUPPRESS_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_NEXT_BD_LSB                 27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_NEXT_BD_WIDTH               4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_NEXT_BD_MASK                0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_USE_NEXT_BD_LSB             26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_USE_NEXT_BD_WIDTH           1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_USE_NEXT_BD_MASK            0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_USE_NEXT_BD_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_VALID_BD_LSB                25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_VALID_BD_WIDTH              1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_VALID_BD_MASK               0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_VALID_BD_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_REL_VALUE_LSB          18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_REL_VALUE_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_REL_VALUE_MASK         0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_REL_VALUE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_REL_ID_LSB             13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_REL_ID_WIDTH           4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_REL_ID_MASK            0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_REL_ID_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_ACQ_ENABLE_LSB         12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_ACQ_ENABLE_WIDTH       1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_ACQ_ENABLE_MASK        0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_ACQ_ENABLE_DEFVAL      0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_ACQ_VALUE_LSB          5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_ACQ_VALUE_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_ACQ_VALUE_MASK         0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_ACQ_VALUE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_ACQ_ID_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_ACQ_ID_WIDTH           4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_ACQ_ID_MASK            0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD13_5_LOCK_ACQ_ID_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_0                               0x0001D1C0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_0_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_0_MASK                          0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_0_BASE_ADDRESS_LSB            14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_0_BASE_ADDRESS_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_0_BASE_ADDRESS_MASK           0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_0_BASE_ADDRESS_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_0_BUFFER_LENGTH_LSB           0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_0_BUFFER_LENGTH_WIDTH         14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_0_BUFFER_LENGTH_MASK          0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_0_BUFFER_LENGTH_DEFVAL        0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1                               0x0001D1C4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_MASK                          0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_ENABLE_COMPRESSION_LSB      31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_ENABLE_COMPRESSION_WIDTH    1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_ENABLE_COMPRESSION_MASK     0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_ENABLE_COMPRESSION_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_ENABLE_PACKET_LSB           30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_ENABLE_PACKET_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_ENABLE_PACKET_MASK          0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_ENABLE_PACKET_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_OUT_OF_ORDER_BD_ID_LSB      24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_OUT_OF_ORDER_BD_ID_WIDTH    6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_OUT_OF_ORDER_BD_ID_MASK     0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_OUT_OF_ORDER_BD_ID_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_PACKET_ID_LSB               19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_PACKET_ID_WIDTH             5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_PACKET_ID_MASK              0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_PACKET_ID_DEFVAL            0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_PACKET_TYPE_LSB             16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_PACKET_TYPE_WIDTH           3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_PACKET_TYPE_MASK            0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_1_PACKET_TYPE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_2                               0x0001D1C8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_2_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_2_MASK                          0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_2_D1_STEPSIZE_LSB             13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_2_D1_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_2_D1_STEPSIZE_MASK            0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_2_D1_STEPSIZE_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_2_D0_STEPSIZE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_2_D0_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_2_D0_STEPSIZE_MASK            0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_2_D0_STEPSIZE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3                               0x0001D1CC
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_MASK                          0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_D1_WRAP_LSB                 21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_D1_WRAP_WIDTH               8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_D1_WRAP_MASK                0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_D1_WRAP_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_D0_WRAP_LSB                 13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_D0_WRAP_WIDTH               8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_D0_WRAP_MASK                0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_D0_WRAP_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_D2_STEPSIZE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_D2_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_D2_STEPSIZE_MASK            0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_3_D2_STEPSIZE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4                               0x0001D1D0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_MASK                          0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_ITERATION_CURRENT_LSB       19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_ITERATION_CURRENT_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_ITERATION_CURRENT_MASK      0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_ITERATION_CURRENT_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_ITERATION_WRAP_LSB          13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_ITERATION_WRAP_WIDTH        6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_ITERATION_WRAP_MASK         0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_ITERATION_WRAP_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_ITERATION_STEPSIZE_LSB      0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_ITERATION_STEPSIZE_WIDTH    13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_ITERATION_STEPSIZE_MASK     0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_4_ITERATION_STEPSIZE_DEFVAL   0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5                               0x0001D1D4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_MASK                          0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_TLAST_SUPPRESS_LSB          31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_TLAST_SUPPRESS_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_TLAST_SUPPRESS_MASK         0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_TLAST_SUPPRESS_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_NEXT_BD_LSB                 27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_NEXT_BD_WIDTH               4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_NEXT_BD_MASK                0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_USE_NEXT_BD_LSB             26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_USE_NEXT_BD_WIDTH           1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_USE_NEXT_BD_MASK            0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_USE_NEXT_BD_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_VALID_BD_LSB                25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_VALID_BD_WIDTH              1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_VALID_BD_MASK               0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_VALID_BD_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_REL_VALUE_LSB          18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_REL_VALUE_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_REL_VALUE_MASK         0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_REL_VALUE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_REL_ID_LSB             13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_REL_ID_WIDTH           4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_REL_ID_MASK            0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_REL_ID_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_ACQ_ENABLE_LSB         12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_ACQ_ENABLE_WIDTH       1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_ACQ_ENABLE_MASK        0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_ACQ_ENABLE_DEFVAL      0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_ACQ_VALUE_LSB          5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_ACQ_VALUE_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_ACQ_VALUE_MASK         0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_ACQ_VALUE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_ACQ_ID_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_ACQ_ID_WIDTH           4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_ACQ_ID_MASK            0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD14_5_LOCK_ACQ_ID_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_0                               0x0001D1E0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_0_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_0_MASK                          0x0FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_0_BASE_ADDRESS_LSB            14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_0_BASE_ADDRESS_WIDTH          14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_0_BASE_ADDRESS_MASK           0x0FFFC000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_0_BASE_ADDRESS_DEFVAL         0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_0_BUFFER_LENGTH_LSB           0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_0_BUFFER_LENGTH_WIDTH         14
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_0_BUFFER_LENGTH_MASK          0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_0_BUFFER_LENGTH_DEFVAL        0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1                               0x0001D1E4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_MASK                          0xFFFF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_ENABLE_COMPRESSION_LSB      31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_ENABLE_COMPRESSION_WIDTH    1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_ENABLE_COMPRESSION_MASK     0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_ENABLE_COMPRESSION_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_ENABLE_PACKET_LSB           30
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_ENABLE_PACKET_WIDTH         1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_ENABLE_PACKET_MASK          0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_ENABLE_PACKET_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_OUT_OF_ORDER_BD_ID_LSB      24
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_OUT_OF_ORDER_BD_ID_WIDTH    6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_OUT_OF_ORDER_BD_ID_MASK     0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_OUT_OF_ORDER_BD_ID_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_PACKET_ID_LSB               19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_PACKET_ID_WIDTH             5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_PACKET_ID_MASK              0x00F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_PACKET_ID_DEFVAL            0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_PACKET_TYPE_LSB             16
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_PACKET_TYPE_WIDTH           3
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_PACKET_TYPE_MASK            0x00070000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_1_PACKET_TYPE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_2                               0x0001D1E8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_2_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_2_MASK                          0x03FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_2_D1_STEPSIZE_LSB             13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_2_D1_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_2_D1_STEPSIZE_MASK            0x03FFE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_2_D1_STEPSIZE_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_2_D0_STEPSIZE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_2_D0_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_2_D0_STEPSIZE_MASK            0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_2_D0_STEPSIZE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3                               0x0001D1EC
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_MASK                          0x1FFFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_D1_WRAP_LSB                 21
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_D1_WRAP_WIDTH               8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_D1_WRAP_MASK                0x1FE00000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_D1_WRAP_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_D0_WRAP_LSB                 13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_D0_WRAP_WIDTH               8
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_D0_WRAP_MASK                0x001FE000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_D0_WRAP_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_D2_STEPSIZE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_D2_STEPSIZE_WIDTH           13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_D2_STEPSIZE_MASK            0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_3_D2_STEPSIZE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4                               0x0001D1F0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_MASK                          0x01FFFFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_ITERATION_CURRENT_LSB       19
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_ITERATION_CURRENT_WIDTH     6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_ITERATION_CURRENT_MASK      0x01F80000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_ITERATION_CURRENT_DEFVAL    0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_ITERATION_WRAP_LSB          13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_ITERATION_WRAP_WIDTH        6
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_ITERATION_WRAP_MASK         0x0007E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_ITERATION_WRAP_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_ITERATION_STEPSIZE_LSB      0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_ITERATION_STEPSIZE_WIDTH    13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_ITERATION_STEPSIZE_MASK     0x00001FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_4_ITERATION_STEPSIZE_DEFVAL   0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5                               0x0001D1F4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_WIDTH                         32
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_MASK                          0xFFFDFFEF
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_TLAST_SUPPRESS_LSB          31
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_TLAST_SUPPRESS_WIDTH        1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_TLAST_SUPPRESS_MASK         0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_TLAST_SUPPRESS_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_NEXT_BD_LSB                 27
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_NEXT_BD_WIDTH               4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_NEXT_BD_MASK                0x78000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_USE_NEXT_BD_LSB             26
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_USE_NEXT_BD_WIDTH           1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_USE_NEXT_BD_MASK            0x04000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_USE_NEXT_BD_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_VALID_BD_LSB                25
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_VALID_BD_WIDTH              1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_VALID_BD_MASK               0x02000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_VALID_BD_DEFVAL             0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_REL_VALUE_LSB          18
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_REL_VALUE_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_REL_VALUE_MASK         0x01FC0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_REL_VALUE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_REL_ID_LSB             13
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_REL_ID_WIDTH           4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_REL_ID_MASK            0x0001E000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_REL_ID_DEFVAL          0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_ACQ_ENABLE_LSB         12
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_ACQ_ENABLE_WIDTH       1
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_ACQ_ENABLE_MASK        0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_ACQ_ENABLE_DEFVAL      0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_ACQ_VALUE_LSB          5
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_ACQ_VALUE_WIDTH        7
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_ACQ_VALUE_MASK         0x00000FE0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_ACQ_VALUE_DEFVAL       0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_ACQ_ID_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_ACQ_ID_WIDTH           4
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_ACQ_ID_MASK            0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_BD15_5_LOCK_ACQ_ID_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL                          0x0001DE00
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_WIDTH                    32
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_MASK                     0x0003FF1B
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_FOT_MODE_LSB           16
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_FOT_MODE_WIDTH         2
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_FOT_MODE_MASK          0x00030000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_FOT_MODE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_CONTROLLER_ID_LSB      8
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_CONTROLLER_ID_WIDTH    8
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_CONTROLLER_ID_MASK     0x0000FF00
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_CONTROLLER_ID_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_DECOMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_DECOMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_DECOMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_DECOMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_ENABLE_OUT_OF_ORDER_LSB 3
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_ENABLE_OUT_OF_ORDER_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_ENABLE_OUT_OF_ORDER_MASK 0x00000008
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_ENABLE_OUT_OF_ORDER_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_RESET_LSB              1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_RESET_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_RESET_MASK             0x00000002
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_CTRL_RESET_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE                   0x0001DE04
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_WIDTH             32
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_MASK              0x80FF000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_START_BD_ID_WIDTH 4
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_START_BD_ID_MASK 0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_0_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL                          0x0001DE08
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_WIDTH                    32
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_MASK                     0x0003FF1B
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_FOT_MODE_LSB           16
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_FOT_MODE_WIDTH         2
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_FOT_MODE_MASK          0x00030000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_FOT_MODE_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_CONTROLLER_ID_LSB      8
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_CONTROLLER_ID_WIDTH    8
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_CONTROLLER_ID_MASK     0x0000FF00
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_CONTROLLER_ID_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_DECOMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_DECOMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_DECOMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_DECOMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_ENABLE_OUT_OF_ORDER_LSB 3
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_ENABLE_OUT_OF_ORDER_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_ENABLE_OUT_OF_ORDER_MASK 0x00000008
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_ENABLE_OUT_OF_ORDER_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_RESET_LSB              1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_RESET_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_RESET_MASK             0x00000002
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_CTRL_RESET_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE                   0x0001DE0C
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_WIDTH             32
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_MASK              0x80FF000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_START_BD_ID_WIDTH 4
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_START_BD_ID_MASK 0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_1_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL                          0x0001DE10
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_WIDTH                    32
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_MASK                     0x0000FF13
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_CONTROLLER_ID_LSB      8
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_CONTROLLER_ID_WIDTH    8
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_CONTROLLER_ID_MASK     0x0000FF00
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_CONTROLLER_ID_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_COMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_COMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_COMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_COMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_RESET_LSB              1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_RESET_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_RESET_MASK             0x00000002
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_CTRL_RESET_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE                   0x0001DE14
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_WIDTH             32
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_MASK              0x80FF000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_START_BD_ID_WIDTH 4
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_START_BD_ID_MASK 0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_0_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL                          0x0001DE18
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_WIDTH                    32
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_MASK                     0x0000FF13
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_CONTROLLER_ID_LSB      8
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_CONTROLLER_ID_WIDTH    8
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_CONTROLLER_ID_MASK     0x0000FF00
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_CONTROLLER_ID_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_COMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_COMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_COMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_COMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_RESET_LSB              1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_RESET_WIDTH            1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_RESET_MASK             0x00000002
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_CTRL_RESET_DEFVAL           0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE                   0x0001DE1C
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_WIDTH             32
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_MASK              0x80FF000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_START_BD_ID_WIDTH 4
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_START_BD_ID_MASK 0x0000000F
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_1_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0                        0x0001DF00
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_WIDTH                  32
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_MASK                   0x0F7C3C3F
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_CUR_BD_LSB           24
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_CUR_BD_WIDTH         4
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_CUR_BD_MASK          0x0F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_CUR_BD_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_SIZE_LSB  20
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_CHANNEL_RUNNING_LSB  19
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_BDS_PER_TASK_LSB 13
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_BDS_PER_TASK_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_BDS_PER_TASK_MASK 0x00002000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_BDS_PER_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_LENGTH_EXCEEDED_LSB 12
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_LENGTH_EXCEEDED_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_LENGTH_EXCEEDED_MASK 0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_LENGTH_EXCEEDED_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_TCT_OR_COUNT_FIFO_FULL_LSB 5
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_TCT_OR_COUNT_FIFO_FULL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_TCT_OR_COUNT_FIFO_FULL_MASK 0x00000020
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_TCT_OR_COUNT_FIFO_FULL_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_STREAM_STARVATION_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_STREAM_STARVATION_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_STREAM_STARVATION_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STATUS_LSB           0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STATUS_WIDTH         2
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STATUS_MASK          0x00000003
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_0_STATUS_DEFVAL        0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1                        0x0001DF04
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_WIDTH                  32
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_MASK                   0x0F7C3C3F
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_CUR_BD_LSB           24
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_CUR_BD_WIDTH         4
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_CUR_BD_MASK          0x0F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_CUR_BD_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_SIZE_LSB  20
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_CHANNEL_RUNNING_LSB  19
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_BDS_PER_TASK_LSB 13
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_BDS_PER_TASK_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_BDS_PER_TASK_MASK 0x00002000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_BDS_PER_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_LENGTH_EXCEEDED_LSB 12
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_LENGTH_EXCEEDED_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_LENGTH_EXCEEDED_MASK 0x00001000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_LENGTH_EXCEEDED_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_TCT_OR_COUNT_FIFO_FULL_LSB 5
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_TCT_OR_COUNT_FIFO_FULL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_TCT_OR_COUNT_FIFO_FULL_MASK 0x00000020
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_TCT_OR_COUNT_FIFO_FULL_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_STREAM_STARVATION_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_STREAM_STARVATION_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_STREAM_STARVATION_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STATUS_LSB           0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STATUS_WIDTH         2
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STATUS_MASK          0x00000003
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_STATUS_1_STATUS_DEFVAL        0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0                        0x0001DF10
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_WIDTH                  32
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_MASK                   0x0F7C083F
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_CUR_BD_LSB           24
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_CUR_BD_WIDTH         4
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_CUR_BD_MASK          0x0F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_CUR_BD_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_SIZE_LSB  20
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_CHANNEL_RUNNING_LSB  19
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_TCT_LSB      5
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_TCT_WIDTH    1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_TCT_MASK     0x00000020
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_TCT_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_STREAM_BACKPRESSURE_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_STREAM_BACKPRESSURE_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_STREAM_BACKPRESSURE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STATUS_LSB           0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STATUS_WIDTH         2
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STATUS_MASK          0x00000003
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_0_STATUS_DEFVAL        0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1                        0x0001DF14
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_WIDTH                  32
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_MASK                   0x0F7C083F
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_CUR_BD_LSB           24
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_CUR_BD_WIDTH         4
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_CUR_BD_MASK          0x0F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_CUR_BD_DEFVAL        0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_SIZE_LSB  20
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_CHANNEL_RUNNING_LSB  19
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_TCT_LSB      5
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_TCT_WIDTH    1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_TCT_MASK     0x00000020
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_TCT_DEFVAL   0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_STREAM_BACKPRESSURE_LSB 4
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_STREAM_BACKPRESSURE_MASK 0x00000010
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_STREAM_BACKPRESSURE_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STATUS_LSB           0
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STATUS_WIDTH         2
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STATUS_MASK          0x00000003
#define XAIEMLGBL_MEMORY_MODULE_DMA_MM2S_STATUS_1_STATUS_DEFVAL        0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0           0x0001DF18
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_WIDTH     32
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_MASK      0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_CURRENT_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_CURRENT_WRITE_COUNT_WIDTH 14
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_CURRENT_WRITE_COUNT_MASK 0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_CURRENT_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1           0x0001DF1C
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_WIDTH     32
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_MASK      0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_CURRENT_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_CURRENT_WRITE_COUNT_WIDTH 14
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_CURRENT_WRITE_COUNT_MASK 0x00003FFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_CURRENT_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0            0x0001DF20
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WIDTH      32
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_MASK       0xFF03FFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_VALID_LSB 31
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_VALID_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_VALID_MASK 0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_VALID_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_LAST_IN_TASK_LSB 30
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_LAST_IN_TASK_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_LAST_IN_TASK_MASK 0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_LAST_IN_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_BD_ID_LSB 24
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_BD_ID_WIDTH 6
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_BD_ID_MASK 0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WRITE_COUNT_WIDTH 18
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WRITE_COUNT_MASK 0x0003FFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1            0x0001DF24
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WIDTH      32
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_MASK       0xFF03FFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_VALID_LSB 31
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_VALID_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_VALID_MASK 0x80000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_VALID_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_LAST_IN_TASK_LSB 30
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_LAST_IN_TASK_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_LAST_IN_TASK_MASK 0x40000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_LAST_IN_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_BD_ID_LSB 24
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_BD_ID_WIDTH 6
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_BD_ID_MASK 0x3F000000
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WRITE_COUNT_WIDTH 18
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WRITE_COUNT_MASK 0x0003FFFF
#define XAIEMLGBL_MEMORY_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK0_VALUE                              0x0001F000
#define XAIEMLGBL_MEMORY_MODULE_LOCK0_VALUE_WIDTH                        32
#define XAIEMLGBL_MEMORY_MODULE_LOCK0_VALUE_MASK                         0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK0_VALUE_LOCK_VALUE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_LOCK0_VALUE_LOCK_VALUE_WIDTH           6
#define XAIEMLGBL_MEMORY_MODULE_LOCK0_VALUE_LOCK_VALUE_MASK            0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK0_VALUE_LOCK_VALUE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK1_VALUE                              0x0001F010
#define XAIEMLGBL_MEMORY_MODULE_LOCK1_VALUE_WIDTH                        32
#define XAIEMLGBL_MEMORY_MODULE_LOCK1_VALUE_MASK                         0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK1_VALUE_LOCK_VALUE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_LOCK1_VALUE_LOCK_VALUE_WIDTH           6
#define XAIEMLGBL_MEMORY_MODULE_LOCK1_VALUE_LOCK_VALUE_MASK            0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK1_VALUE_LOCK_VALUE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK2_VALUE                              0x0001F020
#define XAIEMLGBL_MEMORY_MODULE_LOCK2_VALUE_WIDTH                        32
#define XAIEMLGBL_MEMORY_MODULE_LOCK2_VALUE_MASK                         0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK2_VALUE_LOCK_VALUE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_LOCK2_VALUE_LOCK_VALUE_WIDTH           6
#define XAIEMLGBL_MEMORY_MODULE_LOCK2_VALUE_LOCK_VALUE_MASK            0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK2_VALUE_LOCK_VALUE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK3_VALUE                              0x0001F030
#define XAIEMLGBL_MEMORY_MODULE_LOCK3_VALUE_WIDTH                        32
#define XAIEMLGBL_MEMORY_MODULE_LOCK3_VALUE_MASK                         0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK3_VALUE_LOCK_VALUE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_LOCK3_VALUE_LOCK_VALUE_WIDTH           6
#define XAIEMLGBL_MEMORY_MODULE_LOCK3_VALUE_LOCK_VALUE_MASK            0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK3_VALUE_LOCK_VALUE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK4_VALUE                              0x0001F040
#define XAIEMLGBL_MEMORY_MODULE_LOCK4_VALUE_WIDTH                        32
#define XAIEMLGBL_MEMORY_MODULE_LOCK4_VALUE_MASK                         0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK4_VALUE_LOCK_VALUE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_LOCK4_VALUE_LOCK_VALUE_WIDTH           6
#define XAIEMLGBL_MEMORY_MODULE_LOCK4_VALUE_LOCK_VALUE_MASK            0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK4_VALUE_LOCK_VALUE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK5_VALUE                              0x0001F050
#define XAIEMLGBL_MEMORY_MODULE_LOCK5_VALUE_WIDTH                        32
#define XAIEMLGBL_MEMORY_MODULE_LOCK5_VALUE_MASK                         0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK5_VALUE_LOCK_VALUE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_LOCK5_VALUE_LOCK_VALUE_WIDTH           6
#define XAIEMLGBL_MEMORY_MODULE_LOCK5_VALUE_LOCK_VALUE_MASK            0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK5_VALUE_LOCK_VALUE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK6_VALUE                              0x0001F060
#define XAIEMLGBL_MEMORY_MODULE_LOCK6_VALUE_WIDTH                        32
#define XAIEMLGBL_MEMORY_MODULE_LOCK6_VALUE_MASK                         0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK6_VALUE_LOCK_VALUE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_LOCK6_VALUE_LOCK_VALUE_WIDTH           6
#define XAIEMLGBL_MEMORY_MODULE_LOCK6_VALUE_LOCK_VALUE_MASK            0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK6_VALUE_LOCK_VALUE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK7_VALUE                              0x0001F070
#define XAIEMLGBL_MEMORY_MODULE_LOCK7_VALUE_WIDTH                        32
#define XAIEMLGBL_MEMORY_MODULE_LOCK7_VALUE_MASK                         0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK7_VALUE_LOCK_VALUE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_LOCK7_VALUE_LOCK_VALUE_WIDTH           6
#define XAIEMLGBL_MEMORY_MODULE_LOCK7_VALUE_LOCK_VALUE_MASK            0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK7_VALUE_LOCK_VALUE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK8_VALUE                              0x0001F080
#define XAIEMLGBL_MEMORY_MODULE_LOCK8_VALUE_WIDTH                        32
#define XAIEMLGBL_MEMORY_MODULE_LOCK8_VALUE_MASK                         0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK8_VALUE_LOCK_VALUE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_LOCK8_VALUE_LOCK_VALUE_WIDTH           6
#define XAIEMLGBL_MEMORY_MODULE_LOCK8_VALUE_LOCK_VALUE_MASK            0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK8_VALUE_LOCK_VALUE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK9_VALUE                              0x0001F090
#define XAIEMLGBL_MEMORY_MODULE_LOCK9_VALUE_WIDTH                        32
#define XAIEMLGBL_MEMORY_MODULE_LOCK9_VALUE_MASK                         0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK9_VALUE_LOCK_VALUE_LSB             0
#define XAIEMLGBL_MEMORY_MODULE_LOCK9_VALUE_LOCK_VALUE_WIDTH           6
#define XAIEMLGBL_MEMORY_MODULE_LOCK9_VALUE_LOCK_VALUE_MASK            0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK9_VALUE_LOCK_VALUE_DEFVAL          0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK10_VALUE                             0x0001F0A0
#define XAIEMLGBL_MEMORY_MODULE_LOCK10_VALUE_WIDTH                       32
#define XAIEMLGBL_MEMORY_MODULE_LOCK10_VALUE_MASK                        0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK10_VALUE_LOCK_VALUE_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_LOCK10_VALUE_LOCK_VALUE_WIDTH          6
#define XAIEMLGBL_MEMORY_MODULE_LOCK10_VALUE_LOCK_VALUE_MASK           0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK10_VALUE_LOCK_VALUE_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK11_VALUE                             0x0001F0B0
#define XAIEMLGBL_MEMORY_MODULE_LOCK11_VALUE_WIDTH                       32
#define XAIEMLGBL_MEMORY_MODULE_LOCK11_VALUE_MASK                        0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK11_VALUE_LOCK_VALUE_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_LOCK11_VALUE_LOCK_VALUE_WIDTH          6
#define XAIEMLGBL_MEMORY_MODULE_LOCK11_VALUE_LOCK_VALUE_MASK           0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK11_VALUE_LOCK_VALUE_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK12_VALUE                             0x0001F0C0
#define XAIEMLGBL_MEMORY_MODULE_LOCK12_VALUE_WIDTH                       32
#define XAIEMLGBL_MEMORY_MODULE_LOCK12_VALUE_MASK                        0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK12_VALUE_LOCK_VALUE_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_LOCK12_VALUE_LOCK_VALUE_WIDTH          6
#define XAIEMLGBL_MEMORY_MODULE_LOCK12_VALUE_LOCK_VALUE_MASK           0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK12_VALUE_LOCK_VALUE_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK13_VALUE                             0x0001F0D0
#define XAIEMLGBL_MEMORY_MODULE_LOCK13_VALUE_WIDTH                       32
#define XAIEMLGBL_MEMORY_MODULE_LOCK13_VALUE_MASK                        0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK13_VALUE_LOCK_VALUE_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_LOCK13_VALUE_LOCK_VALUE_WIDTH          6
#define XAIEMLGBL_MEMORY_MODULE_LOCK13_VALUE_LOCK_VALUE_MASK           0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK13_VALUE_LOCK_VALUE_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK14_VALUE                             0x0001F0E0
#define XAIEMLGBL_MEMORY_MODULE_LOCK14_VALUE_WIDTH                       32
#define XAIEMLGBL_MEMORY_MODULE_LOCK14_VALUE_MASK                        0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK14_VALUE_LOCK_VALUE_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_LOCK14_VALUE_LOCK_VALUE_WIDTH          6
#define XAIEMLGBL_MEMORY_MODULE_LOCK14_VALUE_LOCK_VALUE_MASK           0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK14_VALUE_LOCK_VALUE_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK15_VALUE                             0x0001F0F0
#define XAIEMLGBL_MEMORY_MODULE_LOCK15_VALUE_WIDTH                       32
#define XAIEMLGBL_MEMORY_MODULE_LOCK15_VALUE_MASK                        0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK15_VALUE_LOCK_VALUE_LSB            0
#define XAIEMLGBL_MEMORY_MODULE_LOCK15_VALUE_LOCK_VALUE_WIDTH          6
#define XAIEMLGBL_MEMORY_MODULE_LOCK15_VALUE_LOCK_VALUE_MASK           0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCK15_VALUE_LOCK_VALUE_DEFVAL         0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_0                  0x0001F100
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_0_WIDTH            32
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_0_MASK             0x000F003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_SELECT_MASK 0x000F0000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_1                  0x0001F104
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_1_WIDTH            32
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_1_MASK             0x000F003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_SELECT_MASK 0x000F0000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_2                  0x0001F108
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_2_WIDTH            32
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_2_MASK             0x000F003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_SELECT_MASK 0x000F0000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_3                  0x0001F10C
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_3_WIDTH            32
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_3_MASK             0x000F003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_SELECT_MASK 0x000F0000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_4                  0x0001F110
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_4_WIDTH            32
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_4_MASK             0x000F003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_SELECT_MASK 0x000F0000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_5                  0x0001F114
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_5_WIDTH            32
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_5_MASK             0x000F003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_SELECT_MASK 0x000F0000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_6                  0x0001F118
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_6_WIDTH            32
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_6_MASK             0x000F003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_SELECT_MASK 0x000F0000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_7                  0x0001F11C
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_7_WIDTH            32
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_7_MASK             0x000F003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_SELECT_MASK 0x000F0000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW                           0x0001F120
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_WIDTH                     32
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_MASK                      0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_15_LSB    15
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_15_WIDTH  1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_15_MASK   0x00008000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_15_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_14_LSB    14
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_14_WIDTH  1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_14_MASK   0x00004000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_14_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_13_LSB    13
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_13_WIDTH  1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_13_MASK   0x00002000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_13_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_12_LSB    12
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_12_WIDTH  1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_12_MASK   0x00001000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_12_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_11_LSB    11
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_11_WIDTH  1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_11_MASK   0x00000800
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_11_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_10_LSB    10
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_10_WIDTH  1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_10_MASK   0x00000400
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_10_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_9_LSB     9
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_9_WIDTH   1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_9_MASK    0x00000200
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_9_DEFVAL  0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_8_LSB     8
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_8_WIDTH   1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_8_MASK    0x00000100
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_8_DEFVAL  0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_7_LSB     7
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_7_WIDTH   1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_7_MASK    0x00000080
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_7_DEFVAL  0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_6_LSB     6
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_6_WIDTH   1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_6_MASK    0x00000040
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_6_DEFVAL  0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_5_LSB     5
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_5_WIDTH   1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_5_MASK    0x00000020
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_5_DEFVAL  0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_4_LSB     4
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_4_WIDTH   1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_4_MASK    0x00000010
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_4_DEFVAL  0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_3_LSB     3
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_3_WIDTH   1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_3_MASK    0x00000008
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_3_DEFVAL  0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_2_LSB     2
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_2_WIDTH   1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_2_MASK    0x00000004
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_2_DEFVAL  0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_1_LSB     1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_1_WIDTH   1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_1_MASK    0x00000002
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_1_DEFVAL  0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_0_LSB     0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_0_WIDTH   1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_0_MASK    0x00000001
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_0_DEFVAL  0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW                          0x0001F128
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_WIDTH                    32
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_MASK                     0x0000FFFF
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_15_LSB  15
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_15_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_15_MASK 0x00008000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_15_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_14_LSB  14
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_14_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_14_MASK 0x00004000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_14_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_13_LSB  13
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_13_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_13_MASK 0x00002000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_13_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_12_LSB  12
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_12_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_12_MASK 0x00001000
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_12_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_11_LSB  11
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_11_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_11_MASK 0x00000800
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_11_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_10_LSB  10
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_10_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_10_MASK 0x00000400
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_10_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_9_LSB   9
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_9_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_9_MASK  0x00000200
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_9_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_8_LSB   8
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_8_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_8_MASK  0x00000100
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_8_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_7_LSB   7
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_7_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_7_MASK  0x00000080
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_7_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_6_LSB   6
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_6_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_6_MASK  0x00000040
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_6_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_5_LSB   5
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_5_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_5_MASK  0x00000020
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_5_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_4_LSB   4
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_4_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_4_MASK  0x00000010
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_4_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_3_LSB   3
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_3_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_3_MASK  0x00000008
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_3_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_2_LSB   2
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_2_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_2_MASK  0x00000004
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_2_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_1_LSB   1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_1_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_1_MASK  0x00000002
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_1_DEFVAL 0x0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_0_LSB   0
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_0_WIDTH 1
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_0_MASK  0x00000001
#define XAIEMLGBL_MEMORY_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_0_DEFVAL 0x0

#define XAIEMLGBL_MEMORY_MODULE_LOCK_REQUEST                             0x00040000
#define XAIEMLGBL_MEMORY_MODULE_LOCK_REQUEST_WIDTH                       32
#define XAIEMLGBL_MEMORY_MODULE_LOCK_REQUEST_MASK                        0x00000001
#define XAIEMLGBL_MEMORY_MODULE_LOCK_REQUEST_REQUEST_RESULT_LSB        0
#define XAIEMLGBL_MEMORY_MODULE_LOCK_REQUEST_REQUEST_RESULT_WIDTH      1
#define XAIEMLGBL_MEMORY_MODULE_LOCK_REQUEST_REQUEST_RESULT_MASK       0x00000001
#define XAIEMLGBL_MEMORY_MODULE_LOCK_REQUEST_REQUEST_RESULT_DEFVAL     0x0

/* AIE-ML PL module register definitions */
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0                            0x00031000
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_WIDTH                      32
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_MASK                       0x7F7F7F7F
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT1_STOP_EVENT_LSB      24
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT1_STOP_EVENT_WIDTH    7
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT1_STOP_EVENT_MASK     0x7F000000
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT1_STOP_EVENT_DEFVAL   0x0
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT1_START_EVENT_LSB     16
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT1_START_EVENT_WIDTH   7
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT1_START_EVENT_MASK    0x007F0000
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT1_START_EVENT_DEFVAL  0x0
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT0_STOP_EVENT_LSB      8
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT0_STOP_EVENT_WIDTH    7
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT0_STOP_EVENT_MASK     0x00007F00
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT0_STOP_EVENT_DEFVAL   0x0
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT0_START_EVENT_LSB     0
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT0_START_EVENT_WIDTH   7
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT0_START_EVENT_MASK    0x0000007F
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL0_CNT0_START_EVENT_DEFVAL  0x0

#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL1                            0x00031008
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL1_WIDTH                      32
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL1_MASK                       0x00007F7F
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL1_CNT1_RESET_EVENT_LSB     8
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL1_CNT1_RESET_EVENT_WIDTH   7
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL1_CNT1_RESET_EVENT_MASK    0x00007F00
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL1_CNT1_RESET_EVENT_DEFVAL  0x0
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL1_CNT0_RESET_EVENT_LSB     0
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL1_CNT0_RESET_EVENT_WIDTH   7
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL1_CNT0_RESET_EVENT_MASK    0x0000007F
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_CTRL1_CNT0_RESET_EVENT_DEFVAL  0x0

#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0                         0x00031020
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0_WIDTH                   32
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0_MASK                    0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_LSB    0
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_WIDTH  32
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_MASK   0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1                         0x00031024
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1_WIDTH                   32
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1_MASK                    0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1_COUNTER0_VALUE_LSB    0
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1_COUNTER0_VALUE_WIDTH  32
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1_COUNTER0_VALUE_MASK   0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1_COUNTER0_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE             0x00031080
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_WIDTH       32
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_MASK        0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER_EVENT_VALUE_LSB 0
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER_EVENT_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER_EVENT_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE             0x00031084
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_WIDTH       32
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_MASK        0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER_EVENT_VALUE_LSB 0
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER_EVENT_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER_EVENT_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG                  0x00033000
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_WIDTH            32
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_MASK             0x000001FF
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH4_SOUTH5_128_COMBINE_LSB 8
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH4_SOUTH5_128_COMBINE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH4_SOUTH5_128_COMBINE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH4_SOUTH5_128_COMBINE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH5_LSB     7
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH5_WIDTH   1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH5_MASK    0x00000080
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH5_DEFVAL  0x1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH4_LSB     6
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH4_WIDTH   1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH4_MASK    0x00000040
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH4_DEFVAL  0x1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH2_SOUTH3_128_COMBINE_LSB 5
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH2_SOUTH3_128_COMBINE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH2_SOUTH3_128_COMBINE_MASK 0x00000020
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH2_SOUTH3_128_COMBINE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH3_LSB     4
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH3_WIDTH   1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH3_MASK    0x00000010
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH3_DEFVAL  0x1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH2_LSB     3
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH2_WIDTH   1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH2_MASK    0x00000008
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH2_DEFVAL  0x1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH0_SOUTH1_128_COMBINE_LSB 2
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH0_SOUTH1_128_COMBINE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH0_SOUTH1_128_COMBINE_MASK 0x00000004
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH0_SOUTH1_128_COMBINE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH1_LSB     1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH1_WIDTH   1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH1_MASK    0x00000002
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH1_DEFVAL  0x1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH0_LSB     0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH0_WIDTH   1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH0_MASK    0x00000001
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_UPSIZER_CONFIG_SOUTH0_DEFVAL  0x1

#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG                0x00033004
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_WIDTH          32
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_MASK           0x00000FFF
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH6_SOUTH7_128_COMBINE_LSB 11
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH6_SOUTH7_128_COMBINE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH6_SOUTH7_128_COMBINE_MASK 0x00000800
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH6_SOUTH7_128_COMBINE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH7_LSB   10
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH7_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH7_MASK  0x00000400
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH7_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH6_LSB   9
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH6_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH6_MASK  0x00000200
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH6_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH4_SOUTH5_128_COMBINE_LSB 8
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH4_SOUTH5_128_COMBINE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH4_SOUTH5_128_COMBINE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH4_SOUTH5_128_COMBINE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH5_LSB   7
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH5_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH5_MASK  0x00000080
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH5_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH4_LSB   6
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH4_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH4_MASK  0x00000040
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH4_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH2_SOUTH3_128_COMBINE_LSB 5
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH2_SOUTH3_128_COMBINE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH2_SOUTH3_128_COMBINE_MASK 0x00000020
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH2_SOUTH3_128_COMBINE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH3_LSB   4
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH3_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH3_MASK  0x00000010
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH3_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH2_LSB   3
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH2_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH2_MASK  0x00000008
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH2_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH0_SOUTH1_128_COMBINE_LSB 2
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH0_SOUTH1_128_COMBINE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH0_SOUTH1_128_COMBINE_MASK 0x00000004
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH0_SOUTH1_128_COMBINE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH1_LSB   1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH1_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH1_MASK  0x00000002
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH1_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH0_LSB   0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH0_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH0_MASK  0x00000001
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_CONFIG_SOUTH0_DEFVAL 0x1

#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE                0x00033008
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_WIDTH          32
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_MASK           0x000000FF
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH7_LSB   7
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH7_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH7_MASK  0x00000080
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH7_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH6_LSB   6
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH6_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH6_MASK  0x00000040
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH6_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH5_LSB   5
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH5_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH5_MASK  0x00000020
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH5_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH4_LSB   4
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH4_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH4_MASK  0x00000010
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH4_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH3_LSB   3
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH3_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH3_MASK  0x00000008
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH3_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH2_LSB   2
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH2_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH2_MASK  0x00000004
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH2_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH1_LSB   1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH1_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH1_MASK  0x00000002
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH1_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH0_LSB   0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH0_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH0_MASK  0x00000001
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_ENABLE_SOUTH0_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS                0x0003300C
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_WIDTH          32
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_MASK           0x0000003F
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH6_LSB   5
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH6_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH6_MASK  0x00000020
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH6_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH5_LSB   4
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH5_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH5_MASK  0x00000010
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH5_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH4_LSB   3
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH4_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH4_MASK  0x00000008
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH4_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH2_LSB   2
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH2_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH2_MASK  0x00000004
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH2_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH1_LSB   1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH1_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH1_MASK  0x00000002
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH1_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH0_LSB   0
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH0_WIDTH 1
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH0_MASK  0x00000001
#define XAIEMLGBL_PL_MODULE_PL_INTERFACE_DOWNSIZER_BYPASS_SOUTH0_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_TIMER_CONTROL                                0x00034000
#define XAIEMLGBL_PL_MODULE_TIMER_CONTROL_WIDTH                          32
#define XAIEMLGBL_PL_MODULE_TIMER_CONTROL_MASK                           0x80007F00
#define XAIEMLGBL_PL_MODULE_TIMER_CONTROL_RESET_LSB                    31
#define XAIEMLGBL_PL_MODULE_TIMER_CONTROL_RESET_WIDTH                  1
#define XAIEMLGBL_PL_MODULE_TIMER_CONTROL_RESET_MASK                   0x80000000
#define XAIEMLGBL_PL_MODULE_TIMER_CONTROL_RESET_DEFVAL                 0x0
#define XAIEMLGBL_PL_MODULE_TIMER_CONTROL_RESET_EVENT_LSB              8
#define XAIEMLGBL_PL_MODULE_TIMER_CONTROL_RESET_EVENT_WIDTH            7
#define XAIEMLGBL_PL_MODULE_TIMER_CONTROL_RESET_EVENT_MASK             0x00007F00
#define XAIEMLGBL_PL_MODULE_TIMER_CONTROL_RESET_EVENT_DEFVAL           0x0

#define XAIEMLGBL_PL_MODULE_EVENT_GENERATE                               0x00034008
#define XAIEMLGBL_PL_MODULE_EVENT_GENERATE_WIDTH                         32
#define XAIEMLGBL_PL_MODULE_EVENT_GENERATE_MASK                          0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_GENERATE_EVENT_LSB                   0
#define XAIEMLGBL_PL_MODULE_EVENT_GENERATE_EVENT_WIDTH                 7
#define XAIEMLGBL_PL_MODULE_EVENT_GENERATE_EVENT_MASK                  0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_GENERATE_EVENT_DEFVAL                0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST0_A                           0x00034010
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST0_A_WIDTH                     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST0_A_MASK                      0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST0_A_EVENT_LSB               0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST0_A_EVENT_WIDTH             7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST0_A_EVENT_MASK              0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST0_A_EVENT_DEFVAL            0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST1_A                           0x00034014
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST1_A_WIDTH                     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST1_A_MASK                      0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST1_A_EVENT_LSB               0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST1_A_EVENT_WIDTH             7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST1_A_EVENT_MASK              0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST1_A_EVENT_DEFVAL            0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST2_A                           0x00034018
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST2_A_WIDTH                     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST2_A_MASK                      0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST2_A_EVENT_LSB               0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST2_A_EVENT_WIDTH             7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST2_A_EVENT_MASK              0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST2_A_EVENT_DEFVAL            0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST3_A                           0x0003401C
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST3_A_WIDTH                     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST3_A_MASK                      0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST3_A_EVENT_LSB               0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST3_A_EVENT_WIDTH             7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST3_A_EVENT_MASK              0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST3_A_EVENT_DEFVAL            0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST4_A                           0x00034020
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST4_A_WIDTH                     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST4_A_MASK                      0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST4_A_EVENT_LSB               0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST4_A_EVENT_WIDTH             7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST4_A_EVENT_MASK              0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST4_A_EVENT_DEFVAL            0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST5_A                           0x00034024
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST5_A_WIDTH                     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST5_A_MASK                      0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST5_A_EVENT_LSB               0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST5_A_EVENT_WIDTH             7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST5_A_EVENT_MASK              0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST5_A_EVENT_DEFVAL            0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST6_A                           0x00034028
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST6_A_WIDTH                     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST6_A_MASK                      0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST6_A_EVENT_LSB               0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST6_A_EVENT_WIDTH             7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST6_A_EVENT_MASK              0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST6_A_EVENT_DEFVAL            0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST7_A                           0x0003402C
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST7_A_WIDTH                     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST7_A_MASK                      0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST7_A_EVENT_LSB               0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST7_A_EVENT_WIDTH             7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST7_A_EVENT_MASK              0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST7_A_EVENT_DEFVAL            0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST8_A                           0x00034030
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST8_A_WIDTH                     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST8_A_MASK                      0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST8_A_EVENT_LSB               0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST8_A_EVENT_WIDTH             7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST8_A_EVENT_MASK              0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST8_A_EVENT_DEFVAL            0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST9_A                           0x00034034
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST9_A_WIDTH                     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST9_A_MASK                      0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST9_A_EVENT_LSB               0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST9_A_EVENT_WIDTH             7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST9_A_EVENT_MASK              0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST9_A_EVENT_DEFVAL            0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST10_A                          0x00034038
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST10_A_WIDTH                    32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST10_A_MASK                     0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST10_A_EVENT_LSB              0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST10_A_EVENT_WIDTH            7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST10_A_EVENT_MASK             0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST10_A_EVENT_DEFVAL           0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST11_A                          0x0003403C
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST11_A_WIDTH                    32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST11_A_MASK                     0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST11_A_EVENT_LSB              0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST11_A_EVENT_WIDTH            7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST11_A_EVENT_MASK             0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST11_A_EVENT_DEFVAL           0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST12_A                          0x00034040
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST12_A_WIDTH                    32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST12_A_MASK                     0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST12_A_EVENT_LSB              0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST12_A_EVENT_WIDTH            7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST12_A_EVENT_MASK             0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST12_A_EVENT_DEFVAL           0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST13_A                          0x00034044
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST13_A_WIDTH                    32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST13_A_MASK                     0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST13_A_EVENT_LSB              0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST13_A_EVENT_WIDTH            7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST13_A_EVENT_MASK             0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST13_A_EVENT_DEFVAL           0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST14_A                          0x00034048
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST14_A_WIDTH                    32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST14_A_MASK                     0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST14_A_EVENT_LSB              0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST14_A_EVENT_WIDTH            7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST14_A_EVENT_MASK             0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST14_A_EVENT_DEFVAL           0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST15_A                          0x0003404C
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST15_A_WIDTH                    32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST15_A_MASK                     0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST15_A_EVENT_LSB              0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST15_A_EVENT_WIDTH            7
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST15_A_EVENT_MASK             0x0000007F
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST15_A_EVENT_DEFVAL           0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET            0x00034050
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET_WIDTH      32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET_MASK       0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET_SET_LSB  0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET_SET_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR            0x00034054
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR_WIDTH      32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR_MASK       0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR_CLEAR_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE          0x00034058
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE_WIDTH    32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE_MASK     0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE_VALUE_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET             0x00034060
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET_WIDTH       32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET_MASK        0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET_SET_LSB   0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET_SET_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET_SET_MASK  0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR             0x00034064
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR_WIDTH       32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR_MASK        0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR_CLEAR_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE           0x00034068
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE_WIDTH     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE_MASK      0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE_VALUE_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET            0x00034070
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET_WIDTH      32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET_MASK       0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET_SET_LSB  0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET_SET_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR            0x00034074
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR_WIDTH      32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR_MASK       0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR_CLEAR_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE          0x00034078
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE_WIDTH    32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE_MASK     0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE_VALUE_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET             0x00034080
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET_WIDTH       32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET_MASK        0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET_SET_LSB   0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET_SET_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET_SET_MASK  0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR             0x00034084
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR_WIDTH       32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR_MASK        0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR_CLEAR_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE           0x00034088
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE_WIDTH     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE_MASK      0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE_VALUE_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET            0x00034090
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET_WIDTH      32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET_MASK       0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET_SET_LSB  0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET_SET_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR            0x00034094
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR_WIDTH      32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR_MASK       0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR_CLEAR_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE          0x00034098
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE_WIDTH    32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE_MASK     0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE_VALUE_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET             0x000340A0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET_WIDTH       32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET_MASK        0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET_SET_LSB   0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET_SET_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET_SET_MASK  0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR             0x000340A4
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR_WIDTH       32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR_MASK        0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR_CLEAR_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE           0x000340A8
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE_WIDTH     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE_MASK      0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE_VALUE_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET            0x000340B0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET_WIDTH      32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET_MASK       0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET_SET_LSB  0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET_SET_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR            0x000340B4
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR_WIDTH      32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR_MASK       0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR_CLEAR_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE          0x000340B8
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE_WIDTH    32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE_MASK     0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE_VALUE_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET             0x000340C0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET_WIDTH       32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET_MASK        0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET_SET_LSB   0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET_SET_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET_SET_MASK  0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR             0x000340C4
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR_WIDTH       32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR_MASK        0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR_CLEAR_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE           0x000340C8
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE_WIDTH     32
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE_MASK      0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE_VALUE_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL0                               0x000340D0
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL0_WIDTH                         32
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL0_MASK                          0x7F7F0000
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_LSB        24
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_WIDTH      7
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_MASK       0x7F000000
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_DEFVAL     0x0
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_LSB       16
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_WIDTH     7
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_MASK      0x007F0000
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_DEFVAL    0x0

#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL1                               0x000340D4
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL1_WIDTH                         32
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL1_MASK                          0x0000701F
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL1_PACKET_TYPE_LSB             12
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL1_PACKET_TYPE_WIDTH           3
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL1_PACKET_TYPE_MASK            0x00007000
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL1_PACKET_TYPE_DEFVAL          0x0
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL1_ID_LSB                      0
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL1_ID_WIDTH                    5
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL1_ID_MASK                     0x0000001F
#define XAIEMLGBL_PL_MODULE_TRACE_CONTROL1_ID_DEFVAL                   0x0

#define XAIEMLGBL_PL_MODULE_TRACE_STATUS                                 0x000340D8
#define XAIEMLGBL_PL_MODULE_TRACE_STATUS_WIDTH                           32
#define XAIEMLGBL_PL_MODULE_TRACE_STATUS_MASK                            0x00000307
#define XAIEMLGBL_PL_MODULE_TRACE_STATUS_STATE_LSB                     8
#define XAIEMLGBL_PL_MODULE_TRACE_STATUS_STATE_WIDTH                   2
#define XAIEMLGBL_PL_MODULE_TRACE_STATUS_STATE_MASK                    0x00000300
#define XAIEMLGBL_PL_MODULE_TRACE_STATUS_STATE_DEFVAL                  0x0
#define XAIEMLGBL_PL_MODULE_TRACE_STATUS_MODE_LSB                      0
#define XAIEMLGBL_PL_MODULE_TRACE_STATUS_MODE_WIDTH                    3
#define XAIEMLGBL_PL_MODULE_TRACE_STATUS_MODE_MASK                     0x00000007
#define XAIEMLGBL_PL_MODULE_TRACE_STATUS_MODE_DEFVAL                   0x0

#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0                                 0x000340E0
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_WIDTH                           32
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_MASK                            0x7F7F7F7F
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT3_LSB              24
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT3_WIDTH            7
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT3_MASK             0x7F000000
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT3_DEFVAL           0x0
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT2_LSB              16
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT2_WIDTH            7
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT2_MASK             0x007F0000
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT2_DEFVAL           0x0
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT1_LSB              8
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT1_WIDTH            7
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT1_MASK             0x00007F00
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT1_DEFVAL           0x0
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT0_LSB              0
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT0_WIDTH            7
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT0_MASK             0x0000007F
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT0_TRACE_EVENT0_DEFVAL           0x0

#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1                                 0x000340E4
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_WIDTH                           32
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_MASK                            0x7F7F7F7F
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT7_LSB              24
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT7_WIDTH            7
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT7_MASK             0x7F000000
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT7_DEFVAL           0x0
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT6_LSB              16
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT6_WIDTH            7
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT6_MASK             0x007F0000
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT6_DEFVAL           0x0
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT5_LSB              8
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT5_WIDTH            7
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT5_MASK             0x00007F00
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT5_DEFVAL           0x0
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT4_LSB              0
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT4_WIDTH            7
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT4_MASK             0x0000007F
#define XAIEMLGBL_PL_MODULE_TRACE_EVENT1_TRACE_EVENT4_DEFVAL           0x0

#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_LOW_VALUE                   0x000340F0
#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_WIDTH             32
#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_MASK              0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_LSB 0
#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_WIDTH 32
#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_MASK 0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_DEFVAL 0xFFFFFFFF

#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE                  0x000340F4
#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_WIDTH            32
#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_MASK             0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_LSB 0
#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_WIDTH 32
#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_MASK 0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_DEFVAL 0xFFFFFFFF

#define XAIEMLGBL_PL_MODULE_TIMER_LOW                                    0x000340F8
#define XAIEMLGBL_PL_MODULE_TIMER_LOW_WIDTH                              32
#define XAIEMLGBL_PL_MODULE_TIMER_LOW_MASK                               0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_TIMER_LOW_TIMERLOW_LSB                     0
#define XAIEMLGBL_PL_MODULE_TIMER_LOW_TIMERLOW_WIDTH                   32
#define XAIEMLGBL_PL_MODULE_TIMER_LOW_TIMERLOW_MASK                    0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_TIMER_LOW_TIMERLOW_DEFVAL                  0x0

#define XAIEMLGBL_PL_MODULE_TIMER_HIGH                                   0x000340FC
#define XAIEMLGBL_PL_MODULE_TIMER_HIGH_WIDTH                             32
#define XAIEMLGBL_PL_MODULE_TIMER_HIGH_MASK                              0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_TIMER_HIGH_TIMERHIGH_LSB                   0
#define XAIEMLGBL_PL_MODULE_TIMER_HIGH_TIMERHIGH_WIDTH                 32
#define XAIEMLGBL_PL_MODULE_TIMER_HIGH_TIMERHIGH_MASK                  0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_TIMER_HIGH_TIMERHIGH_DEFVAL                0x0

#define XAIEMLGBL_PL_MODULE_EVENT_STATUS0                                0x00034200
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS0_WIDTH                          32
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS0_MASK                           0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_LSB        0
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_WIDTH      32
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_MASK       0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_DEFVAL     0x2

#define XAIEMLGBL_PL_MODULE_EVENT_STATUS1                                0x00034204
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS1_WIDTH                          32
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS1_MASK                           0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_LSB       0
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_WIDTH     32
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_MASK      0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_DEFVAL    0x0

#define XAIEMLGBL_PL_MODULE_EVENT_STATUS2                                0x00034208
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS2_WIDTH                          32
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS2_MASK                           0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_LSB       0
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_WIDTH     32
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_MASK      0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_DEFVAL    0x0

#define XAIEMLGBL_PL_MODULE_EVENT_STATUS3                                0x0003420C
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS3_WIDTH                          32
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS3_MASK                           0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_LSB      0
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_WIDTH    32
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_MASK     0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_DEFVAL   0x0

#define XAIEMLGBL_PL_MODULE_RESERVED0                                    0x00034210
#define XAIEMLGBL_PL_MODULE_RESERVED0_WIDTH                              32
#define XAIEMLGBL_PL_MODULE_RESERVED0_MASK                               0xFFFFFFFF

#define XAIEMLGBL_PL_MODULE_RESERVED1                                    0x00034214
#define XAIEMLGBL_PL_MODULE_RESERVED1_WIDTH                              32
#define XAIEMLGBL_PL_MODULE_RESERVED1_MASK                               0xFFFFFFFF

#define XAIEMLGBL_PL_MODULE_RESERVED2                                    0x00034218
#define XAIEMLGBL_PL_MODULE_RESERVED2_WIDTH                              32
#define XAIEMLGBL_PL_MODULE_RESERVED2_MASK                               0xFFFFFFFF

#define XAIEMLGBL_PL_MODULE_RESERVED3                                    0x0003421C
#define XAIEMLGBL_PL_MODULE_RESERVED3_WIDTH                              32
#define XAIEMLGBL_PL_MODULE_RESERVED3_MASK                               0xFFFFFFFF

#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS                           0x00034400
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_WIDTH                     32
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_MASK                      0x7F7F7F7F
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTD_LSB              24
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTD_WIDTH            7
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTD_MASK             0x7F000000
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTD_DEFVAL           0x0
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTC_LSB              16
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTC_WIDTH            7
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTC_MASK             0x007F0000
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTC_DEFVAL           0x0
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTB_LSB              8
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTB_WIDTH            7
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTB_MASK             0x00007F00
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTB_DEFVAL           0x0
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTA_LSB              0
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTA_WIDTH            7
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTA_MASK             0x0000007F
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_INPUTS_EVENTA_DEFVAL           0x0

#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL                          0x00034404
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_WIDTH                    32
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_MASK                     0x00030303
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_COMBO2_LSB             16
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_COMBO2_WIDTH           2
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_COMBO2_MASK            0x00030000
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_COMBO2_DEFVAL          0x0
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_COMBO1_LSB             8
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_COMBO1_WIDTH           2
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_COMBO1_MASK            0x00000300
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_COMBO1_DEFVAL          0x0
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_COMBO0_LSB             0
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_COMBO0_WIDTH           2
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_COMBO0_MASK            0x00000003
#define XAIEMLGBL_PL_MODULE_COMBO_EVENT_CONTROL_COMBO0_DEFVAL          0x0

#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL                 0x00034408
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_WIDTH           32
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_MASK            0x067F067F
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_LSB 26
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_MASK 0x04000000
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_LSB 25
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_MASK 0x02000000
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_LSB 16
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_WIDTH 7
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_MASK 0x007F0000
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_LSB 10
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_MASK 0x00000400
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_LSB 9
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_MASK 0x00000200
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_LSB 0
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_WIDTH 7
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE                         0x00034500
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_WIDTH                   32
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_MASK                    0x000003FF
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_LSB 9
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_MASK 0x00000200
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_LSB 8
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_LSB     7
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_WIDTH   1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_MASK    0x00000080
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_DEFVAL  0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_LSB     6
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_WIDTH   1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_MASK    0x00000040
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_DEFVAL  0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_LSB     5
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_WIDTH   1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_MASK    0x00000020
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_DEFVAL  0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_LSB     4
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_WIDTH   1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_MASK    0x00000010
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_DEFVAL  0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_LSB         3
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_WIDTH       1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_MASK        0x00000008
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_DEFVAL      0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_LSB         2
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_WIDTH       1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_MASK        0x00000004
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_DEFVAL      0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_LSB 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_MASK 0x00000002
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_LSB        0
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_WIDTH      1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_MASK       0x00000001
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_DEFVAL     0x1

#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE              0x00034504
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_WIDTH        32
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_MASK         0x00FFFFFF
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_MEMORY_STARVATION_LSB 23
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_MEMORY_STARVATION_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_MEMORY_STARVATION_MASK 0x00800000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_MEMORY_STARVATION_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_MEMORY_STARVATION_LSB 22
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_MEMORY_STARVATION_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_MEMORY_STARVATION_MASK 0x00400000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_MEMORY_STARVATION_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_STREAM_BACKPRESSURE_LSB 21
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_STREAM_BACKPRESSURE_MASK 0x00200000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_STREAM_BACKPRESSURE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_STREAM_BACKPRESSURE_LSB 20
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_STREAM_BACKPRESSURE_MASK 0x00100000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_STREAM_BACKPRESSURE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_MEMORY_BACKPRESSURE_LSB 19
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_MEMORY_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_MEMORY_BACKPRESSURE_MASK 0x00080000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_MEMORY_BACKPRESSURE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_MEMORY_BACKPRESSURE_LSB 18
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_MEMORY_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_MEMORY_BACKPRESSURE_MASK 0x00040000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_MEMORY_BACKPRESSURE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_STREAM_STARVATION_LSB 17
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_STREAM_STARVATION_MASK 0x00020000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_STREAM_STARVATION_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_STREAM_STARVATION_LSB 16
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_STREAM_STARVATION_MASK 0x00010000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_STREAM_STARVATION_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_STALLED_LOCK_ACQUIRE_LSB 15
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_STALLED_LOCK_ACQUIRE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_STALLED_LOCK_ACQUIRE_MASK 0x00008000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_STALLED_LOCK_ACQUIRE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_STALLED_LOCK_ACQUIRE_LSB 14
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_STALLED_LOCK_ACQUIRE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_STALLED_LOCK_ACQUIRE_MASK 0x00004000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_STALLED_LOCK_ACQUIRE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_STALLED_LOCK_ACQUIRE_LSB 13
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_STALLED_LOCK_ACQUIRE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_STALLED_LOCK_ACQUIRE_MASK 0x00002000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_STALLED_LOCK_ACQUIRE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_STALLED_LOCK_ACQUIRE_LSB 12
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_STALLED_LOCK_ACQUIRE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_STALLED_LOCK_ACQUIRE_MASK 0x00001000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_STALLED_LOCK_ACQUIRE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_FINISHED_TASK_LSB 11
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_FINISHED_TASK_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_FINISHED_TASK_MASK 0x00000800
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_FINISHED_TASK_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_FINISHED_TASK_LSB 10
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_FINISHED_TASK_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_FINISHED_TASK_MASK 0x00000400
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_FINISHED_TASK_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_FINISHED_TASK_LSB 9
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_FINISHED_TASK_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_FINISHED_TASK_MASK 0x00000200
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_FINISHED_TASK_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_FINISHED_TASK_LSB 8
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_FINISHED_TASK_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_FINISHED_TASK_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_FINISHED_TASK_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_FINISHED_BD_LSB 7
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_FINISHED_BD_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_FINISHED_BD_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_FINISHED_BD_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_FINISHED_BD_LSB 6
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_FINISHED_BD_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_FINISHED_BD_MASK 0x00000040
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_FINISHED_BD_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_FINISHED_BD_LSB 5
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_FINISHED_BD_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_FINISHED_BD_MASK 0x00000020
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_FINISHED_BD_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_FINISHED_BD_LSB 4
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_FINISHED_BD_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_FINISHED_BD_MASK 0x00000010
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_FINISHED_BD_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_START_TASK_LSB 3
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_START_TASK_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_START_TASK_MASK 0x00000008
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_1_START_TASK_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_START_TASK_LSB 2
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_START_TASK_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_START_TASK_MASK 0x00000004
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_MM2S_0_START_TASK_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_START_TASK_LSB 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_START_TASK_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_START_TASK_MASK 0x00000002
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_1_START_TASK_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_START_TASK_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_START_TASK_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_START_TASK_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_DMA_ACTIVITY_ENABLE_DMA_S2MM_0_START_TASK_DEFVAL 0x1

#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE                      0x00034508
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_WIDTH                32
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_MASK                 0x00FFFFFF
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_EQUAL_TO_VALUE_LSB 23
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_EQUAL_TO_VALUE_MASK 0x00800000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_REL_LSB  22
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_REL_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_REL_MASK 0x00400000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_REL_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_GE_LSB 21
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_GE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_GE_MASK 0x00200000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_EQ_LSB 20
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_EQ_MASK 0x00100000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_EQUAL_TO_VALUE_LSB 19
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_EQUAL_TO_VALUE_MASK 0x00080000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_REL_LSB  18
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_REL_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_REL_MASK 0x00040000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_REL_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_GE_LSB 17
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_GE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_GE_MASK 0x00020000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_EQ_LSB 16
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_EQ_MASK 0x00010000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_EQUAL_TO_VALUE_LSB 15
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_EQUAL_TO_VALUE_MASK 0x00008000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_REL_LSB  14
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_REL_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_REL_MASK 0x00004000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_REL_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_GE_LSB 13
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_GE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_GE_MASK 0x00002000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_EQ_LSB 12
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_EQ_MASK 0x00001000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_EQUAL_TO_VALUE_LSB 11
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_EQUAL_TO_VALUE_MASK 0x00000800
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_REL_LSB  10
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_REL_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_REL_MASK 0x00000400
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_REL_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_GE_LSB 9
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_GE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_GE_MASK 0x00000200
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_EQ_LSB 8
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_EQ_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_EQUAL_TO_VALUE_LSB 7
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_EQUAL_TO_VALUE_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_REL_LSB  6
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_REL_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_REL_MASK 0x00000040
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_REL_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_GE_LSB 5
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_GE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_GE_MASK 0x00000020
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_EQ_LSB 4
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_EQ_MASK 0x00000010
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_EQUAL_TO_VALUE_LSB 3
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_EQUAL_TO_VALUE_MASK 0x00000008
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_REL_LSB  2
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_REL_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_REL_MASK 0x00000004
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_REL_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_GE_LSB 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_GE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_GE_MASK 0x00000002
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_EQ_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_EQ_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_EQ_DEFVAL 0x1

#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE                    0x0003450C
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_WIDTH              32
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_MASK               0x00000FFF
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_DMA_TASK_TOKEN_STALL_LSB 11
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_DMA_TASK_TOKEN_STALL_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_DMA_TASK_TOKEN_STALL_MASK 0x00000800
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_DMA_TASK_TOKEN_STALL_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_LOCK_ERROR_LSB   10
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_LOCK_ERROR_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_LOCK_ERROR_MASK  0x00000400
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_LOCK_ERROR_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_DMA_MM2S_ERROR_LSB 9
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_DMA_MM2S_ERROR_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_DMA_MM2S_ERROR_MASK 0x00000200
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_DMA_MM2S_ERROR_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_DMA_S2MM_ERROR_LSB 8
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_DMA_S2MM_ERROR_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_DMA_S2MM_ERROR_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_DMA_S2MM_ERROR_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_BYTE_STROBE_ERROR_LSB 7
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_BYTE_STROBE_ERROR_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_BYTE_STROBE_ERROR_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_BYTE_STROBE_ERROR_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE_LSB 6
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE_MASK 0x00000040
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_UNSUPPORTED_TRAFFIC_LSB 5
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_UNSUPPORTED_TRAFFIC_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_UNSUPPORTED_TRAFFIC_MASK 0x00000020
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_UNSUPPORTED_TRAFFIC_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_SLAVE_NSU_ERROR_LSB 4
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_SLAVE_NSU_ERROR_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_SLAVE_NSU_ERROR_MASK 0x00000010
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_SLAVE_NSU_ERROR_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_DECODE_NSU_ERROR_LSB 3
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_DECODE_NSU_ERROR_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_DECODE_NSU_ERROR_MASK 0x00000008
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_DECODE_NSU_ERROR_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_LSB 2
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_MASK 0x00000004
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_CONTROL_PKT_ERROR_LSB 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_CONTROL_PKT_ERROR_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_CONTROL_PKT_ERROR_MASK 0x00000002
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_CONTROL_PKT_ERROR_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_SLAVE_TILE_ERROR_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_SLAVE_TILE_ERROR_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_SLAVE_TILE_ERROR_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_ERRORS_ENABLE_AXI_MM_SLAVE_TILE_ERROR_DEFVAL 0x1

#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE             0x00034510
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_WIDTH       32
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_MASK        0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_7_LSB 31
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_7_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_7_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_7_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_7_LSB 30
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_7_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_7_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_7_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_7_LSB 29
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_7_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_7_MASK 0x20000000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_7_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_7_LSB 28
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_7_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_7_MASK 0x10000000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_7_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_6_LSB 27
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_6_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_6_MASK 0x08000000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_6_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_6_LSB 26
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_6_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_6_MASK 0x04000000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_6_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_6_LSB 25
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_6_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_6_MASK 0x02000000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_6_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_6_LSB 24
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_6_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_6_MASK 0x01000000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_6_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_5_LSB 23
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_5_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_5_MASK 0x00800000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_5_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_5_LSB 22
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_5_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_5_MASK 0x00400000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_5_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_5_LSB 21
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_5_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_5_MASK 0x00200000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_5_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_5_LSB 20
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_5_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_5_MASK 0x00100000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_5_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_4_LSB 19
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_4_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_4_MASK 0x00080000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_4_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_4_LSB 18
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_4_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_4_MASK 0x00040000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_4_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_4_LSB 17
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_4_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_4_MASK 0x00020000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_4_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_4_LSB 16
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_4_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_4_MASK 0x00010000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_4_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_3_LSB 15
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_3_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_3_MASK 0x00008000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_3_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_3_LSB 14
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_3_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_3_MASK 0x00004000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_3_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_3_LSB 13
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_3_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_3_MASK 0x00002000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_3_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_3_LSB 12
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_3_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_3_MASK 0x00001000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_3_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_2_LSB 11
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_2_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_2_MASK 0x00000800
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_2_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_2_LSB 10
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_2_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_2_MASK 0x00000400
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_2_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_2_LSB 9
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_2_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_2_MASK 0x00000200
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_2_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_2_LSB 8
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_2_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_2_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_2_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_1_LSB 7
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_1_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_1_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_1_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_1_LSB 6
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_1_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_1_MASK 0x00000040
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_1_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_1_LSB 5
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_1_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_1_MASK 0x00000020
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_1_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_1_LSB 4
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_1_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_1_MASK 0x00000010
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_1_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_0_LSB 3
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_0_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_0_MASK 0x00000008
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_0_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_0_LSB 2
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_0_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_0_MASK 0x00000004
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_0_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_0_LSB 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_0_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_0_MASK 0x00000002
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_0_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_0_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_0_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_0_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_0_DEFVAL 0x1

#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE               0x00034514
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_WIDTH         32
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_MASK          0x0000FFFF
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_15_LSB 15
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_15_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_15_MASK 0x00008000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_15_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_14_LSB 14
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_14_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_14_MASK 0x00004000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_14_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_13_LSB 13
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_13_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_13_MASK 0x00002000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_13_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_12_LSB 12
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_12_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_12_MASK 0x00001000
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_12_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_11_LSB 11
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_11_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_11_MASK 0x00000800
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_11_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_10_LSB 10
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_10_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_10_MASK 0x00000400
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_10_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_9_LSB 9
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_9_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_9_MASK 0x00000200
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_9_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_8_LSB 8
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_8_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_8_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_8_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_7_LSB 7
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_7_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_7_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_7_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_6_LSB 6
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_6_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_6_MASK 0x00000040
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_6_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_5_LSB 5
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_5_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_5_MASK 0x00000020
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_5_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_4_LSB 4
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_4_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_4_MASK 0x00000010
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_4_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_3_LSB 3
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_3_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_3_MASK 0x00000008
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_3_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_2_LSB 2
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_2_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_2_MASK 0x00000004
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_2_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_1_LSB 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_1_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_1_MASK 0x00000002
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_1_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_0_LSB 0
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_0_WIDTH 1
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_0_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_EVENT_GROUP_BROADCAST_A_ENABLE_BROADCAST_A_0_DEFVAL 0x1

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_A        0x00035000
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_A_WIDTH  32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_A_MASK   0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_A_IRQ_MASK_A_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_A_IRQ_MASK_A_WIDTH 20
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_A_IRQ_MASK_A_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_A_IRQ_MASK_A_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_A      0x00035004
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_A_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_A_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_A_ENABLE_A_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_A_ENABLE_A_WIDTH 20
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_A_ENABLE_A_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_A_ENABLE_A_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_A     0x00035008
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_A_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_A_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_A_DISABLE_A_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_A_DISABLE_A_WIDTH 20
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_A_DISABLE_A_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_A_DISABLE_A_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_A      0x0003500C
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_A_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_A_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_A_STATUS_A_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_A_STATUS_A_WIDTH 20
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_A_STATUS_A_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_A_STATUS_A_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_A      0x00035010
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_A_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_A_MASK 0x0000000F
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_A_IRQ_NO_A_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_A_IRQ_NO_A_WIDTH 4
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_A_IRQ_NO_A_MASK 0x0000000F
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_A_IRQ_NO_A_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A   0x00035014
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_MASK 0x7F7F7F7F
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT3_LSB 24
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT3_WIDTH 7
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT3_MASK 0x7F000000
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT3_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT2_LSB 16
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT2_WIDTH 7
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT2_MASK 0x007F0000
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT2_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT1_LSB 8
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT1_WIDTH 7
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT1_MASK 0x00007F00
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT1_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT0_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT0_WIDTH 7
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT0_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_A_IRQ_EVENT0_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_SET 0x00035018
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_SET_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_SET_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_SET_SET_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_SET_SET_WIDTH 16
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_CLEAR 0x0003501C
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_CLEAR_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_CLEAR_CLEAR_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_CLEAR_CLEAR_WIDTH 16
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_CLEAR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_CLEAR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_VALUE 0x00035020
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_VALUE_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_VALUE_VALUE_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_A_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_B        0x00035030
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_B_WIDTH  32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_B_MASK   0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_B_IRQ_MASK_B_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_B_IRQ_MASK_B_WIDTH 20
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_B_IRQ_MASK_B_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_MASK_B_IRQ_MASK_B_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_B      0x00035034
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_B_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_B_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_B_ENABLE_B_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_B_ENABLE_B_WIDTH 20
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_B_ENABLE_B_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_ENABLE_B_ENABLE_B_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_B     0x00035038
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_B_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_B_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_B_DISABLE_B_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_B_DISABLE_B_WIDTH 20
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_B_DISABLE_B_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_DISABLE_B_DISABLE_B_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_B      0x0003503C
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_B_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_B_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_B_STATUS_B_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_B_STATUS_B_WIDTH 20
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_B_STATUS_B_MASK 0x000FFFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_STATUS_B_STATUS_B_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_B      0x00035040
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_B_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_B_MASK 0x0000000F
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_B_IRQ_NO_B_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_B_IRQ_NO_B_WIDTH 4
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_B_IRQ_NO_B_MASK 0x0000000F
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_NO_B_IRQ_NO_B_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B   0x00035044
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_MASK 0x7F7F7F7F
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT3_LSB 24
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT3_WIDTH 7
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT3_MASK 0x7F000000
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT3_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT2_LSB 16
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT2_WIDTH 7
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT2_MASK 0x007F0000
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT2_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT1_LSB 8
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT1_WIDTH 7
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT1_MASK 0x00007F00
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT1_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT0_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT0_WIDTH 7
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT0_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_IRQ_EVENT_B_IRQ_EVENT0_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_SET 0x00035048
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_SET_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_SET_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_SET_SET_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_SET_SET_WIDTH 16
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_CLEAR 0x0003504C
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_CLEAR_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_CLEAR_CLEAR_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_CLEAR_CLEAR_WIDTH 16
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_CLEAR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_CLEAR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_VALUE 0x00035050
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_VALUE_WIDTH 32
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_VALUE_VALUE_LSB 0
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_PL_MODULE_INTERRUPT_CONTROLLER_1ST_LEVEL_BLOCK_NORTH_IN_B_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_BISR_CACHE_CTRL                              0x00036000
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_CTRL_WIDTH                        32
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_CTRL_MASK                         0x00000011
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_CTRL_CLEAR_LSB                  4
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_CTRL_CLEAR_WIDTH                1
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_CTRL_CLEAR_MASK                 0x00000010
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_CTRL_CLEAR_DEFVAL               0x0
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_CTRL_TRIGGER_LSB                0
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_CTRL_TRIGGER_WIDTH              1
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_CTRL_TRIGGER_MASK               0x00000001
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_CTRL_TRIGGER_DEFVAL             0x0

#define XAIEMLGBL_PL_MODULE_BISR_CACHE_STATUS                            0x00036008
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_STATUS_WIDTH                      32
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_STATUS_MASK                       0x00000003
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_STATUS_PASS_LSB                 1
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_STATUS_PASS_WIDTH               1
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_STATUS_PASS_MASK                0x00000002
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_STATUS_PASS_DEFVAL              0x0
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_STATUS_DONE_LSB                 0
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_STATUS_DONE_WIDTH               1
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_STATUS_DONE_MASK                0x00000001
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_STATUS_DONE_DEFVAL              0x0

#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA0                             0x00036010
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA0_WIDTH                       32
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA0_DATA_LSB                  0
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA0_DATA_WIDTH                32
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA0_DATA_MASK                 0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA0_DATA_DEFVAL               0x0

#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA1                             0x00036014
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA1_WIDTH                       32
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA1_DATA_LSB                  0
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA1_DATA_WIDTH                32
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA1_DATA_MASK                 0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA1_DATA_DEFVAL               0x0

#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA2                             0x00036018
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA2_WIDTH                       32
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA2_MASK                        0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA2_DATA_LSB                  0
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA2_DATA_WIDTH                32
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA2_DATA_MASK                 0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA2_DATA_DEFVAL               0x0

#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA3                             0x0003601C
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA3_WIDTH                       32
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA3_DATA_LSB                  0
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA3_DATA_WIDTH                32
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA3_DATA_MASK                 0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_CACHE_DATA3_DATA_DEFVAL               0x0

#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA0                              0x00036020
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA0_WIDTH                        32
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA0_MASK                         0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA0_DATA_LSB                   0
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA0_DATA_WIDTH                 32
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA0_DATA_MASK                  0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA0_DATA_DEFVAL                0x0

#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA1                              0x00036024
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA1_WIDTH                        32
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA1_MASK                         0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA1_DATA_LSB                   0
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA1_DATA_WIDTH                 32
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA1_DATA_MASK                  0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA1_DATA_DEFVAL                0x0

#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA2                              0x00036028
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA2_WIDTH                        32
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA2_MASK                         0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA2_DATA_LSB                   0
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA2_DATA_WIDTH                 32
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA2_DATA_MASK                  0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA2_DATA_DEFVAL                0x0

#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA3                              0x0003602C
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA3_WIDTH                        32
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA3_MASK                         0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA3_DATA_LSB                   0
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA3_DATA_WIDTH                 32
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA3_DATA_MASK                  0xFFFFFFFF
#define XAIEMLGBL_PL_MODULE_BISR_TEST_DATA3_DATA_DEFVAL                0x0

#define XAIEMLGBL_PL_MODULE_TILE_CONTROL                                 0x00036030
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_WIDTH                           32
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_MASK                            0x0000000F
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_EAST_LSB         3
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_EAST_WIDTH       1
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_EAST_MASK        0x00000008
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_EAST_DEFVAL      0x0
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_NORTH_LSB        2
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_NORTH_WIDTH      1
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_NORTH_MASK       0x00000004
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_NORTH_DEFVAL     0x0
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_WEST_LSB         1
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_WEST_WIDTH       1
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_WEST_MASK        0x00000002
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_WEST_DEFVAL      0x0
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_SOUTH_LSB        0
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_SOUTH_WIDTH      1
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_SOUTH_MASK       0x00000001
#define XAIEMLGBL_PL_MODULE_TILE_CONTROL_ISOLATE_FROM_SOUTH_DEFVAL     0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL        0x0003F000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_WIDTH  32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASK   0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0            0x0003F004
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_MASK       0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_FIFO0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0           0x0003F008
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASK      0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1           0x0003F00C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASK      0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2           0x0003F010
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASK      0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3           0x0003F014
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASK      0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4           0x0003F018
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_MASK      0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH4_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5           0x0003F01C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_MASK      0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH5_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0            0x0003F020
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_MASK       0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1            0x0003F024
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_MASK       0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST1_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2            0x0003F028
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_MASK       0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST2_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3            0x0003F02C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_MASK       0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_WEST3_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0           0x0003F030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASK      0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1           0x0003F034
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASK      0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2           0x0003F038
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASK      0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3           0x0003F03C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASK      0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4           0x0003F040
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASK      0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5           0x0003F044
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASK      0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0            0x0003F048
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_MASK       0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1            0x0003F04C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_MASK       0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST1_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2            0x0003F050
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_MASK       0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST2_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3            0x0003F054
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_MASK       0xC00000FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_DROP_HEADER_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_CONFIGURATION_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_MASTER_CONFIG_EAST3_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL         0x0003F100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_WIDTH   32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_MASK    0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0            0x0003F104
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_MASK       0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_FIFO_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0           0x0003F108
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_MASK      0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1           0x0003F10C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_MASK      0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2           0x0003F110
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_MASK      0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3           0x0003F114
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_MASK      0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4           0x0003F118
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_MASK      0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5           0x0003F11C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_MASK      0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_6           0x0003F120
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_6_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_6_MASK      0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_6_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_6_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_6_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_6_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_6_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_6_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_6_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_6_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_7           0x0003F124
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_7_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_7_MASK      0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_7_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_7_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_7_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_7_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_7_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_7_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_7_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_7_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0            0x0003F128
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_MASK       0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1            0x0003F12C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_MASK       0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_1_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2            0x0003F130
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_MASK       0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_2_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3            0x0003F134
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_MASK       0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_WEST_3_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0           0x0003F138
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_MASK      0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1           0x0003F13C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_MASK      0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2           0x0003F140
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_MASK      0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3           0x0003F144
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_WIDTH     32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_MASK      0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0            0x0003F148
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_MASK       0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1            0x0003F14C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_MASK       0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_1_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2            0x0003F150
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_MASK       0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_2_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3            0x0003F154
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_MASK       0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_EAST_3_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE             0x0003F158
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_MASK        0xC0000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0          0x0003F200
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_WIDTH    32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK     0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ID_LSB 24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1          0x0003F204
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_WIDTH    32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK     0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ID_LSB 24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2          0x0003F208
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_WIDTH    32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK     0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ID_LSB 24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3          0x0003F20C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_WIDTH    32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK     0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ID_LSB 24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0             0x0003F210
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1             0x0003F214
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2             0x0003F218
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3             0x0003F21C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_FIFO_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0            0x0003F220
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1            0x0003F224
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2            0x0003F228
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3            0x0003F22C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0            0x0003F230
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1            0x0003F234
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2            0x0003F238
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3            0x0003F23C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0            0x0003F240
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1            0x0003F244
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2            0x0003F248
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3            0x0003F24C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0            0x0003F250
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1            0x0003F254
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2            0x0003F258
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3            0x0003F25C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0            0x0003F260
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1            0x0003F264
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2            0x0003F268
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3            0x0003F26C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0            0x0003F270
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1            0x0003F274
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2            0x0003F278
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3            0x0003F27C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0            0x0003F280
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1            0x0003F284
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2            0x0003F288
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3            0x0003F28C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_6_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0            0x0003F290
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1            0x0003F294
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2            0x0003F298
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3            0x0003F29C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_SOUTH_7_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0             0x0003F2A0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1             0x0003F2A4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2             0x0003F2A8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3             0x0003F2AC
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0             0x0003F2B0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1             0x0003F2B4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2             0x0003F2B8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3             0x0003F2BC
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_1_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0             0x0003F2C0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1             0x0003F2C4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2             0x0003F2C8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3             0x0003F2CC
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_2_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0             0x0003F2D0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1             0x0003F2D4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2             0x0003F2D8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3             0x0003F2DC
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_WEST_3_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0            0x0003F2E0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1            0x0003F2E4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2            0x0003F2E8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3            0x0003F2EC
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0            0x0003F2F0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1            0x0003F2F4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2            0x0003F2F8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3            0x0003F2FC
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0            0x0003F300
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1            0x0003F304
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2            0x0003F308
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3            0x0003F30C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0            0x0003F310
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1            0x0003F314
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2            0x0003F318
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3            0x0003F31C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_WIDTH      32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK       0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ID_LSB   24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ID_MASK  0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0             0x0003F320
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1             0x0003F324
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2             0x0003F328
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3             0x0003F32C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0             0x0003F330
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1             0x0003F334
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2             0x0003F338
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3             0x0003F33C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_1_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0             0x0003F340
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1             0x0003F344
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2             0x0003F348
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3             0x0003F34C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_2_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0             0x0003F350
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1             0x0003F354
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2             0x0003F358
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3             0x0003F35C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_WIDTH       32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MASK        0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ID_LSB    24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ID_WIDTH  5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ID_MASK   0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MASK_LSB  16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MSEL_LSB  4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_EAST_3_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0              0x0003F360
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_WIDTH        32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MASK         0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ID_LSB     24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ID_WIDTH   5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ID_MASK    0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ID_DEFVAL  0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MASK_LSB   16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MASK_MASK  0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MSEL_LSB   4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MSEL_MASK  0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ARBIT_LSB  0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1              0x0003F364
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_WIDTH        32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MASK         0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ID_LSB     24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ID_WIDTH   5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ID_MASK    0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ID_DEFVAL  0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MASK_LSB   16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MASK_MASK  0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MSEL_LSB   4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MSEL_MASK  0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ARBIT_LSB  0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2              0x0003F368
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_WIDTH        32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MASK         0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ID_LSB     24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ID_WIDTH   5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ID_MASK    0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ID_DEFVAL  0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MASK_LSB   16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MASK_MASK  0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MSEL_LSB   4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MSEL_MASK  0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ARBIT_LSB  0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3              0x0003F36C
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_WIDTH        32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MASK         0x1F1F0137
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ID_LSB     24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ID_WIDTH   5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ID_MASK    0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ID_DEFVAL  0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MASK_LSB   16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MASK_MASK  0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MSEL_LSB   4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MSEL_MASK  0x00000030
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ARBIT_LSB  0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1 0x0003F800
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_WIDTH 32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_MASK 0x3F1F3F1F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_1_LSB 24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_1_WIDTH 6
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_1_MASK 0x3F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_1_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_1_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_1_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_1_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_1_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_0_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_0_WIDTH 6
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_0_MASK 0x00003F00
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_0_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_0_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_0_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_0_MASK 0x0000001F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_0_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3 0x0003F804
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_WIDTH 32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_MASK 0x3F1F3F1F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_3_LSB 24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_3_WIDTH 6
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_3_MASK 0x3F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_3_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_3_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_3_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_3_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_3_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_2_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_2_WIDTH 6
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_2_MASK 0x00003F00
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_2_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_2_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_2_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_2_MASK 0x0000001F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_2_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL  0x0003F808
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_WIDTH 32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_ENABLE_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_ENABLE_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1 0x0003F810
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_WIDTH 32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_MASK 0x3F1F3F1F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_1_LSB 24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_1_WIDTH 6
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_1_MASK 0x3F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_1_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_1_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_1_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_1_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_1_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_0_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_0_WIDTH 6
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_0_MASK 0x00003F00
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_0_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_0_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_0_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_0_MASK 0x0000001F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_0_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3 0x0003F814
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_WIDTH 32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_MASK 0x3F1F3F1F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_3_LSB 24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_3_WIDTH 6
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_3_MASK 0x3F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_3_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_3_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_3_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_3_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_3_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_2_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_2_WIDTH 6
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_2_MASK 0x00003F00
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_2_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_2_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_2_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_2_MASK 0x0000001F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_2_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL  0x0003F818
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_WIDTH 32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_ENABLE_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_ENABLE_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0         0x0003FF00
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_WIDTH   32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_MASK    0x3F3F3F3F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_MASTER_SLAVE_LSB 29
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_MASTER_SLAVE_MASK 0x20000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_ID_LSB 24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_ID_MASK 0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_MASTER_SLAVE_LSB 21
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_MASTER_SLAVE_MASK 0x00200000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_ID_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_ID_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_MASTER_SLAVE_LSB 13
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_MASTER_SLAVE_MASK 0x00002000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_ID_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_ID_MASK 0x00001F00
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_MASTER_SLAVE_LSB 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_MASTER_SLAVE_MASK 0x00000020
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_ID_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_ID_MASK 0x0000001F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_ID_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1         0x0003FF04
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_WIDTH   32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_MASK    0x3F3F3F3F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_MASTER_SLAVE_LSB 29
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_MASTER_SLAVE_MASK 0x20000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_ID_LSB 24
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_ID_MASK 0x1F000000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_MASTER_SLAVE_LSB 21
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_MASTER_SLAVE_MASK 0x00200000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_ID_LSB 16
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_ID_MASK 0x001F0000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_MASTER_SLAVE_LSB 13
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_MASTER_SLAVE_MASK 0x00002000
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_ID_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_ID_MASK 0x00001F00
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_ID_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_MASTER_SLAVE_LSB 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_MASTER_SLAVE_MASK 0x00000020
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_ID_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_ID_WIDTH 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_ID_MASK 0x0000001F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_ID_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS                  0x0003FF10
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_WIDTH            32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_MASK             0x0000007F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_TILE_CONTROL_LSB 6
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_TILE_CONTROL_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_TILE_CONTROL_MASK 0x00000040
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_TILE_CONTROL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_5_LSB    5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_5_WIDTH  1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_5_MASK   0x00000020
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_5_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_4_LSB    4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_4_WIDTH  1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_4_MASK   0x00000010
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_4_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_3_LSB    3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_3_WIDTH  1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_3_MASK   0x00000008
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_3_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_2_LSB    2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_2_WIDTH  1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_2_MASK   0x00000004
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_2_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_1_LSB    1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_1_WIDTH  1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_1_MASK   0x00000002
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_1_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_0_LSB    0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_0_WIDTH  1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_0_MASK   0x00000001
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_STATUS_SOUTH_0_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION               0x0003FF20
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_WIDTH         32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_MASK          0x000003FF
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SHIM_TRACE_LSB 9
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SHIM_TRACE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SHIM_TRACE_MASK 0x00000200
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SHIM_TRACE_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_TILE_CONTROL_LSB 8
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_TILE_CONTROL_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_TILE_CONTROL_MASK 0x00000100
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_TILE_CONTROL_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_7_LSB 7
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_7_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_7_MASK 0x00000080
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_7_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_6_LSB 6
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_6_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_6_MASK 0x00000040
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_6_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_5_LSB 5
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_5_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_5_MASK 0x00000020
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_5_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_4_LSB 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_4_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_4_MASK 0x00000010
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_4_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_3_LSB 3
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_3_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_3_MASK 0x00000008
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_3_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_2_LSB 2
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_2_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_2_MASK 0x00000004
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_2_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_1_LSB 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_1_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_1_MASK 0x00000002
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_1_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_0_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_0_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_0_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_PARITY_INJECTION_SOUTH_0_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS                0x0003FF30
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_WIDTH          32
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_MASK           0x0000000F
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_TLAST_ERROR_LSB 3
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_TLAST_ERROR_WIDTH 1
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_TLAST_ERROR_MASK 0x00000008
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_TLAST_ERROR_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_SLVERR_ON_ACCESS_LSB 2
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_SLVERR_ON_ACCESS_WIDTH 1
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_SLVERR_ON_ACCESS_MASK 0x00000004
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_SLVERR_ON_ACCESS_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_SECOND_HEADER_PARITY_ERROR_LSB 1
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_SECOND_HEADER_PARITY_ERROR_WIDTH 1
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_SECOND_HEADER_PARITY_ERROR_MASK 0x00000002
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_SECOND_HEADER_PARITY_ERROR_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_FIRST_HEADER_PARITY_ERROR_LSB 0
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_FIRST_HEADER_PARITY_ERROR_WIDTH 1
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_FIRST_HEADER_PARITY_ERROR_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_CONTROL_PACKET_HANDLER_STATUS_FIRST_HEADER_PARITY_ERROR_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS     0x0003FF34
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_WIDTH 32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_ACTIVE_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_ACTIVE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_ACTIVE_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_ACTIVE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD 0x0003FF38
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_WIDTH 32
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_MASK 0x0000000F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_ABORT_PERIOD_LSB 0
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_ABORT_PERIOD_WIDTH 4
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_ABORT_PERIOD_MASK 0x0000000F
#define XAIEMLGBL_PL_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_ABORT_PERIOD_DEFVAL 0x7

#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0                       0x000FFF00
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_WIDTH                 32
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_MASK                  0x0000003B
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_DMA_ADAPTIVE_CLOCK_GATE_LSB 5
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_DMA_ADAPTIVE_CLOCK_GATE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_DMA_ADAPTIVE_CLOCK_GATE_MASK 0x00000020
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_DMA_ADAPTIVE_CLOCK_GATE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_LSB 4
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_MASK 0x00000010
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_CTE_CLOCK_ENABLE_LSB 3
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_CTE_CLOCK_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_CTE_CLOCK_ENABLE_MASK 0x00000008
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_CTE_CLOCK_ENABLE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_PL_INTERFACE_CLOCK_ENABLE_LSB 1
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_PL_INTERFACE_CLOCK_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_PL_INTERFACE_CLOCK_ENABLE_MASK 0x00000002
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_PL_INTERFACE_CLOCK_ENABLE_DEFVAL 0x1
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_STREAM_SWITCH_CLOCK_ENABLE_LSB 0
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_STREAM_SWITCH_CLOCK_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_STREAM_SWITCH_CLOCK_ENABLE_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_0_STREAM_SWITCH_CLOCK_ENABLE_DEFVAL 0x1

#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_1                       0x000FFF04
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_1_WIDTH                 32
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_1_MASK                  0x00000001
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_1_NOC_MODULE_CLOCK_ENABLE_LSB 0
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_1_NOC_MODULE_CLOCK_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_1_NOC_MODULE_CLOCK_ENABLE_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_MODULE_CLOCK_CONTROL_1_NOC_MODULE_CLOCK_ENABLE_DEFVAL 0x1

#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0                       0x000FFF10
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_WIDTH                 32
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_MASK                  0x0000000B
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_CTE_MODULE_RESET_LSB 3
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_CTE_MODULE_RESET_WIDTH 1
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_CTE_MODULE_RESET_MASK 0x00000008
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_CTE_MODULE_RESET_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_PL_INTERFACE_RESET_LSB 1
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_PL_INTERFACE_RESET_WIDTH 1
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_PL_INTERFACE_RESET_MASK 0x00000002
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_PL_INTERFACE_RESET_DEFVAL 0x0
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_STREAM_SWITCH_RESET_LSB 0
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_STREAM_SWITCH_RESET_WIDTH 1
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_STREAM_SWITCH_RESET_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_0_STREAM_SWITCH_RESET_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_1                       0x000FFF14
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_1_WIDTH                 32
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_1_MASK                  0x00000001
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_1_NOC_MODULE_RESET_LSB 0
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_1_NOC_MODULE_RESET_WIDTH 1
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_1_NOC_MODULE_RESET_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_MODULE_RESET_CONTROL_1_NOC_MODULE_RESET_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_COLUMN_CLOCK_CONTROL                         0x000FFF20
#define XAIEMLGBL_PL_MODULE_COLUMN_CLOCK_CONTROL_WIDTH                   32
#define XAIEMLGBL_PL_MODULE_COLUMN_CLOCK_CONTROL_MASK                    0x00000001
#define XAIEMLGBL_PL_MODULE_COLUMN_CLOCK_CONTROL_CLOCK_BUFFER_ENABLE_LSB 0
#define XAIEMLGBL_PL_MODULE_COLUMN_CLOCK_CONTROL_CLOCK_BUFFER_ENABLE_WIDTH 1
#define XAIEMLGBL_PL_MODULE_COLUMN_CLOCK_CONTROL_CLOCK_BUFFER_ENABLE_MASK 0x00000001
#define XAIEMLGBL_PL_MODULE_COLUMN_CLOCK_CONTROL_CLOCK_BUFFER_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_PL_MODULE_CSSD_TRIGGER                                 0x000FFF24
#define XAIEMLGBL_PL_MODULE_CSSD_TRIGGER_WIDTH                           32
#define XAIEMLGBL_PL_MODULE_CSSD_TRIGGER_MASK                            0x00000001
#define XAIEMLGBL_PL_MODULE_CSSD_TRIGGER_TRIGGER_LSB                   0
#define XAIEMLGBL_PL_MODULE_CSSD_TRIGGER_TRIGGER_WIDTH                 1
#define XAIEMLGBL_PL_MODULE_CSSD_TRIGGER_TRIGGER_MASK                  0x00000001
#define XAIEMLGBL_PL_MODULE_CSSD_TRIGGER_TRIGGER_DEFVAL                0x0

#define XAIEMLGBL_PL_MODULE_COLUMN_RESET_CONTROL                         0x000FFF28
#define XAIEMLGBL_PL_MODULE_COLUMN_RESET_CONTROL_WIDTH                   32
#define XAIEMLGBL_PL_MODULE_COLUMN_RESET_CONTROL_MASK                    0x00000001
#define XAIEMLGBL_PL_MODULE_COLUMN_RESET_CONTROL_RESET_LSB             0
#define XAIEMLGBL_PL_MODULE_COLUMN_RESET_CONTROL_RESET_WIDTH           1
#define XAIEMLGBL_PL_MODULE_COLUMN_RESET_CONTROL_RESET_MASK            0x00000001
#define XAIEMLGBL_PL_MODULE_COLUMN_RESET_CONTROL_RESET_DEFVAL          0x0

#define XAIEMLGBL_PL_MODULE_SPARE_REG                                    0x000FFF30
#define XAIEMLGBL_PL_MODULE_SPARE_REG_WIDTH                              32
#define XAIEMLGBL_PL_MODULE_SPARE_REG_MASK                               0x0000FFFF
#define XAIEMLGBL_PL_MODULE_SPARE_REG_SPARE_REG_LSB                    0
#define XAIEMLGBL_PL_MODULE_SPARE_REG_SPARE_REG_WIDTH                  16
#define XAIEMLGBL_PL_MODULE_SPARE_REG_SPARE_REG_MASK                   0x0000FFFF
#define XAIEMLGBL_PL_MODULE_SPARE_REG_SPARE_REG_DEFVAL                 0x0

/* AIE-ML NOC module register definitions */
#define XAIEMLGBL_NOC_MODULE_LOCK0_VALUE                                 0x00014000
#define XAIEMLGBL_NOC_MODULE_LOCK0_VALUE_WIDTH                           32
#define XAIEMLGBL_NOC_MODULE_LOCK0_VALUE_MASK                            0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK0_VALUE_LOCK_VALUE_LSB                0
#define XAIEMLGBL_NOC_MODULE_LOCK0_VALUE_LOCK_VALUE_WIDTH              6
#define XAIEMLGBL_NOC_MODULE_LOCK0_VALUE_LOCK_VALUE_MASK               0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK0_VALUE_LOCK_VALUE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_LOCK1_VALUE                                 0x00014010
#define XAIEMLGBL_NOC_MODULE_LOCK1_VALUE_WIDTH                           32
#define XAIEMLGBL_NOC_MODULE_LOCK1_VALUE_MASK                            0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK1_VALUE_LOCK_VALUE_LSB                0
#define XAIEMLGBL_NOC_MODULE_LOCK1_VALUE_LOCK_VALUE_WIDTH              6
#define XAIEMLGBL_NOC_MODULE_LOCK1_VALUE_LOCK_VALUE_MASK               0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK1_VALUE_LOCK_VALUE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_LOCK2_VALUE                                 0x00014020
#define XAIEMLGBL_NOC_MODULE_LOCK2_VALUE_WIDTH                           32
#define XAIEMLGBL_NOC_MODULE_LOCK2_VALUE_MASK                            0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK2_VALUE_LOCK_VALUE_LSB                0
#define XAIEMLGBL_NOC_MODULE_LOCK2_VALUE_LOCK_VALUE_WIDTH              6
#define XAIEMLGBL_NOC_MODULE_LOCK2_VALUE_LOCK_VALUE_MASK               0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK2_VALUE_LOCK_VALUE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_LOCK3_VALUE                                 0x00014030
#define XAIEMLGBL_NOC_MODULE_LOCK3_VALUE_WIDTH                           32
#define XAIEMLGBL_NOC_MODULE_LOCK3_VALUE_MASK                            0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK3_VALUE_LOCK_VALUE_LSB                0
#define XAIEMLGBL_NOC_MODULE_LOCK3_VALUE_LOCK_VALUE_WIDTH              6
#define XAIEMLGBL_NOC_MODULE_LOCK3_VALUE_LOCK_VALUE_MASK               0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK3_VALUE_LOCK_VALUE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_LOCK4_VALUE                                 0x00014040
#define XAIEMLGBL_NOC_MODULE_LOCK4_VALUE_WIDTH                           32
#define XAIEMLGBL_NOC_MODULE_LOCK4_VALUE_MASK                            0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK4_VALUE_LOCK_VALUE_LSB                0
#define XAIEMLGBL_NOC_MODULE_LOCK4_VALUE_LOCK_VALUE_WIDTH              6
#define XAIEMLGBL_NOC_MODULE_LOCK4_VALUE_LOCK_VALUE_MASK               0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK4_VALUE_LOCK_VALUE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_LOCK5_VALUE                                 0x00014050
#define XAIEMLGBL_NOC_MODULE_LOCK5_VALUE_WIDTH                           32
#define XAIEMLGBL_NOC_MODULE_LOCK5_VALUE_MASK                            0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK5_VALUE_LOCK_VALUE_LSB                0
#define XAIEMLGBL_NOC_MODULE_LOCK5_VALUE_LOCK_VALUE_WIDTH              6
#define XAIEMLGBL_NOC_MODULE_LOCK5_VALUE_LOCK_VALUE_MASK               0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK5_VALUE_LOCK_VALUE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_LOCK6_VALUE                                 0x00014060
#define XAIEMLGBL_NOC_MODULE_LOCK6_VALUE_WIDTH                           32
#define XAIEMLGBL_NOC_MODULE_LOCK6_VALUE_MASK                            0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK6_VALUE_LOCK_VALUE_LSB                0
#define XAIEMLGBL_NOC_MODULE_LOCK6_VALUE_LOCK_VALUE_WIDTH              6
#define XAIEMLGBL_NOC_MODULE_LOCK6_VALUE_LOCK_VALUE_MASK               0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK6_VALUE_LOCK_VALUE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_LOCK7_VALUE                                 0x00014070
#define XAIEMLGBL_NOC_MODULE_LOCK7_VALUE_WIDTH                           32
#define XAIEMLGBL_NOC_MODULE_LOCK7_VALUE_MASK                            0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK7_VALUE_LOCK_VALUE_LSB                0
#define XAIEMLGBL_NOC_MODULE_LOCK7_VALUE_LOCK_VALUE_WIDTH              6
#define XAIEMLGBL_NOC_MODULE_LOCK7_VALUE_LOCK_VALUE_MASK               0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK7_VALUE_LOCK_VALUE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_LOCK8_VALUE                                 0x00014080
#define XAIEMLGBL_NOC_MODULE_LOCK8_VALUE_WIDTH                           32
#define XAIEMLGBL_NOC_MODULE_LOCK8_VALUE_MASK                            0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK8_VALUE_LOCK_VALUE_LSB                0
#define XAIEMLGBL_NOC_MODULE_LOCK8_VALUE_LOCK_VALUE_WIDTH              6
#define XAIEMLGBL_NOC_MODULE_LOCK8_VALUE_LOCK_VALUE_MASK               0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK8_VALUE_LOCK_VALUE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_LOCK9_VALUE                                 0x00014090
#define XAIEMLGBL_NOC_MODULE_LOCK9_VALUE_WIDTH                           32
#define XAIEMLGBL_NOC_MODULE_LOCK9_VALUE_MASK                            0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK9_VALUE_LOCK_VALUE_LSB                0
#define XAIEMLGBL_NOC_MODULE_LOCK9_VALUE_LOCK_VALUE_WIDTH              6
#define XAIEMLGBL_NOC_MODULE_LOCK9_VALUE_LOCK_VALUE_MASK               0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK9_VALUE_LOCK_VALUE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_LOCK10_VALUE                                0x000140A0
#define XAIEMLGBL_NOC_MODULE_LOCK10_VALUE_WIDTH                          32
#define XAIEMLGBL_NOC_MODULE_LOCK10_VALUE_MASK                           0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK10_VALUE_LOCK_VALUE_LSB               0
#define XAIEMLGBL_NOC_MODULE_LOCK10_VALUE_LOCK_VALUE_WIDTH             6
#define XAIEMLGBL_NOC_MODULE_LOCK10_VALUE_LOCK_VALUE_MASK              0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK10_VALUE_LOCK_VALUE_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_LOCK11_VALUE                                0x000140B0
#define XAIEMLGBL_NOC_MODULE_LOCK11_VALUE_WIDTH                          32
#define XAIEMLGBL_NOC_MODULE_LOCK11_VALUE_MASK                           0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK11_VALUE_LOCK_VALUE_LSB               0
#define XAIEMLGBL_NOC_MODULE_LOCK11_VALUE_LOCK_VALUE_WIDTH             6
#define XAIEMLGBL_NOC_MODULE_LOCK11_VALUE_LOCK_VALUE_MASK              0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK11_VALUE_LOCK_VALUE_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_LOCK12_VALUE                                0x000140C0
#define XAIEMLGBL_NOC_MODULE_LOCK12_VALUE_WIDTH                          32
#define XAIEMLGBL_NOC_MODULE_LOCK12_VALUE_MASK                           0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK12_VALUE_LOCK_VALUE_LSB               0
#define XAIEMLGBL_NOC_MODULE_LOCK12_VALUE_LOCK_VALUE_WIDTH             6
#define XAIEMLGBL_NOC_MODULE_LOCK12_VALUE_LOCK_VALUE_MASK              0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK12_VALUE_LOCK_VALUE_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_LOCK13_VALUE                                0x000140D0
#define XAIEMLGBL_NOC_MODULE_LOCK13_VALUE_WIDTH                          32
#define XAIEMLGBL_NOC_MODULE_LOCK13_VALUE_MASK                           0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK13_VALUE_LOCK_VALUE_LSB               0
#define XAIEMLGBL_NOC_MODULE_LOCK13_VALUE_LOCK_VALUE_WIDTH             6
#define XAIEMLGBL_NOC_MODULE_LOCK13_VALUE_LOCK_VALUE_MASK              0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK13_VALUE_LOCK_VALUE_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_LOCK14_VALUE                                0x000140E0
#define XAIEMLGBL_NOC_MODULE_LOCK14_VALUE_WIDTH                          32
#define XAIEMLGBL_NOC_MODULE_LOCK14_VALUE_MASK                           0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK14_VALUE_LOCK_VALUE_LSB               0
#define XAIEMLGBL_NOC_MODULE_LOCK14_VALUE_LOCK_VALUE_WIDTH             6
#define XAIEMLGBL_NOC_MODULE_LOCK14_VALUE_LOCK_VALUE_MASK              0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK14_VALUE_LOCK_VALUE_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_LOCK15_VALUE                                0x000140F0
#define XAIEMLGBL_NOC_MODULE_LOCK15_VALUE_WIDTH                          32
#define XAIEMLGBL_NOC_MODULE_LOCK15_VALUE_MASK                           0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK15_VALUE_LOCK_VALUE_LSB               0
#define XAIEMLGBL_NOC_MODULE_LOCK15_VALUE_LOCK_VALUE_WIDTH             6
#define XAIEMLGBL_NOC_MODULE_LOCK15_VALUE_LOCK_VALUE_MASK              0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCK15_VALUE_LOCK_VALUE_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_0                     0x00014100
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_0_WIDTH               32
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_0_MASK                0x000F003F
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_SELECT_LSB   16
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_SELECT_MASK  0x000F0000
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_VALUE_LSB    0
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_VALUE_WIDTH  6
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_VALUE_MASK   0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_1                     0x00014104
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_1_WIDTH               32
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_1_MASK                0x000F003F
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_SELECT_LSB   16
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_SELECT_MASK  0x000F0000
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_VALUE_LSB    0
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_VALUE_WIDTH  6
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_VALUE_MASK   0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_2                     0x00014108
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_2_WIDTH               32
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_2_MASK                0x000F003F
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_SELECT_LSB   16
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_SELECT_MASK  0x000F0000
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_VALUE_LSB    0
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_VALUE_WIDTH  6
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_VALUE_MASK   0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_3                     0x0001410C
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_3_WIDTH               32
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_3_MASK                0x000F003F
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_SELECT_LSB   16
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_SELECT_MASK  0x000F0000
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_VALUE_LSB    0
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_VALUE_WIDTH  6
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_VALUE_MASK   0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_4                     0x00014110
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_4_WIDTH               32
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_4_MASK                0x000F003F
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_SELECT_LSB   16
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_SELECT_MASK  0x000F0000
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_VALUE_LSB    0
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_VALUE_WIDTH  6
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_VALUE_MASK   0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_5                     0x00014114
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_5_WIDTH               32
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_5_MASK                0x000F003F
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_SELECT_LSB   16
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_SELECT_WIDTH 4
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_SELECT_MASK  0x000F0000
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_VALUE_LSB    0
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_VALUE_WIDTH  6
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_VALUE_MASK   0x0000003F
#define XAIEMLGBL_NOC_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW                              0x00014120
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_WIDTH                        32
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_MASK                         0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_15_LSB       15
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_15_WIDTH     1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_15_MASK      0x00008000
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_15_DEFVAL    0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_14_LSB       14
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_14_WIDTH     1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_14_MASK      0x00004000
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_14_DEFVAL    0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_13_LSB       13
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_13_WIDTH     1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_13_MASK      0x00002000
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_13_DEFVAL    0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_12_LSB       12
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_12_WIDTH     1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_12_MASK      0x00001000
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_12_DEFVAL    0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_11_LSB       11
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_11_WIDTH     1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_11_MASK      0x00000800
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_11_DEFVAL    0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_10_LSB       10
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_10_WIDTH     1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_10_MASK      0x00000400
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_10_DEFVAL    0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_9_LSB        9
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_9_WIDTH      1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_9_MASK       0x00000200
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_9_DEFVAL     0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_8_LSB        8
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_8_WIDTH      1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_8_MASK       0x00000100
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_8_DEFVAL     0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_7_LSB        7
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_7_WIDTH      1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_7_MASK       0x00000080
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_7_DEFVAL     0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_6_LSB        6
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_6_WIDTH      1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_6_MASK       0x00000040
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_6_DEFVAL     0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_5_LSB        5
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_5_WIDTH      1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_5_MASK       0x00000020
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_5_DEFVAL     0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_4_LSB        4
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_4_WIDTH      1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_4_MASK       0x00000010
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_4_DEFVAL     0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_3_LSB        3
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_3_WIDTH      1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_3_MASK       0x00000008
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_3_DEFVAL     0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_2_LSB        2
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_2_WIDTH      1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_2_MASK       0x00000004
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_2_DEFVAL     0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_1_LSB        1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_1_WIDTH      1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_1_MASK       0x00000002
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_1_DEFVAL     0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_0_LSB        0
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_0_WIDTH      1
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_0_MASK       0x00000001
#define XAIEMLGBL_NOC_MODULE_LOCKS_OVERFLOW_LOCK_OVERFLOW_0_DEFVAL     0x0

#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW                             0x00014128
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_WIDTH                       32
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_MASK                        0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_15_LSB     15
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_15_WIDTH   1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_15_MASK    0x00008000
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_15_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_14_LSB     14
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_14_WIDTH   1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_14_MASK    0x00004000
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_14_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_13_LSB     13
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_13_WIDTH   1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_13_MASK    0x00002000
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_13_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_12_LSB     12
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_12_WIDTH   1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_12_MASK    0x00001000
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_12_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_11_LSB     11
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_11_WIDTH   1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_11_MASK    0x00000800
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_11_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_10_LSB     10
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_10_WIDTH   1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_10_MASK    0x00000400
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_10_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_9_LSB      9
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_9_WIDTH    1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_9_MASK     0x00000200
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_9_DEFVAL   0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_8_LSB      8
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_8_WIDTH    1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_8_MASK     0x00000100
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_8_DEFVAL   0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_7_LSB      7
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_7_WIDTH    1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_7_MASK     0x00000080
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_7_DEFVAL   0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_6_LSB      6
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_6_WIDTH    1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_6_MASK     0x00000040
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_6_DEFVAL   0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_5_LSB      5
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_5_WIDTH    1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_5_MASK     0x00000020
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_5_DEFVAL   0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_4_LSB      4
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_4_WIDTH    1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_4_MASK     0x00000010
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_4_DEFVAL   0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_3_LSB      3
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_3_WIDTH    1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_3_MASK     0x00000008
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_3_DEFVAL   0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_2_LSB      2
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_2_WIDTH    1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_2_MASK     0x00000004
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_2_DEFVAL   0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_1_LSB      1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_1_WIDTH    1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_1_MASK     0x00000002
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_1_DEFVAL   0x0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_0_LSB      0
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_0_WIDTH    1
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_0_MASK     0x00000001
#define XAIEMLGBL_NOC_MODULE_LOCKS_UNDERFLOW_LOCK_UNDERFLOW_0_DEFVAL   0x0

#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_MASK         0x00015000
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_MASK_WIDTH   32
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_MASK_MASK    0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_MASK_IRQ_MASK_A_LSB 0
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_MASK_IRQ_MASK_A_WIDTH 16
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_MASK_IRQ_MASK_A_MASK 0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_MASK_IRQ_MASK_A_DEFVAL 0x0

#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_ENABLE       0x00015004
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_ENABLE_WIDTH 32
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_ENABLE_MASK  0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_ENABLE_ENABLE_A_LSB 0
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_ENABLE_ENABLE_A_WIDTH 16
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_ENABLE_ENABLE_A_MASK 0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_ENABLE_ENABLE_A_DEFVAL 0x0

#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_DISABLE      0x00015008
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_DISABLE_WIDTH 32
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_DISABLE_MASK 0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_DISABLE_DISABLE_A_LSB 0
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_DISABLE_DISABLE_A_WIDTH 16
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_DISABLE_DISABLE_A_MASK 0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_DISABLE_DISABLE_A_DEFVAL 0x0

#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_STATUS       0x0001500C
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_STATUS_WIDTH 32
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_STATUS_MASK  0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_STATUS_STATUS_A_LSB 0
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_STATUS_STATUS_A_WIDTH 16
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_STATUS_STATUS_A_MASK 0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_STATUS_STATUS_A_DEFVAL 0x0

#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_INTERRUPT    0x00015010
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_INTERRUPT_WIDTH 32
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_INTERRUPT_MASK 0x00000003
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_INTERRUPT_NOC_INTERRUPT_LSB 0
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_INTERRUPT_NOC_INTERRUPT_WIDTH 2
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_INTERRUPT_NOC_INTERRUPT_MASK 0x00000003
#define XAIEMLGBL_NOC_MODULE_INTERRUPT_CONTROLLER_2ND_LEVEL_INTERRUPT_NOC_INTERRUPT_DEFVAL 0x0

#define XAIEMLGBL_NOC_MODULE_SPARE_REG                                   0x00016000
#define XAIEMLGBL_NOC_MODULE_SPARE_REG_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_SPARE_REG_MASK                              0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_SPARE_REG_SPARE_REG_LSB                   0
#define XAIEMLGBL_NOC_MODULE_SPARE_REG_SPARE_REG_WIDTH                 16
#define XAIEMLGBL_NOC_MODULE_SPARE_REG_SPARE_REG_MASK                  0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_SPARE_REG_SPARE_REG_DEFVAL                0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD0_0                                   0x0001D000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_0_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_0_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_0_BUFFER_LENGTH_LSB               0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_0_BUFFER_LENGTH_WIDTH             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_0_BUFFER_LENGTH_MASK              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_0_BUFFER_LENGTH_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD0_1                                   0x0001D004
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_1_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_1_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_1_BASE_ADDRESS_LOW_LSB            2
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_1_BASE_ADDRESS_LOW_WIDTH          30
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_1_BASE_ADDRESS_LOW_MASK           0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_1_BASE_ADDRESS_LOW_DEFVAL         0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2                                   0x0001D008
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_ENABLE_PACKET_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_ENABLE_PACKET_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_ENABLE_PACKET_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_ENABLE_PACKET_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_OUT_OF_ORDER_BD_ID_LSB          24
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_OUT_OF_ORDER_BD_ID_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_OUT_OF_ORDER_BD_ID_MASK         0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_OUT_OF_ORDER_BD_ID_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_PACKET_ID_LSB                   19
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_PACKET_ID_WIDTH                 5
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_PACKET_ID_MASK                  0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_PACKET_ID_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_PACKET_TYPE_LSB                 16
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_PACKET_TYPE_WIDTH               3
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_PACKET_TYPE_MASK                0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_PACKET_TYPE_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_BASE_ADDRESS_HIGH_LSB           0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_BASE_ADDRESS_HIGH_WIDTH         16
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_BASE_ADDRESS_HIGH_MASK          0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_2_BASE_ADDRESS_HIGH_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3                                   0x0001D00C
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_SECURE_ACCESS_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_SECURE_ACCESS_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_SECURE_ACCESS_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_SECURE_ACCESS_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_D0_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_D0_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_D0_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_D0_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_D0_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_D0_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_D0_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_3_D0_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4                                   0x0001D010
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_BURST_LENGTH_LSB                30
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_BURST_LENGTH_WIDTH              2
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_BURST_LENGTH_MASK               0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_BURST_LENGTH_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_D1_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_D1_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_D1_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_D1_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_D1_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_D1_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_D1_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_4_D1_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5                                   0x0001D014
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_SMID_LSB                        28
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_SMID_WIDTH                      4
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_SMID_MASK                       0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_SMID_DEFVAL                     0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_AXCACHE_LSB                     24
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_AXCACHE_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_AXCACHE_MASK                    0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_AXCACHE_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_AXQOS_LSB                       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_AXQOS_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_AXQOS_MASK                      0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_AXQOS_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_D2_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_D2_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_D2_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_5_D2_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6                                   0x0001D018
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_ITERATION_CURRENT_LSB           26
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_ITERATION_CURRENT_WIDTH         6
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_ITERATION_CURRENT_MASK          0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_ITERATION_CURRENT_DEFVAL        0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_ITERATION_WRAP_LSB              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_ITERATION_WRAP_WIDTH            6
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_ITERATION_WRAP_MASK             0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_ITERATION_WRAP_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_ITERATION_STEPSIZE_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_ITERATION_STEPSIZE_WIDTH        20
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_ITERATION_STEPSIZE_MASK         0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_6_ITERATION_STEPSIZE_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7                                   0x0001D01C
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_MASK                              0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_TLAST_SUPPRESS_LSB              31
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_TLAST_SUPPRESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_TLAST_SUPPRESS_MASK             0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_TLAST_SUPPRESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_NEXT_BD_LSB                     27
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_NEXT_BD_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_NEXT_BD_MASK                    0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_NEXT_BD_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_USE_NEXT_BD_LSB                 26
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_USE_NEXT_BD_WIDTH               1
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_USE_NEXT_BD_MASK                0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_USE_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_VALID_BD_LSB                    25
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_VALID_BD_WIDTH                  1
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_VALID_BD_MASK                   0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_VALID_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_REL_VALUE_LSB              18
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_REL_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_REL_VALUE_MASK             0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_REL_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_REL_ID_LSB                 13
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_REL_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_REL_ID_MASK                0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_REL_ID_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_ACQ_ENABLE_LSB             12
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_ACQ_ENABLE_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_ACQ_ENABLE_MASK            0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_ACQ_ENABLE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_ACQ_VALUE_LSB              5
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_ACQ_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_ACQ_VALUE_MASK             0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_ACQ_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_ACQ_ID_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_ACQ_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_ACQ_ID_MASK                0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD0_7_LOCK_ACQ_ID_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD1_0                                   0x0001D020
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_0_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_0_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_0_BUFFER_LENGTH_LSB               0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_0_BUFFER_LENGTH_WIDTH             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_0_BUFFER_LENGTH_MASK              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_0_BUFFER_LENGTH_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD1_1                                   0x0001D024
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_1_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_1_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_1_BASE_ADDRESS_LOW_LSB            2
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_1_BASE_ADDRESS_LOW_WIDTH          30
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_1_BASE_ADDRESS_LOW_MASK           0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_1_BASE_ADDRESS_LOW_DEFVAL         0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2                                   0x0001D028
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_ENABLE_PACKET_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_ENABLE_PACKET_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_ENABLE_PACKET_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_ENABLE_PACKET_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_OUT_OF_ORDER_BD_ID_LSB          24
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_OUT_OF_ORDER_BD_ID_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_OUT_OF_ORDER_BD_ID_MASK         0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_OUT_OF_ORDER_BD_ID_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_PACKET_ID_LSB                   19
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_PACKET_ID_WIDTH                 5
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_PACKET_ID_MASK                  0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_PACKET_ID_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_PACKET_TYPE_LSB                 16
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_PACKET_TYPE_WIDTH               3
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_PACKET_TYPE_MASK                0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_PACKET_TYPE_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_BASE_ADDRESS_HIGH_LSB           0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_BASE_ADDRESS_HIGH_WIDTH         16
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_BASE_ADDRESS_HIGH_MASK          0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_2_BASE_ADDRESS_HIGH_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3                                   0x0001D02C
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_SECURE_ACCESS_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_SECURE_ACCESS_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_SECURE_ACCESS_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_SECURE_ACCESS_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_D0_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_D0_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_D0_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_D0_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_D0_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_D0_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_D0_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_3_D0_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4                                   0x0001D030
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_BURST_LENGTH_LSB                30
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_BURST_LENGTH_WIDTH              2
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_BURST_LENGTH_MASK               0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_BURST_LENGTH_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_D1_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_D1_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_D1_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_D1_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_D1_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_D1_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_D1_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_4_D1_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5                                   0x0001D034
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_SMID_LSB                        28
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_SMID_WIDTH                      4
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_SMID_MASK                       0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_SMID_DEFVAL                     0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_AXCACHE_LSB                     24
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_AXCACHE_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_AXCACHE_MASK                    0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_AXCACHE_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_AXQOS_LSB                       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_AXQOS_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_AXQOS_MASK                      0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_AXQOS_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_D2_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_D2_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_D2_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_5_D2_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6                                   0x0001D038
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_ITERATION_CURRENT_LSB           26
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_ITERATION_CURRENT_WIDTH         6
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_ITERATION_CURRENT_MASK          0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_ITERATION_CURRENT_DEFVAL        0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_ITERATION_WRAP_LSB              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_ITERATION_WRAP_WIDTH            6
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_ITERATION_WRAP_MASK             0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_ITERATION_WRAP_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_ITERATION_STEPSIZE_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_ITERATION_STEPSIZE_WIDTH        20
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_ITERATION_STEPSIZE_MASK         0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_6_ITERATION_STEPSIZE_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7                                   0x0001D03C
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_MASK                              0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_TLAST_SUPPRESS_LSB              31
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_TLAST_SUPPRESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_TLAST_SUPPRESS_MASK             0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_TLAST_SUPPRESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_NEXT_BD_LSB                     27
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_NEXT_BD_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_NEXT_BD_MASK                    0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_NEXT_BD_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_USE_NEXT_BD_LSB                 26
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_USE_NEXT_BD_WIDTH               1
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_USE_NEXT_BD_MASK                0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_USE_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_VALID_BD_LSB                    25
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_VALID_BD_WIDTH                  1
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_VALID_BD_MASK                   0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_VALID_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_REL_VALUE_LSB              18
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_REL_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_REL_VALUE_MASK             0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_REL_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_REL_ID_LSB                 13
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_REL_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_REL_ID_MASK                0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_REL_ID_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_ACQ_ENABLE_LSB             12
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_ACQ_ENABLE_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_ACQ_ENABLE_MASK            0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_ACQ_ENABLE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_ACQ_VALUE_LSB              5
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_ACQ_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_ACQ_VALUE_MASK             0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_ACQ_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_ACQ_ID_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_ACQ_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_ACQ_ID_MASK                0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD1_7_LOCK_ACQ_ID_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD2_0                                   0x0001D040
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_0_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_0_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_0_BUFFER_LENGTH_LSB               0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_0_BUFFER_LENGTH_WIDTH             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_0_BUFFER_LENGTH_MASK              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_0_BUFFER_LENGTH_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD2_1                                   0x0001D044
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_1_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_1_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_1_BASE_ADDRESS_LOW_LSB            2
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_1_BASE_ADDRESS_LOW_WIDTH          30
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_1_BASE_ADDRESS_LOW_MASK           0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_1_BASE_ADDRESS_LOW_DEFVAL         0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2                                   0x0001D048
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_ENABLE_PACKET_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_ENABLE_PACKET_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_ENABLE_PACKET_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_ENABLE_PACKET_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_OUT_OF_ORDER_BD_ID_LSB          24
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_OUT_OF_ORDER_BD_ID_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_OUT_OF_ORDER_BD_ID_MASK         0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_OUT_OF_ORDER_BD_ID_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_PACKET_ID_LSB                   19
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_PACKET_ID_WIDTH                 5
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_PACKET_ID_MASK                  0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_PACKET_ID_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_PACKET_TYPE_LSB                 16
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_PACKET_TYPE_WIDTH               3
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_PACKET_TYPE_MASK                0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_PACKET_TYPE_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_BASE_ADDRESS_HIGH_LSB           0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_BASE_ADDRESS_HIGH_WIDTH         16
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_BASE_ADDRESS_HIGH_MASK          0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_2_BASE_ADDRESS_HIGH_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3                                   0x0001D04C
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_SECURE_ACCESS_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_SECURE_ACCESS_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_SECURE_ACCESS_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_SECURE_ACCESS_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_D0_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_D0_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_D0_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_D0_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_D0_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_D0_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_D0_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_3_D0_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4                                   0x0001D050
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_BURST_LENGTH_LSB                30
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_BURST_LENGTH_WIDTH              2
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_BURST_LENGTH_MASK               0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_BURST_LENGTH_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_D1_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_D1_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_D1_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_D1_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_D1_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_D1_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_D1_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_4_D1_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5                                   0x0001D054
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_SMID_LSB                        28
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_SMID_WIDTH                      4
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_SMID_MASK                       0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_SMID_DEFVAL                     0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_AXCACHE_LSB                     24
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_AXCACHE_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_AXCACHE_MASK                    0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_AXCACHE_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_AXQOS_LSB                       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_AXQOS_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_AXQOS_MASK                      0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_AXQOS_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_D2_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_D2_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_D2_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_5_D2_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6                                   0x0001D058
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_ITERATION_CURRENT_LSB           26
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_ITERATION_CURRENT_WIDTH         6
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_ITERATION_CURRENT_MASK          0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_ITERATION_CURRENT_DEFVAL        0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_ITERATION_WRAP_LSB              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_ITERATION_WRAP_WIDTH            6
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_ITERATION_WRAP_MASK             0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_ITERATION_WRAP_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_ITERATION_STEPSIZE_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_ITERATION_STEPSIZE_WIDTH        20
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_ITERATION_STEPSIZE_MASK         0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_6_ITERATION_STEPSIZE_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7                                   0x0001D05C
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_MASK                              0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_TLAST_SUPPRESS_LSB              31
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_TLAST_SUPPRESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_TLAST_SUPPRESS_MASK             0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_TLAST_SUPPRESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_NEXT_BD_LSB                     27
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_NEXT_BD_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_NEXT_BD_MASK                    0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_NEXT_BD_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_USE_NEXT_BD_LSB                 26
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_USE_NEXT_BD_WIDTH               1
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_USE_NEXT_BD_MASK                0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_USE_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_VALID_BD_LSB                    25
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_VALID_BD_WIDTH                  1
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_VALID_BD_MASK                   0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_VALID_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_REL_VALUE_LSB              18
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_REL_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_REL_VALUE_MASK             0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_REL_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_REL_ID_LSB                 13
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_REL_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_REL_ID_MASK                0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_REL_ID_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_ACQ_ENABLE_LSB             12
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_ACQ_ENABLE_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_ACQ_ENABLE_MASK            0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_ACQ_ENABLE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_ACQ_VALUE_LSB              5
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_ACQ_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_ACQ_VALUE_MASK             0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_ACQ_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_ACQ_ID_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_ACQ_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_ACQ_ID_MASK                0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD2_7_LOCK_ACQ_ID_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD3_0                                   0x0001D060
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_0_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_0_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_0_BUFFER_LENGTH_LSB               0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_0_BUFFER_LENGTH_WIDTH             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_0_BUFFER_LENGTH_MASK              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_0_BUFFER_LENGTH_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD3_1                                   0x0001D064
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_1_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_1_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_1_BASE_ADDRESS_LOW_LSB            2
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_1_BASE_ADDRESS_LOW_WIDTH          30
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_1_BASE_ADDRESS_LOW_MASK           0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_1_BASE_ADDRESS_LOW_DEFVAL         0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2                                   0x0001D068
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_ENABLE_PACKET_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_ENABLE_PACKET_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_ENABLE_PACKET_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_ENABLE_PACKET_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_OUT_OF_ORDER_BD_ID_LSB          24
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_OUT_OF_ORDER_BD_ID_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_OUT_OF_ORDER_BD_ID_MASK         0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_OUT_OF_ORDER_BD_ID_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_PACKET_ID_LSB                   19
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_PACKET_ID_WIDTH                 5
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_PACKET_ID_MASK                  0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_PACKET_ID_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_PACKET_TYPE_LSB                 16
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_PACKET_TYPE_WIDTH               3
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_PACKET_TYPE_MASK                0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_PACKET_TYPE_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_BASE_ADDRESS_HIGH_LSB           0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_BASE_ADDRESS_HIGH_WIDTH         16
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_BASE_ADDRESS_HIGH_MASK          0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_2_BASE_ADDRESS_HIGH_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3                                   0x0001D06C
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_SECURE_ACCESS_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_SECURE_ACCESS_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_SECURE_ACCESS_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_SECURE_ACCESS_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_D0_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_D0_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_D0_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_D0_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_D0_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_D0_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_D0_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_3_D0_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4                                   0x0001D070
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_BURST_LENGTH_LSB                30
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_BURST_LENGTH_WIDTH              2
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_BURST_LENGTH_MASK               0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_BURST_LENGTH_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_D1_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_D1_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_D1_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_D1_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_D1_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_D1_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_D1_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_4_D1_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5                                   0x0001D074
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_SMID_LSB                        28
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_SMID_WIDTH                      4
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_SMID_MASK                       0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_SMID_DEFVAL                     0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_AXCACHE_LSB                     24
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_AXCACHE_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_AXCACHE_MASK                    0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_AXCACHE_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_AXQOS_LSB                       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_AXQOS_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_AXQOS_MASK                      0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_AXQOS_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_D2_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_D2_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_D2_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_5_D2_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6                                   0x0001D078
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_ITERATION_CURRENT_LSB           26
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_ITERATION_CURRENT_WIDTH         6
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_ITERATION_CURRENT_MASK          0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_ITERATION_CURRENT_DEFVAL        0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_ITERATION_WRAP_LSB              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_ITERATION_WRAP_WIDTH            6
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_ITERATION_WRAP_MASK             0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_ITERATION_WRAP_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_ITERATION_STEPSIZE_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_ITERATION_STEPSIZE_WIDTH        20
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_ITERATION_STEPSIZE_MASK         0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_6_ITERATION_STEPSIZE_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7                                   0x0001D07C
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_MASK                              0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_TLAST_SUPPRESS_LSB              31
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_TLAST_SUPPRESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_TLAST_SUPPRESS_MASK             0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_TLAST_SUPPRESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_NEXT_BD_LSB                     27
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_NEXT_BD_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_NEXT_BD_MASK                    0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_NEXT_BD_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_USE_NEXT_BD_LSB                 26
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_USE_NEXT_BD_WIDTH               1
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_USE_NEXT_BD_MASK                0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_USE_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_VALID_BD_LSB                    25
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_VALID_BD_WIDTH                  1
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_VALID_BD_MASK                   0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_VALID_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_REL_VALUE_LSB              18
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_REL_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_REL_VALUE_MASK             0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_REL_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_REL_ID_LSB                 13
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_REL_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_REL_ID_MASK                0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_REL_ID_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_ACQ_ENABLE_LSB             12
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_ACQ_ENABLE_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_ACQ_ENABLE_MASK            0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_ACQ_ENABLE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_ACQ_VALUE_LSB              5
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_ACQ_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_ACQ_VALUE_MASK             0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_ACQ_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_ACQ_ID_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_ACQ_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_ACQ_ID_MASK                0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD3_7_LOCK_ACQ_ID_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD4_0                                   0x0001D080
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_0_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_0_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_0_BUFFER_LENGTH_LSB               0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_0_BUFFER_LENGTH_WIDTH             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_0_BUFFER_LENGTH_MASK              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_0_BUFFER_LENGTH_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD4_1                                   0x0001D084
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_1_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_1_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_1_BASE_ADDRESS_LOW_LSB            2
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_1_BASE_ADDRESS_LOW_WIDTH          30
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_1_BASE_ADDRESS_LOW_MASK           0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_1_BASE_ADDRESS_LOW_DEFVAL         0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2                                   0x0001D088
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_ENABLE_PACKET_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_ENABLE_PACKET_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_ENABLE_PACKET_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_ENABLE_PACKET_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_OUT_OF_ORDER_BD_ID_LSB          24
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_OUT_OF_ORDER_BD_ID_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_OUT_OF_ORDER_BD_ID_MASK         0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_OUT_OF_ORDER_BD_ID_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_PACKET_ID_LSB                   19
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_PACKET_ID_WIDTH                 5
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_PACKET_ID_MASK                  0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_PACKET_ID_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_PACKET_TYPE_LSB                 16
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_PACKET_TYPE_WIDTH               3
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_PACKET_TYPE_MASK                0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_PACKET_TYPE_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_BASE_ADDRESS_HIGH_LSB           0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_BASE_ADDRESS_HIGH_WIDTH         16
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_BASE_ADDRESS_HIGH_MASK          0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_2_BASE_ADDRESS_HIGH_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3                                   0x0001D08C
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_SECURE_ACCESS_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_SECURE_ACCESS_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_SECURE_ACCESS_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_SECURE_ACCESS_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_D0_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_D0_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_D0_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_D0_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_D0_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_D0_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_D0_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_3_D0_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4                                   0x0001D090
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_BURST_LENGTH_LSB                30
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_BURST_LENGTH_WIDTH              2
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_BURST_LENGTH_MASK               0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_BURST_LENGTH_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_D1_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_D1_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_D1_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_D1_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_D1_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_D1_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_D1_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_4_D1_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5                                   0x0001D094
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_SMID_LSB                        28
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_SMID_WIDTH                      4
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_SMID_MASK                       0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_SMID_DEFVAL                     0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_AXCACHE_LSB                     24
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_AXCACHE_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_AXCACHE_MASK                    0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_AXCACHE_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_AXQOS_LSB                       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_AXQOS_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_AXQOS_MASK                      0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_AXQOS_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_D2_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_D2_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_D2_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_5_D2_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6                                   0x0001D098
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_ITERATION_CURRENT_LSB           26
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_ITERATION_CURRENT_WIDTH         6
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_ITERATION_CURRENT_MASK          0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_ITERATION_CURRENT_DEFVAL        0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_ITERATION_WRAP_LSB              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_ITERATION_WRAP_WIDTH            6
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_ITERATION_WRAP_MASK             0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_ITERATION_WRAP_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_ITERATION_STEPSIZE_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_ITERATION_STEPSIZE_WIDTH        20
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_ITERATION_STEPSIZE_MASK         0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_6_ITERATION_STEPSIZE_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7                                   0x0001D09C
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_MASK                              0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_TLAST_SUPPRESS_LSB              31
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_TLAST_SUPPRESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_TLAST_SUPPRESS_MASK             0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_TLAST_SUPPRESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_NEXT_BD_LSB                     27
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_NEXT_BD_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_NEXT_BD_MASK                    0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_NEXT_BD_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_USE_NEXT_BD_LSB                 26
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_USE_NEXT_BD_WIDTH               1
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_USE_NEXT_BD_MASK                0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_USE_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_VALID_BD_LSB                    25
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_VALID_BD_WIDTH                  1
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_VALID_BD_MASK                   0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_VALID_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_REL_VALUE_LSB              18
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_REL_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_REL_VALUE_MASK             0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_REL_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_REL_ID_LSB                 13
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_REL_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_REL_ID_MASK                0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_REL_ID_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_ACQ_ENABLE_LSB             12
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_ACQ_ENABLE_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_ACQ_ENABLE_MASK            0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_ACQ_ENABLE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_ACQ_VALUE_LSB              5
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_ACQ_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_ACQ_VALUE_MASK             0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_ACQ_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_ACQ_ID_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_ACQ_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_ACQ_ID_MASK                0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD4_7_LOCK_ACQ_ID_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD5_0                                   0x0001D0A0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_0_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_0_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_0_BUFFER_LENGTH_LSB               0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_0_BUFFER_LENGTH_WIDTH             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_0_BUFFER_LENGTH_MASK              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_0_BUFFER_LENGTH_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD5_1                                   0x0001D0A4
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_1_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_1_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_1_BASE_ADDRESS_LOW_LSB            2
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_1_BASE_ADDRESS_LOW_WIDTH          30
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_1_BASE_ADDRESS_LOW_MASK           0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_1_BASE_ADDRESS_LOW_DEFVAL         0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2                                   0x0001D0A8
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_ENABLE_PACKET_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_ENABLE_PACKET_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_ENABLE_PACKET_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_ENABLE_PACKET_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_OUT_OF_ORDER_BD_ID_LSB          24
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_OUT_OF_ORDER_BD_ID_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_OUT_OF_ORDER_BD_ID_MASK         0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_OUT_OF_ORDER_BD_ID_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_PACKET_ID_LSB                   19
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_PACKET_ID_WIDTH                 5
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_PACKET_ID_MASK                  0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_PACKET_ID_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_PACKET_TYPE_LSB                 16
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_PACKET_TYPE_WIDTH               3
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_PACKET_TYPE_MASK                0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_PACKET_TYPE_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_BASE_ADDRESS_HIGH_LSB           0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_BASE_ADDRESS_HIGH_WIDTH         16
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_BASE_ADDRESS_HIGH_MASK          0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_2_BASE_ADDRESS_HIGH_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3                                   0x0001D0AC
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_SECURE_ACCESS_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_SECURE_ACCESS_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_SECURE_ACCESS_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_SECURE_ACCESS_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_D0_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_D0_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_D0_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_D0_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_D0_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_D0_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_D0_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_3_D0_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4                                   0x0001D0B0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_BURST_LENGTH_LSB                30
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_BURST_LENGTH_WIDTH              2
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_BURST_LENGTH_MASK               0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_BURST_LENGTH_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_D1_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_D1_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_D1_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_D1_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_D1_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_D1_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_D1_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_4_D1_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5                                   0x0001D0B4
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_SMID_LSB                        28
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_SMID_WIDTH                      4
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_SMID_MASK                       0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_SMID_DEFVAL                     0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_AXCACHE_LSB                     24
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_AXCACHE_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_AXCACHE_MASK                    0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_AXCACHE_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_AXQOS_LSB                       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_AXQOS_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_AXQOS_MASK                      0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_AXQOS_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_D2_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_D2_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_D2_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_5_D2_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6                                   0x0001D0B8
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_ITERATION_CURRENT_LSB           26
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_ITERATION_CURRENT_WIDTH         6
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_ITERATION_CURRENT_MASK          0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_ITERATION_CURRENT_DEFVAL        0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_ITERATION_WRAP_LSB              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_ITERATION_WRAP_WIDTH            6
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_ITERATION_WRAP_MASK             0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_ITERATION_WRAP_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_ITERATION_STEPSIZE_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_ITERATION_STEPSIZE_WIDTH        20
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_ITERATION_STEPSIZE_MASK         0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_6_ITERATION_STEPSIZE_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7                                   0x0001D0BC
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_MASK                              0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_TLAST_SUPPRESS_LSB              31
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_TLAST_SUPPRESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_TLAST_SUPPRESS_MASK             0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_TLAST_SUPPRESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_NEXT_BD_LSB                     27
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_NEXT_BD_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_NEXT_BD_MASK                    0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_NEXT_BD_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_USE_NEXT_BD_LSB                 26
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_USE_NEXT_BD_WIDTH               1
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_USE_NEXT_BD_MASK                0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_USE_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_VALID_BD_LSB                    25
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_VALID_BD_WIDTH                  1
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_VALID_BD_MASK                   0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_VALID_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_REL_VALUE_LSB              18
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_REL_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_REL_VALUE_MASK             0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_REL_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_REL_ID_LSB                 13
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_REL_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_REL_ID_MASK                0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_REL_ID_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_ACQ_ENABLE_LSB             12
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_ACQ_ENABLE_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_ACQ_ENABLE_MASK            0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_ACQ_ENABLE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_ACQ_VALUE_LSB              5
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_ACQ_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_ACQ_VALUE_MASK             0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_ACQ_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_ACQ_ID_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_ACQ_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_ACQ_ID_MASK                0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD5_7_LOCK_ACQ_ID_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD6_0                                   0x0001D0C0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_0_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_0_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_0_BUFFER_LENGTH_LSB               0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_0_BUFFER_LENGTH_WIDTH             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_0_BUFFER_LENGTH_MASK              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_0_BUFFER_LENGTH_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD6_1                                   0x0001D0C4
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_1_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_1_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_1_BASE_ADDRESS_LOW_LSB            2
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_1_BASE_ADDRESS_LOW_WIDTH          30
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_1_BASE_ADDRESS_LOW_MASK           0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_1_BASE_ADDRESS_LOW_DEFVAL         0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2                                   0x0001D0C8
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_ENABLE_PACKET_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_ENABLE_PACKET_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_ENABLE_PACKET_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_ENABLE_PACKET_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_OUT_OF_ORDER_BD_ID_LSB          24
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_OUT_OF_ORDER_BD_ID_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_OUT_OF_ORDER_BD_ID_MASK         0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_OUT_OF_ORDER_BD_ID_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_PACKET_ID_LSB                   19
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_PACKET_ID_WIDTH                 5
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_PACKET_ID_MASK                  0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_PACKET_ID_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_PACKET_TYPE_LSB                 16
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_PACKET_TYPE_WIDTH               3
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_PACKET_TYPE_MASK                0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_PACKET_TYPE_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_BASE_ADDRESS_HIGH_LSB           0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_BASE_ADDRESS_HIGH_WIDTH         16
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_BASE_ADDRESS_HIGH_MASK          0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_2_BASE_ADDRESS_HIGH_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3                                   0x0001D0CC
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_SECURE_ACCESS_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_SECURE_ACCESS_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_SECURE_ACCESS_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_SECURE_ACCESS_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_D0_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_D0_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_D0_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_D0_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_D0_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_D0_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_D0_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_3_D0_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4                                   0x0001D0D0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_BURST_LENGTH_LSB                30
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_BURST_LENGTH_WIDTH              2
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_BURST_LENGTH_MASK               0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_BURST_LENGTH_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_D1_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_D1_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_D1_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_D1_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_D1_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_D1_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_D1_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_4_D1_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5                                   0x0001D0D4
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_SMID_LSB                        28
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_SMID_WIDTH                      4
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_SMID_MASK                       0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_SMID_DEFVAL                     0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_AXCACHE_LSB                     24
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_AXCACHE_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_AXCACHE_MASK                    0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_AXCACHE_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_AXQOS_LSB                       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_AXQOS_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_AXQOS_MASK                      0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_AXQOS_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_D2_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_D2_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_D2_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_5_D2_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6                                   0x0001D0D8
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_ITERATION_CURRENT_LSB           26
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_ITERATION_CURRENT_WIDTH         6
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_ITERATION_CURRENT_MASK          0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_ITERATION_CURRENT_DEFVAL        0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_ITERATION_WRAP_LSB              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_ITERATION_WRAP_WIDTH            6
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_ITERATION_WRAP_MASK             0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_ITERATION_WRAP_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_ITERATION_STEPSIZE_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_ITERATION_STEPSIZE_WIDTH        20
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_ITERATION_STEPSIZE_MASK         0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_6_ITERATION_STEPSIZE_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7                                   0x0001D0DC
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_MASK                              0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_TLAST_SUPPRESS_LSB              31
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_TLAST_SUPPRESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_TLAST_SUPPRESS_MASK             0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_TLAST_SUPPRESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_NEXT_BD_LSB                     27
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_NEXT_BD_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_NEXT_BD_MASK                    0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_NEXT_BD_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_USE_NEXT_BD_LSB                 26
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_USE_NEXT_BD_WIDTH               1
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_USE_NEXT_BD_MASK                0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_USE_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_VALID_BD_LSB                    25
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_VALID_BD_WIDTH                  1
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_VALID_BD_MASK                   0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_VALID_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_REL_VALUE_LSB              18
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_REL_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_REL_VALUE_MASK             0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_REL_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_REL_ID_LSB                 13
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_REL_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_REL_ID_MASK                0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_REL_ID_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_ACQ_ENABLE_LSB             12
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_ACQ_ENABLE_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_ACQ_ENABLE_MASK            0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_ACQ_ENABLE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_ACQ_VALUE_LSB              5
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_ACQ_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_ACQ_VALUE_MASK             0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_ACQ_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_ACQ_ID_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_ACQ_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_ACQ_ID_MASK                0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD6_7_LOCK_ACQ_ID_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD7_0                                   0x0001D0E0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_0_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_0_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_0_BUFFER_LENGTH_LSB               0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_0_BUFFER_LENGTH_WIDTH             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_0_BUFFER_LENGTH_MASK              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_0_BUFFER_LENGTH_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD7_1                                   0x0001D0E4
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_1_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_1_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_1_BASE_ADDRESS_LOW_LSB            2
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_1_BASE_ADDRESS_LOW_WIDTH          30
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_1_BASE_ADDRESS_LOW_MASK           0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_1_BASE_ADDRESS_LOW_DEFVAL         0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2                                   0x0001D0E8
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_ENABLE_PACKET_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_ENABLE_PACKET_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_ENABLE_PACKET_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_ENABLE_PACKET_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_OUT_OF_ORDER_BD_ID_LSB          24
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_OUT_OF_ORDER_BD_ID_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_OUT_OF_ORDER_BD_ID_MASK         0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_OUT_OF_ORDER_BD_ID_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_PACKET_ID_LSB                   19
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_PACKET_ID_WIDTH                 5
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_PACKET_ID_MASK                  0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_PACKET_ID_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_PACKET_TYPE_LSB                 16
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_PACKET_TYPE_WIDTH               3
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_PACKET_TYPE_MASK                0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_PACKET_TYPE_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_BASE_ADDRESS_HIGH_LSB           0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_BASE_ADDRESS_HIGH_WIDTH         16
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_BASE_ADDRESS_HIGH_MASK          0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_2_BASE_ADDRESS_HIGH_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3                                   0x0001D0EC
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_SECURE_ACCESS_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_SECURE_ACCESS_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_SECURE_ACCESS_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_SECURE_ACCESS_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_D0_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_D0_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_D0_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_D0_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_D0_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_D0_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_D0_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_3_D0_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4                                   0x0001D0F0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_BURST_LENGTH_LSB                30
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_BURST_LENGTH_WIDTH              2
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_BURST_LENGTH_MASK               0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_BURST_LENGTH_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_D1_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_D1_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_D1_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_D1_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_D1_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_D1_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_D1_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_4_D1_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5                                   0x0001D0F4
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_SMID_LSB                        28
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_SMID_WIDTH                      4
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_SMID_MASK                       0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_SMID_DEFVAL                     0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_AXCACHE_LSB                     24
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_AXCACHE_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_AXCACHE_MASK                    0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_AXCACHE_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_AXQOS_LSB                       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_AXQOS_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_AXQOS_MASK                      0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_AXQOS_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_D2_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_D2_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_D2_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_5_D2_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6                                   0x0001D0F8
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_ITERATION_CURRENT_LSB           26
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_ITERATION_CURRENT_WIDTH         6
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_ITERATION_CURRENT_MASK          0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_ITERATION_CURRENT_DEFVAL        0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_ITERATION_WRAP_LSB              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_ITERATION_WRAP_WIDTH            6
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_ITERATION_WRAP_MASK             0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_ITERATION_WRAP_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_ITERATION_STEPSIZE_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_ITERATION_STEPSIZE_WIDTH        20
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_ITERATION_STEPSIZE_MASK         0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_6_ITERATION_STEPSIZE_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7                                   0x0001D0FC
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_MASK                              0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_TLAST_SUPPRESS_LSB              31
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_TLAST_SUPPRESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_TLAST_SUPPRESS_MASK             0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_TLAST_SUPPRESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_NEXT_BD_LSB                     27
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_NEXT_BD_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_NEXT_BD_MASK                    0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_NEXT_BD_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_USE_NEXT_BD_LSB                 26
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_USE_NEXT_BD_WIDTH               1
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_USE_NEXT_BD_MASK                0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_USE_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_VALID_BD_LSB                    25
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_VALID_BD_WIDTH                  1
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_VALID_BD_MASK                   0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_VALID_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_REL_VALUE_LSB              18
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_REL_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_REL_VALUE_MASK             0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_REL_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_REL_ID_LSB                 13
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_REL_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_REL_ID_MASK                0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_REL_ID_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_ACQ_ENABLE_LSB             12
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_ACQ_ENABLE_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_ACQ_ENABLE_MASK            0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_ACQ_ENABLE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_ACQ_VALUE_LSB              5
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_ACQ_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_ACQ_VALUE_MASK             0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_ACQ_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_ACQ_ID_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_ACQ_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_ACQ_ID_MASK                0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD7_7_LOCK_ACQ_ID_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD8_0                                   0x0001D100
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_0_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_0_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_0_BUFFER_LENGTH_LSB               0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_0_BUFFER_LENGTH_WIDTH             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_0_BUFFER_LENGTH_MASK              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_0_BUFFER_LENGTH_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD8_1                                   0x0001D104
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_1_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_1_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_1_BASE_ADDRESS_LOW_LSB            2
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_1_BASE_ADDRESS_LOW_WIDTH          30
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_1_BASE_ADDRESS_LOW_MASK           0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_1_BASE_ADDRESS_LOW_DEFVAL         0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2                                   0x0001D108
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_ENABLE_PACKET_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_ENABLE_PACKET_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_ENABLE_PACKET_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_ENABLE_PACKET_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_OUT_OF_ORDER_BD_ID_LSB          24
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_OUT_OF_ORDER_BD_ID_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_OUT_OF_ORDER_BD_ID_MASK         0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_OUT_OF_ORDER_BD_ID_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_PACKET_ID_LSB                   19
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_PACKET_ID_WIDTH                 5
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_PACKET_ID_MASK                  0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_PACKET_ID_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_PACKET_TYPE_LSB                 16
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_PACKET_TYPE_WIDTH               3
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_PACKET_TYPE_MASK                0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_PACKET_TYPE_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_BASE_ADDRESS_HIGH_LSB           0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_BASE_ADDRESS_HIGH_WIDTH         16
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_BASE_ADDRESS_HIGH_MASK          0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_2_BASE_ADDRESS_HIGH_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3                                   0x0001D10C
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_SECURE_ACCESS_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_SECURE_ACCESS_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_SECURE_ACCESS_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_SECURE_ACCESS_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_D0_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_D0_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_D0_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_D0_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_D0_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_D0_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_D0_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_3_D0_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4                                   0x0001D110
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_BURST_LENGTH_LSB                30
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_BURST_LENGTH_WIDTH              2
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_BURST_LENGTH_MASK               0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_BURST_LENGTH_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_D1_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_D1_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_D1_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_D1_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_D1_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_D1_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_D1_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_4_D1_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5                                   0x0001D114
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_SMID_LSB                        28
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_SMID_WIDTH                      4
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_SMID_MASK                       0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_SMID_DEFVAL                     0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_AXCACHE_LSB                     24
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_AXCACHE_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_AXCACHE_MASK                    0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_AXCACHE_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_AXQOS_LSB                       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_AXQOS_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_AXQOS_MASK                      0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_AXQOS_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_D2_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_D2_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_D2_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_5_D2_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6                                   0x0001D118
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_ITERATION_CURRENT_LSB           26
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_ITERATION_CURRENT_WIDTH         6
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_ITERATION_CURRENT_MASK          0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_ITERATION_CURRENT_DEFVAL        0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_ITERATION_WRAP_LSB              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_ITERATION_WRAP_WIDTH            6
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_ITERATION_WRAP_MASK             0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_ITERATION_WRAP_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_ITERATION_STEPSIZE_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_ITERATION_STEPSIZE_WIDTH        20
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_ITERATION_STEPSIZE_MASK         0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_6_ITERATION_STEPSIZE_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7                                   0x0001D11C
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_MASK                              0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_TLAST_SUPPRESS_LSB              31
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_TLAST_SUPPRESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_TLAST_SUPPRESS_MASK             0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_TLAST_SUPPRESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_NEXT_BD_LSB                     27
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_NEXT_BD_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_NEXT_BD_MASK                    0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_NEXT_BD_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_USE_NEXT_BD_LSB                 26
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_USE_NEXT_BD_WIDTH               1
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_USE_NEXT_BD_MASK                0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_USE_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_VALID_BD_LSB                    25
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_VALID_BD_WIDTH                  1
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_VALID_BD_MASK                   0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_VALID_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_REL_VALUE_LSB              18
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_REL_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_REL_VALUE_MASK             0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_REL_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_REL_ID_LSB                 13
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_REL_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_REL_ID_MASK                0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_REL_ID_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_ACQ_ENABLE_LSB             12
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_ACQ_ENABLE_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_ACQ_ENABLE_MASK            0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_ACQ_ENABLE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_ACQ_VALUE_LSB              5
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_ACQ_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_ACQ_VALUE_MASK             0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_ACQ_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_ACQ_ID_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_ACQ_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_ACQ_ID_MASK                0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD8_7_LOCK_ACQ_ID_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD9_0                                   0x0001D120
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_0_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_0_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_0_BUFFER_LENGTH_LSB               0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_0_BUFFER_LENGTH_WIDTH             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_0_BUFFER_LENGTH_MASK              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_0_BUFFER_LENGTH_DEFVAL            0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD9_1                                   0x0001D124
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_1_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_1_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_1_BASE_ADDRESS_LOW_LSB            2
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_1_BASE_ADDRESS_LOW_WIDTH          30
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_1_BASE_ADDRESS_LOW_MASK           0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_1_BASE_ADDRESS_LOW_DEFVAL         0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2                                   0x0001D128
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_ENABLE_PACKET_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_ENABLE_PACKET_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_ENABLE_PACKET_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_ENABLE_PACKET_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_OUT_OF_ORDER_BD_ID_LSB          24
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_OUT_OF_ORDER_BD_ID_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_OUT_OF_ORDER_BD_ID_MASK         0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_OUT_OF_ORDER_BD_ID_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_PACKET_ID_LSB                   19
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_PACKET_ID_WIDTH                 5
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_PACKET_ID_MASK                  0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_PACKET_ID_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_PACKET_TYPE_LSB                 16
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_PACKET_TYPE_WIDTH               3
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_PACKET_TYPE_MASK                0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_PACKET_TYPE_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_BASE_ADDRESS_HIGH_LSB           0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_BASE_ADDRESS_HIGH_WIDTH         16
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_BASE_ADDRESS_HIGH_MASK          0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_2_BASE_ADDRESS_HIGH_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3                                   0x0001D12C
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_MASK                              0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_SECURE_ACCESS_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_SECURE_ACCESS_WIDTH             1
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_SECURE_ACCESS_MASK              0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_SECURE_ACCESS_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_D0_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_D0_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_D0_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_D0_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_D0_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_D0_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_D0_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_3_D0_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4                                   0x0001D130
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_BURST_LENGTH_LSB                30
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_BURST_LENGTH_WIDTH              2
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_BURST_LENGTH_MASK               0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_BURST_LENGTH_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_D1_WRAP_LSB                     20
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_D1_WRAP_WIDTH                   10
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_D1_WRAP_MASK                    0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_D1_WRAP_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_D1_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_D1_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_D1_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_4_D1_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5                                   0x0001D134
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_SMID_LSB                        28
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_SMID_WIDTH                      4
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_SMID_MASK                       0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_SMID_DEFVAL                     0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_AXCACHE_LSB                     24
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_AXCACHE_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_AXCACHE_MASK                    0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_AXCACHE_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_AXQOS_LSB                       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_AXQOS_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_AXQOS_MASK                      0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_AXQOS_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_D2_STEPSIZE_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_D2_STEPSIZE_WIDTH               20
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_D2_STEPSIZE_MASK                0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_5_D2_STEPSIZE_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6                                   0x0001D138
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_MASK                              0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_ITERATION_CURRENT_LSB           26
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_ITERATION_CURRENT_WIDTH         6
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_ITERATION_CURRENT_MASK          0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_ITERATION_CURRENT_DEFVAL        0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_ITERATION_WRAP_LSB              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_ITERATION_WRAP_WIDTH            6
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_ITERATION_WRAP_MASK             0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_ITERATION_WRAP_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_ITERATION_STEPSIZE_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_ITERATION_STEPSIZE_WIDTH        20
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_ITERATION_STEPSIZE_MASK         0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_6_ITERATION_STEPSIZE_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7                                   0x0001D13C
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_WIDTH                             32
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_MASK                              0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_TLAST_SUPPRESS_LSB              31
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_TLAST_SUPPRESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_TLAST_SUPPRESS_MASK             0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_TLAST_SUPPRESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_NEXT_BD_LSB                     27
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_NEXT_BD_WIDTH                   4
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_NEXT_BD_MASK                    0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_NEXT_BD_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_USE_NEXT_BD_LSB                 26
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_USE_NEXT_BD_WIDTH               1
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_USE_NEXT_BD_MASK                0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_USE_NEXT_BD_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_VALID_BD_LSB                    25
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_VALID_BD_WIDTH                  1
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_VALID_BD_MASK                   0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_VALID_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_REL_VALUE_LSB              18
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_REL_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_REL_VALUE_MASK             0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_REL_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_REL_ID_LSB                 13
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_REL_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_REL_ID_MASK                0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_REL_ID_DEFVAL              0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_ACQ_ENABLE_LSB             12
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_ACQ_ENABLE_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_ACQ_ENABLE_MASK            0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_ACQ_ENABLE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_ACQ_VALUE_LSB              5
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_ACQ_VALUE_WIDTH            7
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_ACQ_VALUE_MASK             0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_ACQ_VALUE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_ACQ_ID_LSB                 0
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_ACQ_ID_WIDTH               4
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_ACQ_ID_MASK                0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD9_7_LOCK_ACQ_ID_DEFVAL              0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD10_0                                  0x0001D140
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_0_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_0_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_0_BUFFER_LENGTH_LSB              0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_0_BUFFER_LENGTH_WIDTH            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_0_BUFFER_LENGTH_MASK             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_0_BUFFER_LENGTH_DEFVAL           0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD10_1                                  0x0001D144
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_1_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_1_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_1_BASE_ADDRESS_LOW_LSB           2
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_1_BASE_ADDRESS_LOW_WIDTH         30
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_1_BASE_ADDRESS_LOW_MASK          0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_1_BASE_ADDRESS_LOW_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2                                  0x0001D148
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_MASK                             0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_ENABLE_PACKET_LSB              30
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_ENABLE_PACKET_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_ENABLE_PACKET_MASK             0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_ENABLE_PACKET_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_OUT_OF_ORDER_BD_ID_LSB         24
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_OUT_OF_ORDER_BD_ID_WIDTH       6
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_OUT_OF_ORDER_BD_ID_MASK        0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_OUT_OF_ORDER_BD_ID_DEFVAL      0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_PACKET_ID_LSB                  19
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_PACKET_ID_WIDTH                5
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_PACKET_ID_MASK                 0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_PACKET_ID_DEFVAL               0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_PACKET_TYPE_LSB                16
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_PACKET_TYPE_WIDTH              3
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_PACKET_TYPE_MASK               0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_PACKET_TYPE_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_BASE_ADDRESS_HIGH_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_BASE_ADDRESS_HIGH_WIDTH        16
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_BASE_ADDRESS_HIGH_MASK         0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_2_BASE_ADDRESS_HIGH_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3                                  0x0001D14C
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_MASK                             0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_SECURE_ACCESS_LSB              30
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_SECURE_ACCESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_SECURE_ACCESS_MASK             0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_SECURE_ACCESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_D0_WRAP_LSB                    20
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_D0_WRAP_WIDTH                  10
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_D0_WRAP_MASK                   0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_D0_WRAP_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_D0_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_D0_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_D0_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_3_D0_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4                                  0x0001D150
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_BURST_LENGTH_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_BURST_LENGTH_WIDTH             2
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_BURST_LENGTH_MASK              0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_BURST_LENGTH_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_D1_WRAP_LSB                    20
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_D1_WRAP_WIDTH                  10
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_D1_WRAP_MASK                   0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_D1_WRAP_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_D1_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_D1_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_D1_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_4_D1_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5                                  0x0001D154
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_SMID_LSB                       28
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_SMID_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_SMID_MASK                      0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_SMID_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_AXCACHE_LSB                    24
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_AXCACHE_WIDTH                  4
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_AXCACHE_MASK                   0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_AXCACHE_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_AXQOS_LSB                      20
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_AXQOS_WIDTH                    4
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_AXQOS_MASK                     0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_AXQOS_DEFVAL                   0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_D2_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_D2_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_D2_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_5_D2_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6                                  0x0001D158
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_ITERATION_CURRENT_LSB          26
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_ITERATION_CURRENT_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_ITERATION_CURRENT_MASK         0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_ITERATION_CURRENT_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_ITERATION_WRAP_LSB             20
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_ITERATION_WRAP_WIDTH           6
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_ITERATION_WRAP_MASK            0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_ITERATION_WRAP_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_ITERATION_STEPSIZE_LSB         0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_ITERATION_STEPSIZE_WIDTH       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_ITERATION_STEPSIZE_MASK        0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_6_ITERATION_STEPSIZE_DEFVAL      0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7                                  0x0001D15C
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_MASK                             0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_TLAST_SUPPRESS_LSB             31
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_TLAST_SUPPRESS_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_TLAST_SUPPRESS_MASK            0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_TLAST_SUPPRESS_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_NEXT_BD_LSB                    27
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_NEXT_BD_WIDTH                  4
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_NEXT_BD_MASK                   0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_NEXT_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_USE_NEXT_BD_LSB                26
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_USE_NEXT_BD_WIDTH              1
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_USE_NEXT_BD_MASK               0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_USE_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_VALID_BD_LSB                   25
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_VALID_BD_WIDTH                 1
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_VALID_BD_MASK                  0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_VALID_BD_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_REL_VALUE_LSB             18
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_REL_VALUE_WIDTH           7
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_REL_VALUE_MASK            0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_REL_VALUE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_REL_ID_LSB                13
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_REL_ID_WIDTH              4
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_REL_ID_MASK               0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_REL_ID_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_ACQ_ENABLE_LSB            12
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_ACQ_ENABLE_WIDTH          1
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_ACQ_ENABLE_MASK           0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_ACQ_ENABLE_DEFVAL         0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_ACQ_VALUE_LSB             5
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_ACQ_VALUE_WIDTH           7
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_ACQ_VALUE_MASK            0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_ACQ_VALUE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_ACQ_ID_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_ACQ_ID_WIDTH              4
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_ACQ_ID_MASK               0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD10_7_LOCK_ACQ_ID_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD11_0                                  0x0001D160
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_0_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_0_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_0_BUFFER_LENGTH_LSB              0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_0_BUFFER_LENGTH_WIDTH            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_0_BUFFER_LENGTH_MASK             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_0_BUFFER_LENGTH_DEFVAL           0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD11_1                                  0x0001D164
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_1_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_1_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_1_BASE_ADDRESS_LOW_LSB           2
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_1_BASE_ADDRESS_LOW_WIDTH         30
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_1_BASE_ADDRESS_LOW_MASK          0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_1_BASE_ADDRESS_LOW_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2                                  0x0001D168
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_MASK                             0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_ENABLE_PACKET_LSB              30
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_ENABLE_PACKET_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_ENABLE_PACKET_MASK             0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_ENABLE_PACKET_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_OUT_OF_ORDER_BD_ID_LSB         24
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_OUT_OF_ORDER_BD_ID_WIDTH       6
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_OUT_OF_ORDER_BD_ID_MASK        0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_OUT_OF_ORDER_BD_ID_DEFVAL      0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_PACKET_ID_LSB                  19
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_PACKET_ID_WIDTH                5
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_PACKET_ID_MASK                 0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_PACKET_ID_DEFVAL               0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_PACKET_TYPE_LSB                16
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_PACKET_TYPE_WIDTH              3
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_PACKET_TYPE_MASK               0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_PACKET_TYPE_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_BASE_ADDRESS_HIGH_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_BASE_ADDRESS_HIGH_WIDTH        16
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_BASE_ADDRESS_HIGH_MASK         0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_2_BASE_ADDRESS_HIGH_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3                                  0x0001D16C
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_MASK                             0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_SECURE_ACCESS_LSB              30
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_SECURE_ACCESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_SECURE_ACCESS_MASK             0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_SECURE_ACCESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_D0_WRAP_LSB                    20
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_D0_WRAP_WIDTH                  10
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_D0_WRAP_MASK                   0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_D0_WRAP_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_D0_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_D0_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_D0_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_3_D0_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4                                  0x0001D170
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_BURST_LENGTH_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_BURST_LENGTH_WIDTH             2
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_BURST_LENGTH_MASK              0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_BURST_LENGTH_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_D1_WRAP_LSB                    20
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_D1_WRAP_WIDTH                  10
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_D1_WRAP_MASK                   0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_D1_WRAP_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_D1_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_D1_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_D1_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_4_D1_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5                                  0x0001D174
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_SMID_LSB                       28
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_SMID_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_SMID_MASK                      0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_SMID_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_AXCACHE_LSB                    24
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_AXCACHE_WIDTH                  4
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_AXCACHE_MASK                   0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_AXCACHE_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_AXQOS_LSB                      20
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_AXQOS_WIDTH                    4
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_AXQOS_MASK                     0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_AXQOS_DEFVAL                   0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_D2_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_D2_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_D2_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_5_D2_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6                                  0x0001D178
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_ITERATION_CURRENT_LSB          26
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_ITERATION_CURRENT_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_ITERATION_CURRENT_MASK         0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_ITERATION_CURRENT_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_ITERATION_WRAP_LSB             20
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_ITERATION_WRAP_WIDTH           6
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_ITERATION_WRAP_MASK            0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_ITERATION_WRAP_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_ITERATION_STEPSIZE_LSB         0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_ITERATION_STEPSIZE_WIDTH       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_ITERATION_STEPSIZE_MASK        0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_6_ITERATION_STEPSIZE_DEFVAL      0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7                                  0x0001D17C
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_MASK                             0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_TLAST_SUPPRESS_LSB             31
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_TLAST_SUPPRESS_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_TLAST_SUPPRESS_MASK            0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_TLAST_SUPPRESS_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_NEXT_BD_LSB                    27
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_NEXT_BD_WIDTH                  4
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_NEXT_BD_MASK                   0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_NEXT_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_USE_NEXT_BD_LSB                26
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_USE_NEXT_BD_WIDTH              1
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_USE_NEXT_BD_MASK               0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_USE_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_VALID_BD_LSB                   25
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_VALID_BD_WIDTH                 1
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_VALID_BD_MASK                  0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_VALID_BD_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_REL_VALUE_LSB             18
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_REL_VALUE_WIDTH           7
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_REL_VALUE_MASK            0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_REL_VALUE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_REL_ID_LSB                13
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_REL_ID_WIDTH              4
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_REL_ID_MASK               0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_REL_ID_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_ACQ_ENABLE_LSB            12
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_ACQ_ENABLE_WIDTH          1
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_ACQ_ENABLE_MASK           0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_ACQ_ENABLE_DEFVAL         0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_ACQ_VALUE_LSB             5
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_ACQ_VALUE_WIDTH           7
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_ACQ_VALUE_MASK            0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_ACQ_VALUE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_ACQ_ID_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_ACQ_ID_WIDTH              4
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_ACQ_ID_MASK               0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD11_7_LOCK_ACQ_ID_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD12_0                                  0x0001D180
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_0_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_0_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_0_BUFFER_LENGTH_LSB              0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_0_BUFFER_LENGTH_WIDTH            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_0_BUFFER_LENGTH_MASK             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_0_BUFFER_LENGTH_DEFVAL           0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD12_1                                  0x0001D184
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_1_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_1_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_1_BASE_ADDRESS_LOW_LSB           2
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_1_BASE_ADDRESS_LOW_WIDTH         30
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_1_BASE_ADDRESS_LOW_MASK          0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_1_BASE_ADDRESS_LOW_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2                                  0x0001D188
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_MASK                             0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_ENABLE_PACKET_LSB              30
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_ENABLE_PACKET_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_ENABLE_PACKET_MASK             0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_ENABLE_PACKET_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_OUT_OF_ORDER_BD_ID_LSB         24
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_OUT_OF_ORDER_BD_ID_WIDTH       6
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_OUT_OF_ORDER_BD_ID_MASK        0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_OUT_OF_ORDER_BD_ID_DEFVAL      0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_PACKET_ID_LSB                  19
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_PACKET_ID_WIDTH                5
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_PACKET_ID_MASK                 0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_PACKET_ID_DEFVAL               0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_PACKET_TYPE_LSB                16
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_PACKET_TYPE_WIDTH              3
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_PACKET_TYPE_MASK               0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_PACKET_TYPE_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_BASE_ADDRESS_HIGH_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_BASE_ADDRESS_HIGH_WIDTH        16
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_BASE_ADDRESS_HIGH_MASK         0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_2_BASE_ADDRESS_HIGH_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3                                  0x0001D18C
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_MASK                             0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_SECURE_ACCESS_LSB              30
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_SECURE_ACCESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_SECURE_ACCESS_MASK             0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_SECURE_ACCESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_D0_WRAP_LSB                    20
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_D0_WRAP_WIDTH                  10
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_D0_WRAP_MASK                   0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_D0_WRAP_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_D0_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_D0_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_D0_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_3_D0_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4                                  0x0001D190
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_BURST_LENGTH_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_BURST_LENGTH_WIDTH             2
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_BURST_LENGTH_MASK              0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_BURST_LENGTH_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_D1_WRAP_LSB                    20
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_D1_WRAP_WIDTH                  10
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_D1_WRAP_MASK                   0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_D1_WRAP_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_D1_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_D1_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_D1_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_4_D1_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5                                  0x0001D194
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_SMID_LSB                       28
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_SMID_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_SMID_MASK                      0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_SMID_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_AXCACHE_LSB                    24
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_AXCACHE_WIDTH                  4
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_AXCACHE_MASK                   0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_AXCACHE_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_AXQOS_LSB                      20
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_AXQOS_WIDTH                    4
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_AXQOS_MASK                     0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_AXQOS_DEFVAL                   0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_D2_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_D2_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_D2_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_5_D2_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6                                  0x0001D198
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_ITERATION_CURRENT_LSB          26
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_ITERATION_CURRENT_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_ITERATION_CURRENT_MASK         0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_ITERATION_CURRENT_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_ITERATION_WRAP_LSB             20
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_ITERATION_WRAP_WIDTH           6
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_ITERATION_WRAP_MASK            0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_ITERATION_WRAP_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_ITERATION_STEPSIZE_LSB         0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_ITERATION_STEPSIZE_WIDTH       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_ITERATION_STEPSIZE_MASK        0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_6_ITERATION_STEPSIZE_DEFVAL      0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7                                  0x0001D19C
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_MASK                             0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_TLAST_SUPPRESS_LSB             31
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_TLAST_SUPPRESS_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_TLAST_SUPPRESS_MASK            0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_TLAST_SUPPRESS_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_NEXT_BD_LSB                    27
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_NEXT_BD_WIDTH                  4
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_NEXT_BD_MASK                   0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_NEXT_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_USE_NEXT_BD_LSB                26
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_USE_NEXT_BD_WIDTH              1
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_USE_NEXT_BD_MASK               0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_USE_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_VALID_BD_LSB                   25
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_VALID_BD_WIDTH                 1
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_VALID_BD_MASK                  0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_VALID_BD_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_REL_VALUE_LSB             18
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_REL_VALUE_WIDTH           7
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_REL_VALUE_MASK            0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_REL_VALUE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_REL_ID_LSB                13
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_REL_ID_WIDTH              4
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_REL_ID_MASK               0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_REL_ID_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_ACQ_ENABLE_LSB            12
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_ACQ_ENABLE_WIDTH          1
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_ACQ_ENABLE_MASK           0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_ACQ_ENABLE_DEFVAL         0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_ACQ_VALUE_LSB             5
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_ACQ_VALUE_WIDTH           7
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_ACQ_VALUE_MASK            0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_ACQ_VALUE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_ACQ_ID_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_ACQ_ID_WIDTH              4
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_ACQ_ID_MASK               0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD12_7_LOCK_ACQ_ID_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD13_0                                  0x0001D1A0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_0_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_0_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_0_BUFFER_LENGTH_LSB              0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_0_BUFFER_LENGTH_WIDTH            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_0_BUFFER_LENGTH_MASK             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_0_BUFFER_LENGTH_DEFVAL           0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD13_1                                  0x0001D1A4
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_1_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_1_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_1_BASE_ADDRESS_LOW_LSB           2
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_1_BASE_ADDRESS_LOW_WIDTH         30
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_1_BASE_ADDRESS_LOW_MASK          0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_1_BASE_ADDRESS_LOW_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2                                  0x0001D1A8
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_MASK                             0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_ENABLE_PACKET_LSB              30
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_ENABLE_PACKET_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_ENABLE_PACKET_MASK             0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_ENABLE_PACKET_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_OUT_OF_ORDER_BD_ID_LSB         24
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_OUT_OF_ORDER_BD_ID_WIDTH       6
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_OUT_OF_ORDER_BD_ID_MASK        0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_OUT_OF_ORDER_BD_ID_DEFVAL      0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_PACKET_ID_LSB                  19
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_PACKET_ID_WIDTH                5
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_PACKET_ID_MASK                 0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_PACKET_ID_DEFVAL               0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_PACKET_TYPE_LSB                16
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_PACKET_TYPE_WIDTH              3
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_PACKET_TYPE_MASK               0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_PACKET_TYPE_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_BASE_ADDRESS_HIGH_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_BASE_ADDRESS_HIGH_WIDTH        16
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_BASE_ADDRESS_HIGH_MASK         0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_2_BASE_ADDRESS_HIGH_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3                                  0x0001D1AC
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_MASK                             0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_SECURE_ACCESS_LSB              30
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_SECURE_ACCESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_SECURE_ACCESS_MASK             0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_SECURE_ACCESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_D0_WRAP_LSB                    20
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_D0_WRAP_WIDTH                  10
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_D0_WRAP_MASK                   0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_D0_WRAP_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_D0_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_D0_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_D0_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_3_D0_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4                                  0x0001D1B0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_BURST_LENGTH_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_BURST_LENGTH_WIDTH             2
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_BURST_LENGTH_MASK              0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_BURST_LENGTH_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_D1_WRAP_LSB                    20
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_D1_WRAP_WIDTH                  10
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_D1_WRAP_MASK                   0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_D1_WRAP_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_D1_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_D1_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_D1_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_4_D1_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5                                  0x0001D1B4
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_SMID_LSB                       28
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_SMID_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_SMID_MASK                      0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_SMID_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_AXCACHE_LSB                    24
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_AXCACHE_WIDTH                  4
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_AXCACHE_MASK                   0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_AXCACHE_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_AXQOS_LSB                      20
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_AXQOS_WIDTH                    4
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_AXQOS_MASK                     0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_AXQOS_DEFVAL                   0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_D2_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_D2_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_D2_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_5_D2_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6                                  0x0001D1B8
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_ITERATION_CURRENT_LSB          26
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_ITERATION_CURRENT_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_ITERATION_CURRENT_MASK         0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_ITERATION_CURRENT_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_ITERATION_WRAP_LSB             20
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_ITERATION_WRAP_WIDTH           6
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_ITERATION_WRAP_MASK            0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_ITERATION_WRAP_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_ITERATION_STEPSIZE_LSB         0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_ITERATION_STEPSIZE_WIDTH       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_ITERATION_STEPSIZE_MASK        0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_6_ITERATION_STEPSIZE_DEFVAL      0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7                                  0x0001D1BC
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_MASK                             0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_TLAST_SUPPRESS_LSB             31
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_TLAST_SUPPRESS_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_TLAST_SUPPRESS_MASK            0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_TLAST_SUPPRESS_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_NEXT_BD_LSB                    27
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_NEXT_BD_WIDTH                  4
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_NEXT_BD_MASK                   0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_NEXT_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_USE_NEXT_BD_LSB                26
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_USE_NEXT_BD_WIDTH              1
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_USE_NEXT_BD_MASK               0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_USE_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_VALID_BD_LSB                   25
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_VALID_BD_WIDTH                 1
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_VALID_BD_MASK                  0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_VALID_BD_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_REL_VALUE_LSB             18
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_REL_VALUE_WIDTH           7
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_REL_VALUE_MASK            0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_REL_VALUE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_REL_ID_LSB                13
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_REL_ID_WIDTH              4
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_REL_ID_MASK               0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_REL_ID_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_ACQ_ENABLE_LSB            12
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_ACQ_ENABLE_WIDTH          1
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_ACQ_ENABLE_MASK           0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_ACQ_ENABLE_DEFVAL         0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_ACQ_VALUE_LSB             5
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_ACQ_VALUE_WIDTH           7
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_ACQ_VALUE_MASK            0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_ACQ_VALUE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_ACQ_ID_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_ACQ_ID_WIDTH              4
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_ACQ_ID_MASK               0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD13_7_LOCK_ACQ_ID_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD14_0                                  0x0001D1C0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_0_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_0_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_0_BUFFER_LENGTH_LSB              0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_0_BUFFER_LENGTH_WIDTH            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_0_BUFFER_LENGTH_MASK             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_0_BUFFER_LENGTH_DEFVAL           0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD14_1                                  0x0001D1C4
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_1_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_1_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_1_BASE_ADDRESS_LOW_LSB           2
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_1_BASE_ADDRESS_LOW_WIDTH         30
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_1_BASE_ADDRESS_LOW_MASK          0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_1_BASE_ADDRESS_LOW_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2                                  0x0001D1C8
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_MASK                             0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_ENABLE_PACKET_LSB              30
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_ENABLE_PACKET_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_ENABLE_PACKET_MASK             0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_ENABLE_PACKET_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_OUT_OF_ORDER_BD_ID_LSB         24
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_OUT_OF_ORDER_BD_ID_WIDTH       6
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_OUT_OF_ORDER_BD_ID_MASK        0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_OUT_OF_ORDER_BD_ID_DEFVAL      0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_PACKET_ID_LSB                  19
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_PACKET_ID_WIDTH                5
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_PACKET_ID_MASK                 0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_PACKET_ID_DEFVAL               0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_PACKET_TYPE_LSB                16
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_PACKET_TYPE_WIDTH              3
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_PACKET_TYPE_MASK               0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_PACKET_TYPE_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_BASE_ADDRESS_HIGH_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_BASE_ADDRESS_HIGH_WIDTH        16
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_BASE_ADDRESS_HIGH_MASK         0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_2_BASE_ADDRESS_HIGH_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3                                  0x0001D1CC
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_MASK                             0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_SECURE_ACCESS_LSB              30
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_SECURE_ACCESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_SECURE_ACCESS_MASK             0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_SECURE_ACCESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_D0_WRAP_LSB                    20
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_D0_WRAP_WIDTH                  10
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_D0_WRAP_MASK                   0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_D0_WRAP_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_D0_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_D0_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_D0_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_3_D0_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4                                  0x0001D1D0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_BURST_LENGTH_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_BURST_LENGTH_WIDTH             2
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_BURST_LENGTH_MASK              0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_BURST_LENGTH_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_D1_WRAP_LSB                    20
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_D1_WRAP_WIDTH                  10
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_D1_WRAP_MASK                   0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_D1_WRAP_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_D1_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_D1_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_D1_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_4_D1_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5                                  0x0001D1D4
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_SMID_LSB                       28
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_SMID_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_SMID_MASK                      0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_SMID_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_AXCACHE_LSB                    24
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_AXCACHE_WIDTH                  4
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_AXCACHE_MASK                   0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_AXCACHE_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_AXQOS_LSB                      20
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_AXQOS_WIDTH                    4
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_AXQOS_MASK                     0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_AXQOS_DEFVAL                   0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_D2_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_D2_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_D2_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_5_D2_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6                                  0x0001D1D8
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_ITERATION_CURRENT_LSB          26
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_ITERATION_CURRENT_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_ITERATION_CURRENT_MASK         0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_ITERATION_CURRENT_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_ITERATION_WRAP_LSB             20
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_ITERATION_WRAP_WIDTH           6
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_ITERATION_WRAP_MASK            0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_ITERATION_WRAP_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_ITERATION_STEPSIZE_LSB         0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_ITERATION_STEPSIZE_WIDTH       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_ITERATION_STEPSIZE_MASK        0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_6_ITERATION_STEPSIZE_DEFVAL      0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7                                  0x0001D1DC
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_MASK                             0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_TLAST_SUPPRESS_LSB             31
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_TLAST_SUPPRESS_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_TLAST_SUPPRESS_MASK            0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_TLAST_SUPPRESS_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_NEXT_BD_LSB                    27
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_NEXT_BD_WIDTH                  4
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_NEXT_BD_MASK                   0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_NEXT_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_USE_NEXT_BD_LSB                26
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_USE_NEXT_BD_WIDTH              1
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_USE_NEXT_BD_MASK               0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_USE_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_VALID_BD_LSB                   25
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_VALID_BD_WIDTH                 1
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_VALID_BD_MASK                  0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_VALID_BD_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_REL_VALUE_LSB             18
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_REL_VALUE_WIDTH           7
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_REL_VALUE_MASK            0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_REL_VALUE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_REL_ID_LSB                13
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_REL_ID_WIDTH              4
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_REL_ID_MASK               0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_REL_ID_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_ACQ_ENABLE_LSB            12
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_ACQ_ENABLE_WIDTH          1
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_ACQ_ENABLE_MASK           0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_ACQ_ENABLE_DEFVAL         0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_ACQ_VALUE_LSB             5
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_ACQ_VALUE_WIDTH           7
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_ACQ_VALUE_MASK            0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_ACQ_VALUE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_ACQ_ID_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_ACQ_ID_WIDTH              4
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_ACQ_ID_MASK               0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD14_7_LOCK_ACQ_ID_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD15_0                                  0x0001D1E0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_0_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_0_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_0_BUFFER_LENGTH_LSB              0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_0_BUFFER_LENGTH_WIDTH            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_0_BUFFER_LENGTH_MASK             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_0_BUFFER_LENGTH_DEFVAL           0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD15_1                                  0x0001D1E4
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_1_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_1_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_1_BASE_ADDRESS_LOW_LSB           2
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_1_BASE_ADDRESS_LOW_WIDTH         30
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_1_BASE_ADDRESS_LOW_MASK          0xFFFFFFFC
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_1_BASE_ADDRESS_LOW_DEFVAL        0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2                                  0x0001D1E8
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_MASK                             0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_ENABLE_PACKET_LSB              30
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_ENABLE_PACKET_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_ENABLE_PACKET_MASK             0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_ENABLE_PACKET_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_OUT_OF_ORDER_BD_ID_LSB         24
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_OUT_OF_ORDER_BD_ID_WIDTH       6
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_OUT_OF_ORDER_BD_ID_MASK        0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_OUT_OF_ORDER_BD_ID_DEFVAL      0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_PACKET_ID_LSB                  19
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_PACKET_ID_WIDTH                5
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_PACKET_ID_MASK                 0x00F80000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_PACKET_ID_DEFVAL               0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_PACKET_TYPE_LSB                16
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_PACKET_TYPE_WIDTH              3
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_PACKET_TYPE_MASK               0x00070000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_PACKET_TYPE_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_BASE_ADDRESS_HIGH_LSB          0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_BASE_ADDRESS_HIGH_WIDTH        16
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_BASE_ADDRESS_HIGH_MASK         0x0000FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_2_BASE_ADDRESS_HIGH_DEFVAL       0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3                                  0x0001D1EC
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_MASK                             0x7FFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_SECURE_ACCESS_LSB              30
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_SECURE_ACCESS_WIDTH            1
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_SECURE_ACCESS_MASK             0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_SECURE_ACCESS_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_D0_WRAP_LSB                    20
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_D0_WRAP_WIDTH                  10
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_D0_WRAP_MASK                   0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_D0_WRAP_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_D0_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_D0_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_D0_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_3_D0_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4                                  0x0001D1F0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_BURST_LENGTH_LSB               30
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_BURST_LENGTH_WIDTH             2
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_BURST_LENGTH_MASK              0xC0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_BURST_LENGTH_DEFVAL            0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_D1_WRAP_LSB                    20
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_D1_WRAP_WIDTH                  10
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_D1_WRAP_MASK                   0x3FF00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_D1_WRAP_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_D1_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_D1_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_D1_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_4_D1_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5                                  0x0001D1F4
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_SMID_LSB                       28
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_SMID_WIDTH                     4
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_SMID_MASK                      0xF0000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_SMID_DEFVAL                    0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_AXCACHE_LSB                    24
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_AXCACHE_WIDTH                  4
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_AXCACHE_MASK                   0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_AXCACHE_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_AXQOS_LSB                      20
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_AXQOS_WIDTH                    4
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_AXQOS_MASK                     0x00F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_AXQOS_DEFVAL                   0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_D2_STEPSIZE_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_D2_STEPSIZE_WIDTH              20
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_D2_STEPSIZE_MASK               0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_5_D2_STEPSIZE_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6                                  0x0001D1F8
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_MASK                             0xFFFFFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_ITERATION_CURRENT_LSB          26
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_ITERATION_CURRENT_WIDTH        6
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_ITERATION_CURRENT_MASK         0xFC000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_ITERATION_CURRENT_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_ITERATION_WRAP_LSB             20
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_ITERATION_WRAP_WIDTH           6
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_ITERATION_WRAP_MASK            0x03F00000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_ITERATION_WRAP_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_ITERATION_STEPSIZE_LSB         0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_ITERATION_STEPSIZE_WIDTH       20
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_ITERATION_STEPSIZE_MASK        0x000FFFFF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_6_ITERATION_STEPSIZE_DEFVAL      0x0

#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7                                  0x0001D1FC
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_MASK                             0xFFFDFFEF
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_TLAST_SUPPRESS_LSB             31
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_TLAST_SUPPRESS_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_TLAST_SUPPRESS_MASK            0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_TLAST_SUPPRESS_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_NEXT_BD_LSB                    27
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_NEXT_BD_WIDTH                  4
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_NEXT_BD_MASK                   0x78000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_NEXT_BD_DEFVAL                 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_USE_NEXT_BD_LSB                26
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_USE_NEXT_BD_WIDTH              1
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_USE_NEXT_BD_MASK               0x04000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_USE_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_VALID_BD_LSB                   25
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_VALID_BD_WIDTH                 1
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_VALID_BD_MASK                  0x02000000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_VALID_BD_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_REL_VALUE_LSB             18
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_REL_VALUE_WIDTH           7
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_REL_VALUE_MASK            0x01FC0000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_REL_VALUE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_REL_ID_LSB                13
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_REL_ID_WIDTH              4
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_REL_ID_MASK               0x0001E000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_REL_ID_DEFVAL             0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_ACQ_ENABLE_LSB            12
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_ACQ_ENABLE_WIDTH          1
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_ACQ_ENABLE_MASK           0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_ACQ_ENABLE_DEFVAL         0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_ACQ_VALUE_LSB             5
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_ACQ_VALUE_WIDTH           7
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_ACQ_VALUE_MASK            0x00000FE0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_ACQ_VALUE_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_ACQ_ID_LSB                0
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_ACQ_ID_WIDTH              4
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_ACQ_ID_MASK               0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_BD15_7_LOCK_ACQ_ID_DEFVAL             0x0

#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL                             0x0001D200
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_WIDTH                       32
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_MASK                        0x0003FF0E
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_FOT_MODE_LSB              16
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_FOT_MODE_WIDTH            2
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_FOT_MODE_MASK             0x00030000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_FOT_MODE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_CONTROLLER_ID_LSB         8
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_CONTROLLER_ID_WIDTH       8
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_CONTROLLER_ID_MASK        0x0000FF00
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_CONTROLLER_ID_DEFVAL      0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_ENABLE_OUT_OF_ORDER_LSB   3
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_ENABLE_OUT_OF_ORDER_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_ENABLE_OUT_OF_ORDER_MASK  0x00000008
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_ENABLE_OUT_OF_ORDER_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_PAUSE_STREAM_LSB          2
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_PAUSE_STREAM_WIDTH        1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_PAUSE_STREAM_MASK         0x00000004
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_PAUSE_STREAM_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_PAUSE_MEM_LSB             1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_PAUSE_MEM_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_PAUSE_MEM_MASK            0x00000002
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_CTRL_PAUSE_MEM_DEFVAL          0x0

#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE                       0x0001D204
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_WIDTH                 32
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_MASK                  0x80FF000F
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_REPEAT_COUNT_LSB    16
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_REPEAT_COUNT_WIDTH  8
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_REPEAT_COUNT_MASK   0x00FF0000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_START_BD_ID_LSB     0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_START_BD_ID_WIDTH   4
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_START_BD_ID_MASK    0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_0_TASK_QUEUE_START_BD_ID_DEFVAL  0x0

#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL                             0x0001D208
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_WIDTH                       32
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_MASK                        0x0003FF0E
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_FOT_MODE_LSB              16
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_FOT_MODE_WIDTH            2
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_FOT_MODE_MASK             0x00030000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_FOT_MODE_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_CONTROLLER_ID_LSB         8
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_CONTROLLER_ID_WIDTH       8
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_CONTROLLER_ID_MASK        0x0000FF00
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_CONTROLLER_ID_DEFVAL      0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_ENABLE_OUT_OF_ORDER_LSB   3
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_ENABLE_OUT_OF_ORDER_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_ENABLE_OUT_OF_ORDER_MASK  0x00000008
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_ENABLE_OUT_OF_ORDER_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_PAUSE_STREAM_LSB          2
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_PAUSE_STREAM_WIDTH        1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_PAUSE_STREAM_MASK         0x00000004
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_PAUSE_STREAM_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_PAUSE_MEM_LSB             1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_PAUSE_MEM_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_PAUSE_MEM_MASK            0x00000002
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_CTRL_PAUSE_MEM_DEFVAL          0x0

#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE                       0x0001D20C
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_WIDTH                 32
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_MASK                  0x80FF000F
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_REPEAT_COUNT_LSB    16
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_REPEAT_COUNT_WIDTH  8
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_REPEAT_COUNT_MASK   0x00FF0000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_START_BD_ID_LSB     0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_START_BD_ID_WIDTH   4
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_START_BD_ID_MASK    0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_1_TASK_QUEUE_START_BD_ID_DEFVAL  0x0

#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL                             0x0001D210
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_WIDTH                       32
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_MASK                        0x0000FF06
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_CONTROLLER_ID_LSB         8
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_CONTROLLER_ID_WIDTH       8
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_CONTROLLER_ID_MASK        0x0000FF00
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_CONTROLLER_ID_DEFVAL      0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_PAUSE_STREAM_LSB          2
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_PAUSE_STREAM_WIDTH        1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_PAUSE_STREAM_MASK         0x00000004
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_PAUSE_STREAM_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_PAUSE_MEM_LSB             1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_PAUSE_MEM_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_PAUSE_MEM_MASK            0x00000002
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_CTRL_PAUSE_MEM_DEFVAL          0x0

#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE                       0x0001D214
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_WIDTH                 32
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_MASK                  0x80FF000F
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_REPEAT_COUNT_LSB    16
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_REPEAT_COUNT_WIDTH  8
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_REPEAT_COUNT_MASK   0x00FF0000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_START_BD_ID_LSB     0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_START_BD_ID_WIDTH   4
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_START_BD_ID_MASK    0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_0_TASK_QUEUE_START_BD_ID_DEFVAL  0x0

#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL                             0x0001D218
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_WIDTH                       32
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_MASK                        0x0000FF06
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_CONTROLLER_ID_LSB         8
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_CONTROLLER_ID_WIDTH       8
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_CONTROLLER_ID_MASK        0x0000FF00
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_CONTROLLER_ID_DEFVAL      0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_PAUSE_STREAM_LSB          2
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_PAUSE_STREAM_WIDTH        1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_PAUSE_STREAM_MASK         0x00000004
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_PAUSE_STREAM_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_PAUSE_MEM_LSB             1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_PAUSE_MEM_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_PAUSE_MEM_MASK            0x00000002
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_CTRL_PAUSE_MEM_DEFVAL          0x0

#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE                       0x0001D21C
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_WIDTH                 32
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_MASK                  0x80FF000F
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_REPEAT_COUNT_LSB    16
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_REPEAT_COUNT_WIDTH  8
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_REPEAT_COUNT_MASK   0x00FF0000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_START_BD_ID_LSB     0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_START_BD_ID_WIDTH   4
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_START_BD_ID_MASK    0x0000000F
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_1_TASK_QUEUE_START_BD_ID_DEFVAL  0x0

#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0                           0x0001D220
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_WIDTH                     32
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_MASK                      0x0F7F3C3F
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_CUR_BD_LSB              24
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_CUR_BD_WIDTH            4
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_CUR_BD_MASK             0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_CUR_BD_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_SIZE_LSB     20
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_SIZE_WIDTH   3
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_SIZE_MASK    0x00700000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_SIZE_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_CHANNEL_RUNNING_LSB     19
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_CHANNEL_RUNNING_WIDTH   1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_CHANNEL_RUNNING_MASK    0x00080000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_CHANNEL_RUNNING_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_AXI_MM_SLAVE_ERROR_LSB  17
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_AXI_MM_SLAVE_ERROR_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_AXI_MM_SLAVE_ERROR_MASK 0x00020000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_AXI_MM_SLAVE_ERROR_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_AXI_MM_DECODE_ERROR_LSB 16
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_AXI_MM_DECODE_ERROR_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_AXI_MM_DECODE_ERROR_MASK 0x00010000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_AXI_MM_DECODE_ERROR_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_BDS_PER_TASK_LSB 13
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_BDS_PER_TASK_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_BDS_PER_TASK_MASK 0x00002000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_BDS_PER_TASK_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_LENGTH_EXCEEDED_LSB 12
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_LENGTH_EXCEEDED_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_LENGTH_EXCEEDED_MASK 0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_LENGTH_EXCEEDED_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_INVALID_LSB    11
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_INVALID_WIDTH  1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_INVALID_MASK   0x00000800
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_TCT_OR_COUNT_FIFO_FULL_LSB 5
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_TCT_OR_COUNT_FIFO_FULL_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_TCT_OR_COUNT_FIFO_FULL_MASK 0x00000020
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_TCT_OR_COUNT_FIFO_FULL_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_STREAM_STARVATION_LSB 4
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_STREAM_STARVATION_MASK 0x00000010
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_STREAM_STARVATION_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_REL_LSB    3
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_REL_WIDTH  1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_REL_MASK   0x00000008
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_ACQ_LSB    2
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_ACQ_WIDTH  1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_ACQ_MASK   0x00000004
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STATUS_LSB              0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STATUS_WIDTH            2
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STATUS_MASK             0x00000003
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_0_STATUS_DEFVAL           0x0

#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1                           0x0001D224
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_WIDTH                     32
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_MASK                      0x0F7F3C3F
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_CUR_BD_LSB              24
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_CUR_BD_WIDTH            4
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_CUR_BD_MASK             0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_CUR_BD_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_SIZE_LSB     20
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_SIZE_WIDTH   3
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_SIZE_MASK    0x00700000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_SIZE_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_CHANNEL_RUNNING_LSB     19
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_CHANNEL_RUNNING_WIDTH   1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_CHANNEL_RUNNING_MASK    0x00080000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_CHANNEL_RUNNING_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_AXI_MM_SLAVE_ERROR_LSB  17
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_AXI_MM_SLAVE_ERROR_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_AXI_MM_SLAVE_ERROR_MASK 0x00020000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_AXI_MM_SLAVE_ERROR_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_AXI_MM_DECODE_ERROR_LSB 16
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_AXI_MM_DECODE_ERROR_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_AXI_MM_DECODE_ERROR_MASK 0x00010000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_AXI_MM_DECODE_ERROR_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_BDS_PER_TASK_LSB 13
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_BDS_PER_TASK_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_BDS_PER_TASK_MASK 0x00002000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_BDS_PER_TASK_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_LENGTH_EXCEEDED_LSB 12
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_LENGTH_EXCEEDED_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_LENGTH_EXCEEDED_MASK 0x00001000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_LENGTH_EXCEEDED_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_INVALID_LSB    11
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_INVALID_WIDTH  1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_INVALID_MASK   0x00000800
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_TCT_OR_COUNT_FIFO_FULL_LSB 5
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_TCT_OR_COUNT_FIFO_FULL_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_TCT_OR_COUNT_FIFO_FULL_MASK 0x00000020
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_TCT_OR_COUNT_FIFO_FULL_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_STREAM_STARVATION_LSB 4
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_STREAM_STARVATION_MASK 0x00000010
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_STREAM_STARVATION_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_REL_LSB    3
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_REL_WIDTH  1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_REL_MASK   0x00000008
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_ACQ_LSB    2
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_ACQ_WIDTH  1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_ACQ_MASK   0x00000004
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STATUS_LSB              0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STATUS_WIDTH            2
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STATUS_MASK             0x00000003
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_STATUS_1_STATUS_DEFVAL           0x0

#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0                           0x0001D228
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_WIDTH                     32
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_MASK                      0x0F7F083F
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_CUR_BD_LSB              24
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_CUR_BD_WIDTH            4
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_CUR_BD_MASK             0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_CUR_BD_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_SIZE_LSB     20
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_SIZE_WIDTH   3
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_SIZE_MASK    0x00700000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_SIZE_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_CHANNEL_RUNNING_LSB     19
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_CHANNEL_RUNNING_WIDTH   1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_CHANNEL_RUNNING_MASK    0x00080000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_CHANNEL_RUNNING_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_AXI_MM_SLAVE_ERROR_LSB  17
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_AXI_MM_SLAVE_ERROR_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_AXI_MM_SLAVE_ERROR_MASK 0x00020000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_AXI_MM_SLAVE_ERROR_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_AXI_MM_DECODE_ERROR_LSB 16
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_AXI_MM_DECODE_ERROR_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_AXI_MM_DECODE_ERROR_MASK 0x00010000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_AXI_MM_DECODE_ERROR_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_INVALID_LSB    11
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_INVALID_WIDTH  1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_INVALID_MASK   0x00000800
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_TCT_LSB         5
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_TCT_WIDTH       1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_TCT_MASK        0x00000020
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_TCT_DEFVAL      0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_STREAM_BACKPRESSURE_LSB 4
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_STREAM_BACKPRESSURE_MASK 0x00000010
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_STREAM_BACKPRESSURE_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_REL_LSB    3
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_REL_WIDTH  1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_REL_MASK   0x00000008
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_ACQ_LSB    2
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_ACQ_WIDTH  1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_ACQ_MASK   0x00000004
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STATUS_LSB              0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STATUS_WIDTH            2
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STATUS_MASK             0x00000003
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_0_STATUS_DEFVAL           0x0

#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1                           0x0001D22C
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_WIDTH                     32
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_MASK                      0x0F7F083F
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_CUR_BD_LSB              24
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_CUR_BD_WIDTH            4
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_CUR_BD_MASK             0x0F000000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_CUR_BD_DEFVAL           0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_SIZE_LSB     20
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_SIZE_WIDTH   3
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_SIZE_MASK    0x00700000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_SIZE_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_CHANNEL_RUNNING_LSB     19
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_CHANNEL_RUNNING_WIDTH   1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_CHANNEL_RUNNING_MASK    0x00080000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_CHANNEL_RUNNING_DEFVAL  0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_AXI_MM_SLAVE_ERROR_LSB  17
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_AXI_MM_SLAVE_ERROR_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_AXI_MM_SLAVE_ERROR_MASK 0x00020000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_AXI_MM_SLAVE_ERROR_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_AXI_MM_DECODE_ERROR_LSB 16
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_AXI_MM_DECODE_ERROR_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_AXI_MM_DECODE_ERROR_MASK 0x00010000
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_AXI_MM_DECODE_ERROR_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_INVALID_LSB    11
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_INVALID_WIDTH  1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_INVALID_MASK   0x00000800
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_TCT_LSB         5
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_TCT_WIDTH       1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_TCT_MASK        0x00000020
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_TCT_DEFVAL      0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_STREAM_BACKPRESSURE_LSB 4
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_STREAM_BACKPRESSURE_MASK 0x00000010
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_STREAM_BACKPRESSURE_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_REL_LSB    3
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_REL_WIDTH  1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_REL_MASK   0x00000008
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_ACQ_LSB    2
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_ACQ_WIDTH  1
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_ACQ_MASK   0x00000004
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STATUS_LSB              0
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STATUS_WIDTH            2
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STATUS_MASK             0x00000003
#define XAIEMLGBL_NOC_MODULE_DMA_MM2S_STATUS_1_STATUS_DEFVAL           0x0

#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0              0x0001D230
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_WIDTH        32
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_MASK         0x0003FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_CURRENT_WRITE_COUNT_LSB 0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_CURRENT_WRITE_COUNT_WIDTH 18
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_CURRENT_WRITE_COUNT_MASK 0x0003FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_CURRENT_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1              0x0001D234
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_WIDTH        32
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_MASK         0x0003FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_CURRENT_WRITE_COUNT_LSB 0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_CURRENT_WRITE_COUNT_WIDTH 18
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_CURRENT_WRITE_COUNT_MASK 0x0003FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_CURRENT_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0               0x0001D238
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WIDTH         32
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_MASK          0xFF03FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_VALID_LSB   31
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_VALID_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_VALID_MASK  0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_VALID_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_LAST_IN_TASK_LSB 30
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_LAST_IN_TASK_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_LAST_IN_TASK_MASK 0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_LAST_IN_TASK_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_BD_ID_LSB   24
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_BD_ID_WIDTH 6
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_BD_ID_MASK  0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WRITE_COUNT_LSB 0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WRITE_COUNT_WIDTH 18
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WRITE_COUNT_MASK 0x0003FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1               0x0001D23C
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WIDTH         32
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_MASK          0xFF03FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_VALID_LSB   31
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_VALID_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_VALID_MASK  0x80000000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_VALID_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_LAST_IN_TASK_LSB 30
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_LAST_IN_TASK_WIDTH 1
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_LAST_IN_TASK_MASK 0x40000000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_LAST_IN_TASK_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_BD_ID_LSB   24
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_BD_ID_WIDTH 6
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_BD_ID_MASK  0x3F000000
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WRITE_COUNT_LSB 0
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WRITE_COUNT_WIDTH 18
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WRITE_COUNT_MASK 0x0003FFFF
#define XAIEMLGBL_NOC_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH2              0x0001E008
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH2_WIDTH        32
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH2_MASK         0x000003FF
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH2_TDEST_LSB  0
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH2_TDEST_WIDTH 10
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH2_TDEST_MASK 0x000003FF
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH2_TDEST_DEFVAL 0x0

#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH3              0x0001E00C
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH3_WIDTH        32
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH3_MASK         0x000003FF
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH3_TDEST_LSB  0
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH3_TDEST_WIDTH 10
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH3_TDEST_MASK 0x000003FF
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH3_TDEST_DEFVAL 0x0

#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH4              0x0001E010
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH4_WIDTH        32
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH4_MASK         0x000003FF
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH4_TDEST_LSB  0
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH4_TDEST_WIDTH 10
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH4_TDEST_MASK 0x000003FF
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH4_TDEST_DEFVAL 0x0

#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH5              0x0001E014
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH5_WIDTH        32
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH5_MASK         0x000003FF
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH5_TDEST_LSB  0
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH5_TDEST_WIDTH 10
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH5_TDEST_MASK 0x000003FF
#define XAIEMLGBL_NOC_MODULE_NOC_INTERFACE_ME_TO_NOC_SOUTH5_TDEST_DEFVAL 0x0

#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG                             0x0001E020
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_WIDTH                       32
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_MASK                        0x0000000F
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_DECERR_BLOCK_LSB          3
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_DECERR_BLOCK_WIDTH        1
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_DECERR_BLOCK_MASK         0x00000008
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_DECERR_BLOCK_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_SLVERR_BLOCK_LSB          2
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_SLVERR_BLOCK_WIDTH        1
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_SLVERR_BLOCK_MASK         0x00000004
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_SLVERR_BLOCK_DEFVAL       0x0
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_SLAVE_SEL_LSB             1
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_SLAVE_SEL_WIDTH           1
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_SLAVE_SEL_MASK            0x00000002
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_SLAVE_SEL_DEFVAL          0x0
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_MASTER_SEL_LSB            0
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_MASTER_SEL_WIDTH          1
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_MASTER_SEL_MASK           0x00000001
#define XAIEMLGBL_NOC_MODULE_ME_AXIMM_CONFIG_MASTER_SEL_DEFVAL         0x0

#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG                                  0x0001F000
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_WIDTH                            32
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_MASK                             0x0000FF00
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH7_LSB                     14
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH7_WIDTH                   2
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH7_MASK                    0x0000C000
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH7_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH6_LSB                     12
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH6_WIDTH                   2
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH6_MASK                    0x00003000
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH6_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH3_LSB                     10
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH3_WIDTH                   2
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH3_MASK                    0x00000C00
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH3_DEFVAL                  0x0
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH2_LSB                     8
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH2_WIDTH                   2
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH2_MASK                    0x00000300
#define XAIEMLGBL_NOC_MODULE_MUX_CONFIG_SOUTH2_DEFVAL                  0x0

#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG                                0x0001F004
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_WIDTH                          32
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_MASK                           0x00000FF0
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH5_LSB                   10
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH5_WIDTH                 2
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH5_MASK                  0x00000C00
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH5_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH4_LSB                   8
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH4_WIDTH                 2
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH4_MASK                  0x00000300
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH4_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH3_LSB                   6
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH3_WIDTH                 2
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH3_MASK                  0x000000C0
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH3_DEFVAL                0x0
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH2_LSB                   4
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH2_WIDTH                 2
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH2_MASK                  0x00000030
#define XAIEMLGBL_NOC_MODULE_DEMUX_CONFIG_SOUTH2_DEFVAL                0x0

#define XAIEMLGBL_NOC_MODULE_LOCK_REQUEST                                0x00040000
#define XAIEMLGBL_NOC_MODULE_LOCK_REQUEST_WIDTH                          32
#define XAIEMLGBL_NOC_MODULE_LOCK_REQUEST_MASK                           0x00000001
#define XAIEMLGBL_NOC_MODULE_LOCK_REQUEST_REQUEST_RESULT_LSB           0
#define XAIEMLGBL_NOC_MODULE_LOCK_REQUEST_REQUEST_RESULT_WIDTH         1
#define XAIEMLGBL_NOC_MODULE_LOCK_REQUEST_REQUEST_RESULT_MASK          0x00000001
#define XAIEMLGBL_NOC_MODULE_LOCK_REQUEST_REQUEST_RESULT_DEFVAL        0x0

/* AIE-ML Mem Tile module register definitions */
#define XAIEMLGBL_MEM_TILE_MODULE_DATAMEMORY                             0x00000000
#define XAIEMLGBL_MEM_TILE_MODULE_DATAMEMORY_WIDTH                       128
#define XAIEMLGBL_MEM_TILE_MODULE_DATAMEMORY_MASK                        0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DATAMEMORY_DATA_LSB                  0
#define XAIEMLGBL_MEM_TILE_MODULE_DATAMEMORY_DATA_WIDTH                128
#define XAIEMLGBL_MEM_TILE_MODULE_DATAMEMORY_DATA_MASK                 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DATAMEMORY_DATA_DEFVAL               0x0

#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0                   0x00091000
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_WIDTH             32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_MASK              0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT1_STOP_EVENT_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT1_STOP_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT1_STOP_EVENT_MASK 0xFF000000
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT1_STOP_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT1_START_EVENT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT1_START_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT1_START_EVENT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT1_START_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT0_STOP_EVENT_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT0_STOP_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT0_STOP_EVENT_MASK 0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT0_STOP_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT0_START_EVENT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT0_START_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT0_START_EVENT_MASK 0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL0_CNT0_START_EVENT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1                   0x00091004
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_WIDTH             32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_MASK              0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT3_STOP_EVENT_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT3_STOP_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT3_STOP_EVENT_MASK 0xFF000000
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT3_STOP_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT3_START_EVENT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT3_START_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT3_START_EVENT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT3_START_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT2_STOP_EVENT_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT2_STOP_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT2_STOP_EVENT_MASK 0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT2_STOP_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT2_START_EVENT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT2_START_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT2_START_EVENT_MASK 0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL1_CNT2_START_EVENT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2                   0x00091008
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_WIDTH             32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_MASK              0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT3_RESET_EVENT_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT3_RESET_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT3_RESET_EVENT_MASK 0xFF000000
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT3_RESET_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT2_RESET_EVENT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT2_RESET_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT2_RESET_EVENT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT2_RESET_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT1_RESET_EVENT_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT1_RESET_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT1_RESET_EVENT_MASK 0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT1_RESET_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT0_RESET_EVENT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT0_RESET_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT0_RESET_EVENT_MASK 0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_CONTROL2_CNT0_RESET_EVENT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0                   0x00091020
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0_WIDTH             32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0_MASK              0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0_COUNTER0_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1                   0x00091024
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1_WIDTH             32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1_MASK              0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1_COUNTER1_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1_COUNTER1_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1_COUNTER1_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1_COUNTER1_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2                   0x00091028
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2_WIDTH             32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2_MASK              0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2_COUNTER2_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2_COUNTER2_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2_COUNTER2_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2_COUNTER2_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3                   0x0009102C
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3_WIDTH             32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3_MASK              0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3_COUNTER3_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3_COUNTER3_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3_COUNTER3_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3_COUNTER3_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE       0x00091080
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_MASK  0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER0_EVENT_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER0_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER0_EVENT_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER0_EVENT_VALUE_COUNTER0_EVENT_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE       0x00091084
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_MASK  0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER1_EVENT_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER1_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER1_EVENT_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER1_EVENT_VALUE_COUNTER1_EVENT_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE       0x00091088
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE_MASK  0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE_COUNTER2_EVENT_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE_COUNTER2_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE_COUNTER2_EVENT_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER2_EVENT_VALUE_COUNTER2_EVENT_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE       0x0009108C
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE_MASK  0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE_COUNTER3_EVENT_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE_COUNTER3_EVENT_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE_COUNTER3_EVENT_VALUE_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_PERFORMANCE_COUNTER3_EVENT_VALUE_COUNTER3_EVENT_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION              0x00092000
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_WIDTH        32
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_MASK         0x0000000F
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE3_LSB  3
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE3_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE3_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE3_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE2_LSB  2
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE2_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE2_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE2_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE1_LSB  1
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE1_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE1_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE0_LSB  0
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE0_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_CHECKBIT_ERROR_GENERATION_LANE0_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_ECC_SCRUBBING_EVENT                    0x00092110
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_SCRUBBING_EVENT_WIDTH              32
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_SCRUBBING_EVENT_MASK               0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_SCRUBBING_EVENT_SCRUBBING_EVENT_NUMBER_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_SCRUBBING_EVENT_SCRUBBING_EVENT_NUMBER_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_SCRUBBING_EVENT_SCRUBBING_EVENT_NUMBER_MASK 0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_SCRUBBING_EVENT_SCRUBBING_EVENT_NUMBER_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_ECC_FAILING_ADDRESS                    0x00092120
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_FAILING_ADDRESS_WIDTH              32
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_FAILING_ADDRESS_MASK               0x000FFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_FAILING_ADDRESS_VALID_LSB        19
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_FAILING_ADDRESS_VALID_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_FAILING_ADDRESS_VALID_MASK       0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_FAILING_ADDRESS_VALID_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_FAILING_ADDRESS_ECC_ERROR_DETECTION_ADDRESS_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_FAILING_ADDRESS_ECC_ERROR_DETECTION_ADDRESS_WIDTH 19
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_FAILING_ADDRESS_ECC_ERROR_DETECTION_ADDRESS_MASK 0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_ECC_FAILING_ADDRESS_ECC_ERROR_DETECTION_ADDRESS_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_CONTROL                          0x00094000
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_CONTROL_WIDTH                    32
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_CONTROL_MASK                     0x8000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_CONTROL_RESET_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_CONTROL_RESET_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_CONTROL_RESET_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_CONTROL_RESET_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_CONTROL_RESET_EVENT_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_CONTROL_RESET_EVENT_WIDTH      8
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_CONTROL_RESET_EVENT_MASK       0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_CONTROL_RESET_EVENT_DEFVAL     0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GENERATE                         0x00094008
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GENERATE_WIDTH                   32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GENERATE_MASK                    0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GENERATE_EVENT_LSB             0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GENERATE_EVENT_WIDTH           8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GENERATE_EVENT_MASK            0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GENERATE_EVENT_DEFVAL          0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST0                       0x00094010
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST0_WIDTH                 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST0_MASK                  0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST0_EVENT_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST0_EVENT_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST0_EVENT_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST0_EVENT_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST1                       0x00094014
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST1_WIDTH                 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST1_MASK                  0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST1_EVENT_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST1_EVENT_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST1_EVENT_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST1_EVENT_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST2                       0x00094018
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST2_WIDTH                 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST2_MASK                  0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST2_EVENT_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST2_EVENT_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST2_EVENT_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST2_EVENT_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST3                       0x0009401C
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST3_WIDTH                 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST3_MASK                  0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST3_EVENT_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST3_EVENT_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST3_EVENT_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST3_EVENT_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST4                       0x00094020
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST4_WIDTH                 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST4_MASK                  0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST4_EVENT_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST4_EVENT_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST4_EVENT_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST4_EVENT_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST5                       0x00094024
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST5_WIDTH                 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST5_MASK                  0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST5_EVENT_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST5_EVENT_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST5_EVENT_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST5_EVENT_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST6                       0x00094028
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST6_WIDTH                 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST6_MASK                  0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST6_EVENT_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST6_EVENT_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST6_EVENT_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST6_EVENT_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST7                       0x0009402C
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST7_WIDTH                 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST7_MASK                  0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST7_EVENT_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST7_EVENT_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST7_EVENT_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST7_EVENT_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST8                       0x00094030
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST8_WIDTH                 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST8_MASK                  0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST8_EVENT_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST8_EVENT_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST8_EVENT_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST8_EVENT_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST9                       0x00094034
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST9_WIDTH                 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST9_MASK                  0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST9_EVENT_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST9_EVENT_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST9_EVENT_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST9_EVENT_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST10                      0x00094038
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST10_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST10_MASK                 0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST10_EVENT_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST10_EVENT_WIDTH        8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST10_EVENT_MASK         0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST10_EVENT_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST11                      0x0009403C
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST11_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST11_MASK                 0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST11_EVENT_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST11_EVENT_WIDTH        8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST11_EVENT_MASK         0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST11_EVENT_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST12                      0x00094040
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST12_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST12_MASK                 0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST12_EVENT_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST12_EVENT_WIDTH        8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST12_EVENT_MASK         0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST12_EVENT_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST13                      0x00094044
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST13_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST13_MASK                 0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST13_EVENT_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST13_EVENT_WIDTH        8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST13_EVENT_MASK         0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST13_EVENT_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST14                      0x00094048
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST14_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST14_MASK                 0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST14_EVENT_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST14_EVENT_WIDTH        8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST14_EVENT_MASK         0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST14_EVENT_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST15                      0x0009404C
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST15_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST15_MASK                 0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST15_EVENT_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST15_EVENT_WIDTH        8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST15_EVENT_MASK         0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST15_EVENT_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET      0x00094050
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET_SET_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET_SET_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR      0x00094054
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR_CLEAR_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE    0x00094058
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_SOUTH_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET       0x00094060
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET_MASK  0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET_SET_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET_SET_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR       0x00094064
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR_MASK  0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR_CLEAR_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE     0x00094068
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_WEST_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET      0x00094070
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET_SET_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET_SET_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR      0x00094074
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR_CLEAR_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE    0x00094078
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_NORTH_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET       0x00094080
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET_MASK  0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET_SET_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET_SET_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR       0x00094084
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR_MASK  0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR_CLEAR_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE     0x00094088
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_A_BLOCK_EAST_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET      0x00094090
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET_SET_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET_SET_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR      0x00094094
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR_CLEAR_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE    0x00094098
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_SOUTH_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET       0x000940A0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET_MASK  0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET_SET_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET_SET_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR       0x000940A4
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR_MASK  0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR_CLEAR_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE     0x000940A8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_WEST_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET      0x000940B0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET_SET_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET_SET_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR      0x000940B4
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR_CLEAR_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE    0x000940B8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_NORTH_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET       0x000940C0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET_MASK  0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET_SET_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET_SET_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET_SET_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_SET_SET_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR       0x000940C4
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR_MASK  0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR_CLEAR_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR_CLEAR_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR_CLEAR_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_CLR_CLEAR_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE     0x000940C8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE_VALUE_WIDTH 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE_VALUE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_BROADCAST_B_BLOCK_EAST_VALUE_VALUE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL0                         0x000940D0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL0_WIDTH                   32
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL0_MASK                    0xFFFF0000
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_LSB  24
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_MASK 0xFF000000
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL0_TRACE_STOP_EVENT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL0_TRACE_START_EVENT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL1                         0x000940D4
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL1_WIDTH                   32
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL1_MASK                    0x0000701F
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL1_PACKET_TYPE_LSB       12
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL1_PACKET_TYPE_WIDTH     3
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL1_PACKET_TYPE_MASK      0x00007000
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL1_PACKET_TYPE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL1_ID_LSB                0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL1_ID_WIDTH              5
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL1_ID_MASK               0x0000001F
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_CONTROL1_ID_DEFVAL             0x0

#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_STATUS                           0x000940D8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_STATUS_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_STATUS_MASK                      0x00000307
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_STATUS_STATE_LSB               8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_STATUS_STATE_WIDTH             2
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_STATUS_STATE_MASK              0x00000300
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_STATUS_STATE_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_STATUS_MODE_LSB                0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_STATUS_MODE_WIDTH              3
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_STATUS_MODE_MASK               0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_STATUS_MODE_DEFVAL             0x0

#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0                           0x000940E0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_MASK                      0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT3_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT3_WIDTH      8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT3_MASK       0xFF000000
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT3_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT2_LSB        16
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT2_WIDTH      8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT2_MASK       0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT2_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT1_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT1_WIDTH      8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT1_MASK       0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT1_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT0_LSB        0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT0_WIDTH      8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT0_MASK       0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT0_TRACE_EVENT0_DEFVAL     0x0

#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1                           0x000940E4
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_MASK                      0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT7_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT7_WIDTH      8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT7_MASK       0xFF000000
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT7_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT6_LSB        16
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT6_WIDTH      8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT6_MASK       0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT6_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT5_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT5_WIDTH      8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT5_MASK       0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT5_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT4_LSB        0
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT4_WIDTH      8
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT4_MASK       0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_TRACE_EVENT1_TRACE_EVENT4_DEFVAL     0x0

#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE             0x000940F0
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_WIDTH       32
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_MASK        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_LOW_VALUE_TIMERTRIGLOW_DEFVAL 0xFFFFFFFF

#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE            0x000940F4
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_WIDTH      32
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_MASK       0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_TRIG_EVENT_HIGH_VALUE_TIMERTRIGHIGH_DEFVAL 0xFFFFFFFF

#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_LOW                              0x000940F8
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_LOW_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_LOW_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_LOW_TIMERLOW_LSB               0
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_LOW_TIMERLOW_WIDTH             32
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_LOW_TIMERLOW_MASK              0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_LOW_TIMERLOW_DEFVAL            0x0

#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_HIGH                             0x000940FC
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_HIGH_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_HIGH_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_HIGH_TIMERHIGH_LSB             0
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_HIGH_TIMERHIGH_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_HIGH_TIMERHIGH_MASK            0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_TIMER_HIGH_TIMERHIGH_DEFVAL          0x0

#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0                            0x00094100
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_MASK                       0x3FF7FFF0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_READ_ACCESS_LSB          29
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_READ_ACCESS_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_READ_ACCESS_MASK         0x20000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_READ_ACCESS_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_WRITE_ACCESS_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_WRITE_ACCESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_WRITE_ACCESS_MASK        0x10000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_WRITE_ACCESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_AXI_ACCESS_LSB           27
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_AXI_ACCESS_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_AXI_ACCESS_MASK          0x08000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_AXI_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_DMA_ACCESS_LSB           26
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_DMA_ACCESS_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_DMA_ACCESS_MASK          0x04000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_DMA_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_EAST_ACCESS_LSB          25
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_EAST_ACCESS_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_EAST_ACCESS_MASK         0x02000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_EAST_ACCESS_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_WEST_ACCESS_LSB          24
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_WEST_ACCESS_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_WEST_ACCESS_MASK         0x01000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_WEST_ACCESS_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_WRITESTROBES_LSB         20
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_WRITESTROBES_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_WRITESTROBES_MASK        0x00F00000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_WRITESTROBES_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_ADDRESS_LSB              4
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_ADDRESS_WIDTH            15
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_ADDRESS_MASK             0x0007FFF0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT0_ADDRESS_DEFVAL           0x0

#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1                            0x00094104
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_MASK                       0x3FF7FFF0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_READ_ACCESS_LSB          29
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_READ_ACCESS_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_READ_ACCESS_MASK         0x20000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_READ_ACCESS_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_WRITE_ACCESS_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_WRITE_ACCESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_WRITE_ACCESS_MASK        0x10000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_WRITE_ACCESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_AXI_ACCESS_LSB           27
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_AXI_ACCESS_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_AXI_ACCESS_MASK          0x08000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_AXI_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_DMA_ACCESS_LSB           26
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_DMA_ACCESS_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_DMA_ACCESS_MASK          0x04000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_DMA_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_EAST_ACCESS_LSB          25
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_EAST_ACCESS_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_EAST_ACCESS_MASK         0x02000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_EAST_ACCESS_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_WEST_ACCESS_LSB          24
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_WEST_ACCESS_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_WEST_ACCESS_MASK         0x01000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_WEST_ACCESS_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_WRITESTROBES_LSB         20
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_WRITESTROBES_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_WRITESTROBES_MASK        0x00F00000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_WRITESTROBES_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_ADDRESS_LSB              4
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_ADDRESS_WIDTH            15
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_ADDRESS_MASK             0x0007FFF0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT1_ADDRESS_DEFVAL           0x0

#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2                            0x00094108
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_MASK                       0x3FF7FFF0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_READ_ACCESS_LSB          29
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_READ_ACCESS_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_READ_ACCESS_MASK         0x20000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_READ_ACCESS_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_WRITE_ACCESS_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_WRITE_ACCESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_WRITE_ACCESS_MASK        0x10000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_WRITE_ACCESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_AXI_ACCESS_LSB           27
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_AXI_ACCESS_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_AXI_ACCESS_MASK          0x08000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_AXI_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_DMA_ACCESS_LSB           26
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_DMA_ACCESS_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_DMA_ACCESS_MASK          0x04000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_DMA_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_EAST_ACCESS_LSB          25
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_EAST_ACCESS_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_EAST_ACCESS_MASK         0x02000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_EAST_ACCESS_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_WEST_ACCESS_LSB          24
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_WEST_ACCESS_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_WEST_ACCESS_MASK         0x01000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_WEST_ACCESS_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_WRITESTROBES_LSB         20
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_WRITESTROBES_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_WRITESTROBES_MASK        0x00F00000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_WRITESTROBES_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_ADDRESS_LSB              4
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_ADDRESS_WIDTH            15
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_ADDRESS_MASK             0x0007FFF0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT2_ADDRESS_DEFVAL           0x0

#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3                            0x0009410C
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_MASK                       0x3FF7FFF0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_READ_ACCESS_LSB          29
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_READ_ACCESS_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_READ_ACCESS_MASK         0x20000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_READ_ACCESS_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_WRITE_ACCESS_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_WRITE_ACCESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_WRITE_ACCESS_MASK        0x10000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_WRITE_ACCESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_AXI_ACCESS_LSB           27
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_AXI_ACCESS_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_AXI_ACCESS_MASK          0x08000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_AXI_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_DMA_ACCESS_LSB           26
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_DMA_ACCESS_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_DMA_ACCESS_MASK          0x04000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_DMA_ACCESS_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_EAST_ACCESS_LSB          25
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_EAST_ACCESS_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_EAST_ACCESS_MASK         0x02000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_EAST_ACCESS_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_WEST_ACCESS_LSB          24
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_WEST_ACCESS_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_WEST_ACCESS_MASK         0x01000000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_WEST_ACCESS_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_WRITESTROBES_LSB         20
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_WRITESTROBES_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_WRITESTROBES_MASK        0x00F00000
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_WRITESTROBES_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_ADDRESS_LSB              4
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_ADDRESS_WIDTH            15
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_ADDRESS_MASK             0x0007FFF0
#define XAIEMLGBL_MEM_TILE_MODULE_WATCHPOINT3_ADDRESS_DEFVAL           0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS0                          0x00094200
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS0_WIDTH                    32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS0_MASK                     0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_LSB  0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS0_EVENT_31_0_STATUS_DEFVAL 0x2

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS1                          0x00094204
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS1_WIDTH                    32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS1_MASK                     0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS1_EVENT_63_32_STATUS_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS2                          0x00094208
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS2_WIDTH                    32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS2_MASK                     0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS2_EVENT_95_64_STATUS_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS3                          0x0009420C
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS3_WIDTH                    32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS3_MASK                     0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS3_EVENT_127_96_STATUS_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS4                          0x00094210
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS4_WIDTH                    32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS4_MASK                     0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS4_EVENT_159_128_STATUS_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS4_EVENT_159_128_STATUS_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS4_EVENT_159_128_STATUS_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS4_EVENT_159_128_STATUS_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS5                          0x00094214
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS5_WIDTH                    32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS5_MASK                     0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS5_EVENT_191_160_STATUS_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS5_EVENT_191_160_STATUS_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS5_EVENT_191_160_STATUS_MASK 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_STATUS5_EVENT_191_160_STATUS_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_RESERVED0                              0x00094220
#define XAIEMLGBL_MEM_TILE_MODULE_RESERVED0_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_RESERVED0_MASK                         0xFFFFFFFF

#define XAIEMLGBL_MEM_TILE_MODULE_RESERVED1                              0x00094224
#define XAIEMLGBL_MEM_TILE_MODULE_RESERVED1_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_RESERVED1_MASK                         0xFFFFFFFF

#define XAIEMLGBL_MEM_TILE_MODULE_RESERVED2                              0x00094228
#define XAIEMLGBL_MEM_TILE_MODULE_RESERVED2_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_RESERVED2_MASK                         0xFFFFFFFF

#define XAIEMLGBL_MEM_TILE_MODULE_RESERVED3                              0x0009422C
#define XAIEMLGBL_MEM_TILE_MODULE_RESERVED3_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_RESERVED3_MASK                         0xFFFFFFFF

#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS                     0x00094400
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_WIDTH               32
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_MASK                0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTD_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTD_WIDTH      8
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTD_MASK       0xFF000000
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTD_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTC_LSB        16
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTC_WIDTH      8
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTC_MASK       0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTC_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTB_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTB_WIDTH      8
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTB_MASK       0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTB_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTA_LSB        0
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTA_WIDTH      8
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTA_MASK       0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_INPUTS_EVENTA_DEFVAL     0x0

#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL                    0x00094404
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_WIDTH              32
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_MASK               0x00030303
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_COMBO2_LSB       16
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_COMBO2_WIDTH     2
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_COMBO2_MASK      0x00030000
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_COMBO2_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_COMBO1_LSB       8
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_COMBO1_WIDTH     2
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_COMBO1_MASK      0x00000300
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_COMBO1_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_COMBO0_LSB       0
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_COMBO0_WIDTH     2
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_COMBO0_MASK      0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_COMBO_EVENT_CONTROL_COMBO0_DEFVAL    0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL           0x00094408
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_WIDTH     32
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_MASK      0x06FF06FF
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_LSB 26
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_MASK 0x04000000
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_FALLING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_LSB 25
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_MASK 0x02000000
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_1_TRIGGER_RISING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_1_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_FALLING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_0_TRIGGER_RISING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_MASK 0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_EDGE_DETECTION_EVENT_CONTROL_EDGE_DETECTION_EVENT_0_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE                   0x00094500
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_WIDTH             32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_MASK              0x00000FFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_1_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_EDGE_DETECTION_EVENT_0_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_3_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_2_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_1_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_LSB 6
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_MASK 0x00000040
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_COMBO_EVENT_0_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT3_EVENT_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT3_EVENT_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT3_EVENT_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT3_EVENT_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT2_EVENT_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT2_EVENT_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT2_EVENT_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT2_EVENT_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_EVENT_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_EVENT_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_EVENT_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT1_EVENT_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_EVENT_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_EVENT_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_EVENT_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_PERF_CNT0_EVENT_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_VALUE_REACHED_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_LSB  0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_0_ENABLE_TIMER_SYNC_DEFVAL 0x1

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE          0x00094504
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WIDTH    32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_MASK     0x0000000F
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_3_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_3_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_3_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_3_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_2_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_2_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_2_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_2_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_1_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_1_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_1_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_0_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_0_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_WATCHPOINT_ENABLE_WATCHPOINT_0_DEFVAL 0x1

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE                 0x00094508
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_MASK            0x00FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_MEMORY_STARVATION_LSB 23
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_MEMORY_STARVATION_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_MEMORY_STARVATION_MASK 0x00800000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_MEMORY_STARVATION_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_MEMORY_STARVATION_LSB 22
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_MEMORY_STARVATION_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_MEMORY_STARVATION_MASK 0x00400000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_MEMORY_STARVATION_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_MEMORY_BACKPRESSURE_LSB 21
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_MEMORY_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_MEMORY_BACKPRESSURE_MASK 0x00200000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_MEMORY_BACKPRESSURE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_MEMORY_BACKPRESSURE_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_MEMORY_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_MEMORY_BACKPRESSURE_MASK 0x00100000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_MEMORY_BACKPRESSURE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_STREAM_BACKPRESSURE_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_STREAM_BACKPRESSURE_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_STREAM_BACKPRESSURE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_STREAM_BACKPRESSURE_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_STREAM_BACKPRESSURE_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_STREAM_BACKPRESSURE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_STREAM_STARVATION_LSB 17
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_STREAM_STARVATION_MASK 0x00020000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_STREAM_STARVATION_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_STREAM_STARVATION_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_STREAM_STARVATION_MASK 0x00010000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_STREAM_STARVATION_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_STALLED_LOCK_ACQUIRE_LSB 15
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_STALLED_LOCK_ACQUIRE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_STALLED_LOCK_ACQUIRE_MASK 0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_STALLED_LOCK_ACQUIRE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_STALLED_LOCK_ACQUIRE_LSB 14
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_STALLED_LOCK_ACQUIRE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_STALLED_LOCK_ACQUIRE_MASK 0x00004000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_STALLED_LOCK_ACQUIRE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_STALLED_LOCK_ACQUIRE_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_STALLED_LOCK_ACQUIRE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_STALLED_LOCK_ACQUIRE_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_STALLED_LOCK_ACQUIRE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_STALLED_LOCK_ACQUIRE_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_STALLED_LOCK_ACQUIRE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_STALLED_LOCK_ACQUIRE_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_STALLED_LOCK_ACQUIRE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_FINISHED_TASK_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_FINISHED_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_FINISHED_TASK_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_FINISHED_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_FINISHED_TASK_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_FINISHED_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_FINISHED_TASK_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_FINISHED_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_FINISHED_TASK_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_FINISHED_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_FINISHED_TASK_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_FINISHED_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_FINISHED_TASK_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_FINISHED_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_FINISHED_TASK_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_FINISHED_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_FINISHED_BD_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_FINISHED_BD_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_FINISHED_BD_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_FINISHED_BD_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_FINISHED_BD_LSB 6
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_FINISHED_BD_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_FINISHED_BD_MASK 0x00000040
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_FINISHED_BD_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_FINISHED_BD_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_FINISHED_BD_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_FINISHED_BD_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_FINISHED_BD_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_FINISHED_BD_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_FINISHED_BD_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_FINISHED_BD_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_FINISHED_BD_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_START_TASK_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_START_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_START_TASK_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL1_START_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_START_TASK_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_START_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_START_TASK_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_MM2S_SEL0_START_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_START_TASK_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_START_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_START_TASK_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL1_START_TASK_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_START_TASK_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_START_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_START_TASK_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_DMA_ENABLE_DMA_S2MM_SEL0_START_TASK_DEFVAL 0x1

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE                0x0009450C
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_WIDTH          32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_MASK           0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_EQUAL_TO_VALUE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_EQUAL_TO_VALUE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_REL_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_REL_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_REL_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_GE_LSB 29
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_GE_MASK 0x20000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_EQ_LSB 28
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_EQ_MASK 0x10000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL7_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_EQUAL_TO_VALUE_LSB 27
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_EQUAL_TO_VALUE_MASK 0x08000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_REL_LSB 26
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_REL_MASK 0x04000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_REL_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_GE_LSB 25
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_GE_MASK 0x02000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_EQ_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_EQ_MASK 0x01000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL6_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_EQUAL_TO_VALUE_LSB 23
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_EQUAL_TO_VALUE_MASK 0x00800000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_REL_LSB 22
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_REL_MASK 0x00400000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_REL_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_GE_LSB 21
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_GE_MASK 0x00200000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_EQ_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_EQ_MASK 0x00100000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL5_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_EQUAL_TO_VALUE_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_EQUAL_TO_VALUE_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_REL_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_REL_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_REL_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_GE_LSB 17
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_GE_MASK 0x00020000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_EQ_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_EQ_MASK 0x00010000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL4_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_EQUAL_TO_VALUE_LSB 15
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_EQUAL_TO_VALUE_MASK 0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_REL_LSB 14
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_REL_MASK 0x00004000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_REL_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_GE_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_GE_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_EQ_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_EQ_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL3_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_EQUAL_TO_VALUE_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_EQUAL_TO_VALUE_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_REL_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_REL_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_REL_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_GE_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_GE_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_EQ_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_EQ_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL2_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_EQUAL_TO_VALUE_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_EQUAL_TO_VALUE_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_REL_LSB 6
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_REL_MASK 0x00000040
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_REL_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_GE_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_GE_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_EQ_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_EQ_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL1_ACQ_EQ_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_EQUAL_TO_VALUE_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_EQUAL_TO_VALUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_EQUAL_TO_VALUE_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_EQUAL_TO_VALUE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_REL_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_REL_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_REL_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_GE_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_GE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_GE_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_GE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_EQ_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_EQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_EQ_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_LOCK_ENABLE_LOCK_SEL0_ACQ_EQ_DEFVAL 0x1

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE       0x00094510
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_MASK  0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_7_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_7_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_7_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_7_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_7_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_7_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_7_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_7_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_7_LSB 29
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_7_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_7_MASK 0x20000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_7_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_7_LSB 28
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_7_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_7_MASK 0x10000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_7_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_6_LSB 27
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_6_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_6_MASK 0x08000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_6_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_6_LSB 26
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_6_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_6_MASK 0x04000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_6_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_6_LSB 25
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_6_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_6_MASK 0x02000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_6_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_6_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_6_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_6_MASK 0x01000000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_6_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_5_LSB 23
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_5_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_5_MASK 0x00800000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_5_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_5_LSB 22
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_5_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_5_MASK 0x00400000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_5_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_5_LSB 21
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_5_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_5_MASK 0x00200000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_5_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_5_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_5_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_5_MASK 0x00100000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_5_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_4_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_4_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_4_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_4_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_4_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_4_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_4_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_4_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_4_LSB 17
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_4_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_4_MASK 0x00020000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_4_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_4_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_4_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_4_MASK 0x00010000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_4_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_3_LSB 15
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_3_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_3_MASK 0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_3_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_3_LSB 14
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_3_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_3_MASK 0x00004000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_3_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_3_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_3_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_3_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_3_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_3_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_3_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_3_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_3_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_2_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_2_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_2_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_2_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_2_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_2_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_2_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_2_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_2_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_2_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_2_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_2_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_2_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_2_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_2_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_2_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_1_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_1_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_1_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_1_LSB 6
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_1_MASK 0x00000040
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_1_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_1_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_1_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_1_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_1_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_1_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_1_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_0_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_0_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_TLAST_0_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_0_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_0_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_STALLED_0_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_0_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_0_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_RUNNING_0_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_0_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_0_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_STREAM_SWITCH_ENABLE_PORT_IDLE_0_DEFVAL 0x1

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE     0x00094514
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_MASK 0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_15_LSB 15
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_15_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_15_MASK 0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_15_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_14_LSB 14
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_14_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_14_MASK 0x00004000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_14_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_13_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_13_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_13_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_13_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_12_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_12_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_12_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_12_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_11_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_11_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_11_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_11_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_10_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_10_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_10_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_10_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_9_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_9_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_9_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_9_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_8_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_8_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_8_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_8_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_7_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_7_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_7_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_7_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_6_LSB 6
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_6_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_6_MASK 0x00000040
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_6_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_5_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_5_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_5_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_5_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_4_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_4_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_4_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_4_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_3_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_3_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_3_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_3_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_2_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_2_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_2_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_2_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_1_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_1_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_1_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_0_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_0_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_MEMORY_CONFLICT_ENABLE_CONFLICT_DM_BANK_0_DEFVAL 0x1

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE               0x00094518
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_WIDTH         32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_MASK          0x00000FFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_TASK_TOKEN_STALL_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_TASK_TOKEN_STALL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_TASK_TOKEN_STALL_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_TASK_TOKEN_STALL_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_LOCK_ERROR_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_LOCK_ERROR_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_LOCK_ERROR_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_LOCK_ERROR_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_AXI_MM_SLAVE_ERROR_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_AXI_MM_SLAVE_ERROR_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_AXI_MM_SLAVE_ERROR_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_AXI_MM_SLAVE_ERROR_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_CONTROL_PKT_ERROR_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_CONTROL_PKT_ERROR_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_CONTROL_PKT_ERROR_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_CONTROL_PKT_ERROR_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_STREAM_PKT_PARITY_ERROR_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_STREAM_PKT_PARITY_ERROR_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_STREAM_PKT_PARITY_ERROR_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_STREAM_PKT_PARITY_ERROR_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_LSB 6
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_MASK 0x00000040
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_STREAM_SWITCH_PORT_PARITY_ERROR_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_MM2S_ERROR_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_MM2S_ERROR_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_MM2S_ERROR_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_MM2S_ERROR_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_S2MM_ERROR_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_S2MM_ERROR_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_S2MM_ERROR_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DMA_S2MM_ERROR_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_2BIT_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_2BIT_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_2BIT_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_2BIT_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_1BIT_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_1BIT_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_1BIT_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_1BIT_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_2BIT_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_2BIT_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_2BIT_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_2BIT_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_CORRECTED_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_CORRECTED_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_CORRECTED_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_ERROR_ENABLE_DM_ECC_ERROR_SCRUB_CORRECTED_DEFVAL 0x1

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE           0x0009451C
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_WIDTH     32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_MASK      0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_15_LSB 15
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_15_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_15_MASK 0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_15_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_14_LSB 14
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_14_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_14_MASK 0x00004000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_14_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_13_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_13_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_13_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_13_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_12_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_12_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_12_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_12_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_11_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_11_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_11_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_11_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_10_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_10_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_10_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_10_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_9_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_9_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_9_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_9_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_8_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_8_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_8_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_8_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_7_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_7_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_7_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_7_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_6_LSB 6
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_6_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_6_MASK 0x00000040
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_6_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_5_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_5_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_5_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_5_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_4_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_4_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_4_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_4_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_3_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_3_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_3_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_3_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_2_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_2_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_2_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_2_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_1_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_1_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_1_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_0_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_0_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_BROADCAST_ENABLE_BROADCAST_A_0_DEFVAL 0x1

#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE          0x00094520
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_WIDTH    32
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_MASK     0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_1_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_1_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_1_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_0_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_0_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_EVENT_GROUP_USER_EVENT_ENABLE_USER_EVENT_0_DEFVAL 0x1

#define XAIEMLGBL_MEM_TILE_MODULE_SPARE_REG                              0x00096000
#define XAIEMLGBL_MEM_TILE_MODULE_SPARE_REG_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_SPARE_REG_MASK                         0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_SPARE_REG_SPARE_REG_LSB              0
#define XAIEMLGBL_MEM_TILE_MODULE_SPARE_REG_SPARE_REG_WIDTH            16
#define XAIEMLGBL_MEM_TILE_MODULE_SPARE_REG_SPARE_REG_MASK             0x0000FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_SPARE_REG_SPARE_REG_DEFVAL           0x0

#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL                           0x00096030
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_MASK                      0x0000000F
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_EAST_LSB   3
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_EAST_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_EAST_MASK  0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_EAST_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_NORTH_LSB  2
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_NORTH_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_NORTH_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_NORTH_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_WEST_LSB   1
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_WEST_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_WEST_MASK  0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_WEST_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_SOUTH_LSB  0
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_SOUTH_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_SOUTH_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_ISOLATE_FROM_SOUTH_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_CSSD_TRIGGER                           0x00096040
#define XAIEMLGBL_MEM_TILE_MODULE_CSSD_TRIGGER_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_CSSD_TRIGGER_MASK                      0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_CSSD_TRIGGER_TRIGGER_LSB             0
#define XAIEMLGBL_MEM_TILE_MODULE_CSSD_TRIGGER_TRIGGER_WIDTH           1
#define XAIEMLGBL_MEM_TILE_MODULE_CSSD_TRIGGER_TRIGGER_MASK            0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_CSSD_TRIGGER_TRIGGER_DEFVAL          0x0

#define XAIEMLGBL_MEM_TILE_MODULE_MEMORY_CONTROL                         0x00096048
#define XAIEMLGBL_MEM_TILE_MODULE_MEMORY_CONTROL_WIDTH                   32
#define XAIEMLGBL_MEM_TILE_MODULE_MEMORY_CONTROL_MASK                    0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_MEMORY_CONTROL_MEMORY_INTERLEAVING_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_MEMORY_CONTROL_MEMORY_INTERLEAVING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_MEMORY_CONTROL_MEMORY_INTERLEAVING_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_MEMORY_CONTROL_MEMORY_INTERLEAVING_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_MEMORY_CONTROL_MEMORY_ZEROISATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_MEMORY_CONTROL_MEMORY_ZEROISATION_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_MEMORY_CONTROL_MEMORY_ZEROISATION_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_MEMORY_CONTROL_MEMORY_ZEROISATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0                              0x000A0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_ENABLE_PACKET_LSB          31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_ENABLE_PACKET_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_ENABLE_PACKET_MASK         0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_ENABLE_PACKET_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_PACKET_TYPE_LSB            28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_PACKET_TYPE_WIDTH          3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_PACKET_TYPE_MASK           0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_PACKET_TYPE_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_PACKET_ID_LSB              23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_PACKET_ID_WIDTH            5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_PACKET_ID_MASK             0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_PACKET_ID_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_OUT_OF_ORDER_BD_ID_LSB     17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_OUT_OF_ORDER_BD_ID_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_OUT_OF_ORDER_BD_ID_MASK    0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_OUT_OF_ORDER_BD_ID_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_BUFFER_LENGTH_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_BUFFER_LENGTH_WIDTH        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_BUFFER_LENGTH_MASK         0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_0_BUFFER_LENGTH_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1                              0x000A0004
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_D0_ZERO_BEFORE_LSB         26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_D0_ZERO_BEFORE_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_D0_ZERO_BEFORE_MASK        0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_D0_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_NEXT_BD_LSB                20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_NEXT_BD_WIDTH              6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_NEXT_BD_MASK               0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_USE_NEXT_BD_LSB            19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_USE_NEXT_BD_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_USE_NEXT_BD_MASK           0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_USE_NEXT_BD_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_BASE_ADDRESS_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_BASE_ADDRESS_WIDTH         19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_BASE_ADDRESS_MASK          0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_1_BASE_ADDRESS_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2                              0x000A0008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_MASK                         0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_TLAST_SUPPRESS_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_TLAST_SUPPRESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_TLAST_SUPPRESS_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_TLAST_SUPPRESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_D0_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_D0_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_D0_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_D0_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_D0_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_D0_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_D0_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_2_D0_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3                              0x000A000C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_D1_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_D1_ZERO_BEFORE_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_D1_ZERO_BEFORE_MASK        0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_D1_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_D1_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_D1_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_D1_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_D1_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_D1_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_D1_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_D1_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_3_D1_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4                              0x000A0010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_ENABLE_COMPRESSION_LSB     31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_ENABLE_COMPRESSION_WIDTH   1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_ENABLE_COMPRESSION_MASK    0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_ENABLE_COMPRESSION_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_D2_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_D2_ZERO_BEFORE_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_D2_ZERO_BEFORE_MASK        0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_D2_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_D2_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_D2_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_D2_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_D2_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_D2_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_D2_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_D2_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_4_D2_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5                              0x000A0014
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D2_ZERO_AFTER_LSB          28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D2_ZERO_AFTER_WIDTH        4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D2_ZERO_AFTER_MASK         0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D2_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D1_ZERO_AFTER_LSB          23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D1_ZERO_AFTER_WIDTH        5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D1_ZERO_AFTER_MASK         0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D1_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D0_ZERO_AFTER_LSB          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D0_ZERO_AFTER_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D0_ZERO_AFTER_MASK         0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D0_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D3_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D3_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D3_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_5_D3_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6                              0x000A0018
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_MASK                         0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_ITERATION_CURRENT_LSB      23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_ITERATION_CURRENT_WIDTH    6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_ITERATION_CURRENT_MASK     0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_ITERATION_CURRENT_DEFVAL   0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_ITERATION_WRAP_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_ITERATION_WRAP_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_ITERATION_WRAP_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_ITERATION_WRAP_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_ITERATION_STEPSIZE_LSB     0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_ITERATION_STEPSIZE_WIDTH   17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_ITERATION_STEPSIZE_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_6_ITERATION_STEPSIZE_DEFVAL  0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7                              0x000A001C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_VALID_BD_LSB               31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_VALID_BD_WIDTH             1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_VALID_BD_MASK              0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_VALID_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_REL_VALUE_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_REL_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_REL_VALUE_MASK        0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_REL_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_REL_ID_LSB            16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_REL_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_REL_ID_MASK           0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_REL_ID_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_ACQ_ENABLE_LSB        15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_ACQ_ENABLE_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_ACQ_ENABLE_MASK       0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_ACQ_ENABLE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_ACQ_VALUE_LSB         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_ACQ_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_ACQ_VALUE_MASK        0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_ACQ_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_ACQ_ID_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_ACQ_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_ACQ_ID_MASK           0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD0_7_LOCK_ACQ_ID_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0                              0x000A0020
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_ENABLE_PACKET_LSB          31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_ENABLE_PACKET_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_ENABLE_PACKET_MASK         0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_ENABLE_PACKET_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_PACKET_TYPE_LSB            28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_PACKET_TYPE_WIDTH          3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_PACKET_TYPE_MASK           0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_PACKET_TYPE_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_PACKET_ID_LSB              23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_PACKET_ID_WIDTH            5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_PACKET_ID_MASK             0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_PACKET_ID_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_OUT_OF_ORDER_BD_ID_LSB     17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_OUT_OF_ORDER_BD_ID_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_OUT_OF_ORDER_BD_ID_MASK    0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_OUT_OF_ORDER_BD_ID_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_BUFFER_LENGTH_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_BUFFER_LENGTH_WIDTH        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_BUFFER_LENGTH_MASK         0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_0_BUFFER_LENGTH_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1                              0x000A0024
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_D0_ZERO_BEFORE_LSB         26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_D0_ZERO_BEFORE_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_D0_ZERO_BEFORE_MASK        0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_D0_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_NEXT_BD_LSB                20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_NEXT_BD_WIDTH              6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_NEXT_BD_MASK               0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_USE_NEXT_BD_LSB            19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_USE_NEXT_BD_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_USE_NEXT_BD_MASK           0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_USE_NEXT_BD_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_BASE_ADDRESS_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_BASE_ADDRESS_WIDTH         19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_BASE_ADDRESS_MASK          0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_1_BASE_ADDRESS_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2                              0x000A0028
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_MASK                         0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_TLAST_SUPPRESS_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_TLAST_SUPPRESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_TLAST_SUPPRESS_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_TLAST_SUPPRESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_D0_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_D0_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_D0_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_D0_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_D0_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_D0_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_D0_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_2_D0_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3                              0x000A002C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_D1_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_D1_ZERO_BEFORE_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_D1_ZERO_BEFORE_MASK        0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_D1_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_D1_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_D1_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_D1_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_D1_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_D1_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_D1_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_D1_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_3_D1_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4                              0x000A0030
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_ENABLE_COMPRESSION_LSB     31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_ENABLE_COMPRESSION_WIDTH   1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_ENABLE_COMPRESSION_MASK    0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_ENABLE_COMPRESSION_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_D2_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_D2_ZERO_BEFORE_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_D2_ZERO_BEFORE_MASK        0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_D2_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_D2_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_D2_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_D2_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_D2_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_D2_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_D2_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_D2_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_4_D2_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5                              0x000A0034
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D2_ZERO_AFTER_LSB          28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D2_ZERO_AFTER_WIDTH        4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D2_ZERO_AFTER_MASK         0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D2_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D1_ZERO_AFTER_LSB          23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D1_ZERO_AFTER_WIDTH        5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D1_ZERO_AFTER_MASK         0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D1_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D0_ZERO_AFTER_LSB          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D0_ZERO_AFTER_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D0_ZERO_AFTER_MASK         0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D0_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D3_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D3_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D3_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_5_D3_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6                              0x000A0038
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_MASK                         0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_ITERATION_CURRENT_LSB      23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_ITERATION_CURRENT_WIDTH    6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_ITERATION_CURRENT_MASK     0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_ITERATION_CURRENT_DEFVAL   0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_ITERATION_WRAP_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_ITERATION_WRAP_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_ITERATION_WRAP_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_ITERATION_WRAP_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_ITERATION_STEPSIZE_LSB     0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_ITERATION_STEPSIZE_WIDTH   17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_ITERATION_STEPSIZE_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_6_ITERATION_STEPSIZE_DEFVAL  0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7                              0x000A003C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_VALID_BD_LSB               31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_VALID_BD_WIDTH             1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_VALID_BD_MASK              0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_VALID_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_REL_VALUE_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_REL_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_REL_VALUE_MASK        0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_REL_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_REL_ID_LSB            16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_REL_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_REL_ID_MASK           0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_REL_ID_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_ACQ_ENABLE_LSB        15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_ACQ_ENABLE_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_ACQ_ENABLE_MASK       0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_ACQ_ENABLE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_ACQ_VALUE_LSB         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_ACQ_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_ACQ_VALUE_MASK        0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_ACQ_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_ACQ_ID_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_ACQ_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_ACQ_ID_MASK           0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD1_7_LOCK_ACQ_ID_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0                              0x000A0040
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_ENABLE_PACKET_LSB          31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_ENABLE_PACKET_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_ENABLE_PACKET_MASK         0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_ENABLE_PACKET_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_PACKET_TYPE_LSB            28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_PACKET_TYPE_WIDTH          3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_PACKET_TYPE_MASK           0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_PACKET_TYPE_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_PACKET_ID_LSB              23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_PACKET_ID_WIDTH            5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_PACKET_ID_MASK             0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_PACKET_ID_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_OUT_OF_ORDER_BD_ID_LSB     17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_OUT_OF_ORDER_BD_ID_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_OUT_OF_ORDER_BD_ID_MASK    0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_OUT_OF_ORDER_BD_ID_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_BUFFER_LENGTH_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_BUFFER_LENGTH_WIDTH        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_BUFFER_LENGTH_MASK         0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_0_BUFFER_LENGTH_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1                              0x000A0044
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_D0_ZERO_BEFORE_LSB         26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_D0_ZERO_BEFORE_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_D0_ZERO_BEFORE_MASK        0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_D0_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_NEXT_BD_LSB                20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_NEXT_BD_WIDTH              6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_NEXT_BD_MASK               0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_USE_NEXT_BD_LSB            19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_USE_NEXT_BD_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_USE_NEXT_BD_MASK           0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_USE_NEXT_BD_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_BASE_ADDRESS_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_BASE_ADDRESS_WIDTH         19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_BASE_ADDRESS_MASK          0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_1_BASE_ADDRESS_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2                              0x000A0048
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_MASK                         0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_TLAST_SUPPRESS_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_TLAST_SUPPRESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_TLAST_SUPPRESS_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_TLAST_SUPPRESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_D0_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_D0_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_D0_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_D0_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_D0_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_D0_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_D0_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_2_D0_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3                              0x000A004C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_D1_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_D1_ZERO_BEFORE_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_D1_ZERO_BEFORE_MASK        0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_D1_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_D1_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_D1_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_D1_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_D1_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_D1_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_D1_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_D1_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_3_D1_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4                              0x000A0050
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_ENABLE_COMPRESSION_LSB     31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_ENABLE_COMPRESSION_WIDTH   1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_ENABLE_COMPRESSION_MASK    0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_ENABLE_COMPRESSION_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_D2_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_D2_ZERO_BEFORE_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_D2_ZERO_BEFORE_MASK        0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_D2_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_D2_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_D2_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_D2_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_D2_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_D2_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_D2_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_D2_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_4_D2_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5                              0x000A0054
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D2_ZERO_AFTER_LSB          28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D2_ZERO_AFTER_WIDTH        4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D2_ZERO_AFTER_MASK         0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D2_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D1_ZERO_AFTER_LSB          23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D1_ZERO_AFTER_WIDTH        5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D1_ZERO_AFTER_MASK         0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D1_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D0_ZERO_AFTER_LSB          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D0_ZERO_AFTER_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D0_ZERO_AFTER_MASK         0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D0_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D3_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D3_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D3_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_5_D3_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6                              0x000A0058
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_MASK                         0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_ITERATION_CURRENT_LSB      23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_ITERATION_CURRENT_WIDTH    6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_ITERATION_CURRENT_MASK     0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_ITERATION_CURRENT_DEFVAL   0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_ITERATION_WRAP_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_ITERATION_WRAP_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_ITERATION_WRAP_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_ITERATION_WRAP_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_ITERATION_STEPSIZE_LSB     0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_ITERATION_STEPSIZE_WIDTH   17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_ITERATION_STEPSIZE_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_6_ITERATION_STEPSIZE_DEFVAL  0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7                              0x000A005C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_VALID_BD_LSB               31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_VALID_BD_WIDTH             1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_VALID_BD_MASK              0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_VALID_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_REL_VALUE_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_REL_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_REL_VALUE_MASK        0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_REL_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_REL_ID_LSB            16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_REL_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_REL_ID_MASK           0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_REL_ID_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_ACQ_ENABLE_LSB        15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_ACQ_ENABLE_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_ACQ_ENABLE_MASK       0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_ACQ_ENABLE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_ACQ_VALUE_LSB         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_ACQ_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_ACQ_VALUE_MASK        0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_ACQ_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_ACQ_ID_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_ACQ_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_ACQ_ID_MASK           0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD2_7_LOCK_ACQ_ID_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0                              0x000A0060
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_ENABLE_PACKET_LSB          31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_ENABLE_PACKET_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_ENABLE_PACKET_MASK         0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_ENABLE_PACKET_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_PACKET_TYPE_LSB            28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_PACKET_TYPE_WIDTH          3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_PACKET_TYPE_MASK           0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_PACKET_TYPE_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_PACKET_ID_LSB              23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_PACKET_ID_WIDTH            5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_PACKET_ID_MASK             0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_PACKET_ID_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_OUT_OF_ORDER_BD_ID_LSB     17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_OUT_OF_ORDER_BD_ID_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_OUT_OF_ORDER_BD_ID_MASK    0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_OUT_OF_ORDER_BD_ID_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_BUFFER_LENGTH_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_BUFFER_LENGTH_WIDTH        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_BUFFER_LENGTH_MASK         0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_0_BUFFER_LENGTH_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1                              0x000A0064
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_D0_ZERO_BEFORE_LSB         26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_D0_ZERO_BEFORE_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_D0_ZERO_BEFORE_MASK        0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_D0_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_NEXT_BD_LSB                20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_NEXT_BD_WIDTH              6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_NEXT_BD_MASK               0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_USE_NEXT_BD_LSB            19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_USE_NEXT_BD_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_USE_NEXT_BD_MASK           0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_USE_NEXT_BD_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_BASE_ADDRESS_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_BASE_ADDRESS_WIDTH         19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_BASE_ADDRESS_MASK          0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_1_BASE_ADDRESS_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2                              0x000A0068
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_MASK                         0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_TLAST_SUPPRESS_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_TLAST_SUPPRESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_TLAST_SUPPRESS_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_TLAST_SUPPRESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_D0_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_D0_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_D0_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_D0_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_D0_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_D0_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_D0_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_2_D0_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3                              0x000A006C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_D1_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_D1_ZERO_BEFORE_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_D1_ZERO_BEFORE_MASK        0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_D1_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_D1_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_D1_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_D1_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_D1_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_D1_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_D1_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_D1_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_3_D1_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4                              0x000A0070
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_ENABLE_COMPRESSION_LSB     31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_ENABLE_COMPRESSION_WIDTH   1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_ENABLE_COMPRESSION_MASK    0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_ENABLE_COMPRESSION_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_D2_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_D2_ZERO_BEFORE_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_D2_ZERO_BEFORE_MASK        0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_D2_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_D2_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_D2_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_D2_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_D2_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_D2_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_D2_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_D2_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_4_D2_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5                              0x000A0074
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D2_ZERO_AFTER_LSB          28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D2_ZERO_AFTER_WIDTH        4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D2_ZERO_AFTER_MASK         0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D2_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D1_ZERO_AFTER_LSB          23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D1_ZERO_AFTER_WIDTH        5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D1_ZERO_AFTER_MASK         0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D1_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D0_ZERO_AFTER_LSB          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D0_ZERO_AFTER_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D0_ZERO_AFTER_MASK         0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D0_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D3_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D3_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D3_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_5_D3_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6                              0x000A0078
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_MASK                         0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_ITERATION_CURRENT_LSB      23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_ITERATION_CURRENT_WIDTH    6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_ITERATION_CURRENT_MASK     0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_ITERATION_CURRENT_DEFVAL   0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_ITERATION_WRAP_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_ITERATION_WRAP_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_ITERATION_WRAP_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_ITERATION_WRAP_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_ITERATION_STEPSIZE_LSB     0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_ITERATION_STEPSIZE_WIDTH   17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_ITERATION_STEPSIZE_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_6_ITERATION_STEPSIZE_DEFVAL  0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7                              0x000A007C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_VALID_BD_LSB               31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_VALID_BD_WIDTH             1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_VALID_BD_MASK              0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_VALID_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_REL_VALUE_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_REL_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_REL_VALUE_MASK        0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_REL_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_REL_ID_LSB            16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_REL_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_REL_ID_MASK           0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_REL_ID_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_ACQ_ENABLE_LSB        15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_ACQ_ENABLE_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_ACQ_ENABLE_MASK       0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_ACQ_ENABLE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_ACQ_VALUE_LSB         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_ACQ_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_ACQ_VALUE_MASK        0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_ACQ_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_ACQ_ID_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_ACQ_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_ACQ_ID_MASK           0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD3_7_LOCK_ACQ_ID_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0                              0x000A0080
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_ENABLE_PACKET_LSB          31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_ENABLE_PACKET_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_ENABLE_PACKET_MASK         0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_ENABLE_PACKET_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_PACKET_TYPE_LSB            28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_PACKET_TYPE_WIDTH          3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_PACKET_TYPE_MASK           0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_PACKET_TYPE_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_PACKET_ID_LSB              23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_PACKET_ID_WIDTH            5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_PACKET_ID_MASK             0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_PACKET_ID_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_OUT_OF_ORDER_BD_ID_LSB     17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_OUT_OF_ORDER_BD_ID_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_OUT_OF_ORDER_BD_ID_MASK    0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_OUT_OF_ORDER_BD_ID_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_BUFFER_LENGTH_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_BUFFER_LENGTH_WIDTH        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_BUFFER_LENGTH_MASK         0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_0_BUFFER_LENGTH_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1                              0x000A0084
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_D0_ZERO_BEFORE_LSB         26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_D0_ZERO_BEFORE_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_D0_ZERO_BEFORE_MASK        0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_D0_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_NEXT_BD_LSB                20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_NEXT_BD_WIDTH              6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_NEXT_BD_MASK               0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_USE_NEXT_BD_LSB            19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_USE_NEXT_BD_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_USE_NEXT_BD_MASK           0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_USE_NEXT_BD_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_BASE_ADDRESS_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_BASE_ADDRESS_WIDTH         19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_BASE_ADDRESS_MASK          0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_1_BASE_ADDRESS_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2                              0x000A0088
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_MASK                         0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_TLAST_SUPPRESS_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_TLAST_SUPPRESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_TLAST_SUPPRESS_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_TLAST_SUPPRESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_D0_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_D0_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_D0_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_D0_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_D0_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_D0_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_D0_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_2_D0_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3                              0x000A008C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_D1_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_D1_ZERO_BEFORE_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_D1_ZERO_BEFORE_MASK        0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_D1_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_D1_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_D1_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_D1_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_D1_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_D1_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_D1_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_D1_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_3_D1_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4                              0x000A0090
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_ENABLE_COMPRESSION_LSB     31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_ENABLE_COMPRESSION_WIDTH   1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_ENABLE_COMPRESSION_MASK    0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_ENABLE_COMPRESSION_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_D2_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_D2_ZERO_BEFORE_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_D2_ZERO_BEFORE_MASK        0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_D2_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_D2_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_D2_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_D2_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_D2_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_D2_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_D2_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_D2_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_4_D2_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5                              0x000A0094
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D2_ZERO_AFTER_LSB          28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D2_ZERO_AFTER_WIDTH        4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D2_ZERO_AFTER_MASK         0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D2_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D1_ZERO_AFTER_LSB          23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D1_ZERO_AFTER_WIDTH        5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D1_ZERO_AFTER_MASK         0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D1_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D0_ZERO_AFTER_LSB          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D0_ZERO_AFTER_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D0_ZERO_AFTER_MASK         0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D0_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D3_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D3_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D3_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_5_D3_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6                              0x000A0098
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_MASK                         0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_ITERATION_CURRENT_LSB      23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_ITERATION_CURRENT_WIDTH    6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_ITERATION_CURRENT_MASK     0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_ITERATION_CURRENT_DEFVAL   0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_ITERATION_WRAP_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_ITERATION_WRAP_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_ITERATION_WRAP_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_ITERATION_WRAP_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_ITERATION_STEPSIZE_LSB     0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_ITERATION_STEPSIZE_WIDTH   17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_ITERATION_STEPSIZE_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_6_ITERATION_STEPSIZE_DEFVAL  0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7                              0x000A009C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_VALID_BD_LSB               31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_VALID_BD_WIDTH             1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_VALID_BD_MASK              0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_VALID_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_REL_VALUE_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_REL_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_REL_VALUE_MASK        0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_REL_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_REL_ID_LSB            16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_REL_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_REL_ID_MASK           0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_REL_ID_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_ACQ_ENABLE_LSB        15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_ACQ_ENABLE_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_ACQ_ENABLE_MASK       0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_ACQ_ENABLE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_ACQ_VALUE_LSB         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_ACQ_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_ACQ_VALUE_MASK        0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_ACQ_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_ACQ_ID_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_ACQ_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_ACQ_ID_MASK           0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD4_7_LOCK_ACQ_ID_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0                              0x000A00A0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_ENABLE_PACKET_LSB          31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_ENABLE_PACKET_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_ENABLE_PACKET_MASK         0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_ENABLE_PACKET_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_PACKET_TYPE_LSB            28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_PACKET_TYPE_WIDTH          3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_PACKET_TYPE_MASK           0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_PACKET_TYPE_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_PACKET_ID_LSB              23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_PACKET_ID_WIDTH            5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_PACKET_ID_MASK             0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_PACKET_ID_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_OUT_OF_ORDER_BD_ID_LSB     17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_OUT_OF_ORDER_BD_ID_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_OUT_OF_ORDER_BD_ID_MASK    0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_OUT_OF_ORDER_BD_ID_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_BUFFER_LENGTH_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_BUFFER_LENGTH_WIDTH        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_BUFFER_LENGTH_MASK         0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_0_BUFFER_LENGTH_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1                              0x000A00A4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_D0_ZERO_BEFORE_LSB         26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_D0_ZERO_BEFORE_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_D0_ZERO_BEFORE_MASK        0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_D0_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_NEXT_BD_LSB                20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_NEXT_BD_WIDTH              6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_NEXT_BD_MASK               0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_USE_NEXT_BD_LSB            19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_USE_NEXT_BD_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_USE_NEXT_BD_MASK           0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_USE_NEXT_BD_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_BASE_ADDRESS_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_BASE_ADDRESS_WIDTH         19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_BASE_ADDRESS_MASK          0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_1_BASE_ADDRESS_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2                              0x000A00A8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_MASK                         0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_TLAST_SUPPRESS_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_TLAST_SUPPRESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_TLAST_SUPPRESS_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_TLAST_SUPPRESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_D0_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_D0_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_D0_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_D0_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_D0_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_D0_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_D0_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_2_D0_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3                              0x000A00AC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_D1_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_D1_ZERO_BEFORE_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_D1_ZERO_BEFORE_MASK        0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_D1_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_D1_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_D1_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_D1_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_D1_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_D1_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_D1_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_D1_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_3_D1_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4                              0x000A00B0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_ENABLE_COMPRESSION_LSB     31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_ENABLE_COMPRESSION_WIDTH   1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_ENABLE_COMPRESSION_MASK    0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_ENABLE_COMPRESSION_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_D2_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_D2_ZERO_BEFORE_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_D2_ZERO_BEFORE_MASK        0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_D2_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_D2_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_D2_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_D2_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_D2_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_D2_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_D2_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_D2_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_4_D2_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5                              0x000A00B4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D2_ZERO_AFTER_LSB          28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D2_ZERO_AFTER_WIDTH        4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D2_ZERO_AFTER_MASK         0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D2_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D1_ZERO_AFTER_LSB          23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D1_ZERO_AFTER_WIDTH        5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D1_ZERO_AFTER_MASK         0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D1_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D0_ZERO_AFTER_LSB          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D0_ZERO_AFTER_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D0_ZERO_AFTER_MASK         0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D0_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D3_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D3_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D3_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_5_D3_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6                              0x000A00B8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_MASK                         0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_ITERATION_CURRENT_LSB      23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_ITERATION_CURRENT_WIDTH    6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_ITERATION_CURRENT_MASK     0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_ITERATION_CURRENT_DEFVAL   0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_ITERATION_WRAP_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_ITERATION_WRAP_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_ITERATION_WRAP_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_ITERATION_WRAP_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_ITERATION_STEPSIZE_LSB     0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_ITERATION_STEPSIZE_WIDTH   17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_ITERATION_STEPSIZE_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_6_ITERATION_STEPSIZE_DEFVAL  0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7                              0x000A00BC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_VALID_BD_LSB               31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_VALID_BD_WIDTH             1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_VALID_BD_MASK              0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_VALID_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_REL_VALUE_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_REL_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_REL_VALUE_MASK        0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_REL_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_REL_ID_LSB            16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_REL_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_REL_ID_MASK           0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_REL_ID_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_ACQ_ENABLE_LSB        15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_ACQ_ENABLE_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_ACQ_ENABLE_MASK       0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_ACQ_ENABLE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_ACQ_VALUE_LSB         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_ACQ_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_ACQ_VALUE_MASK        0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_ACQ_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_ACQ_ID_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_ACQ_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_ACQ_ID_MASK           0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD5_7_LOCK_ACQ_ID_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0                              0x000A00C0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_ENABLE_PACKET_LSB          31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_ENABLE_PACKET_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_ENABLE_PACKET_MASK         0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_ENABLE_PACKET_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_PACKET_TYPE_LSB            28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_PACKET_TYPE_WIDTH          3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_PACKET_TYPE_MASK           0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_PACKET_TYPE_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_PACKET_ID_LSB              23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_PACKET_ID_WIDTH            5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_PACKET_ID_MASK             0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_PACKET_ID_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_OUT_OF_ORDER_BD_ID_LSB     17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_OUT_OF_ORDER_BD_ID_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_OUT_OF_ORDER_BD_ID_MASK    0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_OUT_OF_ORDER_BD_ID_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_BUFFER_LENGTH_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_BUFFER_LENGTH_WIDTH        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_BUFFER_LENGTH_MASK         0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_0_BUFFER_LENGTH_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1                              0x000A00C4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_D0_ZERO_BEFORE_LSB         26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_D0_ZERO_BEFORE_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_D0_ZERO_BEFORE_MASK        0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_D0_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_NEXT_BD_LSB                20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_NEXT_BD_WIDTH              6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_NEXT_BD_MASK               0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_USE_NEXT_BD_LSB            19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_USE_NEXT_BD_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_USE_NEXT_BD_MASK           0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_USE_NEXT_BD_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_BASE_ADDRESS_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_BASE_ADDRESS_WIDTH         19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_BASE_ADDRESS_MASK          0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_1_BASE_ADDRESS_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2                              0x000A00C8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_MASK                         0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_TLAST_SUPPRESS_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_TLAST_SUPPRESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_TLAST_SUPPRESS_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_TLAST_SUPPRESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_D0_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_D0_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_D0_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_D0_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_D0_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_D0_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_D0_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_2_D0_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3                              0x000A00CC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_D1_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_D1_ZERO_BEFORE_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_D1_ZERO_BEFORE_MASK        0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_D1_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_D1_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_D1_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_D1_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_D1_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_D1_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_D1_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_D1_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_3_D1_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4                              0x000A00D0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_ENABLE_COMPRESSION_LSB     31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_ENABLE_COMPRESSION_WIDTH   1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_ENABLE_COMPRESSION_MASK    0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_ENABLE_COMPRESSION_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_D2_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_D2_ZERO_BEFORE_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_D2_ZERO_BEFORE_MASK        0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_D2_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_D2_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_D2_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_D2_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_D2_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_D2_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_D2_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_D2_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_4_D2_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5                              0x000A00D4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D2_ZERO_AFTER_LSB          28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D2_ZERO_AFTER_WIDTH        4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D2_ZERO_AFTER_MASK         0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D2_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D1_ZERO_AFTER_LSB          23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D1_ZERO_AFTER_WIDTH        5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D1_ZERO_AFTER_MASK         0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D1_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D0_ZERO_AFTER_LSB          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D0_ZERO_AFTER_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D0_ZERO_AFTER_MASK         0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D0_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D3_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D3_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D3_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_5_D3_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6                              0x000A00D8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_MASK                         0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_ITERATION_CURRENT_LSB      23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_ITERATION_CURRENT_WIDTH    6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_ITERATION_CURRENT_MASK     0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_ITERATION_CURRENT_DEFVAL   0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_ITERATION_WRAP_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_ITERATION_WRAP_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_ITERATION_WRAP_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_ITERATION_WRAP_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_ITERATION_STEPSIZE_LSB     0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_ITERATION_STEPSIZE_WIDTH   17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_ITERATION_STEPSIZE_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_6_ITERATION_STEPSIZE_DEFVAL  0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7                              0x000A00DC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_VALID_BD_LSB               31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_VALID_BD_WIDTH             1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_VALID_BD_MASK              0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_VALID_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_REL_VALUE_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_REL_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_REL_VALUE_MASK        0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_REL_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_REL_ID_LSB            16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_REL_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_REL_ID_MASK           0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_REL_ID_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_ACQ_ENABLE_LSB        15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_ACQ_ENABLE_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_ACQ_ENABLE_MASK       0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_ACQ_ENABLE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_ACQ_VALUE_LSB         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_ACQ_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_ACQ_VALUE_MASK        0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_ACQ_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_ACQ_ID_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_ACQ_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_ACQ_ID_MASK           0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD6_7_LOCK_ACQ_ID_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0                              0x000A00E0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_ENABLE_PACKET_LSB          31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_ENABLE_PACKET_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_ENABLE_PACKET_MASK         0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_ENABLE_PACKET_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_PACKET_TYPE_LSB            28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_PACKET_TYPE_WIDTH          3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_PACKET_TYPE_MASK           0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_PACKET_TYPE_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_PACKET_ID_LSB              23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_PACKET_ID_WIDTH            5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_PACKET_ID_MASK             0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_PACKET_ID_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_OUT_OF_ORDER_BD_ID_LSB     17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_OUT_OF_ORDER_BD_ID_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_OUT_OF_ORDER_BD_ID_MASK    0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_OUT_OF_ORDER_BD_ID_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_BUFFER_LENGTH_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_BUFFER_LENGTH_WIDTH        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_BUFFER_LENGTH_MASK         0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_0_BUFFER_LENGTH_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1                              0x000A00E4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_D0_ZERO_BEFORE_LSB         26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_D0_ZERO_BEFORE_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_D0_ZERO_BEFORE_MASK        0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_D0_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_NEXT_BD_LSB                20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_NEXT_BD_WIDTH              6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_NEXT_BD_MASK               0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_USE_NEXT_BD_LSB            19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_USE_NEXT_BD_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_USE_NEXT_BD_MASK           0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_USE_NEXT_BD_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_BASE_ADDRESS_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_BASE_ADDRESS_WIDTH         19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_BASE_ADDRESS_MASK          0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_1_BASE_ADDRESS_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2                              0x000A00E8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_MASK                         0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_TLAST_SUPPRESS_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_TLAST_SUPPRESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_TLAST_SUPPRESS_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_TLAST_SUPPRESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_D0_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_D0_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_D0_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_D0_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_D0_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_D0_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_D0_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_2_D0_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3                              0x000A00EC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_D1_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_D1_ZERO_BEFORE_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_D1_ZERO_BEFORE_MASK        0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_D1_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_D1_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_D1_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_D1_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_D1_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_D1_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_D1_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_D1_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_3_D1_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4                              0x000A00F0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_ENABLE_COMPRESSION_LSB     31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_ENABLE_COMPRESSION_WIDTH   1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_ENABLE_COMPRESSION_MASK    0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_ENABLE_COMPRESSION_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_D2_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_D2_ZERO_BEFORE_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_D2_ZERO_BEFORE_MASK        0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_D2_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_D2_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_D2_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_D2_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_D2_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_D2_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_D2_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_D2_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_4_D2_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5                              0x000A00F4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D2_ZERO_AFTER_LSB          28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D2_ZERO_AFTER_WIDTH        4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D2_ZERO_AFTER_MASK         0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D2_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D1_ZERO_AFTER_LSB          23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D1_ZERO_AFTER_WIDTH        5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D1_ZERO_AFTER_MASK         0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D1_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D0_ZERO_AFTER_LSB          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D0_ZERO_AFTER_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D0_ZERO_AFTER_MASK         0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D0_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D3_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D3_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D3_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_5_D3_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6                              0x000A00F8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_MASK                         0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_ITERATION_CURRENT_LSB      23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_ITERATION_CURRENT_WIDTH    6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_ITERATION_CURRENT_MASK     0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_ITERATION_CURRENT_DEFVAL   0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_ITERATION_WRAP_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_ITERATION_WRAP_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_ITERATION_WRAP_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_ITERATION_WRAP_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_ITERATION_STEPSIZE_LSB     0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_ITERATION_STEPSIZE_WIDTH   17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_ITERATION_STEPSIZE_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_6_ITERATION_STEPSIZE_DEFVAL  0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7                              0x000A00FC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_VALID_BD_LSB               31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_VALID_BD_WIDTH             1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_VALID_BD_MASK              0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_VALID_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_REL_VALUE_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_REL_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_REL_VALUE_MASK        0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_REL_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_REL_ID_LSB            16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_REL_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_REL_ID_MASK           0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_REL_ID_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_ACQ_ENABLE_LSB        15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_ACQ_ENABLE_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_ACQ_ENABLE_MASK       0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_ACQ_ENABLE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_ACQ_VALUE_LSB         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_ACQ_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_ACQ_VALUE_MASK        0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_ACQ_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_ACQ_ID_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_ACQ_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_ACQ_ID_MASK           0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD7_7_LOCK_ACQ_ID_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0                              0x000A0100
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_ENABLE_PACKET_LSB          31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_ENABLE_PACKET_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_ENABLE_PACKET_MASK         0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_ENABLE_PACKET_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_PACKET_TYPE_LSB            28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_PACKET_TYPE_WIDTH          3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_PACKET_TYPE_MASK           0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_PACKET_TYPE_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_PACKET_ID_LSB              23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_PACKET_ID_WIDTH            5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_PACKET_ID_MASK             0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_PACKET_ID_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_OUT_OF_ORDER_BD_ID_LSB     17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_OUT_OF_ORDER_BD_ID_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_OUT_OF_ORDER_BD_ID_MASK    0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_OUT_OF_ORDER_BD_ID_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_BUFFER_LENGTH_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_BUFFER_LENGTH_WIDTH        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_BUFFER_LENGTH_MASK         0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_0_BUFFER_LENGTH_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1                              0x000A0104
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_D0_ZERO_BEFORE_LSB         26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_D0_ZERO_BEFORE_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_D0_ZERO_BEFORE_MASK        0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_D0_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_NEXT_BD_LSB                20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_NEXT_BD_WIDTH              6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_NEXT_BD_MASK               0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_USE_NEXT_BD_LSB            19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_USE_NEXT_BD_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_USE_NEXT_BD_MASK           0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_USE_NEXT_BD_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_BASE_ADDRESS_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_BASE_ADDRESS_WIDTH         19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_BASE_ADDRESS_MASK          0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_1_BASE_ADDRESS_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2                              0x000A0108
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_MASK                         0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_TLAST_SUPPRESS_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_TLAST_SUPPRESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_TLAST_SUPPRESS_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_TLAST_SUPPRESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_D0_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_D0_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_D0_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_D0_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_D0_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_D0_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_D0_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_2_D0_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3                              0x000A010C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_D1_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_D1_ZERO_BEFORE_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_D1_ZERO_BEFORE_MASK        0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_D1_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_D1_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_D1_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_D1_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_D1_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_D1_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_D1_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_D1_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_3_D1_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4                              0x000A0110
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_ENABLE_COMPRESSION_LSB     31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_ENABLE_COMPRESSION_WIDTH   1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_ENABLE_COMPRESSION_MASK    0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_ENABLE_COMPRESSION_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_D2_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_D2_ZERO_BEFORE_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_D2_ZERO_BEFORE_MASK        0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_D2_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_D2_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_D2_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_D2_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_D2_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_D2_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_D2_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_D2_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_4_D2_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5                              0x000A0114
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D2_ZERO_AFTER_LSB          28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D2_ZERO_AFTER_WIDTH        4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D2_ZERO_AFTER_MASK         0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D2_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D1_ZERO_AFTER_LSB          23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D1_ZERO_AFTER_WIDTH        5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D1_ZERO_AFTER_MASK         0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D1_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D0_ZERO_AFTER_LSB          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D0_ZERO_AFTER_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D0_ZERO_AFTER_MASK         0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D0_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D3_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D3_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D3_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_5_D3_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6                              0x000A0118
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_MASK                         0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_ITERATION_CURRENT_LSB      23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_ITERATION_CURRENT_WIDTH    6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_ITERATION_CURRENT_MASK     0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_ITERATION_CURRENT_DEFVAL   0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_ITERATION_WRAP_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_ITERATION_WRAP_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_ITERATION_WRAP_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_ITERATION_WRAP_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_ITERATION_STEPSIZE_LSB     0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_ITERATION_STEPSIZE_WIDTH   17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_ITERATION_STEPSIZE_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_6_ITERATION_STEPSIZE_DEFVAL  0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7                              0x000A011C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_VALID_BD_LSB               31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_VALID_BD_WIDTH             1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_VALID_BD_MASK              0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_VALID_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_REL_VALUE_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_REL_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_REL_VALUE_MASK        0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_REL_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_REL_ID_LSB            16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_REL_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_REL_ID_MASK           0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_REL_ID_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_ACQ_ENABLE_LSB        15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_ACQ_ENABLE_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_ACQ_ENABLE_MASK       0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_ACQ_ENABLE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_ACQ_VALUE_LSB         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_ACQ_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_ACQ_VALUE_MASK        0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_ACQ_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_ACQ_ID_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_ACQ_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_ACQ_ID_MASK           0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD8_7_LOCK_ACQ_ID_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0                              0x000A0120
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_ENABLE_PACKET_LSB          31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_ENABLE_PACKET_WIDTH        1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_ENABLE_PACKET_MASK         0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_ENABLE_PACKET_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_PACKET_TYPE_LSB            28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_PACKET_TYPE_WIDTH          3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_PACKET_TYPE_MASK           0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_PACKET_TYPE_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_PACKET_ID_LSB              23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_PACKET_ID_WIDTH            5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_PACKET_ID_MASK             0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_PACKET_ID_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_OUT_OF_ORDER_BD_ID_LSB     17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_OUT_OF_ORDER_BD_ID_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_OUT_OF_ORDER_BD_ID_MASK    0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_OUT_OF_ORDER_BD_ID_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_BUFFER_LENGTH_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_BUFFER_LENGTH_WIDTH        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_BUFFER_LENGTH_MASK         0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_0_BUFFER_LENGTH_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1                              0x000A0124
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_D0_ZERO_BEFORE_LSB         26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_D0_ZERO_BEFORE_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_D0_ZERO_BEFORE_MASK        0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_D0_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_NEXT_BD_LSB                20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_NEXT_BD_WIDTH              6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_NEXT_BD_MASK               0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_NEXT_BD_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_USE_NEXT_BD_LSB            19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_USE_NEXT_BD_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_USE_NEXT_BD_MASK           0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_USE_NEXT_BD_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_BASE_ADDRESS_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_BASE_ADDRESS_WIDTH         19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_BASE_ADDRESS_MASK          0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_1_BASE_ADDRESS_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2                              0x000A0128
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_MASK                         0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_TLAST_SUPPRESS_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_TLAST_SUPPRESS_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_TLAST_SUPPRESS_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_TLAST_SUPPRESS_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_D0_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_D0_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_D0_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_D0_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_D0_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_D0_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_D0_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_2_D0_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3                              0x000A012C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_D1_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_D1_ZERO_BEFORE_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_D1_ZERO_BEFORE_MASK        0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_D1_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_D1_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_D1_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_D1_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_D1_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_D1_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_D1_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_D1_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_3_D1_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4                              0x000A0130
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_ENABLE_COMPRESSION_LSB     31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_ENABLE_COMPRESSION_WIDTH   1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_ENABLE_COMPRESSION_MASK    0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_ENABLE_COMPRESSION_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_D2_ZERO_BEFORE_LSB         27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_D2_ZERO_BEFORE_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_D2_ZERO_BEFORE_MASK        0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_D2_ZERO_BEFORE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_D2_WRAP_LSB                17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_D2_WRAP_WIDTH              10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_D2_WRAP_MASK               0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_D2_WRAP_DEFVAL             0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_D2_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_D2_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_D2_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_4_D2_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5                              0x000A0134
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D2_ZERO_AFTER_LSB          28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D2_ZERO_AFTER_WIDTH        4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D2_ZERO_AFTER_MASK         0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D2_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D1_ZERO_AFTER_LSB          23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D1_ZERO_AFTER_WIDTH        5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D1_ZERO_AFTER_MASK         0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D1_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D0_ZERO_AFTER_LSB          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D0_ZERO_AFTER_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D0_ZERO_AFTER_MASK         0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D0_ZERO_AFTER_DEFVAL       0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D3_STEPSIZE_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D3_STEPSIZE_WIDTH          17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D3_STEPSIZE_MASK           0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_5_D3_STEPSIZE_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6                              0x000A0138
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_MASK                         0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_ITERATION_CURRENT_LSB      23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_ITERATION_CURRENT_WIDTH    6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_ITERATION_CURRENT_MASK     0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_ITERATION_CURRENT_DEFVAL   0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_ITERATION_WRAP_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_ITERATION_WRAP_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_ITERATION_WRAP_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_ITERATION_WRAP_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_ITERATION_STEPSIZE_LSB     0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_ITERATION_STEPSIZE_WIDTH   17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_ITERATION_STEPSIZE_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_6_ITERATION_STEPSIZE_DEFVAL  0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7                              0x000A013C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_WIDTH                        32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_MASK                         0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_VALID_BD_LSB               31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_VALID_BD_WIDTH             1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_VALID_BD_MASK              0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_VALID_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_REL_VALUE_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_REL_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_REL_VALUE_MASK        0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_REL_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_REL_ID_LSB            16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_REL_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_REL_ID_MASK           0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_REL_ID_DEFVAL         0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_ACQ_ENABLE_LSB        15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_ACQ_ENABLE_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_ACQ_ENABLE_MASK       0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_ACQ_ENABLE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_ACQ_VALUE_LSB         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_ACQ_VALUE_WIDTH       7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_ACQ_VALUE_MASK        0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_ACQ_VALUE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_ACQ_ID_LSB            0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_ACQ_ID_WIDTH          8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_ACQ_ID_MASK           0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD9_7_LOCK_ACQ_ID_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0                             0x000A0140
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1                             0x000A0144
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2                             0x000A0148
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3                             0x000A014C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4                             0x000A0150
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5                             0x000A0154
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6                             0x000A0158
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7                             0x000A015C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD10_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0                             0x000A0160
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1                             0x000A0164
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2                             0x000A0168
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3                             0x000A016C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4                             0x000A0170
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5                             0x000A0174
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6                             0x000A0178
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7                             0x000A017C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD11_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0                             0x000A0180
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1                             0x000A0184
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2                             0x000A0188
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3                             0x000A018C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4                             0x000A0190
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5                             0x000A0194
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6                             0x000A0198
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7                             0x000A019C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD12_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0                             0x000A01A0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1                             0x000A01A4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2                             0x000A01A8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3                             0x000A01AC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4                             0x000A01B0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5                             0x000A01B4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6                             0x000A01B8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7                             0x000A01BC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD13_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0                             0x000A01C0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1                             0x000A01C4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2                             0x000A01C8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3                             0x000A01CC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4                             0x000A01D0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5                             0x000A01D4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6                             0x000A01D8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7                             0x000A01DC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD14_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0                             0x000A01E0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1                             0x000A01E4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2                             0x000A01E8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3                             0x000A01EC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4                             0x000A01F0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5                             0x000A01F4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6                             0x000A01F8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7                             0x000A01FC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD15_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0                             0x000A0200
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1                             0x000A0204
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2                             0x000A0208
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3                             0x000A020C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4                             0x000A0210
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5                             0x000A0214
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6                             0x000A0218
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7                             0x000A021C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD16_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0                             0x000A0220
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1                             0x000A0224
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2                             0x000A0228
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3                             0x000A022C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4                             0x000A0230
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5                             0x000A0234
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6                             0x000A0238
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7                             0x000A023C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD17_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0                             0x000A0240
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1                             0x000A0244
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2                             0x000A0248
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3                             0x000A024C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4                             0x000A0250
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5                             0x000A0254
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6                             0x000A0258
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7                             0x000A025C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD18_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0                             0x000A0260
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1                             0x000A0264
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2                             0x000A0268
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3                             0x000A026C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4                             0x000A0270
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5                             0x000A0274
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6                             0x000A0278
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7                             0x000A027C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD19_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0                             0x000A0280
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1                             0x000A0284
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2                             0x000A0288
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3                             0x000A028C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4                             0x000A0290
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5                             0x000A0294
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6                             0x000A0298
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7                             0x000A029C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD20_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0                             0x000A02A0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1                             0x000A02A4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2                             0x000A02A8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3                             0x000A02AC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4                             0x000A02B0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5                             0x000A02B4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6                             0x000A02B8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7                             0x000A02BC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD21_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0                             0x000A02C0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1                             0x000A02C4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2                             0x000A02C8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3                             0x000A02CC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4                             0x000A02D0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5                             0x000A02D4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6                             0x000A02D8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7                             0x000A02DC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD22_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0                             0x000A02E0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1                             0x000A02E4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2                             0x000A02E8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3                             0x000A02EC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4                             0x000A02F0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5                             0x000A02F4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6                             0x000A02F8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7                             0x000A02FC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD23_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0                             0x000A0300
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1                             0x000A0304
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2                             0x000A0308
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3                             0x000A030C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4                             0x000A0310
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5                             0x000A0314
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6                             0x000A0318
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7                             0x000A031C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD24_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0                             0x000A0320
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1                             0x000A0324
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2                             0x000A0328
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3                             0x000A032C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4                             0x000A0330
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5                             0x000A0334
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6                             0x000A0338
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7                             0x000A033C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD25_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0                             0x000A0340
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1                             0x000A0344
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2                             0x000A0348
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3                             0x000A034C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4                             0x000A0350
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5                             0x000A0354
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6                             0x000A0358
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7                             0x000A035C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD26_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0                             0x000A0360
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1                             0x000A0364
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2                             0x000A0368
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3                             0x000A036C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4                             0x000A0370
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5                             0x000A0374
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6                             0x000A0378
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7                             0x000A037C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD27_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0                             0x000A0380
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1                             0x000A0384
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2                             0x000A0388
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3                             0x000A038C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4                             0x000A0390
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5                             0x000A0394
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6                             0x000A0398
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7                             0x000A039C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD28_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0                             0x000A03A0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1                             0x000A03A4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2                             0x000A03A8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3                             0x000A03AC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4                             0x000A03B0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5                             0x000A03B4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6                             0x000A03B8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7                             0x000A03BC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD29_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0                             0x000A03C0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1                             0x000A03C4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2                             0x000A03C8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3                             0x000A03CC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4                             0x000A03D0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5                             0x000A03D4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6                             0x000A03D8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7                             0x000A03DC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD30_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0                             0x000A03E0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1                             0x000A03E4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2                             0x000A03E8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3                             0x000A03EC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4                             0x000A03F0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5                             0x000A03F4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6                             0x000A03F8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7                             0x000A03FC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD31_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0                             0x000A0400
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1                             0x000A0404
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2                             0x000A0408
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3                             0x000A040C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4                             0x000A0410
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5                             0x000A0414
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6                             0x000A0418
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7                             0x000A041C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD32_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0                             0x000A0420
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1                             0x000A0424
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2                             0x000A0428
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3                             0x000A042C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4                             0x000A0430
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5                             0x000A0434
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6                             0x000A0438
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7                             0x000A043C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD33_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0                             0x000A0440
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1                             0x000A0444
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2                             0x000A0448
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3                             0x000A044C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4                             0x000A0450
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5                             0x000A0454
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6                             0x000A0458
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7                             0x000A045C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD34_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0                             0x000A0460
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1                             0x000A0464
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2                             0x000A0468
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3                             0x000A046C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4                             0x000A0470
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5                             0x000A0474
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6                             0x000A0478
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7                             0x000A047C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD35_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0                             0x000A0480
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1                             0x000A0484
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2                             0x000A0488
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3                             0x000A048C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4                             0x000A0490
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5                             0x000A0494
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6                             0x000A0498
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7                             0x000A049C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD36_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0                             0x000A04A0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1                             0x000A04A4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2                             0x000A04A8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3                             0x000A04AC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4                             0x000A04B0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5                             0x000A04B4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6                             0x000A04B8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7                             0x000A04BC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD37_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0                             0x000A04C0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1                             0x000A04C4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2                             0x000A04C8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3                             0x000A04CC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4                             0x000A04D0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5                             0x000A04D4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6                             0x000A04D8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7                             0x000A04DC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD38_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0                             0x000A04E0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1                             0x000A04E4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2                             0x000A04E8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3                             0x000A04EC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4                             0x000A04F0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5                             0x000A04F4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6                             0x000A04F8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7                             0x000A04FC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD39_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0                             0x000A0500
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1                             0x000A0504
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2                             0x000A0508
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3                             0x000A050C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4                             0x000A0510
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5                             0x000A0514
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6                             0x000A0518
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7                             0x000A051C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD40_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0                             0x000A0520
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1                             0x000A0524
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2                             0x000A0528
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3                             0x000A052C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4                             0x000A0530
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5                             0x000A0534
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6                             0x000A0538
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7                             0x000A053C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD41_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0                             0x000A0540
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1                             0x000A0544
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2                             0x000A0548
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3                             0x000A054C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4                             0x000A0550
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5                             0x000A0554
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6                             0x000A0558
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7                             0x000A055C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD42_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0                             0x000A0560
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1                             0x000A0564
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2                             0x000A0568
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3                             0x000A056C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4                             0x000A0570
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5                             0x000A0574
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6                             0x000A0578
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7                             0x000A057C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD43_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0                             0x000A0580
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1                             0x000A0584
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2                             0x000A0588
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3                             0x000A058C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4                             0x000A0590
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5                             0x000A0594
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6                             0x000A0598
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7                             0x000A059C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD44_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0                             0x000A05A0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1                             0x000A05A4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2                             0x000A05A8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3                             0x000A05AC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4                             0x000A05B0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5                             0x000A05B4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6                             0x000A05B8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7                             0x000A05BC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD45_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0                             0x000A05C0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1                             0x000A05C4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2                             0x000A05C8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3                             0x000A05CC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4                             0x000A05D0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5                             0x000A05D4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6                             0x000A05D8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7                             0x000A05DC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD46_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0                             0x000A05E0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_ENABLE_PACKET_LSB         31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_ENABLE_PACKET_WIDTH       1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_ENABLE_PACKET_MASK        0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_ENABLE_PACKET_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_PACKET_TYPE_LSB           28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_PACKET_TYPE_WIDTH         3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_PACKET_TYPE_MASK          0x70000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_PACKET_TYPE_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_PACKET_ID_LSB             23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_PACKET_ID_WIDTH           5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_PACKET_ID_MASK            0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_PACKET_ID_DEFVAL          0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_OUT_OF_ORDER_BD_ID_LSB    17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_OUT_OF_ORDER_BD_ID_WIDTH  6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_OUT_OF_ORDER_BD_ID_MASK   0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_OUT_OF_ORDER_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_BUFFER_LENGTH_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_BUFFER_LENGTH_WIDTH       17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_BUFFER_LENGTH_MASK        0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_0_BUFFER_LENGTH_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1                             0x000A05E4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_D0_ZERO_BEFORE_LSB        26
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_D0_ZERO_BEFORE_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_D0_ZERO_BEFORE_MASK       0xFC000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_D0_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_NEXT_BD_LSB               20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_NEXT_BD_WIDTH             6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_NEXT_BD_MASK              0x03F00000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_NEXT_BD_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_USE_NEXT_BD_LSB           19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_USE_NEXT_BD_WIDTH         1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_USE_NEXT_BD_MASK          0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_USE_NEXT_BD_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_BASE_ADDRESS_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_BASE_ADDRESS_WIDTH        19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_BASE_ADDRESS_MASK         0x0007FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_1_BASE_ADDRESS_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2                             0x000A05E8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_MASK                        0x87FFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_TLAST_SUPPRESS_LSB        31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_TLAST_SUPPRESS_WIDTH      1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_TLAST_SUPPRESS_MASK       0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_TLAST_SUPPRESS_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_D0_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_D0_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_D0_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_D0_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_D0_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_D0_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_D0_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_2_D0_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3                             0x000A05EC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_D1_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_D1_ZERO_BEFORE_WIDTH      5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_D1_ZERO_BEFORE_MASK       0xF8000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_D1_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_D1_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_D1_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_D1_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_D1_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_D1_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_D1_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_D1_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_3_D1_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4                             0x000A05F0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_ENABLE_COMPRESSION_LSB    31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_ENABLE_COMPRESSION_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_ENABLE_COMPRESSION_MASK   0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_ENABLE_COMPRESSION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_D2_ZERO_BEFORE_LSB        27
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_D2_ZERO_BEFORE_WIDTH      4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_D2_ZERO_BEFORE_MASK       0x78000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_D2_ZERO_BEFORE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_D2_WRAP_LSB               17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_D2_WRAP_WIDTH             10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_D2_WRAP_MASK              0x07FE0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_D2_WRAP_DEFVAL            0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_D2_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_D2_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_D2_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_4_D2_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5                             0x000A05F4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D2_ZERO_AFTER_LSB         28
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D2_ZERO_AFTER_WIDTH       4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D2_ZERO_AFTER_MASK        0xF0000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D2_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D1_ZERO_AFTER_LSB         23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D1_ZERO_AFTER_WIDTH       5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D1_ZERO_AFTER_MASK        0x0F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D1_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D0_ZERO_AFTER_LSB         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D0_ZERO_AFTER_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D0_ZERO_AFTER_MASK        0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D0_ZERO_AFTER_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D3_STEPSIZE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D3_STEPSIZE_WIDTH         17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D3_STEPSIZE_MASK          0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_5_D3_STEPSIZE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6                             0x000A05F8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_MASK                        0x1FFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_ITERATION_CURRENT_LSB     23
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_ITERATION_CURRENT_WIDTH   6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_ITERATION_CURRENT_MASK    0x1F800000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_ITERATION_CURRENT_DEFVAL  0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_ITERATION_WRAP_LSB        17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_ITERATION_WRAP_WIDTH      6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_ITERATION_WRAP_MASK       0x007E0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_ITERATION_WRAP_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_ITERATION_STEPSIZE_LSB    0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_ITERATION_STEPSIZE_WIDTH  17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_ITERATION_STEPSIZE_MASK   0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_6_ITERATION_STEPSIZE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7                             0x000A05FC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_WIDTH                       32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_MASK                        0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_VALID_BD_LSB              31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_VALID_BD_WIDTH            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_VALID_BD_MASK             0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_VALID_BD_DEFVAL           0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_REL_VALUE_LSB        24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_REL_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_REL_VALUE_MASK       0x7F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_REL_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_REL_ID_LSB           16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_REL_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_REL_ID_MASK          0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_REL_ID_DEFVAL        0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_ACQ_ENABLE_LSB       15
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_ACQ_ENABLE_WIDTH     1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_ACQ_ENABLE_MASK      0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_ACQ_ENABLE_DEFVAL    0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_ACQ_VALUE_LSB        8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_ACQ_VALUE_WIDTH      7
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_ACQ_VALUE_MASK       0x00007F00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_ACQ_VALUE_DEFVAL     0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_ACQ_ID_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_ACQ_ID_WIDTH         8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_ACQ_ID_MASK          0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_BD47_7_LOCK_ACQ_ID_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL                        0x000A0600
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_WIDTH                  32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_MASK                   0x0003FF1A
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_FOT_MODE_LSB         16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_FOT_MODE_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_FOT_MODE_MASK        0x00030000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_FOT_MODE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_CONTROLLER_ID_LSB    8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_CONTROLLER_ID_WIDTH  8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_CONTROLLER_ID_MASK   0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_CONTROLLER_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_DECOMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_DECOMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_DECOMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_DECOMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_ENABLE_OUT_OF_ORDER_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_ENABLE_OUT_OF_ORDER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_ENABLE_OUT_OF_ORDER_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_ENABLE_OUT_OF_ORDER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_RESET_LSB            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_RESET_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_RESET_MASK           0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_CTRL_RESET_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE                 0x000A0604
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_MASK            0x80FF003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_START_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_START_BD_ID_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_0_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL                        0x000A0608
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_WIDTH                  32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_MASK                   0x0003FF1A
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_FOT_MODE_LSB         16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_FOT_MODE_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_FOT_MODE_MASK        0x00030000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_FOT_MODE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_CONTROLLER_ID_LSB    8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_CONTROLLER_ID_WIDTH  8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_CONTROLLER_ID_MASK   0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_CONTROLLER_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_DECOMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_DECOMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_DECOMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_DECOMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_ENABLE_OUT_OF_ORDER_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_ENABLE_OUT_OF_ORDER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_ENABLE_OUT_OF_ORDER_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_ENABLE_OUT_OF_ORDER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_RESET_LSB            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_RESET_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_RESET_MASK           0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_CTRL_RESET_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE                 0x000A060C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_MASK            0x80FF003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_START_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_START_BD_ID_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_1_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL                        0x000A0610
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_WIDTH                  32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_MASK                   0x0003FF1A
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_FOT_MODE_LSB         16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_FOT_MODE_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_FOT_MODE_MASK        0x00030000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_FOT_MODE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_CONTROLLER_ID_LSB    8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_CONTROLLER_ID_WIDTH  8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_CONTROLLER_ID_MASK   0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_CONTROLLER_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_DECOMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_DECOMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_DECOMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_DECOMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_ENABLE_OUT_OF_ORDER_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_ENABLE_OUT_OF_ORDER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_ENABLE_OUT_OF_ORDER_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_ENABLE_OUT_OF_ORDER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_RESET_LSB            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_RESET_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_RESET_MASK           0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_CTRL_RESET_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE                 0x000A0614
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_MASK            0x80FF003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_START_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_START_BD_ID_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_2_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL                        0x000A0618
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_WIDTH                  32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_MASK                   0x0003FF1A
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_FOT_MODE_LSB         16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_FOT_MODE_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_FOT_MODE_MASK        0x00030000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_FOT_MODE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_CONTROLLER_ID_LSB    8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_CONTROLLER_ID_WIDTH  8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_CONTROLLER_ID_MASK   0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_CONTROLLER_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_DECOMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_DECOMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_DECOMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_DECOMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_ENABLE_OUT_OF_ORDER_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_ENABLE_OUT_OF_ORDER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_ENABLE_OUT_OF_ORDER_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_ENABLE_OUT_OF_ORDER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_RESET_LSB            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_RESET_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_RESET_MASK           0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_CTRL_RESET_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE                 0x000A061C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_MASK            0x80FF003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_START_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_START_BD_ID_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_3_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL                        0x000A0620
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_WIDTH                  32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_MASK                   0x0003FF1A
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_FOT_MODE_LSB         16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_FOT_MODE_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_FOT_MODE_MASK        0x00030000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_FOT_MODE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_CONTROLLER_ID_LSB    8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_CONTROLLER_ID_WIDTH  8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_CONTROLLER_ID_MASK   0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_CONTROLLER_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_DECOMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_DECOMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_DECOMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_DECOMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_ENABLE_OUT_OF_ORDER_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_ENABLE_OUT_OF_ORDER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_ENABLE_OUT_OF_ORDER_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_ENABLE_OUT_OF_ORDER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_RESET_LSB            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_RESET_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_RESET_MASK           0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_CTRL_RESET_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE                 0x000A0624
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_MASK            0x80FF003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_START_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_START_BD_ID_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_4_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL                        0x000A0628
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_WIDTH                  32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_MASK                   0x0003FF1A
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_FOT_MODE_LSB         16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_FOT_MODE_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_FOT_MODE_MASK        0x00030000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_FOT_MODE_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_CONTROLLER_ID_LSB    8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_CONTROLLER_ID_WIDTH  8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_CONTROLLER_ID_MASK   0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_CONTROLLER_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_DECOMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_DECOMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_DECOMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_DECOMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_ENABLE_OUT_OF_ORDER_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_ENABLE_OUT_OF_ORDER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_ENABLE_OUT_OF_ORDER_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_ENABLE_OUT_OF_ORDER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_RESET_LSB            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_RESET_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_RESET_MASK           0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_CTRL_RESET_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE                 0x000A062C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_MASK            0x80FF003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_START_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_START_BD_ID_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_5_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL                        0x000A0630
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_WIDTH                  32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_MASK                   0x0000FF12
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_CONTROLLER_ID_LSB    8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_CONTROLLER_ID_WIDTH  8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_CONTROLLER_ID_MASK   0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_CONTROLLER_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_COMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_COMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_COMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_COMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_RESET_LSB            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_RESET_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_RESET_MASK           0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_CTRL_RESET_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE                 0x000A0634
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_MASK            0x80FF003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_START_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_START_BD_ID_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_0_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL                        0x000A0638
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_WIDTH                  32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_MASK                   0x0000FF12
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_CONTROLLER_ID_LSB    8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_CONTROLLER_ID_WIDTH  8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_CONTROLLER_ID_MASK   0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_CONTROLLER_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_COMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_COMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_COMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_COMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_RESET_LSB            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_RESET_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_RESET_MASK           0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_CTRL_RESET_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE                 0x000A063C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_MASK            0x80FF003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_START_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_START_BD_ID_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_1_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL                        0x000A0640
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_WIDTH                  32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_MASK                   0x0000FF12
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_CONTROLLER_ID_LSB    8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_CONTROLLER_ID_WIDTH  8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_CONTROLLER_ID_MASK   0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_CONTROLLER_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_COMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_COMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_COMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_COMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_RESET_LSB            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_RESET_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_RESET_MASK           0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_CTRL_RESET_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE                 0x000A0644
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_MASK            0x80FF003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_START_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_START_BD_ID_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_2_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL                        0x000A0648
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_WIDTH                  32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_MASK                   0x0000FF12
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_CONTROLLER_ID_LSB    8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_CONTROLLER_ID_WIDTH  8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_CONTROLLER_ID_MASK   0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_CONTROLLER_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_COMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_COMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_COMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_COMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_RESET_LSB            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_RESET_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_RESET_MASK           0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_CTRL_RESET_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE                 0x000A064C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_MASK            0x80FF003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_START_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_START_BD_ID_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_3_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL                        0x000A0650
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_WIDTH                  32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_MASK                   0x0000FF12
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_CONTROLLER_ID_LSB    8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_CONTROLLER_ID_WIDTH  8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_CONTROLLER_ID_MASK   0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_CONTROLLER_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_COMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_COMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_COMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_COMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_RESET_LSB            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_RESET_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_RESET_MASK           0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_CTRL_RESET_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE                 0x000A0654
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_MASK            0x80FF003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_START_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_START_BD_ID_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_4_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL                        0x000A0658
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_WIDTH                  32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_MASK                   0x0000FF12
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_CONTROLLER_ID_LSB    8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_CONTROLLER_ID_WIDTH  8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_CONTROLLER_ID_MASK   0x0000FF00
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_CONTROLLER_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_COMPRESSION_ENABLE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_COMPRESSION_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_COMPRESSION_ENABLE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_COMPRESSION_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_RESET_LSB            1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_RESET_WIDTH          1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_RESET_MASK           0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_CTRL_RESET_DEFVAL         0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE                 0x000A065C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_WIDTH           32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_MASK            0x80FF003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_ENABLE_TOKEN_ISSUE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_ENABLE_TOKEN_ISSUE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_ENABLE_TOKEN_ISSUE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_ENABLE_TOKEN_ISSUE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_REPEAT_COUNT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_REPEAT_COUNT_WIDTH 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_REPEAT_COUNT_MASK 0x00FF0000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_REPEAT_COUNT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_START_BD_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_START_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_START_BD_ID_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_5_START_QUEUE_START_BD_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0                      0x000A0660
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_MASK                 0x3F7C3F3F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_CUR_BD_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_CUR_BD_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_CUR_BD_MASK        0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_CUR_BD_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_SIZE_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_CHANNEL_RUNNING_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_BDS_PER_TASK_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_BDS_PER_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_BDS_PER_TASK_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_BDS_PER_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_LENGTH_EXCEEDED_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_LENGTH_EXCEEDED_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_LENGTH_EXCEEDED_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_FOT_LENGTH_EXCEEDED_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_DM_ACCESS_TO_UNAVAILABLE_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_TCT_OR_COUNT_FIFO_FULL_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_TCT_OR_COUNT_FIFO_FULL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_TCT_OR_COUNT_FIFO_FULL_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_TCT_OR_COUNT_FIFO_FULL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_STREAM_STARVATION_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_STREAM_STARVATION_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_STREAM_STARVATION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STATUS_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STATUS_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STATUS_MASK        0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_0_STATUS_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1                      0x000A0664
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_MASK                 0x3F7C3F3F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_CUR_BD_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_CUR_BD_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_CUR_BD_MASK        0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_CUR_BD_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_SIZE_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_CHANNEL_RUNNING_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_BDS_PER_TASK_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_BDS_PER_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_BDS_PER_TASK_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_BDS_PER_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_LENGTH_EXCEEDED_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_LENGTH_EXCEEDED_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_LENGTH_EXCEEDED_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_FOT_LENGTH_EXCEEDED_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_DM_ACCESS_TO_UNAVAILABLE_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_TCT_OR_COUNT_FIFO_FULL_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_TCT_OR_COUNT_FIFO_FULL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_TCT_OR_COUNT_FIFO_FULL_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_TCT_OR_COUNT_FIFO_FULL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_STREAM_STARVATION_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_STREAM_STARVATION_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_STREAM_STARVATION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STATUS_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STATUS_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STATUS_MASK        0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_1_STATUS_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2                      0x000A0668
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_MASK                 0x3F7C3F3F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_CUR_BD_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_CUR_BD_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_CUR_BD_MASK        0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_CUR_BD_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_TASK_QUEUE_SIZE_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_CHANNEL_RUNNING_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_FOT_BDS_PER_TASK_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_FOT_BDS_PER_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_FOT_BDS_PER_TASK_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_FOT_BDS_PER_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_FOT_LENGTH_EXCEEDED_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_FOT_LENGTH_EXCEEDED_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_FOT_LENGTH_EXCEEDED_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_FOT_LENGTH_EXCEEDED_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_DM_ACCESS_TO_UNAVAILABLE_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_TCT_OR_COUNT_FIFO_FULL_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_TCT_OR_COUNT_FIFO_FULL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_TCT_OR_COUNT_FIFO_FULL_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_TCT_OR_COUNT_FIFO_FULL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_STREAM_STARVATION_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_STREAM_STARVATION_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_STREAM_STARVATION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STATUS_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STATUS_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STATUS_MASK        0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_2_STATUS_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3                      0x000A066C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_MASK                 0x3F7C3F3F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_CUR_BD_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_CUR_BD_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_CUR_BD_MASK        0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_CUR_BD_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_TASK_QUEUE_SIZE_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_CHANNEL_RUNNING_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_FOT_BDS_PER_TASK_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_FOT_BDS_PER_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_FOT_BDS_PER_TASK_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_FOT_BDS_PER_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_FOT_LENGTH_EXCEEDED_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_FOT_LENGTH_EXCEEDED_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_FOT_LENGTH_EXCEEDED_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_FOT_LENGTH_EXCEEDED_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_DM_ACCESS_TO_UNAVAILABLE_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_TCT_OR_COUNT_FIFO_FULL_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_TCT_OR_COUNT_FIFO_FULL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_TCT_OR_COUNT_FIFO_FULL_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_TCT_OR_COUNT_FIFO_FULL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_STREAM_STARVATION_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_STREAM_STARVATION_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_STREAM_STARVATION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STATUS_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STATUS_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STATUS_MASK        0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_3_STATUS_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4                      0x000A0670
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_MASK                 0x3F7C3F3F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_CUR_BD_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_CUR_BD_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_CUR_BD_MASK        0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_CUR_BD_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_TASK_QUEUE_SIZE_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_CHANNEL_RUNNING_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_FOT_BDS_PER_TASK_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_FOT_BDS_PER_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_FOT_BDS_PER_TASK_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_FOT_BDS_PER_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_FOT_LENGTH_EXCEEDED_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_FOT_LENGTH_EXCEEDED_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_FOT_LENGTH_EXCEEDED_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_FOT_LENGTH_EXCEEDED_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_DM_ACCESS_TO_UNAVAILABLE_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_TCT_OR_COUNT_FIFO_FULL_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_TCT_OR_COUNT_FIFO_FULL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_TCT_OR_COUNT_FIFO_FULL_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_TCT_OR_COUNT_FIFO_FULL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_STREAM_STARVATION_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_STREAM_STARVATION_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_STREAM_STARVATION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STATUS_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STATUS_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STATUS_MASK        0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_4_STATUS_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5                      0x000A0674
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_MASK                 0x3F7C3F3F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_CUR_BD_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_CUR_BD_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_CUR_BD_MASK        0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_CUR_BD_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_TASK_QUEUE_SIZE_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_CHANNEL_RUNNING_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_FOT_BDS_PER_TASK_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_FOT_BDS_PER_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_FOT_BDS_PER_TASK_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_FOT_BDS_PER_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_FOT_LENGTH_EXCEEDED_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_FOT_LENGTH_EXCEEDED_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_FOT_LENGTH_EXCEEDED_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_FOT_LENGTH_EXCEEDED_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_DM_ACCESS_TO_UNAVAILABLE_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_TCT_OR_COUNT_FIFO_FULL_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_TCT_OR_COUNT_FIFO_FULL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_TCT_OR_COUNT_FIFO_FULL_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_TCT_OR_COUNT_FIFO_FULL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_STREAM_STARVATION_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_STREAM_STARVATION_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_STREAM_STARVATION_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_STREAM_STARVATION_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STATUS_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STATUS_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STATUS_MASK        0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_STATUS_5_STATUS_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0                      0x000A0680
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_MASK                 0x3F7C0F3F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_CUR_BD_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_CUR_BD_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_CUR_BD_MASK        0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_CUR_BD_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_SIZE_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_CHANNEL_RUNNING_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_DM_ACCESS_TO_UNAVAILABLE_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_TCT_LSB    5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_TCT_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_TCT_MASK   0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_TCT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_STREAM_BACKPRESSURE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_STREAM_BACKPRESSURE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_STREAM_BACKPRESSURE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STATUS_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STATUS_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STATUS_MASK        0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_0_STATUS_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1                      0x000A0684
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_MASK                 0x3F7C0F3F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_CUR_BD_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_CUR_BD_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_CUR_BD_MASK        0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_CUR_BD_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_SIZE_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_CHANNEL_RUNNING_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_DM_ACCESS_TO_UNAVAILABLE_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_TCT_LSB    5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_TCT_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_TCT_MASK   0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_TCT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_STREAM_BACKPRESSURE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_STREAM_BACKPRESSURE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_STREAM_BACKPRESSURE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STATUS_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STATUS_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STATUS_MASK        0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_1_STATUS_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2                      0x000A0688
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_MASK                 0x3F7C0F3F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_CUR_BD_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_CUR_BD_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_CUR_BD_MASK        0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_CUR_BD_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_TASK_QUEUE_SIZE_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_CHANNEL_RUNNING_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_DM_ACCESS_TO_UNAVAILABLE_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_TCT_LSB    5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_TCT_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_TCT_MASK   0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_TCT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_STREAM_BACKPRESSURE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_STREAM_BACKPRESSURE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_STREAM_BACKPRESSURE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STATUS_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STATUS_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STATUS_MASK        0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_2_STATUS_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3                      0x000A068C
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_MASK                 0x3F7C0F3F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_CUR_BD_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_CUR_BD_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_CUR_BD_MASK        0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_CUR_BD_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_TASK_QUEUE_SIZE_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_CHANNEL_RUNNING_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_DM_ACCESS_TO_UNAVAILABLE_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_TCT_LSB    5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_TCT_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_TCT_MASK   0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_TCT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_STREAM_BACKPRESSURE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_STREAM_BACKPRESSURE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_STREAM_BACKPRESSURE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STATUS_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STATUS_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STATUS_MASK        0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_3_STATUS_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4                      0x000A0690
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_MASK                 0x3F7C0F3F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_CUR_BD_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_CUR_BD_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_CUR_BD_MASK        0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_CUR_BD_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_TASK_QUEUE_SIZE_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_CHANNEL_RUNNING_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_DM_ACCESS_TO_UNAVAILABLE_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_TCT_LSB    5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_TCT_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_TCT_MASK   0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_TCT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_STREAM_BACKPRESSURE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_STREAM_BACKPRESSURE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_STREAM_BACKPRESSURE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STATUS_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STATUS_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STATUS_MASK        0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_4_STATUS_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5                      0x000A0694
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_MASK                 0x3F7C0F3F
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_CUR_BD_LSB         24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_CUR_BD_WIDTH       6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_CUR_BD_MASK        0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_CUR_BD_DEFVAL      0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_TASK_QUEUE_SIZE_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_TASK_QUEUE_SIZE_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_TASK_QUEUE_SIZE_MASK 0x00700000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_TASK_QUEUE_SIZE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_CHANNEL_RUNNING_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_CHANNEL_RUNNING_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_CHANNEL_RUNNING_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_CHANNEL_RUNNING_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_TASK_QUEUE_OVERFLOW_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_TASK_QUEUE_OVERFLOW_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_TASK_QUEUE_OVERFLOW_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_TASK_QUEUE_OVERFLOW_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_BD_INVALID_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_BD_INVALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_BD_INVALID_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_BD_INVALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_BD_UNAVAILABLE_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_BD_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_BD_UNAVAILABLE_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_BD_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_DM_ACCESS_TO_UNAVAILABLE_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_DM_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_DM_ACCESS_TO_UNAVAILABLE_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_DM_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_ERROR_LOCK_ACCESS_TO_UNAVAILABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_TCT_LSB    5
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_TCT_WIDTH  1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_TCT_MASK   0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_TCT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_STREAM_BACKPRESSURE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_STREAM_BACKPRESSURE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_STREAM_BACKPRESSURE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_STREAM_BACKPRESSURE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_LOCK_REL_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_LOCK_REL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_LOCK_REL_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_LOCK_REL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_LOCK_ACQ_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_LOCK_ACQ_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_LOCK_ACQ_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STALLED_LOCK_ACQ_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STATUS_LSB         0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STATUS_WIDTH       2
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STATUS_MASK        0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_MM2S_STATUS_5_STATUS_DEFVAL      0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION            0x000A06A0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_WIDTH      32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_MASK       0x07070707
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_MM2S_SEL1_CHANNEL_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_MM2S_SEL1_CHANNEL_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_MM2S_SEL1_CHANNEL_MASK 0x07000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_MM2S_SEL1_CHANNEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_MM2S_SEL0_CHANNEL_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_MM2S_SEL0_CHANNEL_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_MM2S_SEL0_CHANNEL_MASK 0x00070000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_MM2S_SEL0_CHANNEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_S2MM_SEL1_CHANNEL_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_S2MM_SEL1_CHANNEL_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_S2MM_SEL1_CHANNEL_MASK 0x00000700
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_S2MM_SEL1_CHANNEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_S2MM_SEL0_CHANNEL_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_S2MM_SEL0_CHANNEL_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_S2MM_SEL0_CHANNEL_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_EVENT_CHANNEL_SELECTION_S2MM_SEL0_CHANNEL_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0         0x000A06B0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_WIDTH   32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_CURRENT_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_CURRENT_WRITE_COUNT_WIDTH 17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_CURRENT_WRITE_COUNT_MASK 0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_0_CURRENT_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1         0x000A06B4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_WIDTH   32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_CURRENT_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_CURRENT_WRITE_COUNT_WIDTH 17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_CURRENT_WRITE_COUNT_MASK 0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_1_CURRENT_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_2         0x000A06B8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_2_WIDTH   32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_2_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_2_CURRENT_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_2_CURRENT_WRITE_COUNT_WIDTH 17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_2_CURRENT_WRITE_COUNT_MASK 0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_2_CURRENT_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_3         0x000A06BC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_3_WIDTH   32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_3_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_3_CURRENT_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_3_CURRENT_WRITE_COUNT_WIDTH 17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_3_CURRENT_WRITE_COUNT_MASK 0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_3_CURRENT_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_4         0x000A06C0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_4_WIDTH   32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_4_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_4_CURRENT_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_4_CURRENT_WRITE_COUNT_WIDTH 17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_4_CURRENT_WRITE_COUNT_MASK 0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_4_CURRENT_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_5         0x000A06C4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_5_WIDTH   32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_5_MASK    0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_5_CURRENT_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_5_CURRENT_WRITE_COUNT_WIDTH 17
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_5_CURRENT_WRITE_COUNT_MASK 0x0001FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_CURRENT_WRITE_COUNT_5_CURRENT_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0          0x000A06C8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WIDTH    32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_MASK     0xFF03FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_VALID_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_VALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_VALID_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_VALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_LAST_IN_TASK_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_LAST_IN_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_LAST_IN_TASK_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_LAST_IN_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_BD_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_BD_ID_MASK 0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WRITE_COUNT_WIDTH 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WRITE_COUNT_MASK 0x0003FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_0_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1          0x000A06CC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WIDTH    32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_MASK     0xFF03FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_VALID_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_VALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_VALID_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_VALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_LAST_IN_TASK_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_LAST_IN_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_LAST_IN_TASK_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_LAST_IN_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_BD_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_BD_ID_MASK 0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WRITE_COUNT_WIDTH 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WRITE_COUNT_MASK 0x0003FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_1_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2          0x000A06D0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_WIDTH    32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_MASK     0xFF03FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_VALID_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_VALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_VALID_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_VALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_LAST_IN_TASK_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_LAST_IN_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_LAST_IN_TASK_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_LAST_IN_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_BD_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_BD_ID_MASK 0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_WRITE_COUNT_WIDTH 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_WRITE_COUNT_MASK 0x0003FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_2_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3          0x000A06D4
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_WIDTH    32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_MASK     0xFF03FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_VALID_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_VALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_VALID_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_VALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_LAST_IN_TASK_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_LAST_IN_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_LAST_IN_TASK_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_LAST_IN_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_BD_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_BD_ID_MASK 0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_WRITE_COUNT_WIDTH 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_WRITE_COUNT_MASK 0x0003FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_3_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4          0x000A06D8
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_WIDTH    32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_MASK     0xFF03FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_VALID_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_VALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_VALID_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_VALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_LAST_IN_TASK_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_LAST_IN_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_LAST_IN_TASK_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_LAST_IN_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_BD_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_BD_ID_MASK 0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_WRITE_COUNT_WIDTH 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_WRITE_COUNT_MASK 0x0003FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_4_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5          0x000A06DC
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_WIDTH    32
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_MASK     0xFF03FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_VALID_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_VALID_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_VALID_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_VALID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_LAST_IN_TASK_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_LAST_IN_TASK_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_LAST_IN_TASK_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_LAST_IN_TASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_BD_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_BD_ID_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_BD_ID_MASK 0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_BD_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_WRITE_COUNT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_WRITE_COUNT_WIDTH 18
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_WRITE_COUNT_MASK 0x0003FFFF
#define XAIEMLGBL_MEM_TILE_MODULE_DMA_S2MM_FOT_COUNT_FIFO_POP_5_WRITE_COUNT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0       0x000B0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_MASK  0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1       0x000B0004
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_MASK  0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA1_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2       0x000B0008
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_MASK  0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA2_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3       0x000B000C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_MASK  0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA3_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4       0x000B0010
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_MASK  0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA4_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5       0x000B0014
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_MASK  0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_DMA5_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL  0x000B0018
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASK 0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_TILE_CTRL_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0     0x000B001C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASK 0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1     0x000B0020
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASK 0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH1_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2     0x000B0024
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASK 0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH2_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3     0x000B0028
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASK 0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_SOUTH3_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0     0x000B002C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASK 0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH0_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1     0x000B0030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASK 0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH1_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2     0x000B0034
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASK 0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH2_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3     0x000B0038
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASK 0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH3_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4     0x000B003C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASK 0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH4_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5     0x000B0040
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASK 0xC00000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASTER_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASTER_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASTER_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_MASTER_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_PACKET_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_DROP_HEADER_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_DROP_HEADER_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_DROP_HEADER_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_DROP_HEADER_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_CONFIGURATION_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_CONFIGURATION_WIDTH 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_CONFIGURATION_MASK 0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_MASTER_CONFIG_NORTH5_CONFIGURATION_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0       0x000B0100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_MASK  0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1       0x000B0104
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_MASK  0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_1_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_2       0x000B0108
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_2_MASK  0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_2_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_2_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_2_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_2_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_2_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_3       0x000B010C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_3_MASK  0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_3_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_3_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_3_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_3_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_3_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_4       0x000B0110
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_4_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_4_MASK  0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_4_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_4_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_4_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_4_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_4_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_4_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_4_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_4_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_5       0x000B0114
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_5_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_5_MASK  0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_5_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_5_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_5_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_5_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_5_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_5_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_5_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_DMA_5_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL   0x000B0118
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_MASK 0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TILE_CTRL_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0     0x000B011C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_MASK 0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1     0x000B0120
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_MASK 0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_1_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2     0x000B0124
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_MASK 0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_2_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3     0x000B0128
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_MASK 0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_3_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4     0x000B012C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_MASK 0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_4_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5     0x000B0130
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_MASK 0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_SOUTH_5_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0     0x000B0134
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_MASK 0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_0_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1     0x000B0138
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_MASK 0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_1_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2     0x000B013C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_MASK 0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_2_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3     0x000B0140
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_MASK 0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_NORTH_3_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE       0x000B0144
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_MASK  0xC0000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_SLAVE_ENABLE_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_SLAVE_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_SLAVE_ENABLE_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_SLAVE_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_PACKET_ENABLE_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_PACKET_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_PACKET_ENABLE_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_CONFIG_TRACE_PACKET_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0        0x000B0200
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1        0x000B0204
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2        0x000B0208
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3        0x000B020C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0        0x000B0210
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1        0x000B0214
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2        0x000B0218
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3        0x000B021C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_1_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0        0x000B0220
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1        0x000B0224
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2        0x000B0228
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3        0x000B022C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_2_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0        0x000B0230
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1        0x000B0234
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2        0x000B0238
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3        0x000B023C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_3_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0        0x000B0240
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1        0x000B0244
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2        0x000B0248
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3        0x000B024C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_4_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0        0x000B0250
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1        0x000B0254
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2        0x000B0258
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3        0x000B025C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_DMA_5_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0    0x000B0260
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1    0x000B0264
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2    0x000B0268
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3    0x000B026C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TILE_CTRL_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0      0x000B0270
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1      0x000B0274
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2      0x000B0278
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3      0x000B027C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0      0x000B0280
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1      0x000B0284
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2      0x000B0288
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3      0x000B028C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_1_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0      0x000B0290
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1      0x000B0294
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2      0x000B0298
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3      0x000B029C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_2_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0      0x000B02A0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1      0x000B02A4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2      0x000B02A8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3      0x000B02AC
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_3_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0      0x000B02B0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1      0x000B02B4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2      0x000B02B8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3      0x000B02BC
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_4_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0      0x000B02C0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1      0x000B02C4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2      0x000B02C8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3      0x000B02CC
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_SOUTH_5_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0      0x000B02D0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1      0x000B02D4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2      0x000B02D8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3      0x000B02DC
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_0_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0      0x000B02E0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1      0x000B02E4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2      0x000B02E8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3      0x000B02EC
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_1_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0      0x000B02F0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1      0x000B02F4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2      0x000B02F8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3      0x000B02FC
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_2_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0      0x000B0300
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1      0x000B0304
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2      0x000B0308
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3      0x000B030C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK 0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_NORTH_3_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0        0x000B0310
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT0_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1        0x000B0314
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT1_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2        0x000B0318
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT2_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3        0x000B031C
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_WIDTH  32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MASK   0x1F1F0137
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MASK_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MASK_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MASK_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MASK_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ENABLE_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ENABLE_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ENABLE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MSEL_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MSEL_WIDTH 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MSEL_MASK 0x00000030
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_MSEL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ARBIT_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ARBIT_WIDTH 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ARBIT_MASK 0x00000007
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_SLAVE_TRACE_SLOT3_ARBIT_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1 0x000B0800
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_MASK 0x3F1F3F1F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_1_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_1_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_1_MASK 0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_1_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_1_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_1_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_1_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_1_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_0_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_0_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_0_MASK 0x00003F00
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_PACKET_COUNT_0_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_0_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_0_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_0_MASK 0x0000001F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE0_1_SLAVE_ID_0_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3 0x000B0804
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_MASK 0x3F1F3F1F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_3_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_3_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_3_MASK 0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_3_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_3_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_3_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_3_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_3_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_2_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_2_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_2_MASK 0x00003F00
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_PACKET_COUNT_2_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_2_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_2_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_2_MASK 0x0000001F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_SLAVE2_3_SLAVE_ID_2_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL 0x000B0808
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_ENABLE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_ENABLE_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB0_CTRL_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1 0x000B0810
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_MASK 0x3F1F3F1F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_1_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_1_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_1_MASK 0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_1_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_1_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_1_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_1_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_1_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_0_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_0_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_0_MASK 0x00003F00
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_PACKET_COUNT_0_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_0_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_0_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_0_MASK 0x0000001F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE0_1_SLAVE_ID_0_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3 0x000B0814
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_MASK 0x3F1F3F1F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_3_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_3_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_3_MASK 0x3F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_3_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_3_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_3_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_3_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_3_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_2_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_2_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_2_MASK 0x00003F00
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_PACKET_COUNT_2_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_2_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_2_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_2_MASK 0x0000001F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_SLAVE2_3_SLAVE_ID_2_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL 0x000B0818
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_ENABLE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_ENABLE_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_DETERMINISTIC_MERGE_ARB1_CTRL_ENABLE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0   0x000B0F00
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_MASK 0x3F3F3F3F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_MASTER_SLAVE_LSB 29
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_MASTER_SLAVE_MASK 0x20000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_3_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_MASTER_SLAVE_LSB 21
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_MASTER_SLAVE_MASK 0x00200000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_ID_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_ID_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_2_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_MASTER_SLAVE_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_MASTER_SLAVE_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_ID_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_ID_MASK 0x00001F00
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_1_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_MASTER_SLAVE_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_MASTER_SLAVE_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_ID_MASK 0x0000001F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_0_PORT_0_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1   0x000B0F04
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_MASK 0x3F3F3F3F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_MASTER_SLAVE_LSB 29
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_MASTER_SLAVE_MASK 0x20000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_ID_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_ID_MASK 0x1F000000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_7_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_MASTER_SLAVE_LSB 21
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_MASTER_SLAVE_MASK 0x00200000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_ID_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_ID_MASK 0x001F0000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_6_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_MASTER_SLAVE_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_MASTER_SLAVE_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_ID_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_ID_MASK 0x00001F00
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_5_ID_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_MASTER_SLAVE_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_MASTER_SLAVE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_MASTER_SLAVE_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_MASTER_SLAVE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_ID_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_ID_WIDTH 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_ID_MASK 0x0000001F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_EVENT_PORT_SELECTION_1_PORT_4_ID_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS            0x000B0F10
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_WIDTH      32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_MASK       0x0000007F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_TILE_CONTROL_LSB 6
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_TILE_CONTROL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_TILE_CONTROL_MASK 0x00000040
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_TILE_CONTROL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_5_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_5_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_5_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_5_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_4_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_4_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_4_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_4_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_3_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_3_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_3_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_3_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_2_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_2_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_2_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_2_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_1_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_1_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_1_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_0_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_0_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_STATUS_DMA_0_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION         0x000B0F20
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_WIDTH   32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_MASK    0x000000FF
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_MEM_TRACE_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_MEM_TRACE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_MEM_TRACE_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_MEM_TRACE_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_TILE_CONTROL_LSB 6
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_TILE_CONTROL_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_TILE_CONTROL_MASK 0x00000040
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_TILE_CONTROL_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_5_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_5_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_5_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_5_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_4_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_4_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_4_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_4_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_3_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_3_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_3_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_3_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_2_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_2_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_2_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_2_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_1_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_1_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_1_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_0_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_0_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_PARITY_INJECTION_DMA_0_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS     0x000B0F30
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_MASK 0x0000000F
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_TLAST_ERROR_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_TLAST_ERROR_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_TLAST_ERROR_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_TLAST_ERROR_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SLVERR_ON_ACCESS_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SLVERR_ON_ACCESS_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SLVERR_ON_ACCESS_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SLVERR_ON_ACCESS_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SECOND_HEADER_PARITY_ERROR_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SECOND_HEADER_PARITY_ERROR_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SECOND_HEADER_PARITY_ERROR_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_SECOND_HEADER_PARITY_ERROR_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_FIRST_HEADER_PARITY_ERROR_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_FIRST_HEADER_PARITY_ERROR_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_FIRST_HEADER_PARITY_ERROR_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_TILE_CONTROL_PACKET_HANDLER_STATUS_FIRST_HEADER_PARITY_ERROR_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS 0x000B0F34
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_ACTIVE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_ACTIVE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_ACTIVE_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_STATUS_ACTIVE_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD 0x000B0F38
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_WIDTH 32
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_MASK 0x0000000F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_ABORT_PERIOD_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_ABORT_PERIOD_WIDTH 4
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_ABORT_PERIOD_MASK 0x0000000F
#define XAIEMLGBL_MEM_TILE_MODULE_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_ABORT_PERIOD_ABORT_PERIOD_DEFVAL 0x7

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK0_VALUE                            0x000C0000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK0_VALUE_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK0_VALUE_MASK                       0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK0_VALUE_LOCK_VALUE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK0_VALUE_LOCK_VALUE_WIDTH         6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK0_VALUE_LOCK_VALUE_MASK          0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK0_VALUE_LOCK_VALUE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK1_VALUE                            0x000C0010
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK1_VALUE_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK1_VALUE_MASK                       0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK1_VALUE_LOCK_VALUE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK1_VALUE_LOCK_VALUE_WIDTH         6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK1_VALUE_LOCK_VALUE_MASK          0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK1_VALUE_LOCK_VALUE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK2_VALUE                            0x000C0020
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK2_VALUE_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK2_VALUE_MASK                       0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK2_VALUE_LOCK_VALUE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK2_VALUE_LOCK_VALUE_WIDTH         6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK2_VALUE_LOCK_VALUE_MASK          0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK2_VALUE_LOCK_VALUE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK3_VALUE                            0x000C0030
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK3_VALUE_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK3_VALUE_MASK                       0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK3_VALUE_LOCK_VALUE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK3_VALUE_LOCK_VALUE_WIDTH         6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK3_VALUE_LOCK_VALUE_MASK          0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK3_VALUE_LOCK_VALUE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK4_VALUE                            0x000C0040
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK4_VALUE_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK4_VALUE_MASK                       0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK4_VALUE_LOCK_VALUE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK4_VALUE_LOCK_VALUE_WIDTH         6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK4_VALUE_LOCK_VALUE_MASK          0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK4_VALUE_LOCK_VALUE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK5_VALUE                            0x000C0050
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK5_VALUE_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK5_VALUE_MASK                       0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK5_VALUE_LOCK_VALUE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK5_VALUE_LOCK_VALUE_WIDTH         6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK5_VALUE_LOCK_VALUE_MASK          0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK5_VALUE_LOCK_VALUE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK6_VALUE                            0x000C0060
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK6_VALUE_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK6_VALUE_MASK                       0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK6_VALUE_LOCK_VALUE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK6_VALUE_LOCK_VALUE_WIDTH         6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK6_VALUE_LOCK_VALUE_MASK          0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK6_VALUE_LOCK_VALUE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK7_VALUE                            0x000C0070
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK7_VALUE_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK7_VALUE_MASK                       0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK7_VALUE_LOCK_VALUE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK7_VALUE_LOCK_VALUE_WIDTH         6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK7_VALUE_LOCK_VALUE_MASK          0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK7_VALUE_LOCK_VALUE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK8_VALUE                            0x000C0080
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK8_VALUE_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK8_VALUE_MASK                       0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK8_VALUE_LOCK_VALUE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK8_VALUE_LOCK_VALUE_WIDTH         6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK8_VALUE_LOCK_VALUE_MASK          0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK8_VALUE_LOCK_VALUE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK9_VALUE                            0x000C0090
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK9_VALUE_WIDTH                      32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK9_VALUE_MASK                       0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK9_VALUE_LOCK_VALUE_LSB           0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK9_VALUE_LOCK_VALUE_WIDTH         6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK9_VALUE_LOCK_VALUE_MASK          0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK9_VALUE_LOCK_VALUE_DEFVAL        0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK10_VALUE                           0x000C00A0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK10_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK10_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK10_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK10_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK10_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK10_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK11_VALUE                           0x000C00B0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK11_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK11_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK11_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK11_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK11_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK11_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK12_VALUE                           0x000C00C0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK12_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK12_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK12_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK12_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK12_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK12_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK13_VALUE                           0x000C00D0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK13_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK13_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK13_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK13_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK13_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK13_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK14_VALUE                           0x000C00E0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK14_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK14_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK14_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK14_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK14_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK14_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK15_VALUE                           0x000C00F0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK15_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK15_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK15_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK15_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK15_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK15_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK16_VALUE                           0x000C0100
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK16_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK16_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK16_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK16_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK16_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK16_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK17_VALUE                           0x000C0110
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK17_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK17_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK17_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK17_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK17_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK17_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK18_VALUE                           0x000C0120
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK18_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK18_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK18_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK18_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK18_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK18_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK19_VALUE                           0x000C0130
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK19_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK19_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK19_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK19_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK19_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK19_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK20_VALUE                           0x000C0140
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK20_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK20_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK20_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK20_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK20_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK20_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK21_VALUE                           0x000C0150
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK21_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK21_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK21_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK21_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK21_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK21_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK22_VALUE                           0x000C0160
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK22_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK22_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK22_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK22_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK22_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK22_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK23_VALUE                           0x000C0170
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK23_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK23_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK23_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK23_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK23_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK23_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK24_VALUE                           0x000C0180
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK24_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK24_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK24_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK24_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK24_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK24_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK25_VALUE                           0x000C0190
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK25_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK25_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK25_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK25_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK25_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK25_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK26_VALUE                           0x000C01A0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK26_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK26_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK26_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK26_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK26_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK26_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK27_VALUE                           0x000C01B0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK27_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK27_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK27_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK27_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK27_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK27_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK28_VALUE                           0x000C01C0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK28_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK28_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK28_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK28_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK28_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK28_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK29_VALUE                           0x000C01D0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK29_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK29_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK29_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK29_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK29_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK29_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK30_VALUE                           0x000C01E0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK30_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK30_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK30_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK30_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK30_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK30_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK31_VALUE                           0x000C01F0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK31_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK31_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK31_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK31_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK31_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK31_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK32_VALUE                           0x000C0200
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK32_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK32_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK32_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK32_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK32_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK32_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK33_VALUE                           0x000C0210
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK33_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK33_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK33_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK33_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK33_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK33_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK34_VALUE                           0x000C0220
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK34_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK34_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK34_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK34_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK34_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK34_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK35_VALUE                           0x000C0230
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK35_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK35_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK35_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK35_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK35_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK35_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK36_VALUE                           0x000C0240
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK36_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK36_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK36_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK36_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK36_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK36_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK37_VALUE                           0x000C0250
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK37_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK37_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK37_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK37_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK37_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK37_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK38_VALUE                           0x000C0260
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK38_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK38_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK38_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK38_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK38_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK38_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK39_VALUE                           0x000C0270
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK39_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK39_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK39_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK39_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK39_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK39_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK40_VALUE                           0x000C0280
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK40_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK40_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK40_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK40_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK40_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK40_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK41_VALUE                           0x000C0290
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK41_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK41_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK41_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK41_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK41_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK41_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK42_VALUE                           0x000C02A0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK42_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK42_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK42_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK42_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK42_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK42_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK43_VALUE                           0x000C02B0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK43_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK43_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK43_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK43_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK43_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK43_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK44_VALUE                           0x000C02C0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK44_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK44_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK44_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK44_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK44_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK44_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK45_VALUE                           0x000C02D0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK45_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK45_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK45_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK45_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK45_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK45_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK46_VALUE                           0x000C02E0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK46_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK46_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK46_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK46_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK46_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK46_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK47_VALUE                           0x000C02F0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK47_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK47_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK47_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK47_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK47_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK47_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK48_VALUE                           0x000C0300
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK48_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK48_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK48_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK48_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK48_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK48_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK49_VALUE                           0x000C0310
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK49_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK49_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK49_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK49_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK49_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK49_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK50_VALUE                           0x000C0320
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK50_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK50_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK50_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK50_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK50_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK50_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK51_VALUE                           0x000C0330
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK51_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK51_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK51_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK51_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK51_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK51_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK52_VALUE                           0x000C0340
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK52_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK52_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK52_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK52_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK52_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK52_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK53_VALUE                           0x000C0350
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK53_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK53_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK53_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK53_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK53_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK53_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK54_VALUE                           0x000C0360
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK54_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK54_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK54_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK54_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK54_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK54_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK55_VALUE                           0x000C0370
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK55_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK55_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK55_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK55_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK55_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK55_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK56_VALUE                           0x000C0380
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK56_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK56_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK56_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK56_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK56_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK56_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK57_VALUE                           0x000C0390
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK57_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK57_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK57_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK57_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK57_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK57_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK58_VALUE                           0x000C03A0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK58_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK58_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK58_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK58_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK58_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK58_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK59_VALUE                           0x000C03B0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK59_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK59_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK59_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK59_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK59_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK59_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK60_VALUE                           0x000C03C0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK60_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK60_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK60_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK60_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK60_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK60_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK61_VALUE                           0x000C03D0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK61_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK61_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK61_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK61_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK61_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK61_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK62_VALUE                           0x000C03E0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK62_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK62_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK62_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK62_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK62_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK62_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK63_VALUE                           0x000C03F0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK63_VALUE_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK63_VALUE_MASK                      0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK63_VALUE_LOCK_VALUE_LSB          0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK63_VALUE_LOCK_VALUE_WIDTH        6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK63_VALUE_LOCK_VALUE_MASK         0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK63_VALUE_LOCK_VALUE_DEFVAL       0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_0                0x000C0400
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_0_WIDTH          32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_0_MASK           0x003F003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_SELECT_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_SELECT_MASK 0x003F0000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_0_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_1                0x000C0404
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_1_WIDTH          32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_1_MASK           0x003F003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_SELECT_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_SELECT_MASK 0x003F0000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_1_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_2                0x000C0408
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_2_WIDTH          32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_2_MASK           0x003F003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_SELECT_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_SELECT_MASK 0x003F0000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_2_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_3                0x000C040C
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_3_WIDTH          32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_3_MASK           0x003F003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_SELECT_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_SELECT_MASK 0x003F0000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_3_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_4                0x000C0410
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_4_WIDTH          32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_4_MASK           0x003F003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_SELECT_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_SELECT_MASK 0x003F0000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_4_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_5                0x000C0414
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_5_WIDTH          32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_5_MASK           0x003F003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_SELECT_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_SELECT_MASK 0x003F0000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_5_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_6                0x000C0418
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_6_WIDTH          32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_6_MASK           0x003F003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_SELECT_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_SELECT_MASK 0x003F0000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_6_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_7                0x000C041C
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_7_WIDTH          32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_7_MASK           0x003F003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_SELECT_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_SELECT_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_SELECT_MASK 0x003F0000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_SELECT_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_VALUE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_VALUE_WIDTH 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_VALUE_MASK 0x0000003F
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_EVENT_SELECTION_7_LOCK_VALUE_DEFVAL 0x3F

#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0                       0x000C0420
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_WIDTH                 32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_MASK                  0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_31_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_31_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_31_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_31_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_30_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_30_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_30_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_30_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_29_LSB 29
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_29_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_29_MASK 0x20000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_29_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_28_LSB 28
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_28_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_28_MASK 0x10000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_28_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_27_LSB 27
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_27_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_27_MASK 0x08000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_27_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_26_LSB 26
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_26_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_26_MASK 0x04000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_26_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_25_LSB 25
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_25_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_25_MASK 0x02000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_25_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_24_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_24_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_24_MASK 0x01000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_24_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_23_LSB 23
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_23_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_23_MASK 0x00800000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_23_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_22_LSB 22
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_22_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_22_MASK 0x00400000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_22_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_21_LSB 21
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_21_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_21_MASK 0x00200000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_21_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_20_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_20_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_20_MASK 0x00100000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_20_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_19_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_19_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_19_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_19_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_18_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_18_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_18_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_18_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_17_LSB 17
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_17_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_17_MASK 0x00020000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_17_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_16_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_16_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_16_MASK 0x00010000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_16_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_15_LSB 15
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_15_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_15_MASK 0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_15_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_14_LSB 14
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_14_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_14_MASK 0x00004000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_14_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_13_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_13_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_13_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_13_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_12_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_12_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_12_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_12_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_11_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_11_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_11_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_11_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_10_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_10_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_10_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_10_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_9_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_9_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_9_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_9_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_8_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_8_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_8_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_8_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_7_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_7_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_7_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_7_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_6_LSB 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_6_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_6_MASK 0x00000040
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_6_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_5_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_5_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_5_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_5_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_4_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_4_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_4_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_4_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_3_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_3_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_3_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_3_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_2_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_2_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_2_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_2_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_1_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_1_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_1_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_0_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_0_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_0_LOCK_OVERFLOW_0_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1                       0x000C0424
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_WIDTH                 32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_MASK                  0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_63_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_63_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_63_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_63_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_62_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_62_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_62_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_62_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_61_LSB 29
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_61_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_61_MASK 0x20000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_61_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_60_LSB 28
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_60_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_60_MASK 0x10000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_60_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_59_LSB 27
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_59_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_59_MASK 0x08000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_59_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_58_LSB 26
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_58_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_58_MASK 0x04000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_58_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_57_LSB 25
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_57_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_57_MASK 0x02000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_57_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_56_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_56_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_56_MASK 0x01000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_56_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_55_LSB 23
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_55_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_55_MASK 0x00800000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_55_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_54_LSB 22
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_54_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_54_MASK 0x00400000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_54_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_53_LSB 21
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_53_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_53_MASK 0x00200000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_53_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_52_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_52_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_52_MASK 0x00100000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_52_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_51_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_51_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_51_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_51_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_50_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_50_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_50_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_50_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_49_LSB 17
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_49_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_49_MASK 0x00020000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_49_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_48_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_48_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_48_MASK 0x00010000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_48_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_47_LSB 15
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_47_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_47_MASK 0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_47_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_46_LSB 14
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_46_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_46_MASK 0x00004000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_46_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_45_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_45_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_45_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_45_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_44_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_44_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_44_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_44_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_43_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_43_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_43_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_43_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_42_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_42_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_42_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_42_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_41_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_41_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_41_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_41_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_40_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_40_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_40_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_40_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_39_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_39_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_39_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_39_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_38_LSB 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_38_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_38_MASK 0x00000040
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_38_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_37_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_37_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_37_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_37_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_36_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_36_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_36_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_36_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_35_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_35_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_35_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_35_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_34_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_34_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_34_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_34_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_33_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_33_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_33_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_33_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_32_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_32_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_32_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_OVERFLOW_1_LOCK_OVERFLOW_32_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0                      0x000C0428
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_MASK                 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_31_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_31_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_31_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_31_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_30_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_30_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_30_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_30_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_29_LSB 29
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_29_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_29_MASK 0x20000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_29_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_28_LSB 28
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_28_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_28_MASK 0x10000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_28_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_27_LSB 27
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_27_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_27_MASK 0x08000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_27_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_26_LSB 26
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_26_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_26_MASK 0x04000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_26_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_25_LSB 25
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_25_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_25_MASK 0x02000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_25_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_24_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_24_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_24_MASK 0x01000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_24_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_23_LSB 23
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_23_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_23_MASK 0x00800000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_23_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_22_LSB 22
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_22_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_22_MASK 0x00400000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_22_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_21_LSB 21
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_21_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_21_MASK 0x00200000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_21_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_20_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_20_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_20_MASK 0x00100000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_20_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_19_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_19_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_19_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_19_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_18_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_18_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_18_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_18_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_17_LSB 17
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_17_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_17_MASK 0x00020000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_17_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_16_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_16_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_16_MASK 0x00010000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_16_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_15_LSB 15
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_15_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_15_MASK 0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_15_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_14_LSB 14
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_14_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_14_MASK 0x00004000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_14_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_13_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_13_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_13_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_13_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_12_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_12_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_12_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_12_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_11_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_11_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_11_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_11_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_10_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_10_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_10_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_10_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_9_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_9_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_9_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_9_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_8_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_8_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_8_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_8_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_7_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_7_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_7_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_7_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_6_LSB 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_6_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_6_MASK 0x00000040
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_6_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_5_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_5_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_5_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_5_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_4_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_4_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_4_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_4_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_3_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_3_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_3_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_3_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_2_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_2_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_2_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_2_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_1_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_1_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_1_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_1_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_0_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_0_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_0_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_0_LOCK_UNDERFLOW_0_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1                      0x000C042C
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_WIDTH                32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_MASK                 0xFFFFFFFF
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_63_LSB 31
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_63_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_63_MASK 0x80000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_63_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_62_LSB 30
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_62_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_62_MASK 0x40000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_62_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_61_LSB 29
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_61_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_61_MASK 0x20000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_61_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_60_LSB 28
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_60_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_60_MASK 0x10000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_60_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_59_LSB 27
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_59_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_59_MASK 0x08000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_59_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_58_LSB 26
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_58_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_58_MASK 0x04000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_58_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_57_LSB 25
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_57_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_57_MASK 0x02000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_57_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_56_LSB 24
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_56_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_56_MASK 0x01000000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_56_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_55_LSB 23
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_55_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_55_MASK 0x00800000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_55_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_54_LSB 22
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_54_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_54_MASK 0x00400000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_54_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_53_LSB 21
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_53_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_53_MASK 0x00200000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_53_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_52_LSB 20
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_52_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_52_MASK 0x00100000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_52_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_51_LSB 19
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_51_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_51_MASK 0x00080000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_51_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_50_LSB 18
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_50_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_50_MASK 0x00040000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_50_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_49_LSB 17
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_49_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_49_MASK 0x00020000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_49_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_48_LSB 16
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_48_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_48_MASK 0x00010000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_48_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_47_LSB 15
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_47_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_47_MASK 0x00008000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_47_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_46_LSB 14
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_46_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_46_MASK 0x00004000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_46_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_45_LSB 13
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_45_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_45_MASK 0x00002000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_45_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_44_LSB 12
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_44_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_44_MASK 0x00001000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_44_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_43_LSB 11
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_43_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_43_MASK 0x00000800
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_43_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_42_LSB 10
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_42_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_42_MASK 0x00000400
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_42_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_41_LSB 9
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_41_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_41_MASK 0x00000200
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_41_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_40_LSB 8
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_40_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_40_MASK 0x00000100
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_40_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_39_LSB 7
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_39_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_39_MASK 0x00000080
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_39_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_38_LSB 6
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_38_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_38_MASK 0x00000040
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_38_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_37_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_37_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_37_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_37_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_36_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_36_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_36_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_36_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_35_LSB 3
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_35_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_35_MASK 0x00000008
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_35_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_34_LSB 2
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_34_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_34_MASK 0x00000004
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_34_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_33_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_33_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_33_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_33_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_32_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_32_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_32_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_LOCKS_UNDERFLOW_1_LOCK_UNDERFLOW_32_DEFVAL 0x0

#define XAIEMLGBL_MEM_TILE_MODULE_LOCK_REQUEST                           0x000D0000
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK_REQUEST_WIDTH                     32
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK_REQUEST_MASK                      0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK_REQUEST_REQUEST_RESULT_LSB      0
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK_REQUEST_REQUEST_RESULT_WIDTH    1
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK_REQUEST_REQUEST_RESULT_MASK     0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_LOCK_REQUEST_REQUEST_RESULT_DEFVAL   0x0

#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL                   0x000FFF00
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_WIDTH             32
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_MASK              0x00000033
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_DMA_ADAPTIVE_CLOCK_GATE_LSB 5
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_DMA_ADAPTIVE_CLOCK_GATE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_DMA_ADAPTIVE_CLOCK_GATE_MASK 0x00000020
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_DMA_ADAPTIVE_CLOCK_GATE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_LSB 4
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_MASK 0x00000010
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_ADAPTIVE_CLOCK_GATE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_MEMORY_MODULE_CLOCK_ENABLE_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_MEMORY_MODULE_CLOCK_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_MEMORY_MODULE_CLOCK_ENABLE_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_MEMORY_MODULE_CLOCK_ENABLE_DEFVAL 0x1
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_CLOCK_ENABLE_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_CLOCK_ENABLE_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_CLOCK_ENABLE_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_CLOCK_CONTROL_STREAM_SWITCH_CLOCK_ENABLE_DEFVAL 0x1

#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_RESET_CONTROL                   0x000FFF10
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_RESET_CONTROL_WIDTH             32
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_RESET_CONTROL_MASK              0x00000003
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_RESET_CONTROL_MEMORY_RESET_LSB 1
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_RESET_CONTROL_MEMORY_RESET_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_RESET_CONTROL_MEMORY_RESET_MASK 0x00000002
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_RESET_CONTROL_MEMORY_RESET_DEFVAL 0x0
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_RESET_CONTROL_STREAM_SWITCH_RESET_LSB 0
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_RESET_CONTROL_STREAM_SWITCH_RESET_WIDTH 1
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_RESET_CONTROL_STREAM_SWITCH_RESET_MASK 0x00000001
#define XAIEMLGBL_MEM_TILE_MODULE_MODULE_RESET_CONTROL_STREAM_SWITCH_RESET_DEFVAL 0x0

#endif /* XAIEMLGBL_PARAMS_H */
/** @} */
