[ICO]NameLast modifiedSize
[PARENTDIR]Parent Directory  -
[ ]vck190-pl-aie-gmio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 2.3M
[ ]zcu104-pl-vcu-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 2.3M
[ ]vek280-pl-aie-gmio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 1.9M
[ ]vrk160-pl-aie-gmio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 863K
[ ]vek280-pl-vdu-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 434K
[ ]zcu102-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 370K
[ ]vpk180-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 365K
[ ]vek385-pl-aie-gmio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 350K
[ ]zcu104-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 342K
[ ]zcu208-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 341K
[ ]zcu111-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 338K
[ ]zcu106-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 331K
[ ]vrk165-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 281K
[ ]vrk160-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 281K
[ ]vpk120-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 281K
[ ]vek280-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 266K
[ ]zcu106-pl-vcu-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 247K
[ ]vck190-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 238K
[ ]vmk180-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 237K
[ ]zc706-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 131K
[ ]zc702-pl-bram-gpio-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 121K
[ ]versal-2ve-2vm-vek385-pl-axi_uartlite-fw_2026.1_0308_1_03090000.tar.gz2026-05-30 03:20 95K

© Copyright 2019 Xilinx Inc.