This design is targeted for xczu28dr board (part number: xczu28dr-ffvg1517-2-e)

Zynq UltraScale+ Design Summary

Device	xczu28dr
SpeedGrade	-2
Part	xczu28dr-ffvg1517-2-e
Description	Zynq UltraScale+ PS Configuration Report
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction	Drive Strength(mA)
MIO 0	Quad SPI Flash	sclk_out	cmos	fast	pullup	out	12
MIO 1	Quad SPI Flash	miso_mo1	cmos	fast	pullup	inout	12
MIO 2	Quad SPI Flash	mo2	cmos	fast	pullup	inout	12
MIO 3	Quad SPI Flash	mo3	cmos	fast	pullup	inout	12
MIO 4	Quad SPI Flash	mosi_mi0	cmos	fast	pullup	inout	12
MIO 5	Quad SPI Flash	n_ss_out	cmos	fast	pullup	out	12
MIO 6	Feedback Clk	clk_for_lpbk	cmos	fast	pullup	out	12
MIO 7	Quad SPI Flash	n_ss_out_upper	cmos	fast	pullup	out	12
MIO 8	Quad SPI Flash	mo_upper[0]	cmos	fast	pullup	inout	12
MIO 9	Quad SPI Flash	mo_upper[1]	cmos	fast	pullup	inout	12
MIO 10	Quad SPI Flash	mo_upper[2]	cmos	fast	pullup	inout	12
MIO 11	Quad SPI Flash	mo_upper[3]	cmos	fast	pullup	inout	12
MIO 12	Quad SPI Flash	sclk_out_upper	cmos	fast	pullup	out	12
MIO 13	GPIO0 MIO	gpio0[13]	cmos	fast	pullup	inout	12
MIO 14	I2C 0	scl_out	cmos	fast	pullup	inout	12
MIO 15	I2C 0	sda_out	cmos	fast	pullup	inout	12
MIO 16	I2C 1	scl_out	cmos	fast	pullup	inout	12
MIO 17	I2C 1	sda_out	cmos	fast	pullup	inout	12
MIO 18	UART 0	rxd	cmos	fast	pullup	in	12
MIO 19	UART 0	txd	cmos	fast	pullup	out	12
MIO 20	GPIO0 MIO	gpio0[20]	cmos	fast	pullup	inout	12
MIO 21	GPIO0 MIO	gpio0[21]	cmos	fast	pullup	inout	12
MIO 22	GPIO0 MIO	gpio0[22]	cmos	fast	pullup	inout	12
MIO 23	GPIO0 MIO	gpio0[23]	cmos	fast	pullup	inout	12
MIO 24	GPIO0 MIO	gpio0[24]	cmos	fast	pullup	inout	12
MIO 25	GPIO0 MIO	gpio0[25]	cmos	fast	pullup	inout	12
MIO 26	PMU GPI 0	gpi[0]	cmos	fast	pullup	in	12
MIO 27	DPAUX	dp_aux_data_out	cmos	fast	pullup	out	12
MIO 28	DPAUX	dp_hot_plug_detect	cmos	fast	pullup	in	12
MIO 29	DPAUX	dp_aux_data_oe	cmos	fast	pullup	out	12
MIO 30	DPAUX	dp_aux_data_in	cmos	fast	pullup	in	12
MIO 31	GPIO1 MIO	gpio1[31]	cmos	fast	pullup	inout	12
MIO 32	PMU GPO 0	gpo[0]	cmos	fast	pullup	out	12
MIO 33	PMU GPO 1	gpo[1]	cmos	fast	pullup	out	12
MIO 34	PMU GPO 2	gpo[2]	cmos	fast	pullup	out	12
MIO 35	PMU GPO 3	gpo[3]	cmos	fast	pullup	out	12
MIO 36	PMU GPO 4	gpo[4]	cmos	fast	pullup	out	12
MIO 37	PMU GPO 5	gpo[5]	cmos	fast	pullup	out	12
MIO 38	GPIO1 MIO	gpio1[38]	cmos	fast	pullup	inout	12
MIO 39	SD 1	sdio1_data_out[4]	cmos	fast	pullup	inout	12
MIO 40	SD 1	sdio1_data_out[5]	cmos	fast	pullup	inout	12
MIO 41	SD 1	sdio1_data_out[6]	cmos	fast	pullup	inout	12
MIO 42	SD 1	sdio1_data_out[7]	cmos	fast	pullup	inout	12
MIO 43	GPIO1 MIO	gpio1[43]	cmos	fast	pullup	inout	12
MIO 44	GPIO1 MIO	gpio1[44]	cmos	fast	pullup	inout	12
MIO 45	SD 1	sdio1_cd_n	cmos	fast	pullup	in	12
MIO 46	SD 1	sdio1_data_out[0]	cmos	fast	pullup	inout	12
MIO 47	SD 1	sdio1_data_out[1]	cmos	fast	pullup	inout	12
MIO 48	SD 1	sdio1_data_out[2]	cmos	fast	pullup	inout	12
MIO 49	SD 1	sdio1_data_out[3]	cmos	fast	pullup	inout	12
MIO 50	SD 1	sdio1_cmd_out	cmos	fast	pullup	inout	12
MIO 51	SD 1	sdio1_clk_out	cmos	fast	pullup	out	12
MIO 52	USB 0	ulpi_clk_in	cmos	fast	pullup	in	12
MIO 53	USB 0	ulpi_dir	cmos	fast	pullup	in	12
MIO 54	USB 0	ulpi_tx_data[2]	cmos	fast	pullup	inout	12
MIO 55	USB 0	ulpi_nxt	cmos	fast	pullup	in	12
MIO 56	USB 0	ulpi_tx_data[0]	cmos	fast	pullup	inout	12
MIO 57	USB 0	ulpi_tx_data[1]	cmos	fast	pullup	inout	12
MIO 58	USB 0	ulpi_stp	cmos	fast	pullup	out	12
MIO 59	USB 0	ulpi_tx_data[3]	cmos	fast	pullup	inout	12
MIO 60	USB 0	ulpi_tx_data[4]	cmos	fast	pullup	inout	12
MIO 61	USB 0	ulpi_tx_data[5]	cmos	fast	pullup	inout	12
MIO 62	USB 0	ulpi_tx_data[6]	cmos	fast	pullup	inout	12
MIO 63	USB 0	ulpi_tx_data[7]	cmos	fast	pullup	inout	12
MIO 64	Gem 3	rgmii_tx_clk	cmos	fast	pullup	out	12
MIO 65	Gem 3	rgmii_txd[0]	cmos	fast	pullup	out	12
MIO 66	Gem 3	rgmii_txd[1]	cmos	fast	pullup	out	12
MIO 67	Gem 3	rgmii_txd[2]	cmos	fast	pullup	out	12
MIO 68	Gem 3	rgmii_txd[3]	cmos	fast	pullup	out	12
MIO 69	Gem 3	rgmii_tx_ctl	cmos	fast	pullup	out	12
MIO 70	Gem 3	rgmii_rx_clk	cmos	fast	pullup	in	12
MIO 71	Gem 3	rgmii_rxd[0]	cmos	fast	pullup	in	12
MIO 72	Gem 3	rgmii_rxd[1]	cmos	fast	pullup	in	12
MIO 73	Gem 3	rgmii_rxd[2]	cmos	fast	pullup	in	12
MIO 74	Gem 3	rgmii_rxd[3]	cmos	fast	pullup	in	12
MIO 75	Gem 3	rgmii_rx_ctl	cmos	fast	pullup	in	12
MIO 76	MDIO 3	gem3_mdc	cmos	fast	pullup	out	12
MIO 77	MDIO 3	gem3_mdio_out	cmos	fast	pullup	inout	12

PS Clocks information

PSS REF CLK : 33.333

Name	Source	Input Frequency (MHz)
APLL	PSS_REF_CLK	2399.976
DPLL	PSS_REF_CLK	2133.312
VPLL	PSS_REF_CLK	2366.643
RPLL	PSS_REF_CLK	2333.310
IOPLL	PSS_REF_CLK	2333.310

Peripheral	Source	Actual Frequency (MHz)
GEM3 freq (MHz)	IOPLL	124.998749
USB0 freq (MHz)	IOPLL	249.997498
QSPI freq (MHz)	IOPLL	124.998749
SDIO1 freq (MHz)	IOPLL	187.498123
UART0 freq (MHz)	IOPLL	99.999001
UART1 freq (MHz)	IOPLL	99.999001
I2C0 freq (MHz)	IOPLL	99.999001
I2C1 freq (MHz)	IOPLL	99.999001
CPU_R5 freq (MHz)	IOPLL	499.994995
IOU_SWITCH freq (MHz)	IOPLL	249.997498
LPD_SWITCH freq (MHz)	IOPLL	499.994995
LPD_LSBUS freq (MHz)	IOPLL	99.999001
GEM_TSU freq (MHz)	IOPLL	249.997498
TIMESTAMP freq (MHz)	IOPLL	99.999001
PSU__CRL_APB__USB3_REF_CTRL__freqmhz	IOPLL	19.999800
PCAP freq (MHz)	IOPLL	187.498123
DBG_LPD freq (MHz)	IOPLL	249.997498
ADMA freq (MHz)	IOPLL	499.994995
PL0 freq (MHz)	IOPLL	99.999001
PL1 freq (MHz)	IOPLL	24.999750
PL2 freq (MHz)	IOPLL	299.997009
PL3 freq (MHz)	IOPLL	374.996246
AMS freq (MHz)	IOPLL	51.723621
ACPU freq (MHz)	APLL	1199.988037
DBG FPD freq (MHz)	IOPLL	249.997498
DP VIDEO freq (MHz)	VPLL	295.830383
DP AUDIO freq (MHz)	RPLL	24.305313
DP STC freq (MHz)	RPLL	25.925667
SATA freq (MHz)	IOPLL	249.997498
DDR_CTRL freq MHz)	DPLL	533.328003
GDMA freq (MHz)	APLL	599.994019
DPDMA freq (MHz)	APLL	599.994019
TOPSW_MAIN freq (MHz)	DPLL	533.328003
TOPSW_LSBUS freq (MHz)	IOPLL	99.999001
DBG TSTMP freq (MHz)	IOPLL	249.997498

DDR Memory information

Parameter name	Value	Description
ENABLE	1	Enable the PS DDR Controller
DDR Interface freq (MHz)	1067	--
MEMORY TYPE	DDR 4	Type of memory interface
DM DBI	UDIMM
BUS WIDTH	64 Bit	Data width of DDR interface, not including ECC data width
ECC	Disabled	Enables error correction code support
SPEED BIN	DDR4_2133P	Speed Bin
CL	15	Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL	14	CAS write latency setting in memory clock cycles
DDR AL	0	Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD	15	tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP	15	Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC	46.5	Row cycle time (ns)
T RAS MIN	33	Minimum number of memory clock cycles required between an Active and Precharge command
T FAW	21.0	Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH	8 Bits	Width of individual DRAM components
DEVICE CAPACITY	4096 MBits	Storage capacity of individual DRAM components
BG ADDR COUNT	2	Number of bank group address pins
RANK ADDR COUNT	0	Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT	2	Number of bank address pins
ROW ADDR COUNT	15	Number of row address pins
COL ADDR COUNT	10	Number of column address bits
C_DDR_RAM_HIGHADDR	0xFFFFFFFF	--

GT lanes information

Protocol	GT lane#	Ref Clk Sel	Ref freq (MHz)
DP	GT Lane0	Ref Clk1	27
USB0	GT Lane2	Ref Clk2	26
SATA	GT Lane3	Ref Clk3	125