/dts-v1/;
/plugin/;
&fpga {
	firmware-name = "vpl_gen_fixed_pld.pdi";
	misc_clk_0: misc_clk_0 {
		compatible = "fixed-clock";
		clock-frequency = <78125000>;
		#clock-cells = <0>;
	};
};

&amba {
	axi_intc_0: interrupt-controller@a4000000 {
		#interrupt-cells = <2>;
		interrupts = < 0 84 4 >;
		xlnx,sense-of-irq-edge-type = "Rising";
		xlnx,edk-special = "INTR_CTRL";
		xlnx,kind-of-intr = <0x7fff>;
		xlnx,kind-of-edge = <0xffffffff>;
		xlnx,irq-is-level = <1>;
		xlnx,has-ivr = <1>;
		compatible = "xlnx,axi-intc-4.1" , "xlnx,xps-intc-1.00.a";
		xlnx,disable-synchronizers = <0>;
		xlnx,kind-of-lvl = <0xffffffff>;
		xlnx,ivar-reset-value = <0x10>;
		xlnx,irq-active = <0x1>;
		interrupt-parent = <&gic>;
		xlnx,en-cascade-mode = <0>;
		xlnx,ip-name = "axi_intc";
		xlnx,has-ilr = <0>;
		reg = <0x0 0xa4000000 0x0 0x10000>;
		xlnx,addr-width = <0x20>;
		clocks = <&misc_clk_0>;
		xlnx,s-axi-aclk-freq-mhz = <0x4a817c8>;
		xlnx,num-sw-intr = <0>;
		xlnx,irq-connection = <1>;
		xlnx,num-intr-inputs = <0x20>;
		xlnx,has-sie = <1>;
		xlnx,enable-async = <0>;
		xlnx,has-cie = <1>;
		xlnx,num-sync-ff = <2>;
		xlnx,edk-iptype = "PERIPHERAL";
		xlnx,mb-clk-not-connected = <1>;
		xlnx,has-ipr = <1>;
		xlnx,sense-of-irq-level-type = "Active_High";
		xlnx,cascade-master = <0>;
		xlnx,processor-clk-freq-mhz = <100>;
		xlnx,is-fast = <0x0>;
		clock-names = "s_axi_aclk";
		xlnx,has-fast = <0>;
		xlnx,ivar-rst-val = <0x10>;
		interrupt-controller;
		interrupt-names = "irq";
		xlnx,async-intr = <0xffffffff>;
		xlnx,name = "axi_intc_0";
	};
	ai_engine_0: ai_engine@20000000000 {
		xlnx,num-mi-axi = <8>;
		compatible = "xlnx,ai-engine-2.0" , "xlnx,ai-engine-v2.0";
		xlnx,aie-ref-clk-freqmhz = <0x1fc9f08>;
		xlnx,aie-col-dict = "col00 0x20000000000 col01 0x20002000000 col02 0x20004000000 col03 0x20006000000 col04 0x20008000000 col05 0x2000A000000 col06 0x2000C000000 col07 0x2000E000000 col08 0x20010000000 col09 0x20012000000 col10 0x20014000000 col11 0x20016000000 col12 0x20018000000 col13 0x2001A000000 col14 0x2001C000000 col15 0x2001E000000 col16 0x20020000000 col17 0x20022000000 col18 0x20024000000 col19 0x20026000000 col20 0x20028000000 col21 0x2002A000000 col22 0x2002C000000 col23 0x2002E000000 col24 0x20030000000 col25 0x20032000000 col26 0x20034000000 col27 0x20036000000 col28 0x20038000000 col29 0x2003A000000 col30 0x2003C000000 col31 0x2003E000000 col32 0x20040000000 col33 0x20042000000 col34 0x20044000000 col35 0x20046000000 col36 0x20048000000 col37 0x2004A000000";
		xlnx,num-mi-axis = <0>;
		xlnx,en-addr-virtualization = <0>;
		xlnx,aie-max-freq = <1250>;
		xlnx,aie-gen = /bits/ 8 <0x2>;
		xlnx,mem-rows = /bits/ 8 <1 2>;
		xlnx,mi-destid-pins;
		xlnx,ip-name = "ai_engine";
		#size-cells = <2>;
		xlnx,num-si-axi = <1>;
		xlnx,fast-pm-write;
		reg = <0x00000200 0x00000000 0x00000001 0x00000000>;
		clocks = <&aie_core_ref_clk_0>;
		xlnx,num-noc-axis-clks = <0>;
		ranges;
		xlnx,num-clks = <0>;
		xlnx,partition-enabled = <0>;
		#address-cells = <2>;
		xlnx,num-si-axis = <0>;
		xlnx,name-mi-axi = "M00_AXI";
		xlnx,num-column = <1>;
		xlnx,aie-core-ref-ctrl-freqmhz = <1250>;
		xlnx,clk-names = "aclk0";
		xlnx,fast-dm-write;
		xlnx,edk-iptype = "PERIPHERAL";
		xlnx,selected-nsu = <0>;
		xlnx,available-nsu = "NOC_NSU128_X1Y6 0x20000000000 NOC_NSU128_X2Y6 0x20002000000 NOC_NSU128_X3Y6 0x20008000000 NOC_NSU128_X4Y6 0x2000A000000 NOC_NSU128_X5Y6 0x20018000000 NOC_NSU128_X6Y6 0x20020000000 NOC_NSU128_X7Y6 0x2002C000000 NOC_NSU128_X8Y6 0x20032000000 NOC_NSU128_X9Y6 0x2003E000000 NOC_NSU128_X10Y6 0x20042000000 NOC_NSU128_X11Y6 0x20046000000 NOC_NSU128_X12Y6 0x2004A000000";
		clock-names = "aclk0";
		power-domains = <&versal_firmware 0x18800000>;
		xlnx,num-trig-in = <0>;
		xlnx,nsu-dict = "NOC_NSU128_X1Y6 0x20000000000 NOC_NSU128_X2Y6 0x20002000000 NOC_NSU128_X3Y6 0x20008000000 NOC_NSU128_X4Y6 0x2000A000000 NOC_NSU128_X5Y6 0x20018000000 NOC_NSU128_X6Y6 0x20020000000 NOC_NSU128_X7Y6 0x2002C000000 NOC_NSU128_X8Y6 0x20032000000 NOC_NSU128_X9Y6 0x2003E000000 NOC_NSU128_X10Y6 0x20042000000 NOC_NSU128_X11Y6 0x20046000000 NOC_NSU128_X12Y6 0x2004A000000";
		xlnx,en-ext-rst = <1>;
		xlnx,num-trig-out = <0>;
		xlnx,core-rows = /bits/ 8 <3 8>;
		xlnx,shim-rows = /bits/ 8 <0 1>;
		xlnx,name-si-axi = "S00_AXI";
		xlnx,start-column = <0>;
		xlnx,name = "ai_engine_0";
		xlnx,aie-site = "AIE_ML";
		aie_aperture_0: aie_aperture@20000000000 {
			xlnx,device-name = <0>;
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x94 0x4>, <0x0 0x95 0x4>, <0x0 0x96 0x4>;
			#address-cells = <2>;
			power-domains = <&versal_firmware 0x18800000>;
			xlnx,node-id = <0x18800000>;
			#size-cells = <2>;
			interrupt-names = "interrupt1" , "interrupt2" , "interrupt3";
			reg = <0x00000200 0x00000000 0x00000001 0x00000000>;
			xlnx,columns = < 0 38 >;
		};
	};
	aie_core_ref_clk_0: aie_core_ref_clk_0 {
		compatible = "fixed-clock";
		clock-frequency = <1250000000>;
		#clock-cells = <0>;
	};
	zyxclmm_drm {
		compatible = "xlnx,zocl-versal";
		interrupts-extended = <&axi_intc_0 0 4>, <&axi_intc_0 1 4>, <&axi_intc_0 2 4>, <&axi_intc_0 3 4>, <&axi_intc_0 4 4>, <&axi_intc_0 5 4>, <&axi_intc_0 6 4>, <&axi_intc_0 7 4>, <&axi_intc_0 8 4>, <&axi_intc_0 9 4>, <&axi_intc_0 10 4>, <&axi_intc_0 11 4>, <&axi_intc_0 12 4>, <&axi_intc_0 13 4>, <&axi_intc_0 14 4>, <&axi_intc_0 15 4>, <&axi_intc_0 16 4>, <&axi_intc_0 17 4>, <&axi_intc_0 18 4>, <&axi_intc_0 19 4>, <&axi_intc_0 20 4>, <&axi_intc_0 21 4>, <&axi_intc_0 22 4>, <&axi_intc_0 23 4>, <&axi_intc_0 24 4>, <&axi_intc_0 25 4>, <&axi_intc_0 26 4>, <&axi_intc_0 27 4>, <&axi_intc_0 28 4>, <&axi_intc_0 29 4>, <&axi_intc_0 30 4>, <&axi_intc_0 31 4>;
	};
};
