Zynq UltraScale+ MPSoC PS configuration detail

Zynq UltraScale+ Summary Report
User Configurations
MIO Configurations

CLK Configurations

DDR Configurations

GT Configurations
This design is targeted for xczu4eg board (part number: xczu4eg-sfvc784-2-e)

## Zynq UltraScale+ Design Summary

Device | xczu4eg
SpeedGrade | -2
Part | xczu4eg-sfvc784-2-e
Description | Zynq UltraScale+ PS Configuration Report
Vendor | Xilinx

## MIO Table View

MIO Pin | Peripheral | Signal | IO Type | Speed | Pullup | Direction | Drive Strength(mA)
MIO 0 | GPIO0 MIO | gpio0[0] | cmos | fast | pullup | inout | 12
MIO 1 | GPIO0 MIO | gpio0[1] | cmos | fast | pullup | inout | 12
MIO 2 | GPIO0 MIO | gpio0[2] | cmos | fast | pullup | inout | 12
MIO 3 | GPIO0 MIO | gpio0[3] | cmos | fast | pullup | inout | 12
MIO 4 | GPIO0 MIO | gpio0[4] | cmos | fast | pullup | inout | 12
MIO 5 | GPIO0 MIO | gpio0[5] | cmos | fast | pullup | inout | 12
MIO 6 | GPIO0 MIO | gpio0[6] | cmos | fast | pullup | inout | 12
MIO 7 | GPIO0 MIO | gpio0[7] | cmos | fast | pullup | inout | 12
MIO 8 | GPIO0 MIO | gpio0[8] | cmos | fast | pullup | inout | 12
MIO 9 | GPIO0 MIO | gpio0[9] | cmos | fast | pullup | inout | 12
MIO 10 | GPIO0 MIO | gpio0[10] | cmos | fast | pullup | inout | 12
MIO 11 | GPIO0 MIO | gpio0[11] | cmos | fast | pullup | inout | 12
MIO 12 | GPIO0 MIO | gpio0[12] | cmos | fast | pullup | inout | 12
MIO 13 | GPIO0 MIO | gpio0[13] | cmos | fast | pullup | inout | 12
MIO 14 | GPIO0 MIO | gpio0[14] | cmos | fast | pullup | inout | 12
MIO 15 | GPIO0 MIO | gpio0[15] | cmos | fast | pullup | inout | 12
MIO 16 | GPIO0 MIO | gpio0[16] | cmos | fast | pullup | inout | 12
MIO 17 | GPIO0 MIO | gpio0[17] | cmos | fast | pullup | inout | 12
MIO 18 | GPIO0 MIO | gpio0[18] | cmos | fast | pullup | inout | 12
MIO 19 | GPIO0 MIO | gpio0[19] | cmos | fast | pullup | inout | 12
MIO 20 | GPIO0 MIO | gpio0[20] | cmos | fast | pullup | inout | 12
MIO 21 | GPIO0 MIO | gpio0[21] | cmos | fast | pullup | inout | 12
MIO 22 | GPIO0 MIO | gpio0[22] | cmos | fast | pullup | inout | 12
MIO 23 | GPIO0 MIO | gpio0[23] | cmos | fast | pullup | inout | 12
MIO 24 | GPIO0 MIO | gpio0[24] | cmos | fast | pullup | inout | 12
MIO 25 | GPIO0 MIO | gpio0[25] | cmos | fast | pullup | inout | 12
MIO 26 | GPIO1 MIO | gpio1[26] | cmos | fast | pullup | inout | 12
MIO 27 | GPIO1 MIO | gpio1[27] | cmos | fast | pullup | inout | 12
MIO 28 | GPIO1 MIO | gpio1[28] | cmos | fast | pullup | inout | 12
MIO 29 | GPIO1 MIO | gpio1[29] | cmos | fast | pullup | inout | 12
MIO 30 | GPIO1 MIO | gpio1[30] | cmos | fast | pullup | inout | 12
MIO 31 | GPIO1 MIO | gpio1[31] | cmos | fast | pullup | inout | 12
MIO 32 | GPIO1 MIO | gpio1[32] | cmos | fast | pullup | inout | 12
MIO 33 | GPIO1 MIO | gpio1[33] | cmos | fast | pullup | inout | 12
MIO 34 | I2C 0 | scl_out | cmos | fast | pullup | inout | 12
MIO 35 | I2C 0 | sda_out | cmos | fast | pullup | inout | 12
MIO 36 | I2C 1 | scl_out | cmos | fast | pullup | inout | 12
MIO 37 | I2C 1 | sda_out | cmos | fast | pullup | inout | 12
MIO 38 | UART 0 | rxd | cmos | fast | pullup | in | 12
MIO 39 | UART 0 | txd | cmos | fast | pullup | out | 12
MIO 40 | GPIO1 MIO | gpio1[40] | cmos | fast | pullup | inout | 12
MIO 41 | GPIO1 MIO | gpio1[41] | cmos | fast | pullup | inout | 12
MIO 42 | GPIO1 MIO | gpio1[42] | cmos | fast | pullup | inout | 12
MIO 43 | GPIO1 MIO | gpio1[43] | cmos | fast | pullup | inout | 12
MIO 44 | GPIO1 MIO | gpio1[44] | cmos | fast | pullup | inout | 12
MIO 45 | SD 1 | sdio1_cd_n | cmos | fast | pullup | in | 12
MIO 46 | SD 1 | sdio1_data_out[0] | cmos | fast | pullup | inout | 12
MIO 47 | SD 1 | sdio1_data_out[1] | cmos | fast | pullup | inout | 12
MIO 48 | SD 1 | sdio1_data_out[2] | cmos | fast | pullup | inout | 12
MIO 49 | SD 1 | sdio1_data_out[3] | cmos | fast | pullup | inout | 12
MIO 50 | SD 1 | sdio1_cmd_out | cmos | fast | pullup | inout | 12
MIO 51 | SD 1 | sdio1_clk_out | cmos | fast | pullup | out | 12
MIO 52 | GPIO2 MIO | gpio2[52] | cmos | fast | pullup | inout | 12
MIO 53 | GPIO2 MIO | gpio2[53] | cmos | fast | pullup | inout | 12
MIO 54 | GPIO2 MIO | gpio2[54] | cmos | fast | pullup | inout | 12
MIO 55 | GPIO2 MIO | gpio2[55] | cmos | fast | pullup | inout | 12
MIO 56 | GPIO2 MIO | gpio2[56] | cmos | fast | pullup | inout | 12
MIO 57 | GPIO2 MIO | gpio2[57] | cmos | fast | pullup | inout | 12
MIO 58 | GPIO2 MIO | gpio2[58] | cmos | fast | pullup | inout | 12
MIO 59 | GPIO2 MIO | gpio2[59] | cmos | fast | pullup | inout | 12
MIO 60 | GPIO2 MIO | gpio2[60] | cmos | fast | pullup | inout | 12
MIO 61 | GPIO2 MIO | gpio2[61] | cmos | fast | pullup | inout | 12
MIO 62 | GPIO2 MIO | gpio2[62] | cmos | fast | pullup | inout | 12
MIO 63 | GPIO2 MIO | gpio2[63] | cmos | fast | pullup | inout | 12
MIO 64 | GPIO2 MIO | gpio2[64] | cmos | fast | pullup | inout | 12
MIO 65 | GPIO2 MIO | gpio2[65] | cmos | fast | pullup | inout | 12
MIO 66 | GPIO2 MIO | gpio2[66] | cmos | fast | pullup | inout | 12
MIO 67 | GPIO2 MIO | gpio2[67] | cmos | fast | pullup | inout | 12
MIO 68 | GPIO2 MIO | gpio2[68] | cmos | fast | pullup | inout | 12
MIO 69 | GPIO2 MIO | gpio2[69] | cmos | fast | pullup | inout | 12
MIO 70 | GPIO2 MIO | gpio2[70] | cmos | fast | pullup | inout | 12
MIO 71 | GPIO2 MIO | gpio2[71] | cmos | fast | pullup | inout | 12
MIO 72 | GPIO2 MIO | gpio2[72] | cmos | fast | pullup | inout | 12
MIO 73 | GPIO2 MIO | gpio2[73] | cmos | fast | pullup | inout | 12
MIO 74 | GPIO2 MIO | gpio2[74] | cmos | fast | pullup | inout | 12
MIO 75 | GPIO2 MIO | gpio2[75] | cmos | fast | pullup | inout | 12
MIO 76 | MDIO 0 | gem0_mdc | cmos | fast | pullup | out | 12
MIO 77 | MDIO 0 | gem0_mdio_out | cmos | fast | pullup | inout | 12

## PS Clocks information

PSS REF CLK : 33.333

Name | Source | Input Frequency (MHz)
APLL | PSS_REF_CLK | 2399.976
DPLL | PSS_REF_CLK | 2133.312
VPLL | PSS_REF_CLK | 2366.643
RPLL | PSS_REF_CLK | 2333.310
IOPLL | PSS_REF_CLK | 2333.310

Peripheral | Source | Actual Frequency (MHz)
GEM0 freq (MHz) | IOPLL | 124.998749
SDIO1 freq (MHz) | IOPLL | 187.498123
UART0 freq (MHz) | IOPLL | 99.999001
I2C0 freq (MHz) | IOPLL | 99.999001
I2C1 freq (MHz) | IOPLL | 99.999001
CPU_R5 freq (MHz) | IOPLL | 499.994995
IOU_SWITCH freq (MHz) | IOPLL | 249.997498
LPD_SWITCH freq (MHz) | IOPLL | 499.994995
LPD_LSBUS freq (MHz) | IOPLL | 99.999001
GEM_TSU freq (MHz) | IOPLL | 249.997498
TIMESTAMP freq (MHz) | IOPLL | 99.999001
PCAP freq (MHz) | IOPLL | 187.498123
DBG_LPD freq (MHz) | IOPLL | 249.997498
ADMA freq (MHz) | IOPLL | 499.994995
PL0 freq (MHz) | IOPLL | 99.999001
PL1 freq (MHz) | IOPLL | 24.999750
PL2 freq (MHz) | IOPLL | 299.997009
PL3 freq (MHz) | IOPLL | 374.996246
AMS freq (MHz) | IOPLL | 51.723621
ACPU freq (MHz) | APLL | 1199.988037
DBG FPD freq (MHz) | IOPLL | 249.997498
DDR_CTRL freq MHz) | DPLL | 533.328003
GPU freq (MHz) | IOPLL | 499.994995
GDMA freq (MHz) | APLL | 599.994019
DPDMA freq (MHz) | APLL | 599.994019
TOPSW_MAIN freq (MHz) | DPLL | 533.328003
TOPSW_LSBUS freq (MHz) | IOPLL | 99.999001
DBG TSTMP freq (MHz) | IOPLL | 249.997498

## DDR Memory information

Parameter name | Value | Description
ENABLE | 1 | Enable the PS DDR Controller
DDR Interface freq (MHz) | 1067 | --
MEMORY TYPE | LPDDR 4 | Type of memory interface
DM DBI | Components |
BUS WIDTH | 32 Bit | Data width of DDR interface, not including ECC data width
ECC | Disabled | Enables error correction code support
SPEED BIN | LPDDR4_2133 | Speed Bin
CL | NA | Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL | NA | CAS write latency setting in memory clock cycles
DDR AL | 0 | Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD | 20 | tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP | 23 | Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC | 63 | Row cycle time (ns)
T RAS MIN | 42 | Minimum number of memory clock cycles required between an Active and Precharge command
T FAW | 40 | Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH | 32 Bits | Width of individual DRAM components
DEVICE CAPACITY | 16384 MBits | Storage capacity of individual DRAM components
BG ADDR COUNT | NA | Number of bank group address pins
RANK ADDR COUNT | 0 | Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT | 3 | Number of bank address pins
ROW ADDR COUNT | 16 | Number of row address pins
COL ADDR COUNT | 10 | Number of column address bits
C_DDR_RAM_HIGHADDR | 0x7FFFFFFF | --

## GT lanes information

Protocol | GT lane# | Ref Clk Sel | Ref freq (MHz)
Gem0 | GT Lane0 | Ref Clk0 | 125