/ {
	amba_pl: amba_pl {
		ranges;
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		firmware-name = "ve2302_pcie_qdma_base.pdi";
		fpga_PR: fpga-PR {
			ranges;
			compatible = "fpga-region";
			#address-cells = <2>;
			#size-cells = <2>;
		};
		misc_clk_0: misc_clk_0 {
			compatible = "fixed-clock";
			clock-frequency = <125000000>;
			#clock-cells = <0>;
		};
		blp_blp_logic_ert_support_axi_intc_0_31: interrupt-controller@20202020000 {
			#interrupt-cells = <2>;
			interrupts = < 0 93 1 >;
			xlnx,sense-of-irq-edge-type = "Rising";
			xlnx,edk-special = "INTR_CTRL";
			xlnx,kind-of-intr = <0x1>;
			xlnx,kind-of-edge = <0xffffffff>;
			xlnx,irq-is-level = <0>;
			xlnx,has-ivr = <1>;
			compatible = "xlnx,axi-intc-4.1" , "xlnx,xps-intc-1.00.a";
			xlnx,disable-synchronizers = <0>;
			xlnx,kind-of-lvl = <0xffffffff>;
			xlnx,ivar-reset-value = <0x10>;
			xlnx,irq-active = <0x1>;
			interrupt-parent = <&imux>;
			xlnx,rable = <0>;
			xlnx,en-cascade-mode = <0>;
			xlnx,ip-name = "axi_intc";
			xlnx,has-ilr = <0>;
			reg = <0x00000202 0x02020000 0x0 0x1000>;
			xlnx,addr-width = <0x20>;
			clocks = <&versal_clk 65>;
			xlnx,s-axi-aclk-freq-mhz = <0x5f5e0a4>;
			xlnx,num-sw-intr = <0>;
			xlnx,irq-connection = <1>;
			xlnx,num-intr-inputs = <0x20>;
			xlnx,has-sie = <1>;
			xlnx,enable-async = <0>;
			xlnx,has-cie = <1>;
			xlnx,num-sync-ff = <2>;
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,mb-clk-not-connected = <1>;
			xlnx,has-ipr = <1>;
			xlnx,sense-of-irq-level-type = "Active_High";
			xlnx,cascade-master = <0>;
			xlnx,processor-clk-freq-mhz = <100>;
			status = "okay";
			xlnx,is-fast = <0x0>;
			clock-names = "s_axi_aclk";
			xlnx,has-fast = <0>;
			xlnx,ivar-rst-val = <0x10>;
			interrupt-controller;
			interrupt-names = "irq";
			xlnx,async-intr = <0xffffffff>;
			xlnx,name = "blp_blp_logic_ert_support_axi_intc_0_31";
		};
		blp_blp_logic_axi_blp_dbg_hub: axi_dbg_hub@20105000000 {
			compatible = "xlnx,axi-dbg-hub-2.0";
			xlnx,rable = <0>;
			xlnx,core-name = "axi_dbg_hub_v2_0";
			xlnx,ip-name = "axi_dbg_hub";
			xlnx,addr-offset = <0x201 0x05000000>;
			xlnx,address-list = "Master0 /blp/cips/PMC_NOC_AXI_0/SEG_axi_blp_dbg_hub_Mem0 vlnv0 xilinx.com:ip:versal_cips:3.4 Address0 0x0000020105000000 Range0 0x0000000000200000 Master1 /blp/qdma_0/M_AXI/SEG_axi_blp_dbg_hub_Mem0 vlnv1 xilinx.com:ip:qdma:5.0 Address1 0x0000020105000000 Range1 0x0000000000200000 Master2 /blp/qdma_0/M_AXI_BRIDGE/SEG_axi_blp_dbg_hub_Mem0 vlnv2 xilinx.com:ip:qdma:5.0 Address2 0x0000020105000000 Range2 0x0000000000200000";
			xlnx,axi-addr-width = <64>;
			reg = <0x00000201 0x05000000 0x0 0x200000>;
			clocks = <&versal_clk 65>;
			xlnx,axi-id-width = <2>;
			xlnx,num-wr-outstanding-txn = <1>;
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,num-debug-cores = <0>;
			xlnx,addr-range = <0x200000>;
			xlnx,axis-tdata-width = <32>;
			status = "okay";
			xlnx,axi-data-width = <128>;
			clock-names = "aclk";
			xlnx,num-rd-outstanding-txn = <1>;
			xlnx,en-fallback = <0>;
			xlnx,name = "blp_blp_logic_axi_blp_dbg_hub";
		};
		blp_blp_logic_axi_firewall_user: axi_firewall@80001000 {
			xlnx,protocol = <2>;
			compatible = "xlnx,axi-firewall-1.2";
			xlnx,enable-pipelining = <1>;
			xlnx,enable-protocol-checks = <1>;
			xlnx,awuser-width = <0>;
			xlnx,has-rresp = <1>;
			xlnx,has-bresp = <1>;
			xlnx,supports-narrow = <0>;
			xlnx,read-write-mode = "READ_WRITE";
			xlnx,rable = <0>;
			xlnx,has-prot = <1>;
			xlnx,wdata-width = <32>;
			xlnx,ruser-width = <0>;
			xlnx,buser-width = <0>;
			xlnx,has-aclken = <0>;
			xlnx,ip-name = "axi_firewall";
			xlnx,num-write-threads = <1>;
			reg = <0x0 0x80001000 0x0 0x1000>;
			xlnx,addr-width = <64>;
			clocks = <&versal_clk 65>;
			xlnx,num-read-threads = <1>;
			xlnx,has-lock = <1>;
			xlnx,id-width = <0>;
			xlnx,enable-initial-delay = <1>;
			xlnx,has-wstrb = <1>;
			xlnx,has-aresetn = <1>;
			xlnx,wuser-width = <0>;
			xlnx,has-qos = <1>;
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,has-region = <1>;
			xlnx,has-cache = <1>;
			xlnx,num-write-outstanding = <32>;
			xlnx,enable-prescaler = <1>;
			xlnx,num-read-outstanding = <32>;
			status = "okay";
			clock-names = "aclk";
			xlnx,data-width = <32>;
			xlnx,aruser-width = <0>;
			xlnx,firewall-mode = <0>;
			xlnx,enable-ctl-clock = <0>;
			xlnx,has-burst = <1>;
			xlnx,rdata-width = <32>;
			xlnx,mask-err-resp = <1>;
			xlnx,enable-timeout-checks = <1>;
			xlnx,name = "blp_blp_logic_axi_firewall_user";
		};
		blp_blp_logic_axi_intc_gcq_apu: interrupt-controller@402031000 {
			#interrupt-cells = <2>;
			interrupts = < 0 95 1 >;
			xlnx,sense-of-irq-edge-type = "Rising";
			xlnx,edk-special = "INTR_CTRL";
			xlnx,kind-of-intr = <0x1>;
			xlnx,kind-of-edge = <0xffffffff>;
			xlnx,irq-is-level = <0>;
			xlnx,has-ivr = <1>;
			compatible = "xlnx,axi-intc-4.1" , "xlnx,xps-intc-1.00.a";
			xlnx,disable-synchronizers = <0>;
			xlnx,kind-of-lvl = <0xffffffff>;
			xlnx,ivar-reset-value = <0x10>;
			xlnx,irq-active = <0x1>;
			interrupt-parent = <&imux>;
			xlnx,rable = <0>;
			xlnx,en-cascade-mode = <0>;
			xlnx,ip-name = "axi_intc";
			xlnx,has-ilr = <0>;
			reg = <0x00000004 0x02031000 0x0 0x1000>;
			xlnx,addr-width = <0x20>;
			clocks = <&versal_clk 65>;
			xlnx,s-axi-aclk-freq-mhz = <0x5f5e0a4>;
			xlnx,num-sw-intr = <0>;
			xlnx,irq-connection = <1>;
			xlnx,num-intr-inputs = <0x1>;
			xlnx,has-sie = <1>;
			xlnx,enable-async = <0>;
			xlnx,has-cie = <1>;
			xlnx,num-sync-ff = <2>;
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,mb-clk-not-connected = <1>;
			xlnx,has-ipr = <1>;
			xlnx,sense-of-irq-level-type = "Active_High";
			xlnx,cascade-master = <0>;
			xlnx,processor-clk-freq-mhz = <100>;
			status = "okay";
			xlnx,is-fast = <0x0>;
			clock-names = "s_axi_aclk";
			xlnx,has-fast = <0>;
			xlnx,ivar-rst-val = <0x10>;
			interrupt-controller;
			interrupt-names = "irq";
			xlnx,async-intr = <0xfffffffe>;
			xlnx,name = "blp_blp_logic_axi_intc_gcq_apu";
		};
		blp_blp_logic_axi_intc_uart_apu: interrupt-controller@402030000 {
			#interrupt-cells = <2>;
			interrupts = < 0 94 1 >;
			xlnx,sense-of-irq-edge-type = "Rising";
			xlnx,edk-special = "INTR_CTRL";
			xlnx,kind-of-intr = <0x1>;
			xlnx,kind-of-edge = <0xffffffff>;
			xlnx,irq-is-level = <0>;
			xlnx,has-ivr = <1>;
			compatible = "xlnx,axi-intc-4.1" , "xlnx,xps-intc-1.00.a";
			xlnx,disable-synchronizers = <0>;
			xlnx,kind-of-lvl = <0xffffffff>;
			xlnx,ivar-reset-value = <0x10>;
			xlnx,irq-active = <0x1>;
			interrupt-parent = <&imux>;
			xlnx,rable = <0>;
			xlnx,en-cascade-mode = <0>;
			xlnx,ip-name = "axi_intc";
			xlnx,has-ilr = <0>;
			reg = <0x00000004 0x02030000 0x0 0x1000>;
			xlnx,addr-width = <0x20>;
			clocks = <&versal_clk 65>;
			xlnx,s-axi-aclk-freq-mhz = <0x5f5e0a4>;
			xlnx,num-sw-intr = <0>;
			xlnx,irq-connection = <1>;
			xlnx,num-intr-inputs = <0x2>;
			xlnx,has-sie = <1>;
			xlnx,enable-async = <0>;
			xlnx,has-cie = <1>;
			xlnx,num-sync-ff = <2>;
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,mb-clk-not-connected = <1>;
			xlnx,has-ipr = <1>;
			xlnx,sense-of-irq-level-type = "Active_High";
			xlnx,cascade-master = <0>;
			xlnx,processor-clk-freq-mhz = <100>;
			status = "okay";
			xlnx,is-fast = <0x0>;
			clock-names = "s_axi_aclk";
			xlnx,has-fast = <0>;
			xlnx,ivar-rst-val = <0x10>;
			interrupt-controller;
			interrupt-names = "irq";
			xlnx,async-intr = <0xfffffffe>;
			xlnx,name = "blp_blp_logic_axi_intc_uart_apu";
		};
		blp_blp_logic_axi_uart_apu0: serial@402020000 {
			interrupts = < 0 0 >;
			compatible = "xlnx,axi-uartlite-2.0" , "xlnx,xps-uartlite-1.00.a";
			xlnx,uartlite-board-interface = "Custom";
			xlnx,s-axi-aclk-freq-hz-d = <0x5f5e0a4>;
			interrupt-parent = <&blp_blp_logic_axi_intc_uart_apu>;
			xlnx,rable = <0>;
			xlnx,ip-name = "axi_uartlite";
			reg = <0x00000004 0x02020000 0x0 0x1000>;
			xlnx,baudrate = <230400>;
			clocks = <&versal_clk 65>;
			current-speed = <230400>;
			xlnx,use-parity = <0>;
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,odd-parity = <0>;
			status = "okay";
			clock-names = "s_axi_aclk";
			interrupt-names = "interrupt";
			xlnx,name = "blp_blp_logic_axi_uart_apu0";
			xlnx,data-bits = <8>;
			xlnx,parity = "No_Parity";
		};
		blp_blp_logic_axi_uart_mgmt_apu0: serial@20102021000 {
			compatible = "xlnx,axi-uartlite-2.0" , "xlnx,xps-uartlite-1.00.a";
			xlnx,uartlite-board-interface = "Custom";
			xlnx,s-axi-aclk-freq-hz-d = <0x5f5e0a4>;
			xlnx,rable = <0>;
			xlnx,ip-name = "axi_uartlite";
			reg = <0x00000201 0x02021000 0x0 0x1000>;
			xlnx,baudrate = <230400>;
			clocks = <&versal_clk 65>;
			current-speed = <230400>;
			xlnx,use-parity = <0>;
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,odd-parity = <0>;
			status = "okay";
			clock-names = "s_axi_aclk";
			xlnx,name = "blp_blp_logic_axi_uart_mgmt_apu0";
			xlnx,data-bits = <8>;
			xlnx,parity = "No_Parity";
		};
		blp_blp_logic_axi_uart_mgmt_rpu: serial@20102020000 {
			compatible = "xlnx,axi-uartlite-2.0" , "xlnx,xps-uartlite-1.00.a";
			xlnx,uartlite-board-interface = "Custom";
			xlnx,s-axi-aclk-freq-hz-d = <0x5f5e0a4>;
			xlnx,rable = <0>;
			xlnx,ip-name = "axi_uartlite";
			reg = <0x00000201 0x02020000 0x0 0x1000>;
			xlnx,baudrate = <230400>;
			clocks = <&versal_clk 65>;
			current-speed = <230400>;
			xlnx,use-parity = <0>;
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,odd-parity = <0>;
			status = "okay";
			clock-names = "s_axi_aclk";
			xlnx,name = "blp_blp_logic_axi_uart_mgmt_rpu";
			xlnx,data-bits = <8>;
			xlnx,parity = "No_Parity";
		};
		blp_blp_logic_axi_uart_rpu: serial@80021000 {
			interrupts = < 0 87 1 >;
			compatible = "xlnx,axi-uartlite-2.0" , "xlnx,xps-uartlite-1.00.a";
			xlnx,uartlite-board-interface = "Custom";
			xlnx,s-axi-aclk-freq-hz-d = <0x5f5e0a4>;
			interrupt-parent = <&imux>;
			xlnx,rable = <0>;
			xlnx,ip-name = "axi_uartlite";
			reg = <0x0 0x80021000 0x0 0x1000>;
			xlnx,baudrate = <230400>;
			clocks = <&versal_clk 65>;
			current-speed = <230400>;
			xlnx,use-parity = <0>;
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,odd-parity = <0>;
			status = "okay";
			clock-names = "s_axi_aclk";
			interrupt-names = "interrupt";
			xlnx,name = "blp_blp_logic_axi_uart_rpu";
			xlnx,data-bits = <8>;
			xlnx,parity = "No_Parity";
		};
		blp_blp_logic_base_clocking_force_reset_gpio: gpio@20102040000 {
			xlnx,gpio-board-interface = "Custom";
			compatible = "xlnx,axi-gpio-2.0" , "xlnx,xps-gpio-1.00.a";
			xlnx,all-outputs = <1>;
			#gpio-cells = <2>;
			xlnx,gpio-width = <1>;
			xlnx,rable = <0>;
			xlnx,dout-default = <0x0>;
			xlnx,is-dual = <1>;
			xlnx,ip-name = "axi_gpio";
			xlnx,tri-default-2 = <0xffffffff>;
			reg = <0x00000201 0x02040000 0x0 0x1000>;
			xlnx,all-inputs-2 = <1>;
			clocks = <&versal_clk 65>;
			xlnx,all-outputs-2 = <0>;
			gpio-controller;
			xlnx,interrupt-present = <0>;
			xlnx,gpio2-board-interface = "Custom";
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,dout-default-2 = <0x0>;
			status = "okay";
			xlnx,gpio2-width = <1>;
			clock-names = "s_axi_aclk";
			xlnx,tri-default = <0xffffffff>;
			xlnx,name = "blp_blp_logic_base_clocking_force_reset_gpio";
			xlnx,all-inputs = <0>;
		};
		blp_blp_logic_base_clocking_pr_reset_gpio: gpio@80020000 {
			xlnx,gpio-board-interface = "Custom";
			compatible = "xlnx,axi-gpio-2.0" , "xlnx,xps-gpio-1.00.a";
			xlnx,all-outputs = <1>;
			#gpio-cells = <2>;
			xlnx,gpio-width = <2>;
			xlnx,rable = <0>;
			xlnx,dout-default = <0x0>;
			xlnx,is-dual = <1>;
			xlnx,ip-name = "axi_gpio";
			xlnx,tri-default-2 = <0xffffffff>;
			reg = <0x0 0x80020000 0x0 0x1000>;
			xlnx,all-inputs-2 = <1>;
			clocks = <&versal_clk 65>;
			xlnx,all-outputs-2 = <0>;
			gpio-controller;
			xlnx,interrupt-present = <0>;
			xlnx,gpio2-board-interface = "Custom";
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,dout-default-2 = <0x0>;
			status = "okay";
			xlnx,gpio2-width = <2>;
			clock-names = "s_axi_aclk";
			xlnx,tri-default = <0xffffffff>;
			xlnx,name = "blp_blp_logic_base_clocking_pr_reset_gpio";
			xlnx,all-inputs = <0>;
		};
		blp_blp_logic_gcq_m2r: cmd_queue@20102010000 {
			compatible = "xlnx,cmd-queue-2.0";
			interrupts = < 0 84 1 >;
			xlnx,rable = <0>;
			interrupt-parent = <&imux>;
			xlnx,ip-name = "cmd_queue";
			reg = <0x0 0x80010000 0x0 0x1000 0x00000201 0x02010000 0x0 0x1000>;
			clocks = <&versal_clk 65>;
			xlnx,s01-addr-width = <12>;
			xlnx,edk-iptype = "PERIPHERAL";
			status = "okay";
			clock-names = "aclk";
			xlnx,s00-addr-width = <12>;
			interrupt-names = "irq_sq";
			xlnx,name = "blp_blp_logic_gcq_m2r";
		};
		blp_blp_logic_gcq_r2a: cmd_queue@80011000 {
			compatible = "xlnx,cmd-queue-2.0";
			interrupts = < 0 85 1 0 92 1 >;
			xlnx,rable = <0>;
			interrupt-parent = <&imux>;
			xlnx,ip-name = "cmd_queue";
			reg = <0x0 0x80011000 0x0 0x1000 0x00000004 0x02000000 0x0 0x1000>;
			clocks = <&versal_clk 65>;
			xlnx,s01-addr-width = <12>;
			xlnx,edk-iptype = "PERIPHERAL";
			status = "okay";
			clock-names = "aclk";
			xlnx,s00-addr-width = <12>;
			interrupt-names = "irq_cq" , "irq_sq";
			xlnx,name = "blp_blp_logic_gcq_r2a";
		};
		blp_blp_logic_gcq_u2a_0: cmd_queue@20202010000 {
			compatible = "xlnx,cmd-queue-2.0";
			interrupts = < 0 0 >;
			xlnx,rable = <0>;
			interrupt-parent = <&blp_blp_logic_axi_intc_gcq_apu>;
			xlnx,ip-name = "cmd_queue";
			reg = <0x00000004 0x02010000 0x0 0x1000 0x00000202 0x02010000 0x0 0x1000>;
			clocks = <&versal_clk 65>;
			xlnx,s01-addr-width = <12>;
			xlnx,edk-iptype = "PERIPHERAL";
			status = "okay";
			clock-names = "aclk";
			xlnx,s00-addr-width = <12>;
			interrupt-names = "irq_sq";
			xlnx,name = "blp_blp_logic_gcq_u2a_0";
		};
		blp_blp_logic_hw_discovery: hw_discovery@20102001000 {
			xlnx,xdevicefamily = "versal";
			xlnx,pf2-entry-major-version-5 = <0>;
			xlnx,pf0-entry-type-1 = <0x53>;
			xlnx,pf1-entry-bar-5 = <0>;
			xlnx,pf2-entry-major-version-6 = <0>;
			xlnx,pf0-entry-type-2 = <0x55>;
			xlnx,pf1-entry-bar-6 = <0>;
			xlnx,pf2-entry-major-version-7 = <0>;
			xlnx,pf2-entry-addr-0 = <0x0>;
			xlnx,pf0-entry-type-3 = <0x50>;
			xlnx,pf1-entry-bar-7 = <0>;
			xlnx,pf2-entry-major-version-8 = <0>;
			xlnx,pf2-entry-addr-1 = <0x0>;
			xlnx,pf0-entry-type-4 = <0x0>;
			xlnx,pf1-entry-bar-8 = <0>;
			xlnx,pf2-entry-major-version-9 = <0>;
			xlnx,pf2-entry-addr-2 = <0x0>;
			xlnx,pf0-entry-type-5 = <0x0>;
			xlnx,pf1-entry-bar-9 = <0>;
			xlnx,pf3-entry-major-version-10 = <0>;
			xlnx,pf2-entry-addr-3 = <0x0>;
			xlnx,pf0-entry-type-6 = <0x0>;
			xlnx,pf3-entry-major-version-11 = <0>;
			xlnx,pf2-entry-addr-4 = <0x0>;
			reg = <0x00000201 0x02001000 0x0 0x1000 0x00000202 0x02001000 0x0 0x1000>;
			xlnx,pf0-entry-type-7 = <0x0>;
			xlnx,pf3-entry-major-version-12 = <0>;
			xlnx,pf2-entry-addr-5 = <0x0>;
			xlnx,pf0-entry-type-8 = <0x0>;
			xlnx,pf3-entry-major-version-13 = <0>;
			xlnx,pf2-entry-addr-6 = <0x0>;
			xlnx,pf0-entry-type-9 = <0x0>;
			xlnx,pf3-entry-major-version-14 = <0>;
			xlnx,pf2-entry-addr-7 = <0x0>;
			xlnx,pf3-entry-major-version-15 = <0>;
			xlnx,pf2-entry-addr-8 = <0x0>;
			xlnx,pf2-entry-addr-9 = <0x0>;
			xlnx,pf2-entry-major-version-10 = <0>;
			xlnx,pf1-entry-bar-10 = <0>;
			xlnx,pf2-entry-major-version-11 = <0>;
			xlnx,pf1-entry-bar-11 = <0>;
			xlnx,pf2-entry-major-version-12 = <0>;
			xlnx,pf1-entry-bar-12 = <0>;
			xlnx,pf2-entry-major-version-13 = <0>;
			xlnx,pf1-entry-bar-13 = <0>;
			xlnx,pf2-entry-major-version-14 = <0>;
			xlnx,pf1-low-offset = <0x200100>;
			xlnx,pf0-s-axi-addr-width = <32>;
			xlnx,pf1-entry-bar-14 = <0>;
			xlnx,pf2-entry-major-version-15 = <0>;
			xlnx,pf1-entry-bar-15 = <0>;
			xlnx,pf1-entry-version-type-0 = <0x1>;
			xlnx,pf1-entry-major-version-10 = <0>;
			xlnx,pf1-entry-version-type-1 = <0x0>;
			xlnx,pf0-entry-rsvd0-0 = <0x0>;
			xlnx,pf1-entry-major-version-11 = <0>;
			xlnx,pf2-endpoint-names = <0>;
			xlnx,pf1-entry-version-type-2 = <0x0>;
			xlnx,pf0-entry-rsvd0-1 = <0x3>;
			xlnx,pf1-entry-major-version-12 = <0>;
			xlnx,pf1-entry-version-type-3 = <0x0>;
			xlnx,pf0-entry-rsvd0-2 = <0x0>;
			xlnx,pf1-entry-major-version-13 = <0>;
			xlnx,pf1-entry-version-type-4 = <0x0>;
			xlnx,pf0-entry-rsvd0-3 = <0x0>;
			xlnx,pf1-entry-major-version-14 = <0>;
			xlnx,pf3-entry-rsvd0-10 = <0x0>;
			xlnx,pf1-entry-version-type-5 = <0x0>;
			xlnx,pf0-entry-rsvd0-4 = <0x0>;
			xlnx,pf1-entry-major-version-15 = <0>;
			xlnx,pf3-entry-rsvd0-11 = <0x0>;
			xlnx,pf1-entry-version-type-6 = <0x0>;
			xlnx,pf0-entry-major-version-0 = <1>;
			xlnx,pf0-entry-rsvd0-5 = <0x0>;
			xlnx,pf1-entry-addr-0 = <0x2000000>;
			xlnx,pf3-entry-rsvd0-12 = <0x0>;
			xlnx,pf1-entry-version-type-7 = <0x0>;
			xlnx,pf0-entry-major-version-10 = <0>;
			xlnx,pf0-entry-major-version-1 = <1>;
			xlnx,pf0-entry-bar-0 = <0>;
			xlnx,pf0-entry-rsvd0-6 = <0x0>;
			xlnx,pf1-entry-addr-1 = <0x0>;
			xlnx,pf1-entry-addr-10 = <0x0>;
			xlnx,pf3-entry-rsvd0-13 = <0x0>;
			xlnx,pf1-entry-version-type-8 = <0x0>;
			xlnx,pf0-entry-major-version-11 = <0>;
			xlnx,pf0-entry-bar-1 = <0>;
			xlnx,pf0-entry-major-version-2 = <1>;
			xlnx,pf0-entry-rsvd0-7 = <0x0>;
			xlnx,pf1-entry-addr-11 = <0x0>;
			xlnx,pf1-entry-addr-2 = <0x0>;
			xlnx,pf3-entry-rsvd0-14 = <0x0>;
			xlnx,pf1-entry-version-type-9 = <0x0>;
			xlnx,pf0-entry-bar-2 = <0>;
			xlnx,pf0-entry-major-version-12 = <0>;
			xlnx,pf0-entry-major-version-3 = <0>;
			xlnx,pf0-entry-rsvd0-8 = <0x0>;
			xlnx,pf1-entry-addr-12 = <0x0>;
			xlnx,pf1-entry-addr-3 = <0x0>;
			xlnx,pf3-entry-rsvd0-15 = <0x0>;
			xlnx,pf0-entry-bar-3 = <0>;
			xlnx,pf0-entry-major-version-13 = <0>;
			xlnx,pf0-entry-major-version-4 = <0>;
			xlnx,pf0-entry-rsvd0-9 = <0x0>;
			xlnx,pf1-entry-addr-13 = <0x0>;
			xlnx,pf1-entry-addr-4 = <0x0>;
			xlnx,pf0-entry-bar-4 = <0>;
			xlnx,pf0-entry-major-version-14 = <0>;
			xlnx,pf0-entry-major-version-5 = <0>;
			xlnx,pf1-entry-addr-14 = <0x0>;
			xlnx,pf1-entry-addr-5 = <0x0>;
			xlnx,pf0-entry-bar-5 = <0>;
			xlnx,name = "blp_blp_logic_hw_discovery";
			xlnx,pf0-entry-major-version-15 = <0>;
			xlnx,pf0-entry-major-version-6 = <0>;
			xlnx,pf1-entry-addr-15 = <0x0>;
			xlnx,pf1-entry-addr-6 = <0x0>;
			xlnx,pf0-entry-bar-6 = <0>;
			xlnx,pf0-entry-major-version-7 = <0>;
			xlnx,pf1-entry-addr-7 = <0x0>;
			xlnx,pf0-entry-bar-7 = <0>;
			xlnx,pf0-entry-major-version-8 = <0>;
			xlnx,pf1-entry-addr-8 = <0x0>;
			xlnx,pf2-s-axi-addr-width = <32>;
			xlnx,pf0-entry-bar-8 = <0>;
			xlnx,pf0-entry-major-version-9 = <0>;
			xlnx,pf1-entry-addr-9 = <0x0>;
			xlnx,pf0-entry-bar-9 = <0>;
			xlnx,pf0-entry-bar-10 = <0>;
			xlnx,pf0-entry-bar-11 = <0>;
			xlnx,pf0-entry-bar-12 = <0>;
			xlnx,pf0-entry-bar-13 = <0>;
			xlnx,pf0-entry-bar-14 = <0>;
			xlnx,pf3-num-slots-bar-layout-table = <1>;
			xlnx,pf0-entry-bar-15 = <0>;
			xlnx,pf2-low-offset = <0x0>;
			clock-names = "aclk_ctrl" , "aclk_pcie";
			xlnx,pf0-entry-addr-0 = <0x2010000>;
			xlnx,pf0-entry-type-10 = <0x0>;
			xlnx,pf3-entry-minor-version-10 = <0>;
			xlnx,pf0-entry-addr-1 = <0x2000000>;
			xlnx,pf0-entry-type-11 = <0x0>;
			xlnx,pf3-entry-minor-version-11 = <0>;
			xlnx,pf0-entry-addr-2 = <0x8000000>;
			xlnx,pf0-entry-type-12 = <0x0>;
			xlnx,pf3-entry-minor-version-12 = <0>;
			xlnx,pf0-entry-addr-3 = <0x2002000>;
			xlnx,pf0-entry-type-13 = <0x0>;
			xlnx,pf3-entry-minor-version-13 = <0>;
			xlnx,pf0-entry-addr-4 = <0x0>;
			xlnx,pf0-entry-type-14 = <0x0>;
			xlnx,pf3-entry-minor-version-14 = <0>;
			xlnx,pf0-entry-addr-5 = <0x0>;
			xlnx,pf0-entry-type-15 = <0x0>;
			xlnx,pf3-entry-minor-version-15 = <0>;
			xlnx,pf0-entry-addr-6 = <0x0>;
			xlnx,pf0-entry-addr-7 = <0x0>;
			xlnx,pf3-entry-minor-version-0 = <0>;
			xlnx,pf2-entry-minor-version-10 = <0>;
			xlnx,pf0-entry-addr-8 = <0x0>;
			xlnx,pf3-entry-minor-version-1 = <0>;
			xlnx,pf2-entry-minor-version-11 = <0>;
			xlnx,pf0-entry-addr-9 = <0x0>;
			xlnx,pf3-entry-minor-version-2 = <0>;
			xlnx,pf2-entry-minor-version-12 = <0>;
			xlnx,pf3-entry-minor-version-3 = <0>;
			xlnx,pf2-entry-minor-version-13 = <0>;
			xlnx,pf3-entry-minor-version-4 = <0>;
			xlnx,pf2-entry-version-type-0 = <0x0>;
			xlnx,pf2-entry-minor-version-14 = <0>;
			xlnx,pf3-entry-minor-version-5 = <0>;
			xlnx,pf2-entry-version-type-1 = <0x0>;
			xlnx,pf2-entry-minor-version-15 = <0>;
			xlnx,pf3-entry-minor-version-6 = <0>;
			xlnx,pf2-entry-version-type-2 = <0x0>;
			xlnx,pf3-entry-minor-version-7 = <0>;
			xlnx,pf2-entry-version-type-3 = <0x0>;
			xlnx,pf1-entry-minor-version-10 = <0>;
			xlnx,pf3-entry-minor-version-8 = <0>;
			xlnx,pf2-entry-version-type-4 = <0x0>;
			xlnx,pf1-s-axi-data-width = <32>;
			xlnx,pf1-entry-minor-version-11 = <0>;
			xlnx,pf3-entry-minor-version-9 = <0>;
			xlnx,pf2-entry-version-type-5 = <0x0>;
			xlnx,pf1-entry-minor-version-12 = <0>;
			xlnx,pf3-low-offset = <0x0>;
			xlnx,pf2-entry-version-type-6 = <0x0>;
			xlnx,pf1-entry-minor-version-13 = <0>;
			xlnx,pf2-entry-version-type-7 = <0x0>;
			xlnx,pf0-bar-index = <0>;
			xlnx,pf1-entry-minor-version-14 = <0>;
			xlnx,pf2-entry-version-type-8 = <0x0>;
			xlnx,pf1-entry-minor-version-15 = <0>;
			xlnx,pf2-entry-version-type-9 = <0x0>;
			xlnx,pf1-entry-rsvd0-0 = <0x1>;
			xlnx,pf1-entry-rsvd0-1 = <0x0>;
			xlnx,pf0-entry-minor-version-10 = <0>;
			xlnx,pf1-entry-rsvd0-2 = <0x0>;
			xlnx,pf0-entry-minor-version-11 = <0>;
			xlnx,pf1-entry-rsvd0-3 = <0x0>;
			xlnx,pf0-entry-minor-version-12 = <0>;
			xlnx,pf1-entry-rsvd0-4 = <0x0>;
			xlnx,pf0-entry-minor-version-13 = <0>;
			xlnx,pf1-entry-rsvd0-5 = <0x0>;
			xlnx,pf0-entry-minor-version-14 = <0>;
			xlnx,pf2-entry-addr-10 = <0x0>;
			xlnx,pf1-entry-rsvd0-6 = <0x0>;
			xlnx,pf0-entry-minor-version-15 = <0>;
			xlnx,pf2-entry-addr-11 = <0x0>;
			xlnx,pf1-entry-rsvd0-7 = <0x0>;
			xlnx,pf2-entry-addr-12 = <0x0>;
			xlnx,pf1-entry-rsvd0-8 = <0x0>;
			xlnx,pf2-entry-addr-13 = <0x0>;
			xlnx,pf1-entry-rsvd0-9 = <0x0>;
			xlnx,pf2-entry-addr-14 = <0x0>;
			xlnx,pf3-high-offset = <0x0>;
			xlnx,pf2-entry-addr-15 = <0x0>;
			xlnx,pf3-s-axi-data-width = <32>;
			xlnx,pf2-entry-version-type-10 = <0x0>;
			xlnx,pf2-entry-version-type-11 = <0x0>;
			xlnx,next-cap-addr = <0x0>;
			xlnx,pf1-entry-minor-version-0 = <0>;
			xlnx,pf2-entry-version-type-12 = <0x0>;
			xlnx,pf1-entry-minor-version-1 = <0>;
			xlnx,pf2-entry-version-type-13 = <0x0>;
			xlnx,pf1-entry-minor-version-2 = <0>;
			xlnx,pf2-entry-version-type-14 = <0x0>;
			xlnx,pf1-entry-minor-version-3 = <0>;
			xlnx,pf2-entry-version-type-15 = <0x0>;
			xlnx,pf1-entry-minor-version-4 = <0>;
			xlnx,pf1-entry-minor-version-5 = <0>;
			status = "okay";
			xlnx,pf1-endpoint-names = "ep_mailbox_user_00 {type 0x53 reserve 0x1}";
			xlnx,pf1-entry-minor-version-6 = <0>;
			xlnx,pf1-entry-minor-version-7 = <0>;
			xlnx,pf0-num-slots-bar-layout-table = <4>;
			xlnx,pf1-entry-minor-version-8 = <0>;
			xlnx,pf2-entry-rsvd0-10 = <0x0>;
			xlnx,pf1-entry-minor-version-9 = <0>;
			xlnx,pf2-entry-rsvd0-11 = <0x0>;
			xlnx,pf2-entry-rsvd0-12 = <0x0>;
			xlnx,pf1-entry-type-10 = <0x0>;
			xlnx,pf2-entry-rsvd0-13 = <0x0>;
			xlnx,pf1-entry-type-11 = <0x0>;
			xlnx,pf2-entry-rsvd0-14 = <0x0>;
			xlnx,pf1-entry-type-12 = <0x0>;
			xlnx,pf2-entry-rsvd0-15 = <0x0>;
			xlnx,pf1-entry-type-13 = <0x0>;
			xlnx,pf3-entry-version-type-0 = <0x0>;
			xlnx,pf2-bar-index = <0>;
			xlnx,pf1-entry-type-14 = <0x0>;
			xlnx,pf3-entry-version-type-1 = <0x0>;
			xlnx,pf1-entry-type-15 = <0x0>;
			xlnx,pf3-entry-version-type-2 = <0x0>;
			xlnx,pf3-entry-version-type-3 = <0x0>;
			xlnx,pf3-entry-version-type-4 = <0x0>;
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,pf3-entry-version-type-5 = <0x0>;
			xlnx,pf3-entry-version-type-6 = <0x0>;
			xlnx,pf3-entry-version-type-7 = <0x0>;
			xlnx,pf3-entry-major-version-0 = <0>;
			xlnx,pf3-entry-version-type-8 = <0x0>;
			xlnx,pf3-entry-major-version-1 = <0>;
			xlnx,pf3-entry-version-type-9 = <0x0>;
			xlnx,pf3-entry-major-version-2 = <0>;
			xlnx,pf3-entry-major-version-3 = <0>;
			xlnx,pf2-high-offset = <0x0>;
			xlnx,pf3-entry-major-version-4 = <0>;
			xlnx,pf3-entry-major-version-5 = <0>;
			xlnx,pf3-entry-major-version-6 = <0>;
			xlnx,pf3-entry-major-version-7 = <0>;
			xlnx,pf0-entry-version-type-10 = <0x0>;
			xlnx,pf3-entry-major-version-8 = <0>;
			xlnx,inject-endpoints = <0>;
			xlnx,pf0-entry-version-type-11 = <0x0>;
			xlnx,pf3-entry-major-version-9 = <0>;
			xlnx,pf0-entry-version-type-12 = <0x0>;
			xlnx,pf2-entry-rsvd0-0 = <0x0>;
			xlnx,pf0-entry-version-type-13 = <0x0>;
			xlnx,pf2-entry-rsvd0-1 = <0x0>;
			xlnx,pf0-entry-version-type-14 = <0x0>;
			xlnx,pf2-entry-rsvd0-2 = <0x0>;
			xlnx,pf0-entry-version-type-15 = <0x0>;
			xlnx,pf2-entry-rsvd0-3 = <0x0>;
			xlnx,pf2-entry-rsvd0-4 = <0x0>;
			xlnx,pf2-entry-rsvd0-5 = <0x0>;
			xlnx,pf3-entry-addr-10 = <0x0>;
			xlnx,pf2-entry-rsvd0-6 = <0x0>;
			xlnx,num-pfs = <2>;
			xlnx,pf3-entry-addr-11 = <0x0>;
			xlnx,pf2-entry-rsvd0-7 = <0x0>;
			xlnx,pf3-entry-addr-12 = <0x0>;
			xlnx,pf2-entry-rsvd0-8 = <0x0>;
			xlnx,pf3-entry-addr-13 = <0x0>;
			xlnx,pf2-entry-rsvd0-9 = <0x0>;
			xlnx,pf3-entry-addr-14 = <0x0>;
			xlnx,pf3-entry-addr-15 = <0x0>;
			xlnx,pf1-entry-major-version-0 = <1>;
			xlnx,pf1-entry-major-version-1 = <0>;
			xlnx,pf1-entry-major-version-2 = <0>;
			xlnx,pf1-entry-major-version-3 = <0>;
			xlnx,pf1-high-offset = <0x0>;
			xlnx,pf1-entry-major-version-4 = <0>;
			xlnx,pf2-num-slots-bar-layout-table = <1>;
			xlnx,pf1-entry-major-version-5 = <0>;
			compatible = "xlnx,hw-discovery-1.0";
			xlnx,pf1-entry-major-version-6 = <0>;
			xlnx,pf1-entry-major-version-7 = <0>;
			xlnx,pf2-entry-type-10 = <0x0>;
			xlnx,pf1-entry-major-version-8 = <0>;
			xlnx,pf2-entry-type-11 = <0x0>;
			xlnx,pf1-entry-major-version-9 = <0>;
			xlnx,pf2-entry-type-12 = <0x0>;
			xlnx,pf2-entry-type-13 = <0x0>;
			xlnx,pf2-entry-type-14 = <0x0>;
			xlnx,pf2-entry-type-15 = <0x0>;
			xlnx,pf1-s-axi-addr-width = <32>;
			xlnx,pf0-endpoint-names = "ep_blp_rom_00 {type 0x50 reserve 0x0} ep_mailbox_mgmt_00 {type 0x53 reserve 0x3} ep_xgq_mgmt_to_rpu_sq_pi_00 {type 0x54 reserve 0x0} ep_xgq_payload_mgmt_00 {type 0x55 reserve 0x0}";
			xlnx,pf1-entry-rsvd0-10 = <0x0>;
			xlnx,pf3-entry-rsvd0-0 = <0x0>;
			xlnx,pf1-entry-rsvd0-11 = <0x0>;
			xlnx,pf3-entry-rsvd0-1 = <0x0>;
			xlnx,pf1-entry-rsvd0-12 = <0x0>;
			xlnx,pf3-entry-rsvd0-2 = <0x0>;
			xlnx,pf1-entry-rsvd0-13 = <0x0>;
			xlnx,pf3-entry-rsvd0-3 = <0x0>;
			xlnx,pf1-entry-rsvd0-14 = <0x0>;
			xlnx,pf3-s-axi-addr-width = <32>;
			xlnx,pf3-entry-rsvd0-4 = <0x0>;
			xlnx,pf1-entry-rsvd0-15 = <0x0>;
			xlnx,pf3-entry-rsvd0-5 = <0x0>;
			xlnx,pf3-entry-rsvd0-6 = <0x0>;
			xlnx,pf0-high-offset = <0x0>;
			xlnx,pf3-entry-rsvd0-7 = <0x0>;
			xlnx,pf3-entry-rsvd0-8 = <0x0>;
			xlnx,pf3-entry-rsvd0-9 = <0x0>;
			xlnx,cap-base-addr = <0x600>;
			xlnx,pf0-s-axi-data-width = <32>;
			xlnx,pf3-entry-type-0 = <0x0>;
			xlnx,pf3-entry-type-1 = <0x0>;
			xlnx,pf3-entry-type-2 = <0x0>;
			xlnx,pf3-entry-type-3 = <0x0>;
			xlnx,pf3-entry-bar-0 = <0>;
			xlnx,pf3-entry-type-4 = <0x0>;
			xlnx,pf3-entry-bar-1 = <0>;
			xlnx,pf3-entry-type-5 = <0x0>;
			xlnx,pf3-entry-bar-2 = <0>;
			xlnx,pf3-entry-type-6 = <0x0>;
			xlnx,pf3-entry-bar-3 = <0>;
			xlnx,pf3-entry-type-7 = <0x0>;
			xlnx,pf3-entry-bar-4 = <0>;
			xlnx,pf3-entry-type-8 = <0x0>;
			xlnx,pf3-entry-bar-5 = <0>;
			xlnx,pf3-entry-type-9 = <0x0>;
			xlnx,pf3-entry-type-10 = <0x0>;
			xlnx,pf3-entry-bar-6 = <0>;
			xlnx,rable = <0>;
			xlnx,pf3-entry-type-11 = <0x0>;
			xlnx,pf3-entry-bar-7 = <0>;
			xlnx,pf3-entry-type-12 = <0x0>;
			xlnx,pf3-entry-bar-8 = <0>;
			xlnx,ip-name = "hw_discovery";
			xlnx,pf3-entry-version-type-10 = <0x0>;
			xlnx,pf3-entry-type-13 = <0x0>;
			xlnx,pf3-entry-bar-9 = <0>;
			xlnx,pf3-entry-version-type-11 = <0x0>;
			xlnx,pf3-entry-type-14 = <0x0>;
			xlnx,pf2-entry-minor-version-0 = <0>;
			xlnx,pf3-entry-version-type-12 = <0x0>;
			xlnx,pf3-entry-type-15 = <0x0>;
			xlnx,pf2-entry-minor-version-1 = <0>;
			xlnx,pf3-entry-version-type-13 = <0x0>;
			xlnx,pf2-s-axi-data-width = <32>;
			xlnx,pf2-entry-minor-version-2 = <0>;
			xlnx,pf3-entry-version-type-14 = <0x0>;
			xlnx,pf2-entry-minor-version-3 = <0>;
			xlnx,pf3-entry-version-type-15 = <0x0>;
			xlnx,pf2-entry-minor-version-4 = <0>;
			xlnx,pf2-entry-minor-version-5 = <0>;
			xlnx,pf2-entry-minor-version-6 = <0>;
			xlnx,pf3-endpoint-names = <0>;
			xlnx,pf2-entry-minor-version-7 = <0>;
			xlnx,pf2-entry-minor-version-8 = <0>;
			xlnx,pf2-entry-minor-version-9 = <0>;
			xlnx,pf2-entry-type-0 = <0x0>;
			xlnx,pf2-entry-type-1 = <0x0>;
			xlnx,pf2-entry-type-2 = <0x0>;
			xlnx,pf2-entry-type-3 = <0x0>;
			xlnx,pf1-bar-index = <2>;
			xlnx,pf2-entry-type-4 = <0x0>;
			xlnx,pf2-entry-type-5 = <0x0>;
			xlnx,pf2-entry-type-6 = <0x0>;
			xlnx,pf2-entry-type-7 = <0x0>;
			xlnx,pf2-entry-type-8 = <0x0>;
			xlnx,pf2-entry-type-9 = <0x0>;
			xlnx,pf2-entry-bar-0 = <0>;
			xlnx,pf2-entry-bar-1 = <0>;
			xlnx,pf3-entry-bar-10 = <0>;
			xlnx,pf2-entry-bar-2 = <0>;
			xlnx,pf3-entry-bar-11 = <0>;
			xlnx,pf2-entry-bar-3 = <0>;
			xlnx,pf3-entry-bar-12 = <0>;
			xlnx,pf2-entry-bar-4 = <0>;
			xlnx,pf3-entry-bar-13 = <0>;
			xlnx,pf2-entry-bar-5 = <0>;
			xlnx,pf3-entry-bar-14 = <0>;
			xlnx,pf2-entry-bar-6 = <0>;
			xlnx,pf3-entry-bar-15 = <0>;
			xlnx,pf2-entry-bar-7 = <0>;
			xlnx,pf2-entry-bar-8 = <0>;
			xlnx,pf1-entry-version-type-10 = <0x0>;
			xlnx,manual = <1>;
			xlnx,pf2-entry-bar-9 = <0>;
			xlnx,pf1-entry-version-type-11 = <0x0>;
			xlnx,pf0-entry-minor-version-0 = <2>;
			xlnx,pf1-entry-version-type-12 = <0x0>;
			xlnx,pf0-entry-minor-version-1 = <0>;
			clocks = <&versal_clk 65>, <&misc_clk_0>;
			xlnx,pf1-entry-version-type-13 = <0x0>;
			xlnx,pf0-entry-minor-version-2 = <0>;
			xlnx,pf1-entry-version-type-14 = <0x0>;
			xlnx,pf1-entry-type-0 = <0x53>;
			xlnx,pf0-entry-minor-version-3 = <0>;
			xlnx,pf1-entry-version-type-15 = <0x0>;
			xlnx,pf1-entry-type-1 = <0x0>;
			xlnx,pf0-entry-addr-10 = <0x0>;
			xlnx,pf0-entry-minor-version-4 = <0>;
			xlnx,pf1-entry-type-2 = <0x0>;
			xlnx,pf0-entry-addr-11 = <0x0>;
			xlnx,pf0-entry-minor-version-5 = <0>;
			xlnx,pf0-entry-version-type-0 = <0x1>;
			xlnx,pf3-entry-addr-0 = <0x0>;
			xlnx,pf1-entry-type-3 = <0x0>;
			xlnx,pf0-entry-addr-12 = <0x0>;
			xlnx,pf0-entry-minor-version-6 = <0>;
			xlnx,pf0-entry-version-type-1 = <0x1>;
			xlnx,pf3-entry-addr-1 = <0x0>;
			xlnx,pf1-entry-type-4 = <0x0>;
			xlnx,pf0-entry-addr-13 = <0x0>;
			xlnx,pf0-entry-minor-version-7 = <0>;
			xlnx,pf0-entry-version-type-2 = <0x1>;
			xlnx,pf3-entry-addr-2 = <0x0>;
			xlnx,pf1-entry-type-5 = <0x0>;
			xlnx,pf0-entry-addr-14 = <0x0>;
			xlnx,pf0-entry-minor-version-8 = <0>;
			xlnx,pf0-entry-rsvd0-10 = <0x0>;
			xlnx,pf0-entry-version-type-3 = <0x1>;
			xlnx,pf3-entry-addr-3 = <0x0>;
			xlnx,pf1-entry-type-6 = <0x0>;
			xlnx,pf0-entry-addr-15 = <0x0>;
			xlnx,pf0-entry-minor-version-9 = <0>;
			xlnx,pf0-entry-rsvd0-11 = <0x0>;
			xlnx,pf0-entry-version-type-4 = <0x0>;
			xlnx,pf3-entry-addr-4 = <0x0>;
			xlnx,pf1-entry-type-7 = <0x0>;
			xlnx,pf0-entry-rsvd0-12 = <0x0>;
			xlnx,pf0-entry-version-type-5 = <0x0>;
			xlnx,pf3-entry-addr-5 = <0x0>;
			xlnx,pf1-entry-type-8 = <0x0>;
			xlnx,pf0-entry-rsvd0-13 = <0x0>;
			xlnx,pf0-entry-version-type-6 = <0x0>;
			xlnx,pf3-entry-addr-6 = <0x0>;
			xlnx,pf1-entry-type-9 = <0x0>;
			xlnx,pf0-entry-rsvd0-14 = <0x0>;
			xlnx,pf0-entry-version-type-7 = <0x0>;
			xlnx,pf3-entry-addr-7 = <0x0>;
			xlnx,pf0-entry-rsvd0-15 = <0x0>;
			xlnx,pf0-entry-version-type-8 = <0x0>;
			xlnx,pf3-entry-addr-8 = <0x0>;
			xlnx,pf0-entry-version-type-9 = <0x0>;
			xlnx,pf3-entry-addr-9 = <0x0>;
			xlnx,pf2-entry-bar-10 = <0>;
			xlnx,pf3-bar-index = <0>;
			xlnx,pf2-entry-bar-11 = <0>;
			xlnx,pf1-num-slots-bar-layout-table = <1>;
			xlnx,pf2-entry-bar-12 = <0>;
			xlnx,pf0-low-offset = <0x200100>;
			xlnx,pf2-entry-bar-13 = <0>;
			xlnx,pf2-entry-bar-14 = <0>;
			xlnx,pf2-entry-bar-15 = <0>;
			xlnx,pf2-entry-major-version-0 = <0>;
			xlnx,pf1-entry-bar-0 = <2>;
			xlnx,pf2-entry-major-version-1 = <0>;
			xlnx,pf1-entry-bar-1 = <0>;
			xlnx,pf2-entry-major-version-2 = <0>;
			xlnx,pf1-entry-bar-2 = <0>;
			xlnx,pf2-entry-major-version-3 = <0>;
			xlnx,pf1-entry-bar-3 = <0>;
			xlnx,pf2-entry-major-version-4 = <0>;
			xlnx,pf0-entry-type-0 = <0x54>;
			xlnx,pf1-entry-bar-4 = <0>;
		};
		blp_blp_logic_pf_mailbox: mailbox@20102000000 {
			xlnx,s1-axi-aclk-freq-mhz = <0x5f5e0a4>;
			compatible = "xlnx,mailbox-2.1";
			xlnx,interconnect-port-0 = <2>;
			xlnx,interconnect-port-1 = <2>;
			xlnx,rable = <0>;
			xlnx,mailbox-depth = <16>;
			xlnx,s1-axi-data-width = <32>;
			xlnx,s0-axi-addr-width = <32>;
			xlnx,ip-name = "mailbox";
			reg = <0x00000201 0x02000000 0x0 0x1000 0x00000202 0x02000000 0x0 0x1000>;
			xlnx,async-clks = <0>;
			xlnx,impl-style = <0>;
			clocks = <&versal_clk 65>, <&versal_clk 65>;
			xlnx,read-clock-period-0 = <0>;
			xlnx,read-clock-period-1 = <0>;
			xlnx,num-sync-ff = <2>;
			xlnx,async-interrupts = <1>;
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,enable-bus-error = <0>;
			xlnx,s0-axi-data-width = <32>;
			status = "okay";
			xlnx,ext-reset-high = <1>;
			clock-names = "S0_AXI_ACLK" , "S1_AXI_ACLK";
			xlnx,s1-axi-addr-width = <32>;
			xlnx,s0-axi-aclk-freq-mhz = <0x5f5e0a4>;
			xlnx,name = "blp_blp_logic_pf_mailbox";
		};
		blp_blp_logic_pfm_irq_ctlr: pfm_irq_ctlr@80044000 {
			compatible = "xlnx,pfm-irq-ctlr-1.0";
			xlnx,rable = <0>;
			xlnx,num-of-irq-pf0 = <1>;
			xlnx,num-of-irq-pf1 = <1>;
			xlnx,ip-name = "pfm_irq_ctlr";
			xlnx,cpm-type = <0>;
			xlnx,num-of-pfs = <2>;
			xlnx,num-of-irq-pf2 = <32>;
			reg = <0x0 0x80044000 0x0 0x1000>;
			xlnx,addr-width = <10>;
			clocks = <&misc_clk_0>;
			xlnx,num-of-irq-pf3 = <32>;
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,axi-ctrl-en = <1>;
			xlnx,edge-select-pf0 = <0x0>;
			status = "okay";
			xlnx,edge-select-pf1 = <0x0>;
			clock-names = "aclk";
			xlnx,edge-select-pf2 = <0x0>;
			xlnx,max-pf-length = <32>;
			xlnx,edge-select-pf3 = <0x0>;
			xlnx,name = "blp_blp_logic_pfm_irq_ctlr";
		};
		blp_blp_logic_ulp_clocking_clkwiz_aclk_kernel_00: clk_wizard@80042000 {
			xlnx,reset-type = "ACTIVE_HIGH";
			xlnx,clk-out1-port = "clk_out1";
			xlnx,clkout1-actual-duty-cycle = <50>;
			xlnx,clkout2-phase = <0>;
			xlnx,clkout1-dyn-ps = <00>;
			xlnx,use-locked-deskew1 = <0>;
			xlnx,use-locked-deskew2 = <0>;
			xlnx,clkout3-drives = "BUFG";
			xlnx,deskew-delay1 = <0>;
			reg = <0x0 0x80042000 0x0 0x1000>;
			xlnx,deskew-delay2 = <0>;
			xlnx,clkin2-deskew-port = "clkin2_deskew";
			xlnx,clkout4-grouping = "Auto";
			xlnx,d-max = <107>;
			xlnx,divide6-auto = <0>;
			xlnx,clkout1-phase = <0>;
			xlnx,clkout2-requested-out-freq = <100>;
			xlnx,clkout7-divide = <12>;
			xlnx,use-locked = <1>;
			xlnx,clkin1-ibufds = <0>;
			xlnx,input-clk-stopped-port = "input_clk_stopped";
			xlnx,clkout1-drives = "No_buffer";
			xlnx,divide3-auto = <0>;
			xlnx,clkout4-duty-cycle = <0x7a120>;
			xlnx,clkout4-mbufgce-mode = "PERFORMANCE";
			xlnx,use-dyn-reconfig = <1>;
			xlnx,clkout6-actual-duty-cycle = <50>;
			xlnx,clkout6-requested-duty-cycle = <50>;
			xlnx,deskew2-in = <0>;
			xlnx,deskew1-fb = <1>;
			xlnx,clkin2-jitter-ps = <100>;
			xlnx,feedback-source = "FDBK_AUTO";
			xlnx,clkout5-requested-out-freq = <100>;
			xlnx,bufgce-div-ce-type = "SYNC";
			xlnx,name = "blp_blp_logic_ulp_clocking_clkwiz_aclk_kernel_00";
			xlnx,clkout5-divide = <12>;
			xlnx,current-path = "clk_wizard_v1_0";
			xlnx,prim-in-freq = <0x1fc9f08>;
			xlnx,clkout-matched-routing = "false,false,false,false,false,false,false";
			xlnx,deskew2-lock-circuit-en;
			xlnx,clk-in2-board-interface = "Custom";
			xlnx,clkin1-deskew-port = "clkin1_deskew";
			xlnx,clkin1-ui-jitter = <0x2710>;
			xlnx,clkout3-mbufgce-mode = "PERFORMANCE";
			xlnx,use-inclk-switchover = <0>;
			clock-names = "clk_in1" , "s_axi_aclk";
			xlnx,clkout3-divide = <12>;
			xlnx,clkout5-duty-cycle = <0x7a120>;
			xlnx,clkout1-grouping = "Auto";
			xlnx,use-dyn-phase-shift = <0>;
			xlnx,o-min = <3>;
			xlnx,daddr-port = "daddr";
			xlnx,clkout-grouping = "Auto,Auto,Auto,Auto,Auto,Auto,Auto";
			xlnx,clkin1-bufg = <0>;
			xlnx,precision = <1>;
			clock-output-names = "0x80042000-clk_out1";
			xlnx,clkout1-divide = <10>;
			xlnx,use-phase-alignment = <0>;
			xlnx,ref-clk-freq = <100>;
			xlnx,pllbufgcediv = <0>;
			xlnx,deskew1-in = <0>;
			xlnx,inclk-sum-row0 = "Input , Clock , Freq , (MHz) , Input , Jitter , (UI)";
			xlnx,clkout7-requested-duty-cycle = <50>;
			xlnx,inclk-sum-row1 = "primary , 100.000 , 0.010";
			xlnx,inclk-sum-row2 = "secondary , 100.000 , 0.010";
			xlnx,clkout2-mbufgce-mode = "PERFORMANCE";
			xlnx,din-port = "din";
			xlnx,reset-board-interface = "Custom";
			xlnx,clkout5-actual-duty-cycle = <50>;
			xlnx,clkout-requested-phase = "0.000,0.000,0.000,0.000,0.000,0.000,0.000";
			xlnx,clkout6-duty-cycle = <0x7a120>;
			xlnx,clkout1-requested-duty-cycle = <50>;
			xlnx,vco-max = <4320>;
			xlnx,use-freq-synth = <1>;
			xlnx,clkout5-used = <0>;
			xlnx,d-min = <1>;
			xlnx,clk-out6-port = "clk_out6";
			xlnx,clk-tree1 = <0>;
			xlnx,clkout2-sequence-number = <1>;
			xlnx,clkout-used = "true,false,false,false,false,false,false";
			xlnx,clk-tree2 = <0>;
			xlnx,clk-tree3 = <0>;
			xlnx,clkin1-period = <0x1c9c4ac>;
			xlnx,clkout2-used = <0>;
			xlnx,clkout4-sequence-number = <1>;
			xlnx,psincdec-port = "psincdec";
			xlnx,clk-tree4 = <0>;
			xlnx,clkfbin-ibuf = <0>;
			xlnx,clk-tree5 = <0>;
			xlnx,clk-out3-port = "clk_out3";
			xlnx,clkout6-sequence-number = <1>;
			xlnx,clkout-port = "clk_out1,clk_out2,clk_out3,clk_out4,clk_out5,clk_out6,clk_out7";
			xlnx,locked-deskew1-port = "locked_deskew1";
			xlnx,clk-tree6 = <0>;
			xlnx,clk-tree7 = <0>;
			xlnx,clkin2-ibuf = <0>;
			xlnx,clkfbout-fract = <0>;
			xlnx,clkout5-grouping = "Auto";
			xlnx,pllbufgcediv1 = <0>;
			xlnx,nr-outputs = <1>;
			xlnx,pllbufgcediv2 = <0>;
			xlnx,pllbufgcediv3 = <0>;
			xlnx,pllbufgcediv4 = <0>;
			xlnx,clkout1-mbufgce-mode = "PERFORMANCE";
			xlnx,clkfb-deskew-port = "clkfb_deskew";
			xlnx,clkout2-matched-routing = <0>;
			xlnx,safeclock-startup-mode = "DESKEW_MODE";
			xlnx,ref-jitter1 = <0x2710>;
			xlnx,ref-jitter2 = <0x2710>;
			status = "okay";
			xlnx,clkout4-matched-routing = <0>;
			xlnx,clkout6-dyn-ps = <00>;
			xlnx,clkout6-matched-routing = <0>;
			xlnx,clkout7-duty-cycle = <0x7a120>;
			xlnx,outclk-sum-row1 = "no , clk_out1 , output";
			xlnx,outclk-sum-row2 = "no , clk_out2 , output";
			xlnx,jitter-sel = "No_Jitter";
			xlnx,outclk-sum-row3 = "no , clk_out3 , output";
			xlnx,outclk-sum-row4 = "no , clk_out4 , output";
			xlnx,outclk-sum-row5 = "no , clk_out5 , output";
			xlnx,clkout7-actual-phase = <0>;
			xlnx,outclk-sum-row6 = "no , clk_out6 , output";
			xlnx,outclk-sum-row7 = "no , clk_out7 , output";
			xlnx,divide5-auto = <0>;
			xlnx,deskew-fb1 = <1>;
			xlnx,deskew-fb2 = <1>;
			xlnx,clkfbin-obuf = <0>;
			xlnx,psdone-port = "psdone";
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,clkout3-requested-out-freq = <100>;
			xlnx,divide2-auto = <0>;
			xlnx,clkout4-dyn-ps = <00>;
			xlnx,ss-mode = "CENTER_HIGH";
			xlnx,clkfbout-mult = <1>;
			xlnx,clkout-requested-duty-cycle = "50.000,50.000,50.000,50.000,50.000,50.000,50.000";
			xlnx,clkout6-drives = "BUFG";
			xlnx,ss-mod-period = <4000>;
			xlnx,clkout2-actual-out-freq = <0x5f5dd18>;
			xlnx,clkout2-requested-duty-cycle = <50>;
			xlnx,numbufgce = <0>;
			xlnx,clkout4-actual-duty-cycle = <50>;
			xlnx,clkout4-actual-out-freq = <0x5f5dd18>;
			xlnx,primary-port = "clk_in1";
			xlnx,clkout6-actual-out-freq = <0x5f5dd18>;
			xlnx,clkout6-requested-out-freq = <100>;
			xlnx,clkfbout-oddr = <0>;
			xlnx,use-locked-fb = <0>;
			xlnx,locked-fb-port = "locked_fb";
			xlnx,clkout2-requested-phase = <0>;
			xlnx,relative-inclk = "REL_PRIMARY";
			xlnx,clkout4-requested-phase = <0>;
			xlnx,enable-user-clock0 = <0>;
			xlnx,clkout2-dyn-ps = <00>;
			xlnx,clkout2-grouping = "Auto";
			xlnx,enable-user-clock1 = <0>;
			xlnx,clkout6-actual-phase = <0>;
			xlnx,clkout6-requested-phase = <0>;
			xlnx,clkout-requested-out-frequency = "300,100.000,100.000,100.000,100.000,100.000,100.000";
			xlnx,ss-mod-freq = <250>;
			xlnx,enable-user-clock2 = <0>;
			xlnx,enable-user-clock3 = <0>;
			xlnx,primitive-type = "MMCM";
			xlnx,ce-sync-ext = <0>;
			xlnx,clkout4-drives = "BUFG";
			xlnx,den-port = "den";
			xlnx,use-safe-clock-startup = <0>;
			xlnx,dwe-port = "dwe";
			xlnx,drdy-port = "drdy";
			xlnx,vco-min = <2160>;
			xlnx,clk-in-sel-port = "clk_in_sel";
			xlnx,clkin1-jitter-ps = <100>;
			xlnx,deskew-delay-path1;
			xlnx,deskew-delay-path2;
			xlnx,enable-pll0 = <0>;
			xlnx,enable-pll1 = <0>;
			xlnx,clkin2-ibufds = <0>;
			xlnx,clkfb2-deskew-port = "clkfb2_deskew";
			xlnx,clkout2-drives = "BUFG";
			xlnx,use-inclk-stopped = <0>;
			compatible = "xlnx,clk-wizard-1.0" , "xlnx,versal-clk-wizard";
			xlnx,clkout5-actual-phase = <0>;
			xlnx,reset-port = "reset";
			xlnx,sim-device = "VERSAL_AI_EDGE";
			xlnx,speed-grade = <2>;
			xlnx,clkout6-divide = <12>;
			xlnx,clkout3-requested-duty-cycle = <50>;
			xlnx,prim-source = "No_buffer";
			xlnx,clkout7-used = <0>;
			xlnx,deskew1-delay-en;
			xlnx,use-clkfb-stopped = <0>;
			xlnx,clkout6-grouping = "Auto";
			xlnx,compensation = "AUTO";
			xlnx,mmcmbufgcediv = <0>;
			xlnx,clkin-deskew-port = "clkin_deskew";
			xlnx,clkout3-actual-duty-cycle = <50>;
			xlnx,clkout4-used = <0>;
			xlnx,clk-out5-port = "clk_out5";
			xlnx,psclk-port = "psclk";
			xlnx,ce-type = "SYNC";
			xlnx,clkfbout-phase = <0>;
			xlnx,clkout4-divide = <12>;
			xlnx,primitive = "MMCM";
			xlnx,clkout1-used = <1>;
			xlnx,deskew1-lock-circuit-en;
			xlnx,clk-in1-board-interface = "Custom";
			xlnx,clk-out2-port = "clk_out2";
			xlnx,clkout4-actual-phase = <0>;
			xlnx,power-down-port = "power_down";
			xlnx,clkfb1-deskew-port = "clkfb1_deskew";
			xlnx,bandwidth = "OPTIMIZED";
			xlnx,clkin1-ibuf = <0>;
			xlnx,user-clk-freq0 = <100>;
			xlnx,deskew1-delay-path = "ClkFb_Path";
			xlnx,user-clk-freq1 = <100>;
			xlnx,clkoutfb-phase-ctrl = <00>;
			xlnx,user-clk-freq2 = <100>;
			xlnx,user-clk-freq3 = <100>;
			xlnx,use-clock-sequencing = <0>;
			xlnx,secondary-source = "Single_ended_clock_capable_pin";
			xlnx,cddcdone-port = "cddcdone";
			xlnx,clkout2-divide = <12>;
			xlnx,actual-vco = <0xb2cfe8d0>;
			xlnx,clkout7-phase = <0>;
			xlnx,psen-port = "psen";
			xlnx,m-max = <432>;
			xlnx,deskew-delay-en1;
			xlnx,dclk-port = "dclk";
			xlnx,deskew-delay-en2;
			xlnx,outclk-sum-row0a = "Output , Output , Phase , Duty , Pk-to-Pk , Phase";
			xlnx,divide7-auto = <0>;
			xlnx,clkout1-requested-out-freq = <100>;
			xlnx,outclk-sum-row0b = "Clock , Freq , (MHz) , (degrees) , Cycle , () , Jitter , (ps) , Error , (ps)";
			xlnx,locked-port = "locked";
			xlnx,enable-clock-monitor = <0>;
			xlnx,clkin2-ui-jitter = <0x2710>;
			xlnx,ss-mod-time = <0xfa0>;
			xlnx,divide4-auto = <0>;
			xlnx,auto-primitive = "MMCM";
			xlnx,drp-addr-set1 = "00000328 , 0000032c , 00000330 , 00000334 , 00000338 , 0000033c , 00000340 , 00000344 , 00000348 , 0000034c , 00000350 , 00000354 , 00000358 , 0000035c , 00000360 , 00000364 , 00000368 , 0000036c , 00000370 , 00000374 , 00000378 , 0000037c , 00000380 , 00000384 , 00000388 , 0000038c , 00000390 , 00000394 , 00000398 , 0000039c , 000003a0 , 000003a4 , 000003a8 , 000003ac , 000003b0 , 000003b4 , 000003b8 , 000003bc , 000003c0 , 000003c4 , 000003c8 , 000003cc , 000003d0 , 000003d4 , 000003d8 , 000003dc , 000003e0 , 000003e4 , 000003e8 , 000003ec , 000003f0 , 000003f4 , 000003f8 , 000003fc";
			xlnx,drp-addr-set2 = "00000328 , 0000032c , 00000330 , 00000334 , 00000338 , 0000033c , 00000340 , 00000344 , 00000348 , 0000034c , 00000350 , 00000354 , 00000358 , 0000035c , 00000360 , 00000364 , 00000368 , 0000036c , 00000370 , 00000374 , 00000378 , 0000037c , 00000380 , 00000384 , 00000388 , 0000038c , 00000390 , 00000394 , 00000398 , 0000039c , 000003a0 , 000003a4 , 000003a8 , 000003ac , 000003b0 , 000003b4 , 000003b8 , 000003bc , 000003c0 , 000003c4 , 000003c8 , 000003cc , 000003d0 , 000003d4 , 000003d8 , 000003dc , 000003e0 , 000003e4 , 000003e8 , 000003ec , 000003f0 , 000003f4 , 000003f8 , 000003fc";
			xlnx,drp-addr-set3 = "00000328 , 0000032c , 00000330 , 00000334 , 00000338 , 0000033c , 00000340 , 00000344 , 00000348 , 0000034c , 00000350 , 00000354 , 00000358 , 0000035c , 00000360 , 00000364 , 00000368 , 0000036c , 00000370 , 00000374 , 00000378 , 0000037c , 00000380 , 00000384 , 00000388 , 0000038c , 00000390 , 00000394 , 00000398 , 0000039c , 000003a0 , 000003a4 , 000003a8 , 000003ac , 000003b0 , 000003b4 , 000003b8 , 000003bc , 000003c0 , 000003c4 , 000003c8 , 000003cc , 000003d0 , 000003d4 , 000003d8 , 000003dc , 000003e0 , 000003e4 , 000003e8 , 000003ec , 000003f0 , 000003f4 , 000003f8 , 000003fc";
			xlnx,clkout3-actual-phase = <0>;
			xlnx,clkout-mbufgce-mode = "PERFORMANCE,PERFORMANCE,PERFORMANCE,PERFORMANCE,PERFORMANCE,PERFORMANCE,PERFORMANCE";
			xlnx,use-power-down = <1>;
			xlnx,divide1-auto = <0>;
			xlnx,clkout3-grouping = "Auto";
			xlnx,clkout4-requested-duty-cycle = <50>;
			xlnx,clkout4-requested-out-freq = <100>;
			xlnx,rable = <0>;
			xlnx,clkout6-phase = <0>;
			xlnx,num-out-clks = <1>;
			xlnx,ip-name = "clk_wizard";
			xlnx,auto-nummbufgce = <0>;
			xlnx,deskew-in1 = <0>;
			xlnx,deskew2-delay = <0>;
			xlnx,deskew-in2 = <0>;
			xlnx,mmcmbufgcediv1 = <0>;
			xlnx,deskew2-delay-path = "ClkFb_Path";
			xlnx,mmcmbufgcediv2 = <0>;
			xlnx,clkin2-period = <0x13de432>;
			xlnx,clkout1-duty-cycle = <0x7a120>;
			xlnx,mmcmbufgcediv3 = <0>;
			xlnx,mmcmbufgcediv4 = <0>;
			xlnx,mmcmbufgcediv5 = <0>;
			xlnx,dout-port = "dout";
			xlnx,mmcmbufgcediv6 = <0>;
			xlnx,clkout1-sequence-number = <1>;
			xlnx,mmcmbufgcediv7 = <0>;
			xlnx,cddcreq-port = "cddcreq";
			xlnx,clkout7-requested-out-freq = <100>;
			xlnx,use-spread-spectrum;
			xlnx,clkout3-sequence-number = <1>;
			xlnx,clkout7-mbufgce-mode = "PERFORMANCE";
			xlnx,clkout2-actual-duty-cycle = <50>;
			xlnx,clkout5-sequence-number = <1>;
			xlnx,clkout5-phase = <0>;
			xlnx,clkout7-sequence-number = <1>;
			xlnx,deskew1-delay = <0>;
			xlnx,clkfb-in-port = "clkfb_in";
			xlnx,zhold;
			xlnx,clkout2-actual-phase = <0>;
			xlnx,clkout7-dyn-ps = <00>;
			xlnx,deskew-lock-circuit-en1 = <0>;
			xlnx,clkout-dyn-ps = "None,None,None,None,None,None,None";
			xlnx,deskew-lock-circuit-en2 = <0>;
			xlnx,clkfbout-bufg = <0>;
			xlnx,clkout1-matched-routing = <0>;
			xlnx,interface-selection = <1>;
			xlnx,clkout3-matched-routing = <0>;
			xlnx,override-primitive = <0>;
			xlnx,calc-done = "empty";
			xlnx,clkout5-matched-routing = <0>;
			xlnx,clkfbin-obufds = <0>;
			xlnx,actual-pfd = <0xa98a58>;
			xlnx,clkout7-matched-routing = <0>;
			xlnx,clkin2-bufg = <0>;
			xlnx,clkout2-duty-cycle = <0x7a120>;
			xlnx,clkout4-phase = <0>;
			xlnx,clkout5-dyn-ps = <00>;
			xlnx,clkout6-mbufgce-mode = "PERFORMANCE";
			xlnx,clkout7-actual-duty-cycle = <50>;
			clocks = <&versal_clk 66>, <&versal_clk 66>;
			xlnx,deskew2-delay-en;
			xlnx,clkout7-grouping = "Auto";
			xlnx,clkfbin-ibufds = <0>;
			xlnx,clkfb-bufg = <0>;
			xlnx,clkout7-drives = "BUFG";
			xlnx,clkout-drives = "No_buffer,BUFG,BUFG,BUFG,BUFG,BUFG,BUFG";
			xlnx,clkout5-requested-duty-cycle = <50>;
			xlnx,drp-data-set1 = "4b06 , 0001 , 1600 , 8787 , 1b00 , 0202 , 0a00 , 0303 , 0a00 , 0303 , 0a00 , 0303 , f37c , 7c4d , d042 , ebd8 , ec5f , edfb , aacd , 4428 , 002f , 0000 , 0400 , 0101 , 000f , 0006 , 0000 , 0000 , 0e80 , 40e1 , 43e9 , 1188 , 0008 , 0001 , 0000 , 00c0 , 0dfd , 0961 , 0001 , 0000 , 068b , 0a00 , 0303 , 0a00 , 0303 , 0a00 , 0303 , 0000 , 0000 , 0000 , 0000 , 0000 , 0f00 , 0001";
			xlnx,divclk-divide = <3>;
			xlnx,clkfb-in-signaling = "SINGLE";
			xlnx,drp-data-set2 = "4b06 , 0001 , 1600 , 8787 , 1a00 , 0202 , 0b00 , 0101 , 0a00 , 0000 , 0a00 , 0101 , f37c , 7c4d , d042 , ebd8 , ec5f , edfb , aacd , 4428 , 002f , 0000 , 0400 , 0101 , 000f , 0006 , 0000 , 0000 , 0e80 , 40e1 , 43e9 , 1188 , 0008 , 0001 , 0000 , 00c0 , 0dfd , 0961 , 0001 , 0000 , 068b , 0a00 , 0303 , 0b00 , 0101 , 0a00 , 0202 , 0000 , 0000 , 0000 , 0000 , 0000 , 0f00 , 0001";
			xlnx,clkout1-actual-phase = <0>;
			xlnx,drp-data-set3 = "4b06 , 0001 , 1600 , 8787 , 1b00 , 0202 , 0a00 , 0303 , 0a00 , 0303 , 0a00 , 0303 , f37c , 7c4d , d042 , ebd8 , ec5f , edfb , aacd , 4428 , 002f , 0000 , 0400 , 0101 , 000f , 0006 , 0000 , 0000 , 0e80 , 40e1 , 43e9 , 1188 , 0008 , 0001 , 0000 , 00c0 , 0dfd , 0961 , 0001 , 0000 , 068b , 0a00 , 0303 , 0a00 , 0303 , 0a00 , 0303 , 0000 , 0000 , 0000 , 0000 , 0000 , 0f00 , 0001";
			xlnx,deskew2-fb = <1>;
			xlnx,secondary-port = "clk_in2";
			xlnx,clkout1-actual-out-freq = <0x11e19748>;
			xlnx,clkout3-phase = <0>;
			xlnx,numbufg = <0>;
			xlnx,clkout3-actual-out-freq = <0x5f5dd18>;
			xlnx,use-reset = <1>;
			xlnx,clkout3-dyn-ps = <00>;
			xlnx,m-min = <5>;
			xlnx,clkout5-actual-out-freq = <0x5f5dd18>;
			xlnx,clkout6-used = <0>;
			xlnx,perf-mode = "FULL";
			xlnx,clkfb-stopped-port = "clkfb_stopped";
			xlnx,clk-out7-port = "clk_out7";
			xlnx,clkout1-requested-phase = <0>;
			xlnx,clkout7-actual-out-freq = <0x5f5dd18>;
			xlnx,phaseshift-mode = "LATENCY";
			xlnx,clkfb-out-port = "clkfb_out";
			xlnx,clkout5-drives = "BUFG";
			xlnx,o-max = <432>;
			xlnx,clkout3-requested-phase = <0>;
			xlnx,jitter-options = "UI";
			xlnx,clkout3-used = <0>;
			xlnx,clkout5-requested-phase = <0>;
			xlnx,clk-out4-port = "clk_out4";
			xlnx,clkout3-duty-cycle = <0x7a120>;
			xlnx,locked-deskew2-port = "locked_deskew2";
			xlnx,clkout7-requested-phase = <0>;
			xlnx,secondary-in-freq = <48>;
			xlnx,clkout5-mbufgce-mode = "PERFORMANCE";
			xlnx,use-min-power = <0>;
			#clock-cells = <1>;
			xlnx,nummbufgce = <0>;
		};
		blp_blp_logic_ulp_clocking_clkwiz_aclk_kernel_01: clk_wizard@80043000 {
			xlnx,reset-type = "ACTIVE_HIGH";
			xlnx,clk-out1-port = "clk_out1";
			xlnx,clkout1-actual-duty-cycle = <50>;
			xlnx,clkout2-phase = <0>;
			xlnx,clkout1-dyn-ps = <00>;
			xlnx,use-locked-deskew1 = <0>;
			xlnx,use-locked-deskew2 = <0>;
			xlnx,clkout3-drives = "BUFG";
			xlnx,deskew-delay1 = <0>;
			reg = <0x0 0x80043000 0x0 0x1000>;
			xlnx,deskew-delay2 = <0>;
			xlnx,clkin2-deskew-port = "clkin2_deskew";
			xlnx,clkout4-grouping = "Auto";
			xlnx,d-max = <107>;
			xlnx,divide6-auto = <0>;
			xlnx,clkout1-phase = <0>;
			xlnx,clkout2-requested-out-freq = <100>;
			xlnx,clkout7-divide = <12>;
			xlnx,use-locked = <1>;
			xlnx,clkin1-ibufds = <0>;
			xlnx,input-clk-stopped-port = "input_clk_stopped";
			xlnx,clkout1-drives = "No_buffer";
			xlnx,divide3-auto = <0>;
			xlnx,clkout4-duty-cycle = <0x7a120>;
			xlnx,clkout4-mbufgce-mode = "PERFORMANCE";
			xlnx,use-dyn-reconfig = <1>;
			xlnx,clkout6-actual-duty-cycle = <50>;
			xlnx,clkout6-requested-duty-cycle = <50>;
			xlnx,deskew2-in = <0>;
			xlnx,deskew1-fb = <1>;
			xlnx,clkin2-jitter-ps = <100>;
			xlnx,feedback-source = "FDBK_AUTO";
			xlnx,clkout5-requested-out-freq = <100>;
			xlnx,bufgce-div-ce-type = "SYNC";
			xlnx,name = "blp_blp_logic_ulp_clocking_clkwiz_aclk_kernel_01";
			xlnx,clkout5-divide = <12>;
			xlnx,current-path = "clk_wizard_v1_0";
			xlnx,prim-in-freq = <0x1fc9f08>;
			xlnx,clkout-matched-routing = "false,false,false,false,false,false,false";
			xlnx,deskew2-lock-circuit-en;
			xlnx,clk-in2-board-interface = "Custom";
			xlnx,clkin1-deskew-port = "clkin1_deskew";
			xlnx,clkin1-ui-jitter = <0x2710>;
			xlnx,clkout3-mbufgce-mode = "PERFORMANCE";
			xlnx,use-inclk-switchover = <0>;
			clock-names = "clk_in1" , "s_axi_aclk";
			xlnx,clkout3-divide = <12>;
			xlnx,clkout5-duty-cycle = <0x7a120>;
			xlnx,clkout1-grouping = "Auto";
			xlnx,use-dyn-phase-shift = <0>;
			xlnx,o-min = <3>;
			xlnx,daddr-port = "daddr";
			xlnx,clkout-grouping = "Auto,Auto,Auto,Auto,Auto,Auto,Auto";
			xlnx,clkin1-bufg = <0>;
			xlnx,precision = <1>;
			clock-output-names = "0x80043000-clk_out1";
			xlnx,clkout1-divide = <12>;
			xlnx,use-phase-alignment = <0>;
			xlnx,ref-clk-freq = <100>;
			xlnx,pllbufgcediv = <0>;
			xlnx,deskew1-in = <0>;
			xlnx,inclk-sum-row0 = "Input , Clock , Freq , (MHz) , Input , Jitter , (UI)";
			xlnx,clkout7-requested-duty-cycle = <50>;
			xlnx,inclk-sum-row1 = "primary , 100.000 , 0.010";
			xlnx,inclk-sum-row2 = "secondary , 100.000 , 0.010";
			xlnx,clkout2-mbufgce-mode = "PERFORMANCE";
			xlnx,din-port = "din";
			xlnx,reset-board-interface = "Custom";
			xlnx,clkout5-actual-duty-cycle = <50>;
			xlnx,clkout-requested-phase = "0.000,0.000,0.000,0.000,0.000,0.000,0.000";
			xlnx,clkout6-duty-cycle = <0x7a120>;
			xlnx,clkout1-requested-duty-cycle = <50>;
			xlnx,vco-max = <4320>;
			xlnx,use-freq-synth = <1>;
			xlnx,clkout5-used = <0>;
			xlnx,d-min = <1>;
			xlnx,clk-out6-port = "clk_out6";
			xlnx,clk-tree1 = <0>;
			xlnx,clkout2-sequence-number = <1>;
			xlnx,clkout-used = "true,false,false,false,false,false,false";
			xlnx,clk-tree2 = <0>;
			xlnx,clk-tree3 = <0>;
			xlnx,clkin1-period = <0x1c9c4ac>;
			xlnx,clkout2-used = <0>;
			xlnx,clkout4-sequence-number = <1>;
			xlnx,psincdec-port = "psincdec";
			xlnx,clk-tree4 = <0>;
			xlnx,clkfbin-ibuf = <0>;
			xlnx,clk-tree5 = <0>;
			xlnx,clk-out3-port = "clk_out3";
			xlnx,clkout6-sequence-number = <1>;
			xlnx,clkout-port = "clk_out1,clk_out2,clk_out3,clk_out4,clk_out5,clk_out6,clk_out7";
			xlnx,locked-deskew1-port = "locked_deskew1";
			xlnx,clk-tree6 = <0>;
			xlnx,clk-tree7 = <0>;
			xlnx,clkin2-ibuf = <0>;
			xlnx,clkfbout-fract = <0>;
			xlnx,clkout5-grouping = "Auto";
			xlnx,pllbufgcediv1 = <0>;
			xlnx,nr-outputs = <1>;
			xlnx,pllbufgcediv2 = <0>;
			xlnx,pllbufgcediv3 = <0>;
			xlnx,pllbufgcediv4 = <0>;
			xlnx,clkout1-mbufgce-mode = "PERFORMANCE";
			xlnx,clkfb-deskew-port = "clkfb_deskew";
			xlnx,clkout2-matched-routing = <0>;
			xlnx,safeclock-startup-mode = "DESKEW_MODE";
			xlnx,ref-jitter1 = <0x2710>;
			xlnx,ref-jitter2 = <0x2710>;
			status = "okay";
			xlnx,clkout4-matched-routing = <0>;
			xlnx,clkout6-dyn-ps = <00>;
			xlnx,clkout6-matched-routing = <0>;
			xlnx,clkout7-duty-cycle = <0x7a120>;
			xlnx,outclk-sum-row1 = "no , clk_out1 , output";
			xlnx,outclk-sum-row2 = "no , clk_out2 , output";
			xlnx,jitter-sel = "No_Jitter";
			xlnx,outclk-sum-row3 = "no , clk_out3 , output";
			xlnx,outclk-sum-row4 = "no , clk_out4 , output";
			xlnx,outclk-sum-row5 = "no , clk_out5 , output";
			xlnx,clkout7-actual-phase = <0>;
			xlnx,outclk-sum-row6 = "no , clk_out6 , output";
			xlnx,outclk-sum-row7 = "no , clk_out7 , output";
			xlnx,divide5-auto = <0>;
			xlnx,deskew-fb1 = <1>;
			xlnx,deskew-fb2 = <1>;
			xlnx,clkfbin-obuf = <0>;
			xlnx,psdone-port = "psdone";
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,clkout3-requested-out-freq = <100>;
			xlnx,divide2-auto = <0>;
			xlnx,clkout4-dyn-ps = <00>;
			xlnx,ss-mode = "CENTER_HIGH";
			xlnx,clkfbout-mult = <1>;
			xlnx,clkout-requested-duty-cycle = "50.000,50.000,50.000,50.000,50.000,50.000,50.000";
			xlnx,clkout6-drives = "BUFG";
			xlnx,ss-mod-period = <4000>;
			xlnx,clkout2-actual-out-freq = <0x5f5dd18>;
			xlnx,clkout2-requested-duty-cycle = <50>;
			xlnx,numbufgce = <0>;
			xlnx,clkout4-actual-duty-cycle = <50>;
			xlnx,clkout4-actual-out-freq = <0x5f5dd18>;
			xlnx,primary-port = "clk_in1";
			xlnx,clkout6-actual-out-freq = <0x5f5dd18>;
			xlnx,clkout6-requested-out-freq = <100>;
			xlnx,clkfbout-oddr = <0>;
			xlnx,use-locked-fb = <0>;
			xlnx,locked-fb-port = "locked_fb";
			xlnx,clkout2-requested-phase = <0>;
			xlnx,relative-inclk = "REL_PRIMARY";
			xlnx,clkout4-requested-phase = <0>;
			xlnx,enable-user-clock0 = <0>;
			xlnx,clkout2-dyn-ps = <00>;
			xlnx,clkout2-grouping = "Auto";
			xlnx,enable-user-clock1 = <0>;
			xlnx,clkout6-actual-phase = <0>;
			xlnx,clkout6-requested-phase = <0>;
			xlnx,clkout-requested-out-frequency = "250,100.000,100.000,100.000,100.000,100.000,100.000";
			xlnx,ss-mod-freq = <250>;
			xlnx,enable-user-clock2 = <0>;
			xlnx,enable-user-clock3 = <0>;
			xlnx,primitive-type = "MMCM";
			xlnx,ce-sync-ext = <0>;
			xlnx,clkout4-drives = "BUFG";
			xlnx,den-port = "den";
			xlnx,use-safe-clock-startup = <0>;
			xlnx,dwe-port = "dwe";
			xlnx,drdy-port = "drdy";
			xlnx,vco-min = <2160>;
			xlnx,clk-in-sel-port = "clk_in_sel";
			xlnx,clkin1-jitter-ps = <100>;
			xlnx,deskew-delay-path1;
			xlnx,deskew-delay-path2;
			xlnx,enable-pll0 = <0>;
			xlnx,enable-pll1 = <0>;
			xlnx,clkin2-ibufds = <0>;
			xlnx,clkfb2-deskew-port = "clkfb2_deskew";
			xlnx,clkout2-drives = "BUFG";
			xlnx,use-inclk-stopped = <0>;
			compatible = "xlnx,clk-wizard-1.0" , "xlnx,versal-clk-wizard";
			xlnx,clkout5-actual-phase = <0>;
			xlnx,reset-port = "reset";
			xlnx,sim-device = "VERSAL_AI_EDGE";
			xlnx,speed-grade = <2>;
			xlnx,clkout6-divide = <12>;
			xlnx,clkout3-requested-duty-cycle = <50>;
			xlnx,prim-source = "No_buffer";
			xlnx,clkout7-used = <0>;
			xlnx,deskew1-delay-en;
			xlnx,use-clkfb-stopped = <0>;
			xlnx,clkout6-grouping = "Auto";
			xlnx,compensation = "AUTO";
			xlnx,mmcmbufgcediv = <0>;
			xlnx,clkin-deskew-port = "clkin_deskew";
			xlnx,clkout3-actual-duty-cycle = <50>;
			xlnx,clkout4-used = <0>;
			xlnx,clk-out5-port = "clk_out5";
			xlnx,psclk-port = "psclk";
			xlnx,ce-type = "SYNC";
			xlnx,clkfbout-phase = <0>;
			xlnx,clkout4-divide = <12>;
			xlnx,primitive = "MMCM";
			xlnx,clkout1-used = <1>;
			xlnx,deskew1-lock-circuit-en;
			xlnx,clk-in1-board-interface = "Custom";
			xlnx,clk-out2-port = "clk_out2";
			xlnx,clkout4-actual-phase = <0>;
			xlnx,power-down-port = "power_down";
			xlnx,clkfb1-deskew-port = "clkfb1_deskew";
			xlnx,bandwidth = "OPTIMIZED";
			xlnx,clkin1-ibuf = <0>;
			xlnx,user-clk-freq0 = <100>;
			xlnx,deskew1-delay-path = "ClkFb_Path";
			xlnx,user-clk-freq1 = <100>;
			xlnx,clkoutfb-phase-ctrl = <00>;
			xlnx,user-clk-freq2 = <100>;
			xlnx,user-clk-freq3 = <100>;
			xlnx,use-clock-sequencing = <0>;
			xlnx,secondary-source = "Single_ended_clock_capable_pin";
			xlnx,cddcdone-port = "cddcdone";
			xlnx,clkout2-divide = <12>;
			xlnx,actual-vco = <0xb2cfe8d0>;
			xlnx,clkout7-phase = <0>;
			xlnx,psen-port = "psen";
			xlnx,m-max = <432>;
			xlnx,deskew-delay-en1;
			xlnx,dclk-port = "dclk";
			xlnx,deskew-delay-en2;
			xlnx,outclk-sum-row0a = "Output , Output , Phase , Duty , Pk-to-Pk , Phase";
			xlnx,divide7-auto = <0>;
			xlnx,clkout1-requested-out-freq = <100>;
			xlnx,outclk-sum-row0b = "Clock , Freq , (MHz) , (degrees) , Cycle , () , Jitter , (ps) , Error , (ps)";
			xlnx,locked-port = "locked";
			xlnx,enable-clock-monitor = <0>;
			xlnx,clkin2-ui-jitter = <0x2710>;
			xlnx,ss-mod-time = <0xfa0>;
			xlnx,divide4-auto = <0>;
			xlnx,auto-primitive = "MMCM";
			xlnx,drp-addr-set1 = "00000328 , 0000032c , 00000330 , 00000334 , 00000338 , 0000033c , 00000340 , 00000344 , 00000348 , 0000034c , 00000350 , 00000354 , 00000358 , 0000035c , 00000360 , 00000364 , 00000368 , 0000036c , 00000370 , 00000374 , 00000378 , 0000037c , 00000380 , 00000384 , 00000388 , 0000038c , 00000390 , 00000394 , 00000398 , 0000039c , 000003a0 , 000003a4 , 000003a8 , 000003ac , 000003b0 , 000003b4 , 000003b8 , 000003bc , 000003c0 , 000003c4 , 000003c8 , 000003cc , 000003d0 , 000003d4 , 000003d8 , 000003dc , 000003e0 , 000003e4 , 000003e8 , 000003ec , 000003f0 , 000003f4 , 000003f8 , 000003fc";
			xlnx,drp-addr-set2 = "00000328 , 0000032c , 00000330 , 00000334 , 00000338 , 0000033c , 00000340 , 00000344 , 00000348 , 0000034c , 00000350 , 00000354 , 00000358 , 0000035c , 00000360 , 00000364 , 00000368 , 0000036c , 00000370 , 00000374 , 00000378 , 0000037c , 00000380 , 00000384 , 00000388 , 0000038c , 00000390 , 00000394 , 00000398 , 0000039c , 000003a0 , 000003a4 , 000003a8 , 000003ac , 000003b0 , 000003b4 , 000003b8 , 000003bc , 000003c0 , 000003c4 , 000003c8 , 000003cc , 000003d0 , 000003d4 , 000003d8 , 000003dc , 000003e0 , 000003e4 , 000003e8 , 000003ec , 000003f0 , 000003f4 , 000003f8 , 000003fc";
			xlnx,drp-addr-set3 = "00000328 , 0000032c , 00000330 , 00000334 , 00000338 , 0000033c , 00000340 , 00000344 , 00000348 , 0000034c , 00000350 , 00000354 , 00000358 , 0000035c , 00000360 , 00000364 , 00000368 , 0000036c , 00000370 , 00000374 , 00000378 , 0000037c , 00000380 , 00000384 , 00000388 , 0000038c , 00000390 , 00000394 , 00000398 , 0000039c , 000003a0 , 000003a4 , 000003a8 , 000003ac , 000003b0 , 000003b4 , 000003b8 , 000003bc , 000003c0 , 000003c4 , 000003c8 , 000003cc , 000003d0 , 000003d4 , 000003d8 , 000003dc , 000003e0 , 000003e4 , 000003e8 , 000003ec , 000003f0 , 000003f4 , 000003f8 , 000003fc";
			xlnx,clkout3-actual-phase = <0>;
			xlnx,clkout-mbufgce-mode = "PERFORMANCE,PERFORMANCE,PERFORMANCE,PERFORMANCE,PERFORMANCE,PERFORMANCE,PERFORMANCE";
			xlnx,use-power-down = <1>;
			xlnx,divide1-auto = <0>;
			xlnx,clkout3-grouping = "Auto";
			xlnx,clkout4-requested-duty-cycle = <50>;
			xlnx,clkout4-requested-out-freq = <100>;
			xlnx,rable = <0>;
			xlnx,clkout6-phase = <0>;
			xlnx,num-out-clks = <1>;
			xlnx,ip-name = "clk_wizard";
			xlnx,auto-nummbufgce = <0>;
			xlnx,deskew-in1 = <0>;
			xlnx,deskew2-delay = <0>;
			xlnx,deskew-in2 = <0>;
			xlnx,mmcmbufgcediv1 = <0>;
			xlnx,deskew2-delay-path = "ClkFb_Path";
			xlnx,mmcmbufgcediv2 = <0>;
			xlnx,clkin2-period = <0x13de432>;
			xlnx,clkout1-duty-cycle = <0x7a120>;
			xlnx,mmcmbufgcediv3 = <0>;
			xlnx,mmcmbufgcediv4 = <0>;
			xlnx,mmcmbufgcediv5 = <0>;
			xlnx,dout-port = "dout";
			xlnx,mmcmbufgcediv6 = <0>;
			xlnx,clkout1-sequence-number = <1>;
			xlnx,mmcmbufgcediv7 = <0>;
			xlnx,cddcreq-port = "cddcreq";
			xlnx,clkout7-requested-out-freq = <100>;
			xlnx,use-spread-spectrum;
			xlnx,clkout3-sequence-number = <1>;
			xlnx,clkout7-mbufgce-mode = "PERFORMANCE";
			xlnx,clkout2-actual-duty-cycle = <50>;
			xlnx,clkout5-sequence-number = <1>;
			xlnx,clkout5-phase = <0>;
			xlnx,clkout7-sequence-number = <1>;
			xlnx,deskew1-delay = <0>;
			xlnx,clkfb-in-port = "clkfb_in";
			xlnx,zhold;
			xlnx,clkout2-actual-phase = <0>;
			xlnx,clkout7-dyn-ps = <00>;
			xlnx,deskew-lock-circuit-en1 = <0>;
			xlnx,clkout-dyn-ps = "None,None,None,None,None,None,None";
			xlnx,deskew-lock-circuit-en2 = <0>;
			xlnx,clkfbout-bufg = <0>;
			xlnx,clkout1-matched-routing = <0>;
			xlnx,interface-selection = <1>;
			xlnx,clkout3-matched-routing = <0>;
			xlnx,override-primitive = <0>;
			xlnx,calc-done = "empty";
			xlnx,clkout5-matched-routing = <0>;
			xlnx,clkfbin-obufds = <0>;
			xlnx,actual-pfd = <0xa98a58>;
			xlnx,clkout7-matched-routing = <0>;
			xlnx,clkin2-bufg = <0>;
			xlnx,clkout2-duty-cycle = <0x7a120>;
			xlnx,clkout4-phase = <0>;
			xlnx,clkout5-dyn-ps = <00>;
			xlnx,clkout6-mbufgce-mode = "PERFORMANCE";
			xlnx,clkout7-actual-duty-cycle = <50>;
			clocks = <&versal_clk 66>, <&versal_clk 66>;
			xlnx,deskew2-delay-en;
			xlnx,clkout7-grouping = "Auto";
			xlnx,clkfbin-ibufds = <0>;
			xlnx,clkfb-bufg = <0>;
			xlnx,clkout7-drives = "BUFG";
			xlnx,clkout-drives = "No_buffer,BUFG,BUFG,BUFG,BUFG,BUFG,BUFG";
			xlnx,clkout5-requested-duty-cycle = <50>;
			xlnx,drp-data-set1 = "4b06 , 0001 , 1600 , 8787 , 1a00 , 0303 , 0a00 , 0303 , 0a00 , 0303 , 0a00 , 0303 , f37c , 7c4d , d042 , ebd8 , ec5f , edfb , aacd , 4428 , 002f , 0000 , 0400 , 0101 , 000f , 0006 , 0000 , 0000 , 0e80 , 40e1 , 43e9 , 1188 , 0008 , 0001 , 0000 , 00c0 , 0dfd , 0961 , 0001 , 0000 , 068b , 0a00 , 0303 , 0a00 , 0303 , 0a00 , 0303 , 0000 , 0000 , 0000 , 0000 , 0000 , 0f00 , 0001";
			xlnx,divclk-divide = <3>;
			xlnx,clkfb-in-signaling = "SINGLE";
			xlnx,drp-data-set2 = "4b06 , 0001 , 1600 , 8787 , 1a00 , 0202 , 0b00 , 0101 , 0a00 , 0000 , 0a00 , 0101 , f37c , 7c4d , d042 , ebd8 , ec5f , edfb , aacd , 4428 , 002f , 0000 , 0400 , 0101 , 000f , 0006 , 0000 , 0000 , 0e80 , 40e1 , 43e9 , 1188 , 0008 , 0001 , 0000 , 00c0 , 0dfd , 0961 , 0001 , 0000 , 068b , 0a00 , 0303 , 0b00 , 0101 , 0a00 , 0202 , 0000 , 0000 , 0000 , 0000 , 0000 , 0f00 , 0001";
			xlnx,clkout1-actual-phase = <0>;
			xlnx,drp-data-set3 = "4b06 , 0001 , 1600 , 8787 , 1a00 , 0303 , 0a00 , 0303 , 0a00 , 0303 , 0a00 , 0303 , f37c , 7c4d , d042 , ebd8 , ec5f , edfb , aacd , 4428 , 002f , 0000 , 0400 , 0101 , 000f , 0006 , 0000 , 0000 , 0e80 , 40e1 , 43e9 , 1188 , 0008 , 0001 , 0000 , 00c0 , 0dfd , 0961 , 0001 , 0000 , 068b , 0a00 , 0303 , 0a00 , 0303 , 0a00 , 0303 , 0000 , 0000 , 0000 , 0000 , 0000 , 0f00 , 0001";
			xlnx,deskew2-fb = <1>;
			xlnx,secondary-port = "clk_in2";
			xlnx,clkout1-actual-out-freq = <0xee6a8bc>;
			xlnx,clkout3-phase = <0>;
			xlnx,numbufg = <0>;
			xlnx,clkout3-actual-out-freq = <0x5f5dd18>;
			xlnx,use-reset = <1>;
			xlnx,clkout3-dyn-ps = <00>;
			xlnx,m-min = <5>;
			xlnx,clkout5-actual-out-freq = <0x5f5dd18>;
			xlnx,clkout6-used = <0>;
			xlnx,perf-mode = "FULL";
			xlnx,clkfb-stopped-port = "clkfb_stopped";
			xlnx,clk-out7-port = "clk_out7";
			xlnx,clkout1-requested-phase = <0>;
			xlnx,clkout7-actual-out-freq = <0x5f5dd18>;
			xlnx,phaseshift-mode = "LATENCY";
			xlnx,clkfb-out-port = "clkfb_out";
			xlnx,clkout5-drives = "BUFG";
			xlnx,o-max = <432>;
			xlnx,clkout3-requested-phase = <0>;
			xlnx,jitter-options = "UI";
			xlnx,clkout3-used = <0>;
			xlnx,clkout5-requested-phase = <0>;
			xlnx,clk-out4-port = "clk_out4";
			xlnx,clkout3-duty-cycle = <0x7a120>;
			xlnx,locked-deskew2-port = "locked_deskew2";
			xlnx,clkout7-requested-phase = <0>;
			xlnx,secondary-in-freq = <48>;
			xlnx,clkout5-mbufgce-mode = "PERFORMANCE";
			xlnx,use-min-power = <0>;
			#clock-cells = <1>;
			xlnx,nummbufgce = <0>;
		};
		blp_blp_logic_ulp_clocking_shell_utils_ucc: shell_utils_ucc@80030000 {
			compatible = "xlnx,shell-utils-ucc-1.0";
			xlnx,ext-tog-enable = <1>;
			xlnx,num-clocks = <2>;
			xlnx,rable = <0>;
			xlnx,ip-name = "shell_utils_ucc";
			reg = <0x0 0x80030000 0x0 0x10000>;
			xlnx,freq-cnt-ref-clk-hz = <33333>;
			clocks = <&versal_clk 65>, <&versal_clk 66>, <&misc_clk_0>, <&blp_blp_logic_ulp_clocking_clkwiz_aclk_kernel_00 0>, <&blp_blp_logic_ulp_clocking_clkwiz_aclk_kernel_01 0>;
			xlnx,edk-iptype = "PERIPHERAL";
			status = "okay";
			clock-names = "aclk_ctrl" , "aclk_freerun" , "aclk_pcie" , "clk_in_kernel_00" , "clk_in_kernel_01";
			xlnx,name = "blp_blp_logic_ulp_clocking_shell_utils_ucc";
		};
		blp_blp_logic_uuid_register: uuid_register@20102002000 {
			xlnx,rable = <0>;
			compatible = "xlnx,uuid-register-1.0";
			status = "okay";
			clock-names = "S_AXI_ACLK";
			xlnx,ip-name = "uuid_register";
			xlnx,edk-iptype = "PERIPHERAL";
			reg = <0x0 0x80045000 0x0 0x1000 0x00000201 0x02002000 0x0 0x1000>;
			clocks = <&versal_clk 65>;
			xlnx,name = "blp_blp_logic_uuid_register";
		};
		blp_qdma_0: axi-pcie@20107000000 {
			xlnx,num-vfs-pf3 = <0>;
			xlnx,dbg-en = "DEBUG_NONE";
			xlnx,pf0-bar1-control = <0x0>;
			xlnx,pf3-bar6-control = <0x0>;
			reg = <0x00000201 0x07000000 0x0 0x4000>;
			xlnx,pf1-msix-cap-pba-bir-qdma = "BAR_1:0";
			xlnx,pf0-sriov-bar3-control = <0x0>;
			xlnx,pf2-sriov-bar2-scale = "Kilobytes";
			xlnx,pf2-bar1-type-qdma = "AXI_Bridge_Master";
			xlnx,dma-2rp;
			xlnx,pf2-sriov-bar3-type = "AXI_Bridge_Master";
			xlnx,pf3-bar4-size-qdma = <128>;
			xlnx,select-quad = "GTH_Quad_128";
			xlnx,pf2-sriov-bar0-type = "DMA";
			xlnx,pf1-class-code-qdma = <120000>;
			xlnx,pf1-msix-cap-pba-offset-qdma = <34000>;
			xlnx,sys-rst-n-board-interface = "Custom";
			xlnx,ats-cap-nextptr = <0x0>;
			xlnx,pf3-sriov-bar3-control = <0x0>;
			xlnx,coreclk-freq = <500>;
			xlnx,pf2-bar1-scale-qdma = "Megabytes";
			xlnx,pf2-sriov-bar1-scale = "Kilobytes";
			xlnx,example-design-type = "RTL";
			xlnx,pf0-expansion-rom-size-qdma = <4>;
			xlnx,pf1-bar0-prefetchable-qdma;
			xlnx,pf2-bar6-control = <0x0>;
			xlnx,pf3-msix-cap-table-bir-qdma = "BAR_1:0";
			xlnx,pf0-bar3-aperture-size = <0x0>;
			xlnx,pf0-msi-cap-multimsgcap = <0>;
			xlnx,usr-irq-exdes;
			xlnx,pf1-msix-cap-pba-offset = <00010050>;
			xlnx,timeout-mult = <0x3>;
			xlnx,pf2-sriov-bar0-scale = "Kilobytes";
			xlnx,pf0-bar0-enabled-qdma;
			xlnx,pf1-msix-cap-pba-bir = "BAR_0";
			xlnx,pf3-bar3-aperture-size = <00000000>;
			xlnx,pf1-vendor-id = <0x10ee>;
			xlnx,minimal-dma-en;
			xlnx,msix-impl-ext;
			clock-names = "user_clk_sd";
			xlnx,vfg0-msix-cap-table-size-qdma = <007>;
			xlnx,pf2-bar2-scale-qdma = "Kilobytes";
			xlnx,pf1-sriov-bar4-type = "AXI_Bridge_Master";
			xlnx,pf2-bar2-size-qdma = <4>;
			xlnx,pf1-bar6-control = <0x0>;
			xlnx,pf2-bar0-64bit-qdma;
			xlnx,pf1-sriov-bar1-type = "AXI_Bridge_Master";
			xlnx,pf2-rbar-num = <1>;
			xlnx,pf2-sriov-bar1-control = <0x0>;
			xlnx,rx-ssc-ppm = <0>;
			xlnx,pcie-board-interface = "Custom";
			xlnx,vdm-en;
			xlnx,ref-clk-freq = <0>;
			xlnx,pf1-msi-cap-multimsgcap = "1_vector";
			xlnx,axilite-master-en;
			xlnx,pf0-msix-cap-pba-offset-qdma = <34000>;
			xlnx,pf2-bar3-scale-qdma = "Kilobytes";
			xlnx,wrb-coal-loop-fix-disable = <0>;
			xlnx,pf0-bar6-control = <0x0>;
			xlnx,csr-axilite-slave;
			xlnx,pf3-sriov-bar5-size = <4>;
			xlnx,pf1-sriov-first-vf-offset = <0>;
			xlnx,pf3-bar2-type-qdma = "AXI_Lite_Master";
			xlnx,pf1-msix-enabled-qdma;
			xlnx,pf3-sriov-bar2-size = <4>;
			xlnx,xdma-aperture-size = <0xd>;
			xlnx,pf1-bar0-size-qdma = <256>;
			xlnx,pf0-sriov-bar5-type = "AXI_Bridge_Master";
			xlnx,num-queues = <512>;
			status = "okay";
			xlnx,pf0-subsystem-vendor-id = <0x10ee>;
			xlnx,pf1-msix-cap-table-offset-qdma = <30000>;
			xlnx,pcie-extended-tag;
			xlnx,pf0-sriov-func-dep-link = <0000>;
			xlnx,pf0-sriov-bar2-type = "AXI_Lite_Master";
			xlnx,pf2-msi-cap-multimsgcap = "1_vector";
			xlnx,pf2-bar4-scale-qdma = "Kilobytes";
			xlnx,barlite-msix-pf0 = <0x4>;
			xlnx,barlite-msix-pf1 = <000001>;
			xlnx,pf2-bar6-aperture-size = <00000000>;
			xlnx,barlite-msix-pf2 = <000000>;
			xlnx,barlite-msix-pf3 = <000000>;
			xlnx,pf2-bar2-64bit-qdma;
			xlnx,pf3-addr-mask = <0xfff>;
			xlnx,bar5-indicator = <0>;
			xlnx,pf3-bar2-enabled-qdma;
			xlnx,pf3-revision-id = <0x0>;
			xlnx,pf2-bar1-aperture-size = <00000000>;
			xlnx,vfg1-msix-cap-table-bir-qdma = "BAR_1:0";
			xlnx,enable-jtag-dbg;
			xlnx,en-bridge;
			xlnx,dedicate-perst;
			xlnx,msix-int-table-en = <0>;
			xlnx,pf2-bar0-type-qdma = "DMA";
			xlnx,shared-logic = <0>;
			xlnx,split-dma;
			xlnx,pf2-bar5-scale-qdma = "Kilobytes";
			xlnx,pf2-sriov-bar3-size = <4>;
			xlnx,xdma-num-pcie-tag = <256>;
			xlnx,pf3-bar3-size-qdma = <128>;
			xlnx,pf1-subsystem-vendor-id = <0x10ee>;
			xlnx,ccix-dvsec;
			xlnx,pf1-sriov-func-dep-link = <0001>;
			xlnx,pf3-bar0-control = <0x0>;
			xlnx,xdma-en;
			xlnx,pf2-sriov-bar0-size = <32>;
			xlnx,pf3-msi-cap-multimsgcap = "1_vector";
			xlnx,vfg2-msix-cap-table-offset-qdma = <4000>;
			xlnx,pf2-sriov-bar2-prefetchable;
			xlnx,pf0-class-code-interface-qdma = <00>;
			xlnx,pf2-rbar-cap-bar0 = <0xfff0>;
			xlnx,axi-vip-in-exdes;
			xlnx,pf1-sriov-cap-initial-vf = <0>;
			xlnx,pf2-rbar-cap-bar1 = <0x0>;
			xlnx,pf2-rbar-cap-bar2 = <0x0>;
			xlnx,barlite-mb-pf0 = <0>;
			xlnx,pf2-rbar-cap-bar3 = <0x0>;
			xlnx,barlite-mb-pf1 = <0>;
			xlnx,pf2-rbar-cap-bar4 = <0x0>;
			xlnx,barlite-mb-pf2 = <0>;
			xlnx,axibar-0 = <0x0>;
			xlnx,pf2-rbar-cap-bar5 = <0x0>;
			xlnx,barlite-mb-pf3 = <0>;
			xlnx,axibar-1 = <0x0>;
			xlnx,pf2-base-class-menu-qdma = "Memory_controller";
			xlnx,axibar-2 = <0x0>;
			xlnx,axilite-master-scale = "Megabytes";
			xlnx,axibar-3 = <0x0>;
			xlnx,xdma-dsc-bypass;
			xlnx,include-baroffset-reg = <0x1>;
			xlnx,axibar-4 = <0x0>;
			xlnx,axibar-5 = <0x0>;
			xlnx,pf1-sriov-bar2-64bit;
			xlnx,pf1-class-code-base-qdma = <12>;
			xlnx,axist-bypass-aperture-size = <0xd>;
			xlnx,pf2-bar0-control = <0x0>;
			xlnx,pf2-sub-class-interface-menu-qdma = "Other_memory_controller";
			xlnx,pf0-vendor-id = <0x10ee>;
			xlnx,pf3-bar0-enabled-qdma;
			xlnx,legacy-cfg-ext-if;
			xlnx,pf1-msix-cap-table-bir-qdma = "BAR_1:0";
			xlnx,pf0-vf-bar3-aperture-size = <00000000>;
			xlnx,pf2-subsystem-vendor-id = <0x10ee>;
			xlnx,pf2-sriov-func-dep-link = <0002>;
			xlnx,pf1-sriov-bar2-enabled;
			xlnx,pf1-sriov-bar4-control = <0x0>;
			xlnx,pf2-bar1-size-qdma = <128>;
			xlnx,pf1-sriov-bar4-size = <4>;
			xlnx,pf1-vf-bar6-aperture-size = <0x0>;
			xlnx,pf2-class-code-interface-qdma = <00>;
			xlnx,pf1-bar4-aperture-size = <0x0>;
			xlnx,pf1-sriov-bar1-size = <4>;
			xlnx,enable-resource-reduction;
			xlnx,cfg-mgmt-if;
			xlnx,parity-settings = "None";
			xlnx,pf1-bar0-control = <0x7>;
			xlnx,pf1-sriov-bar0-64bit;
			xlnx,pf1-vf-bar1-aperture-size = <00000000>;
			xlnx,pf2-sriov-bar0-prefetchable;
			xlnx,pf2-vf-bar4-aperture-size = <00000000>;
			xlnx,pf0-msix-cap-table-offset = "00008000";
			xlnx,cmp-col-reg-0 = <1>;
			xlnx,cmp-col-reg-1 = <0>;
			xlnx,cmp-col-reg-2 = <0>;
			xlnx,vfg2-msix-cap-pba-bir-qdma = "BAR_1:0";
			xlnx,cmp-col-reg-3 = <0>;
			xlnx,cmp-col-reg-4 = <0>;
			xlnx,cmp-col-reg-5 = <0>;
			xlnx,msix-type = "HARD";
			xlnx,cmp-col-reg-6 = <0>;
			xlnx,pf3-subsystem-vendor-id = <0x10ee>;
			xlnx,cmp-col-reg-7 = <0>;
			xlnx,pf0-msix-cap-table-size = <020>;
			xlnx,pf3-vf-bar2-aperture-size = <00000000>;
			xlnx,pf3-sriov-func-dep-link = <0003>;
			xlnx,sriov-en = <0>;
			xlnx,pf3-bar1-type-qdma = "AXI_Bridge_Master";
			xlnx,soft-nic-bridge;
			xlnx,pf3-expansion-rom-type-qdma = "Expansion_ROM";
			xlnx,pf0-bar0-control = <0x7>;
			xlnx,pf3-bar5-control = <0x0>;
			xlnx,pf0-sriov-bar0-enabled;
			xlnx,pf0-sriov-bar2-control = <0x7>;
			xlnx,pf0-sriov-bar5-size = <4>;
			xlnx,pciebar2axibar-xdma = <0x0>;
			xlnx,sim-model;
			xlnx,bar-indicator = "BAR_0";
			xlnx,gtwiz-in-core = <1>;
			xlnx,pf0-sriov-bar2-size = <4>;
			xlnx,pf3-sriov-bar0-enabled;
			xlnx,pf3-sriov-bar2-control = <0x0>;
			xlnx,pcie-blk-type = <1>;
			xlnx,vu9p-board;
			xlnx,pf2-addr-mask = <0xfff>;
			xlnx,dma-en = <1>;
			xlnx,bar4-indicator = <0>;
			xlnx,pf0-bar5-type-qdma = "AXI_Bridge_Master";
			xlnx,pf0-msix-cap-table-bir = "BAR_0";
			xlnx,pf0-vc-cap-enabled;
			xlnx,pf2-bar5-control = <0x0>;
			xlnx,pf3-interrupt-pin = <001>;
			xlnx,pf1-msix-cap-table-size = <020>;
			xlnx,csr-slcr = <0x90000000>;
			xlnx,pf3-msix-cap-pba-bir-qdma = "BAR_1:0";
			xlnx,pf3-pciebar2axibar-0 = <0x0>;
			xlnx,pf3-pciebar2axibar-1 = <0x30000000>;
			xlnx,dsc-byp-mode = "NONE";
			xlnx,pf3-pciebar2axibar-2 = <0x30000000>;
			xlnx,pf3-bar2-size-qdma = <4>;
			xlnx,pf3-pciebar2axibar-3 = <0x0>;
			xlnx,pf3-pciebar2axibar-4 = <0x0>;
			xlnx,pf0-bar2-aperture-size = <0xb>;
			xlnx,pf3-pciebar2axibar-5 = <0x0>;
			xlnx,pf3-pciebar2axibar-6 = <0000000000000000000000000000000000000000000000000000000000000000>;
			xlnx,pf1-bar5-control = <0x0>;
			xlnx,pf2-sriov-bar0-control = <0x0>;
			xlnx,pf3-bar2-aperture-size = <00000000>;
			xlnx,pciebar2axibar-0 = <0x201 0x00000000>;
			xlnx,pciebar2axibar-1 = <0x0>;
			xlnx,pciebar2axibar-2 = <0x0>;
			xlnx,pciebar2axibar-3 = <0x0>;
			xlnx,pciebar2axibar-4 = <0x0>;
			xlnx,pf3-device-id = <0xb338>;
			xlnx,pciebar2axibar-5 = <0x0>;
			xlnx,pciebar2axibar-6 = <0000000000000000000000000000000000000000000000000000000000000000>;
			xlnx,pf0-sriov-bar2-prefetchable;
			xlnx,xdma-axist-bypass;
			xlnx,xdma-rnum-rids = <32>;
			xlnx,pf0-bar5-control = <0x0>;
			xlnx,pf3-msix-cap-table-size-qdma = <007>;
			xlnx,en-axi-slave-if;
			xlnx,pf2-bar0-size-qdma = <256>;
			xlnx,pf3-class-code-qdma = "058000";
			xlnx,sriov-first-vf-offset = <16>;
			xlnx,pf0-bar5-index = <7>;
			xlnx,h2c-num-chnl = <4>;
			xlnx,dma-mm = <1>;
			xlnx,axi-addr-width = <64>;
			xlnx,s-axi-num-read = <8>;
			xlnx,egw-is-parent-ip = <1>;
			xlnx,async-clk-enable;
			xlnx,pf0-bar4-index = <7>;
			xlnx,comp-timeout = <1>;
			xlnx,xdma-control = <0x4>;
			xlnx,rx-detect = <0>;
			xlnx,pf0-sriov-bar0-prefetchable;
			xlnx,pf3-bar0-type-qdma = "DMA";
			xlnx,pf3-sriov-first-vf-offset = <0>;
			xlnx,pf1-bar5-index = <7>;
			xlnx,use-standard-interfaces;
			xlnx,pf2-bar5-aperture-size = <00000000>;
			xlnx,pf3-sriov-bar4-type = "AXI_Bridge_Master";
			xlnx,pcie-id-if;
			xlnx,pf0-bar3-index = <7>;
			xlnx,pf0-sub-class-interface-menu-qdma = "Other_memory_controller";
			xlnx,pf3-sriov-bar1-type = "AXI_Bridge_Master";
			xlnx,pf2-sriov-bar5-control = <0x0>;
			xlnx,enable-pcie-debug-ports;
			xlnx,func-mode = <1>;
			xlnx,num-of-bars = <0x2>;
			xlnx,pf2-bar0-aperture-size = <00000000>;
			reg-names = "cfg" , "breg";
			xlnx,xlnx-ref-board = "EMB-PLUS-VPR-4616";
			xlnx,dma-reset-source-sel = <0>;
			#interrupt-cells = <1>;
			xlnx,pf1-bar4-index = <7>;
			xlnx,pl-link-cap-max-link-width = <8>;
			xlnx,pf1-expansion-rom-type-qdma = "Expansion_ROM";
			xlnx,pf2-msix-cap-table-size-qdma = <007>;
			xlnx,vcu118-board;
			xlnx,pf0-sriov-vf-device-id = "C038";
			xlnx,pf0-bar2-index = <7>;
			xlnx,pf1-addr-mask = <0x7ffffff>;
			xlnx,bar3-indicator = <0>;
			xlnx,silicon-rev = "Pre-Production";
			xlnx,mhost-en;
			xlnx,pf0-bar4-type-qdma = "AXI_Bridge_Master";
			xlnx,pf2-bar5-index = <7>;
			xlnx,xdma-wnum-rids = <32>;
			xlnx,cmp-err-reg-0 = <2>;
			xlnx,cmp-err-reg-1 = <0>;
			xlnx,pf0-pciebar2axibar-0 = <0x201 0x00000000>;
			xlnx,cmp-err-reg-2 = <0>;
			xlnx,pf0-pciebar2axibar-1 = <0x0>;
			xlnx,pf3-sriov-vf-device-id = "C338";
			xlnx,cmp-err-reg-3 = <0>;
			xlnx,pf0-pciebar2axibar-2 = <0x0>;
			xlnx,pf1-bar3-index = <7>;
			xlnx,cmp-err-reg-4 = <0>;
			xlnx,pf0-pciebar2axibar-3 = <0x0>;
			xlnx,cmp-err-reg-5 = <0>;
			xlnx,pf0-pciebar2axibar-4 = <0x0>;
			xlnx,pf1-sriov-bar5-scale = "Kilobytes";
			xlnx,cmp-err-reg-6 = <0>;
			xlnx,pf0-pciebar2axibar-5 = <0x0>;
			xlnx,cmp-err-reg-7 = <0>;
			xlnx,pf0-pciebar2axibar-6 = <0x0>;
			xlnx,pf0-bar1-index = <7>;
			xlnx,pf1-rbar-cap-bar0 = <0xfff0>;
			xlnx,pl-upstream-facing;
			xlnx,pf1-rbar-cap-bar1 = <0x0>;
			xlnx,pf1-rbar-cap-bar2 = <0x0>;
			xlnx,pf1-rbar-cap-bar3 = <0x0>;
			xlnx,pf1-rbar-cap-bar4 = <0x0>;
			xlnx,pf1-rbar-cap-bar5 = <0x0>;
			xlnx,pf2-bar4-index = <7>;
			xlnx,pf3-bar1-size-qdma = <128>;
			xlnx,dma-st = <0>;
			xlnx,pf2-sriov-bar5-type = "AXI_Bridge_Master";
			xlnx,pf3-expansion-rom-size-qdma = <4>;
			xlnx,pf1-bar2-index = <7>;
			xlnx,tl-pf-enable-reg = <2>;
			xlnx,pf1-sriov-bar3-control = <0x0>;
			xlnx,pf1-sriov-bar4-scale = "Kilobytes";
			xlnx,pf2-sriov-bar2-type = "AXI_Lite_Master";
			xlnx,pf0-bar0-index = <0>;
			xlnx,pf3-bar5-index = <7>;
			xlnx,xdma-axi-intf-mm = <1>;
			xlnx,rq-seq-num-ignore = <0>;
			xlnx,axisten-freq = <250>;
			xlnx,enable-code = <0000>;
			xlnx,pf2-bar3-index = <7>;
			xlnx,edk-iptype = "PERIPHERAL";
			xlnx,cfg-space-enable;
			xlnx,gen4-eieos-0s7;
			xlnx,pf1-bar1-index = <7>;
			xlnx,pf2-device-id = <0x923f>;
			xlnx,vendor-id = "10EE";
			xlnx,pf0-vf-bar2-aperture-size = <00000000>;
			xlnx,axilite-master-size = <1>;
			xlnx,gt-available = "GTYP_QUAD_X0Y0,GTYP_QUAD_X0Y1";
			xlnx,pf1-sriov-bar3-scale = "Kilobytes";
			xlnx,port-type = <0x1>;
			xlnx,pf1-vf-bar5-aperture-size = <00000000>;
			xlnx,pf3-bar4-index = <7>;
			xlnx,pf0-bar5-size-qdma = <128>;
			xlnx,pf1-bar3-aperture-size = <0x0>;
			xlnx,pf2-bar2-index = <7>;
			xlnx,pf1-msix-cap-table-size-qdma = "01F";
			xlnx,pf3-sriov-cap-ver = <1>;
			xlnx,pf1-sriov-supported-page-size = <00000553>;
			xlnx,pf1-bar0-index = <0>;
			xlnx,pf1-bar0-scale-qdma = "Kilobytes";
			xlnx,pf1-vf-bar0-aperture-size = <00000000>;
			xlnx,pf1-sriov-bar2-scale = "Kilobytes";
			xlnx,pf3-rbar-num = <1>;
			xlnx,pf2-vf-bar3-aperture-size = <00000000>;
			xlnx,pf3-bar3-index = <7>;
			xlnx,dma-mode-en;
			xlnx,pf0-msix-enabled-qdma;
			xlnx,pf3-bar4-control = <0x0>;
			xlnx,pf3-vf-bar6-aperture-size = <0x0>;
			xlnx,pf0-sriov-bar1-control = <0x0>;
			xlnx,pf2-bar1-index = <7>;
			xlnx,pf1-sriov-bar3-type = "AXI_Bridge_Master";
			xlnx,xdma-non-incremental-exdes;
			xlnx,type1-prefetchable-membase-memlimit = "Disabled";
			xlnx,axilite-master-control = <0x4>;
			xlnx,pf1-sriov-bar1-scale = "Kilobytes";
			xlnx,versal-part-type = "HXX";
			xlnx,pf1-sriov-bar0-type = "DMA";
			xlnx,pf0-class-code-qdma = <120000>;
			xlnx,pf3-msix-cap-table-offset-qdma = <30000>;
			xlnx,pf3-vf-bar1-aperture-size = <00000000>;
			xlnx,enable-auto-rxeq;
			xlnx,cfg-ext-if;
			compatible = "xlnx,qdma-5.0" , "xlnx,qdma-host-3.00";
			xlnx,pf3-bar2-index = <7>;
			xlnx,pf3-sriov-bar1-control = <0x0>;
			xlnx,pf1-bar5-type-qdma = "AXI_Bridge_Master";
			xlnx,pf0-msix-cap-pba-bir-qdma = "BAR_3:2";
			xlnx,pf1-bar1-scale-qdma = "Megabytes";
			xlnx,pf2-bar0-index = <0>;
			device_type = "pci";
			xlnx,pl-disable-lane-reversal;
			xlnx,pf2-bar2-enabled-qdma;
			xlnx,pf2-bar4-control = <0x0>;
			xlnx,axist-bypass-scale = "Megabytes";
			xlnx,pf3-sriov-supported-page-size = <00000553>;
			xlnx,pf1-sriov-bar0-scale = "Kilobytes";
			xlnx,pf0-msix-cap-pba-bir = "BAR_0";
			xlnx,flr-enable;
			xlnx,pf3-bar1-index = <7>;
			xlnx,multq-en = <1>;
			xlnx,pf3-sriov-bar2-64bit;
			xlnx,pf3-sriov-bar4-size = <4>;
			xlnx,pf0-rbar-num = <1>;
			xlnx,mdma-pfch-cache-depth = <16>;
			xlnx,testname = "mm";
			xlnx,pf3-sriov-bar1-size = <4>;
			xlnx,pf2-interrupt-pin = <001>;
			xlnx,pf1-bar2-scale-qdma = "Megabytes";
			xlnx,pf3-bar0-index = <0>;
			xlnx,pf2-sriov-cap-initial-vf = <0>;
			xlnx,m-axi-num-read = <8>;
			xlnx,pf0-msix-cap-table-size-qdma = "01F";
			xlnx,pf0-bar6-aperture-size = <0x0>;
			xlnx,pf0-sriov-bar4-type = "AXI_Bridge_Master";
			xlnx,pf1-bar4-control = <0x0>;
			xlnx,metering-on = <1>;
			xlnx,pf3-base-class-menu-qdma = "Memory_controller";
			xlnx,pf0-addr-mask = <0x3ffff>;
			xlnx,pf1-bar0-64bit-qdma;
			xlnx,xdma-axilite-master;
			xlnx,mailbox-enable;
			xlnx,pf0-sriov-bar1-type = "AXI_Bridge_Master";
			xlnx,bar2-indicator = <0>;
			xlnx,pf0-bar3-type-qdma = "AXI_Bridge_Master";
			interrupt-map-mask = < 0 0 0 7 >;
			xlnx,axisten-if-msix-rx-parity-en;
			xlnx,pf2-class-code-base-qdma = <05>;
			xlnx,pf1-bar2-prefetchable-qdma;
			xlnx,pf0-bar1-aperture-size = <0x0>;
			xlnx,pf3-bar6-aperture-size = <00000000>;
			xlnx,pf3-sriov-bar0-64bit;
			xlnx,pf0-msix-cap-table-offset-qdma = <30000>;
			xlnx,pf1-bar3-scale-qdma = "Kilobytes";
			xlnx,pf3-bar1-aperture-size = <00000000>;
			xlnx,enable-gen4;
			xlnx,pf0-bar4-control = <0x0>;
			xlnx,pf2-bar0-enabled-qdma;
			xlnx,pf3-bar0-size-qdma = <256>;
			xlnx,pf0-revision-id = <0x0>;
			xlnx,pf2-sriov-bar5-size = <4>;
			xlnx,s-axi-id-width = <4>;
			xlnx,msix-enabled;
			xlnx,pf2-sriov-bar2-size = <4>;
			xlnx,xlnx-ddr-ex;
			xlnx,enable-ccix;
			xlnx,last-core-cap-addr = <0x100>;
			xlnx,pf1-expansion-rom-size-qdma = <4>;
			xlnx,mult-pf-des;
			xlnx,pf1-device-id = <0x5701>;
			xlnx,pll-type = <2>;
			xlnx,timeout0-sel = <0xe>;
			xlnx,pf0-sriov-first-vf-offset = <16>;
			xlnx,lane-order = "Bottom";
			xlnx,pf1-bar4-scale-qdma = "Kilobytes";
			xlnx,soft-nic;
			xlnx,barlite-ext-pf0 = <000000>;
			xlnx,pf0-bar4-size-qdma = <128>;
			xlnx,barlite-ext-pf1 = <000000>;
			xlnx,barlite-ext-pf2 = <000000>;
			xlnx,barlite-ext-pf3 = <000000>;
			xlnx,pf1-bar2-64bit-qdma;
			xlnx,pf3-enabled = <0>;
			xlnx,vfg1-msix-cap-table-offset-qdma = <4000>;
			xlnx,enable-error-injection;
			xlnx,debug-mode = "DEBUG_NONE";
			xlnx,gt-selected = "GTYP_QUAD_X0Y0,GTYP_QUAD_X0Y1";
			xlnx,pf3-msix-enabled-qdma;
			xlnx,pf1-bar5-scale-qdma = "Kilobytes";
			xlnx,pf1-sriov-bar3-size = <4>;
			xlnx,pf2-sriov-bar2-enabled;
			xlnx,pf2-sriov-bar4-control = <0x0>;
			xlnx,mcap-enablement = "NONE";
			xlnx,pf1-sriov-bar0-size = <32>;
			xlnx,csr-module = <1>;
			xlnx,pf2-bar4-aperture-size = <00000000>;
			xlnx,pf1-bar4-type-qdma = "AXI_Bridge_Master";
			xlnx,vf-barlite-ext-pf0 = <000000>;
			xlnx,vf-barlite-ext-pf1 = <000000>;
			xlnx,vf-barlite-ext-pf2 = <000000>;
			xlnx,vf-barlite-ext-pf3 = <000000>;
			xlnx,pf0-sriov-bar2-64bit;
			xlnx,pf3-msix-vectors = <0>;
			xlnx,versal-part-type-hxx = "HXX";
			xlnx,msi-x-options = "MSI-X_External";
			xlnx,copy-sriov-pf0;
			xlnx,rx-ppm-offset = <0>;
			xlnx,axisten-if-enable-msg-route-override;
			xlnx,axibar-highaddr-0 = <0x0>;
			xlnx,versal;
			xlnx,axibar-highaddr-1 = <0x0>;
			xlnx,axibar-highaddr-2 = <0x0>;
			xlnx,axibar-highaddr-3 = <0x0>;
			xlnx,axibar-highaddr-4 = <0x0>;
			xlnx,vfg3-msix-cap-pba-offset-qdma = <4800>;
			xlnx,name = "blp_qdma_0";
			xlnx,axibar-highaddr-5 = <0x0>;
			xlnx,pf1-sriov-bar0-enabled;
			xlnx,pf1-sriov-bar2-control = <0x7>;
			xlnx,pf2-msix-vectors = <8>;
			xlnx,pf0-bar0-prefetchable-qdma;
			xlnx,pf0-sriov-bar4-size = <4>;
			xlnx,pf0-rbar-cap-bar0 = <0xfff0>;
			xlnx,h2c-xdma-chnl = <0x1>;
			xlnx,pf0-rbar-cap-bar1 = <0x0>;
			xlnx,pf0-sriov-bar0-64bit;
			xlnx,pf0-rbar-cap-bar2 = <0x0>;
			xlnx,bar1-indicator = <0>;
			xlnx,pf0-rbar-cap-bar3 = <0x0>;
			xlnx,pf0-bar2-type-qdma = "DMA";
			xlnx,pf0-rbar-cap-bar4 = <0x0>;
			xlnx,pf0-sriov-bar1-size = <4>;
			xlnx,enable-clock-delay-grp;
			xlnx,pf0-rbar-cap-bar5 = <0x0>;
			xlnx,c2h-stream-cpl-err-bit-pos0 = <2>;
			xlnx,c2h-stream-cpl-err-bit-pos1 = <0>;
			xlnx,c2h-stream-cpl-err-bit-pos2 = <0>;
			xlnx,c2h-stream-cpl-err-bit-pos3 = <0>;
			xlnx,pf1-bar5-size-qdma = <128>;
			xlnx,c2h-stream-cpl-err-bit-pos4 = <0>;
			xlnx,c2h-stream-cpl-err-bit-pos5 = <0>;
			xlnx,c2h-stream-cpl-err-bit-pos6 = <0>;
			xlnx,c2h-stream-cpl-err-bit-pos7 = <0>;
			xlnx,vfg2-msix-cap-table-bir-qdma = "BAR_1:0";
			xlnx,pf0-vf-bar6-aperture-size = <0x0>;
			xlnx,pf1-msix-cap-table-bir = "BAR_0";
			xlnx,pf1-msix-vectors = <32>;
			xlnx,pf0-base-class-menu-qdma = "Memory_controller";
			xlnx,axibar-notranslate = <0>;
			xlnx,pf0-vf-bar1-aperture-size = <00000000>;
			xlnx,enable-pcie-debug-axi4-st;
			xlnx,xdma-st-infinite-desc-exdes;
			xlnx,pf1-vf-bar4-aperture-size = <00000000>;
			xlnx,pf3-bar3-control = <0x0>;
			xlnx,pf0-sriov-bar0-control = <0x7>;
			xlnx,pf3-sriov-bar2-prefetchable;
			xlnx,pf1-bar2-aperture-size = <0x14>;
			xlnx,user-clk-freq = <2>;
			xlnx,shell-bridge = <0>;
			xlnx,pf3-sub-class-interface-menu-qdma = "Other_memory_controller";
			xlnx,pf2-sriov-cap-ver = <1>;
			xlnx,vfg1-msix-cap-pba-bir-qdma = "BAR_1:0";
			xlnx,pf0-device-id = <0x5700>;
			xlnx,pf2-bar5-type-qdma = "AXI_Bridge_Master";
			xlnx,pf0-msix-vectors = <32>;
			xlnx,pf3-sriov-bar0-control = <0x0>;
			xlnx,pf2-vf-bar2-aperture-size = <00000000>;
			xlnx,xdma-rnum-chnl = <4>;
			xlnx,pf0-bar3-size-qdma = <128>;
			xlnx,all-speeds-all-sides;
			xlnx,pf3-vf-bar5-aperture-size = <00000000>;
			xlnx,vfg2-msix-cap-pba-offset-qdma = <4800>;
			xlnx,mode-selection = "Advanced";
			xlnx,pf2-bar3-control = <0x0>;
			xlnx,pf2-msix-cap-table-bir-qdma = "BAR_1:0";
			xlnx,enable-more;
			xlnx,pf3-vf-bar0-aperture-size = <00000000>;
			xlnx,pf2-pciebar2axibar-0 = <0x0>;
			xlnx,pf2-pciebar2axibar-1 = <0x20000000>;
			xlnx,tandem-rfsoc;
			xlnx,gt-loc-num = "X99Y99";
			xlnx,pf2-pciebar2axibar-2 = <0x20000000>;
			xlnx,pf2-pciebar2axibar-3 = <0x0>;
			xlnx,pf3-sriov-bar5-scale = "Kilobytes";
			xlnx,is-board-project = <1>;
			xlnx,pf2-pciebar2axibar-4 = <0x0>;
			xlnx,pf2-pciebar2axibar-5 = <0x0>;
			xlnx,pf2-pciebar2axibar-6 = <0000000000000000000000000000000000000000000000000000000000000000>;
			xlnx,pcie-pfs-supported = <2>;
			xlnx,pipe-line-stage = <2>;
			xlnx,pciebar2axibar-axist-bypass = <0x0>;
			xlnx,axist-bypass-en;
			xlnx,pf1-bar3-control = <0x0>;
			xlnx,pf1-bar3-type-qdma = "AXI_Bridge_Master";
			xlnx,wrb-coal-max-buf = <16>;
			xlnx,pl-link-cap-max-link-speed = <4>;
			xlnx,pf3-sriov-bar4-scale = "Kilobytes";
			xlnx,pf3-sriov-bar0-prefetchable;
			xlnx,pcie-blk-locn = <0>;
			xlnx,pf2-msix-cap-pba-bir-qdma = "BAR_1:0";
			xlnx,pf1-interrupt-pin = <001>;
			xlnx,pf0-vf-pciebar2axibar-0 = <0x0>;
			xlnx,pf3-bar0-scale-qdma = "Kilobytes";
			xlnx,pf0-vf-pciebar2axibar-1 = <0x40000000>;
			xlnx,pf0-bar5-aperture-size = <0x0>;
			xlnx,pf0-vf-pciebar2axibar-2 = <0x40000000>;
			xlnx,pf3-sriov-bar3-scale = "Kilobytes";
			xlnx,pf0-vf-pciebar2axibar-3 = <0x0>;
			xlnx,pf0-vf-pciebar2axibar-4 = <0x0>;
			xlnx,pf0-link-status-slot-clock-config;
			xlnx,pf0-vf-pciebar2axibar-5 = <0x0>;
			xlnx,msix-pcie-internal = <0>;
			xlnx,pf0-bar3-control = <0x0>;
			xlnx,enable-ibert;
			xlnx,pf0-sriov-bar5-control = <0x0>;
			xlnx,pf3-sriov-bar3-type = "AXI_Bridge_Master";
			xlnx,functional-mode = "QDMA";
			xlnx,pf0-bar0-aperture-size = <0x15>;
			xlnx,pf3-bar5-aperture-size = <00000000>;
			xlnx,disable-bram-pipeline;
			xlnx,vfg1-msix-cap-pba-offset-qdma = <4800>;
			xlnx,pf3-subsystem-id = <0x7>;
			interrupt-names = "misc" , "msi0" , "msi1";
			xlnx,data-mover;
			xlnx,pf3-sriov-bar0-type = "DMA";
			xlnx,pf3-sriov-bar2-scale = "Kilobytes";
			xlnx,pf2-class-code-qdma = "058000";
			xlnx,gtwiz-in-core-us = <1>;
			xlnx,pf3-sriov-bar5-control = <0x0>;
			xlnx,enable-at-ports;
			xlnx,bar0-indicator = <1>;
			xlnx,xdma-wnum-chnl = <4>;
			xlnx,pf0-bar1-type-qdma = "AXI_Bridge_Master";
			xlnx,pf1-class-code-interface-qdma = <00>;
			xlnx,pf3-bar0-aperture-size = <00000000>;
			xlnx,pf3-bar1-scale-qdma = "Megabytes";
			xlnx,ccix-enable;
			xlnx,pf1-bar4-size-qdma = <128>;
			xlnx,pf1-sriov-vf-device-id = "C138";
			xlnx,pf1-vf-pciebar2axibar-0 = <0x0>;
			xlnx,pf3-sriov-bar1-scale = "Kilobytes";
			xlnx,pf1-vf-pciebar2axibar-1 = <0x50000000>;
			xlnx,pf1-vf-pciebar2axibar-2 = <0x50000000>;
			xlnx,pf1-vf-pciebar2axibar-3 = <0x0>;
			xlnx,pf1-vf-pciebar2axibar-4 = <0x0>;
			xlnx,pf1-vf-pciebar2axibar-5 = <0x0>;
			xlnx,pf2-subsystem-id = <0x7>;
			xlnx,pf2-enabled = <0>;
			xlnx,pf3-expansion-rom-scale-qdma = "Kilobytes";
			xlnx,pf1-revision-id = <0x0>;
			xlnx,parity-prop = <0>;
			xlnx,ultrascale;
			xlnx,pf3-sriov-bar0-scale = "Kilobytes";
			xlnx,vfg0-msix-cap-table-bir-qdma = "BAR_1:0";
			xlnx,pf3-bar2-scale-qdma = "Kilobytes";
			xlnx,pf2-sriov-bar4-type = "AXI_Bridge_Master";
			xlnx,pf3-bar0-64bit-qdma;
			xlnx,pf2-sriov-bar1-type = "AXI_Bridge_Master";
			xlnx,pf3-class-code-interface-qdma = <00>;
			xlnx,pf2-sriov-bar3-control = <0x0>;
			xlnx,old-bridge-timeout = <0>;
			xlnx,pf1-subsystem-id = <0xe>;
			xlnx,pf2-bar4-type-qdma = "AXI_Bridge_Master";
			xlnx,pf0-bar2-size-qdma = <256>;
			xlnx,pf2-sriov-first-vf-offset = <0>;
			xlnx,pf2-vf-pciebar2axibar-0 = <0x0>;
			xlnx,pf2-vf-pciebar2axibar-1 = <0x60000000>;
			xlnx,en-debug-ports;
			xlnx,pf2-vf-pciebar2axibar-2 = <0x60000000>;
			xlnx,ext-sys-clk-bufg;
			xlnx,pf1-sriov-bar2-prefetchable;
			xlnx,pf2-vf-pciebar2axibar-3 = <0x0>;
			xlnx,vfg0-msix-cap-pba-offset-qdma = <4800>;
			xlnx,rable = <0>;
			xlnx,axilite-master-aperture-size = <0xd>;
			xlnx,pf2-vf-pciebar2axibar-4 = <0x0>;
			xlnx,ip-name = "qdma";
			xlnx,pf2-vf-pciebar2axibar-5 = <0x0>;
			xlnx,bridge-burst;
			xlnx,pf0-sriov-bar5-scale = "Kilobytes";
			xlnx,pciebar2axibar-axil-master = <0x0>;
			xlnx,pf1-bar2-enabled-qdma;
			xlnx,pf3-bar3-scale-qdma = "Kilobytes";
			xlnx,pf2-bar3-aperture-size = <00000000>;
			xlnx,pf0-subsystem-id = <0xe>;
			xlnx,phy-lp-txpreset = <4>;
			xlnx,pf0-sriov-bar4-scale = "Kilobytes";
			xlnx,pf3-sriov-cap-initial-vf = <0>;
			xlnx,pf0-msix-cap-table-bir-qdma = "BAR_3:2";
			xlnx,pf1-sriov-bar5-type = "AXI_Bridge_Master";
			xlnx,xdma-scale = "Megabytes";
			xlnx,pf1-sriov-bar1-control = <0x0>;
			xlnx,pf1-bar2-type-qdma = "AXI_Bridge_Master";
			xlnx,pf1-sriov-bar2-type = "AXI_Lite_Master";
			xlnx,pf2-expansion-rom-scale-qdma = "Kilobytes";
			xlnx,pf3-vf-pciebar2axibar-0 = <0x0>;
			xlnx,pf3-vf-pciebar2axibar-1 = <0x70000000>;
			xlnx,gtcom-in-core = <2>;
			xlnx,pf3-bar4-scale-qdma = "Kilobytes";
			xlnx,pf3-class-code-base-qdma = <05>;
			xlnx,pf3-vf-pciebar2axibar-2 = <0x70000000>;
			xlnx,num-of-sc = <1>;
			xlnx,pf3-vf-pciebar2axibar-3 = <0x0>;
			xlnx,pf3-vf-pciebar2axibar-4 = <0x0>;
			xlnx,pf2-bar5-size-qdma = <128>;
			xlnx,pf3-vf-pciebar2axibar-5 = <0x0>;
			xlnx,pf0-sriov-bar3-scale = "Kilobytes";
			clocks = <&misc_clk_0>;
			xlnx,pf1-sub-class-interface-menu-qdma = "Other_memory_controller";
			xlnx,pf3-vf-addr-mask = <0xfff>;
			xlnx,pf3-bar2-64bit-qdma;
			xlnx,sys-reset-polarity = <0>;
			xlnx,pf1-rbar-num = <1>;
			xlnx,en-axi-mm-qdma;
			xlnx,pf1-sriov-bar0-prefetchable;
			xlnx,pf0-sriov-bar2-scale = "Kilobytes";
			xlnx,pf2-msix-cap-table-offset-qdma = <30000>;
			xlnx,pf1-bar0-enabled-qdma;
			xlnx,barlite1 = <1>;
			xlnx,barlite2 = <7>;
			xlnx,pf0-bar0-scale-qdma = "Megabytes";
			xlnx,pf3-bar5-scale-qdma = "Kilobytes";
			xlnx,xdma-sts-ports;
			xlnx,pf3-sriov-bar3-size = <4>;
			xlnx,s-axi-num-write = <8>;
			xlnx,pf2-vf-addr-mask = <0xfff>;
			xlnx,pf0-vf-bar5-aperture-size = <00000000>;
			xlnx,pf3-bar2-control = <0x0>;
			xlnx,pf3-sriov-bar0-size = <32>;
			xlnx,pf2-expansion-rom-type-qdma = "Expansion_ROM";
			xlnx,pf0-sriov-bar1-scale = "Kilobytes";
			xlnx,pf0-bar0-type-qdma = "AXI_Bridge_Master";
			xlnx,pf3-bar5-type-qdma = "AXI_Bridge_Master";
			#size-cells = <2>;
			xlnx,adv-int-usr;
			xlnx,pf0-sriov-bar3-type = "AXI_Bridge_Master";
			xlnx,c2h-num-chnl = <4>;
			xlnx,pf1-bar3-size-qdma = <128>;
			xlnx,pf1-bar6-aperture-size = <0x0>;
			xlnx,en-gt-selection;
			xlnx,barlite-int-pf0 = <0x4>;
			xlnx,pf0-vf-bar0-aperture-size = <00000000>;
			xlnx,tl-credits-cd = <15>;
			xlnx,barlite-int-pf1 = <000001>;
			xlnx,pf0-sriov-bar0-type = "DMA";
			xlnx,barlite-int-pf2 = <000000>;
			xlnx,barlite-int-pf3 = <000000>;
			xlnx,disable-user-clock-root;
			xlnx,pf1-vf-bar3-aperture-size = <00000000>;
			xlnx,tl-credits-ch = <15>;
			xlnx,pf0-sriov-bar0-scale = "Kilobytes";
			xlnx,pf0-bar1-scale-qdma = "Megabytes";
			xlnx,pf2-vf-bar6-aperture-size = <0x0>;
			xlnx,pf1-bar1-aperture-size = <0x0>;
			xlnx,pf1-expansion-rom-scale-qdma = "Kilobytes";
			xlnx,pf1-vf-addr-mask = <0xfff>;
			ranges = <0x43000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001>;
			xlnx,pf1-sriov-cap-ver = <1>;
			xlnx,pf2-bar2-control = <0x0>;
			xlnx,pf2-sriov-bar2-64bit;
			xlnx,vfg3-msix-cap-table-offset-qdma = <4000>;
			xlnx,xdma-num-usr-irq = <16>;
			xlnx,pf2-vf-bar1-aperture-size = <00000000>;
			xlnx,plltype = "QPLL1";
			xlnx,vsec-cap-addr = <0xe00>;
			xlnx,pf3-vf-bar4-aperture-size = <00000000>;
			xlnx,pf2-msix-enabled-qdma;
			xlnx,pf2-sriov-bar4-size = <4>;
			xlnx,usr-irq-xdma-type-interface;
			xlnx,pf1-msix-cap-table-offset = <00010040>;
			xlnx,c2h-stream-cpl-data-size = <0>;
			xlnx,en-qdma;
			xlnx,pf2-sriov-bar1-size = <4>;
			xlnx,dsc-bypass-rd = <0>;
			xlnx,axisten-if-enable-msg-route = <0x1efff>;
			xlnx,pf2-bar3-type-qdma = "AXI_Bridge_Master";
			xlnx,pf1-msix-enabled;
			xlnx,vfg3-msix-cap-pba-bir-qdma = "BAR_1:0";
			xlnx,vf-barlite-int-pf0 = <000000>;
			xlnx,pf0-bar2-scale-qdma = "Kilobytes";
			xlnx,vf-barlite-int-pf1 = <000000>;
			xlnx,pf0-vf-addr-mask = <0xfff>;
			xlnx,vf-barlite-int-pf2 = <000000>;
			xlnx,dma-completion = <0>;
			xlnx,msix-preset = <0>;
			xlnx,pf0-bar1-size-qdma = <128>;
			xlnx,pf1-bar2-control = <0x7>;
			xlnx,vf-barlite-int-pf3 = <000000>;
			xlnx,enable-64bit;
			xlnx,pf0-bar0-64bit-qdma;
			xlnx,vu9p-tul-ex;
			xlnx,pf2-sriov-bar0-64bit;
			xlnx,virtio-en;
			xlnx,type1-membase-memlimit-enable = "Disabled";
			xlnx,dsc-bypass-rd-out = <0>;
			xlnx,enable-dvsec;
			xlnx,acs-ext-cap-enable;
			xlnx,en-transceiver-status-ports;
			xlnx,pf0-msix-enabled;
			xlnx,rp-msi-enabled;
			xlnx,pf0-bar2-control = <0x7>;
			xlnx,pf0-bar3-scale-qdma = "Kilobytes";
			xlnx,pf0-sriov-bar2-enabled;
			xlnx,pf0-sriov-bar4-control = <0x0>;
			#address-cells = <3>;
			xlnx,pf0-interrupt-pin = <0x1>;
			xlnx,pr-cap-nextptr = <0x0>;
			xlnx,pf3-vendor-id = <0x10ee>;
			xlnx,axist-bypass-control = <0x4>;
			xlnx,pf1-sriov-bar5-size = <4>;
			xlnx,pf0-expansion-rom-scale-qdma = "Kilobytes";
			xlnx,pf0-bar4-aperture-size = <0x0>;
			xlnx,pf1-bar1-type-qdma = "AXI_Bridge_Master";
			xlnx,vfg0-msix-cap-table-offset-qdma = <4000>;
			xlnx,pf1-sriov-bar2-size = <4>;
			xlnx,pf3-sriov-bar4-control = <0x0>;
			xlnx,pf3-sriov-bar2-enabled;
			xlnx,pf2-bar4-size-qdma = <128>;
			xlnx,en-axi-master-if;
			xlnx,dsc-bypass-wr-out = <0>;
			xlnx,pf3-bar4-aperture-size = <00000000>;
			xlnx,pf0-sriov-cap-initial-vf = <8>;
			xlnx,dsc-bypass-rd-csr = <1>;
			xlnx,pf0-bar4-scale-qdma = "Kilobytes";
			xlnx,pf1-base-class-menu-qdma = "Memory_controller";
			xlnx,dsc-bypass-wr = <0>;
			xlnx,pf1-enabled = <1>;
			xlnx,pf0-bar2-64bit-qdma;
			xlnx,pf0-class-code-base-qdma = <12>;
			xlnx,rq-rcfg-en;
			xlnx,pf0-sriov-supported-page-size = <00000553>;
			xlnx,drp-clk-sel = <0>;
			xlnx,ins-loss-profile = "Add-in_Card";
			xlnx,alf-cap-enable;
			xlnx,pf3-bar4-type-qdma = "AXI_Bridge_Master";
			xlnx,xdma-size = <1>;
			xlnx,pf0-bar5-scale-qdma = "Kilobytes";
			xlnx,pf2-sriov-bar0-enabled;
			xlnx,pf2-sriov-bar2-control = <0x0>;
			xlnx,pf0-sriov-bar3-size = <4>;
			xlnx,pf1-bar2-size-qdma = <128>;
			xlnx,dsc-bypass-wr-csr = <1>;
			xlnx,max-num-queue = <512>;
			xlnx,pf0-sriov-bar0-size = <32>;
			xlnx,dma-intf-sel-qdma = "AXI_MM";
			xlnx,timeout1-sel = <0xf>;
			xlnx,axi-aclk-loopback;
			xlnx,pf0-expansion-rom-type-qdma = "Expansion_ROM";
			xlnx,enable-ats-switch;
			xlnx,vfg3-msix-cap-table-size-qdma = <007>;
			xlnx,pf2-sriov-supported-page-size = <00000553>;
			xlnx,pf2-revision-id = <0x0>;
			xlnx,v7-gen3;
			xlnx,c2h-stream-cpl-col-bit-pos0 = <1>;
			xlnx,pf0-class-code-sub-qdma = <00>;
			xlnx,c2h-stream-cpl-col-bit-pos1 = <0>;
			xlnx,c2h-stream-cpl-col-bit-pos2 = <0>;
			xlnx,c2h-stream-cpl-col-bit-pos3 = <0>;
			xlnx,c2h-stream-cpl-col-bit-pos4 = <0>;
			xlnx,gtwiz-in-core-usp = <1>;
			xlnx,c2h-stream-cpl-col-bit-pos5 = <0>;
			xlnx,c2h-xdma-chnl = <0x1>;
			xlnx,c2h-stream-cpl-col-bit-pos6 = <0>;
			xlnx,c2h-stream-cpl-col-bit-pos7 = <0>;
			xlnx,master-cal-only;
			xlnx,pf2-bar2-type-qdma = "AXI_Lite_Master";
			xlnx,pipe-sim;
			xlnx,pf2-expansion-rom-size-qdma = <4>;
			xlnx,xdma-axilite-slave;
			xlnx,pf1-sriov-bar0-control = <0x7>;
			xlnx,dev-port-type = <0>;
			xlnx,pf0-bar0-size-qdma = <256>;
			xlnx,pf3-bar5-size-qdma = <128>;
			xlnx,msi-enabled;
			xlnx,pf2-bar2-aperture-size = <00000000>;
			xlnx,mm-slave-en = <0>;
			xlnx,pf3-msix-cap-pba-offset-qdma = <34000>;
			xlnx,ins-loss-nyq = <15>;
			xlnx,pf1-class-code-sub-qdma = <00>;
			xlnx,pf3-rbar-cap-bar0 = <0xfff0>;
			xlnx,axi-id-width = <4>;
			xlnx,pf3-rbar-cap-bar1 = <0x0>;
			xlnx,pf3-rbar-cap-bar2 = <0x0>;
			xlnx,core-clk-freq = <2>;
			xlnx,firstvf-offset-pf0 = <16>;
			xlnx,pf3-rbar-cap-bar3 = <0x0>;
			xlnx,axibar2pciebar-0 = <0x0>;
			xlnx,firstvf-offset-pf1 = <0>;
			xlnx,pf3-rbar-cap-bar4 = <0x0>;
			xlnx,axibar2pciebar-1 = <0x0>;
			xlnx,firstvf-offset-pf2 = <0>;
			xlnx,pf2-vendor-id = <0x10ee>;
			xlnx,pf3-rbar-cap-bar5 = <0x0>;
			xlnx,axibar2pciebar-2 = <0x0>;
			xlnx,firstvf-offset-pf3 = <0>;
			xlnx,axibar2pciebar-3 = <0x0>;
			xlnx,axibar2pciebar-4 = <0x0>;
			xlnx,pf1-bar0-type-qdma = "DMA";
			xlnx,vfg2-msix-cap-table-size-qdma = <007>;
			xlnx,axibar2pciebar-5 = <0x0>;
			xlnx,pf3-bar1-control = <0x0>;
			xlnx,pf0-bar2-prefetchable-qdma;
			xlnx,pf2-bar3-size-qdma = <128>;
			xlnx,axist-bypass-size = <1>;
			xlnx,gtcom-in-core-usp = <2>;
			xlnx,disable-eq-synchronizer;
			xlnx,axi-data-width = <256>;
			xlnx,en-pcie-debug-ports;
			xlnx,pf0-vf-bar4-aperture-size = <00000000>;
			xlnx,pf2-class-code-sub-qdma = <80>;
			xlnx,pciebar-num = <6>;
			xlnx,pfch-cache-depth = <16>;
			xlnx,axibar-num = <1>;
			xlnx,iep-en;
			xlnx,free-run-freq = <0>;
			xlnx,pf1-pciebar2axibar-0 = <0x0>;
			xlnx,ultrascale-plus;
			xlnx,m-axi-num-write = <32>;
			xlnx,enable-pcie-debug;
			xlnx,pf1-pciebar2axibar-1 = <0x10000000>;
			xlnx,pf2-bar1-control = <0x0>;
			xlnx,pf1-pciebar2axibar-2 = <0x202 0x00000000>;
			xlnx,pf1-bar5-aperture-size = <0x0>;
			xlnx,pf1-pciebar2axibar-3 = <0x0>;
			xlnx,pf2-msix-cap-pba-offset-qdma = <34000>;
			xlnx,vfg0-msix-cap-pba-bir-qdma = "BAR_1:0";
			xlnx,pf0-msix-impl-locn = "External";
			xlnx,pf1-pciebar2axibar-4 = <0x0>;
			xlnx,pf2-sriov-bar5-scale = "Kilobytes";
			xlnx,pf1-pciebar2axibar-5 = <0x0>;
			xlnx,pf1-pciebar2axibar-6 = <0000000000000000000000000000000000000000000000000000000000000000>;
			xlnx,pf3-sriov-bar5-type = "AXI_Bridge_Master";
			xlnx,pf1-vf-bar2-aperture-size = <00000000>;
			interrupt-map = <0 0 0 1 &pcie_intc_1 0>, <0 0 0 2 &pcie_intc_1 1>, <0 0 0 3 &pcie_intc_1 2>, <0 0 0 4 &pcie_intc_1 3>;
			xlnx,pf1-sriov-bar5-control = <0x0>;
			xlnx,pf3-sriov-bar2-type = "AXI_Lite_Master";
			xlnx,pf2-vf-bar5-aperture-size = <00000000>;
			xlnx,pf3-bar3-type-qdma = "AXI_Bridge_Master";
			xlnx,pf1-bar0-aperture-size = <0xb>;
			xlnx,ext-xvc-vsec-enable;
			xlnx,pf0-sriov-cap-ver = <1>;
			xlnx,pf1-bar1-size-qdma = <128>;
			xlnx,pf2-sriov-bar4-scale = "Kilobytes";
			xlnx,pf1-bar1-control = <0x0>;
			xlnx,pf2-vf-bar0-aperture-size = <00000000>;
			xlnx,rbar-enable;
			xlnx,pf3-class-code-sub-qdma = <80>;
			xlnx,vfg3-msix-cap-table-bir-qdma = "BAR_1:0";
			xlnx,pf3-vf-bar3-aperture-size = <00000000>;
			xlnx,vfg1-msix-cap-table-size-qdma = <007>;
			xlnx,pf2-sriov-vf-device-id = "C238";
			xlnx,pf0-bar2-enabled-qdma;
			xlnx,pf2-sriov-bar3-scale = "Kilobytes";
			xlnx,num-vfs-pf0 = <8>;
			xlnx,pf2-bar0-scale-qdma = "Kilobytes";
			xlnx,num-vfs-pf1 = <0>;
			xlnx,num-vfs-pf2 = <0>;
			xlnx,pf0-msix-cap-pba-offset = "00008FE0";
			pcie_intc_1: interrupt-controller {
				#interrupt-cells = <1>;
				#address-cells = <0>;
				interrupt-controller;
			};
		};
	};
};
