// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Xilinx Versal with PM
 *
 * (C) Copyright 2017-2022 Xilinx, Inc.
 * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */

/ {
	alt_ref_clk: alt_ref_clk {
		bootph-all;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <33333333>;
	};

	pl_alt_ref_clk: pl_alt_ref_clk {
		bootph-all;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <33333333>;
	};

	ref_clk: ref_clk {
		bootph-all;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <33333333>;
	};

	firmware {
		versal_firmware: versal-firmware {
			compatible = "xlnx,versal-firmware-wip";
			bootph-all;
			method = "smc";
			#power-domain-cells = <1>;

			versal_clk: clock-controller {
				bootph-all;
				#clock-cells = <1>;
				compatible = "xlnx,versal-clk";
				clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;
				clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk";
			};

			zynqmp_power: zynqmp-power {
				compatible = "xlnx,zynqmp-power";
				interrupt-parent = <&gic>;
				interrupts = <0 30 4>;
				mboxes = <&ipi_mailbox_pmu1 0>,
					 <&ipi_mailbox_pmu1 1>;
				mbox-names = "tx", "rx";
			};
		};
	};

	zynqmp_ipi {
		compatible = "xlnx,zynqmp-ipi-mailbox";
		interrupt-parent = <&gic>;
		interrupts = <0 30 4>;
		xlnx,ipi-id = <2>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ipi_mailbox_pmu1: mailbox@ff3f0440 {
			reg = <0 0xff3f0440 0 0x20>,
			      <0 0xff3f0460 0 0x20>,
			      <0 0xff3f0280 0 0x20>,
			      <0 0xff3f02a0 0 0x20>;
			reg-names = "local_request_region", "local_response_region",
				    "remote_request_region", "remote_response_region";
			#mbox-cells = <1>;
			xlnx,ipi-id = <1>;
		};
	};
};

&cpu0 {
	clocks = <&versal_clk 77>;
};

&can0 {
	clocks = <&versal_clk 96>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x1822401f>;
};

&can1 {
	clocks = <&versal_clk 97>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x18224020>;
};

&gem0 {
	clocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>;
	power-domains = <&versal_firmware 0x18224019>;
};

&gem1 {
	clocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>;
	power-domains = <&versal_firmware 0x1822401a>;
};

&gpio0 {
	clocks = <&versal_clk 82>;
	power-domains = <&versal_firmware 0x18224023>;
};

&gpio1 {
	clocks = <&versal_clk 61>;
	power-domains = <&versal_firmware 0x18224023>;
};

&i2c0 {
	clocks = <&versal_clk 98>;
	power-domains = <&versal_firmware 0x1822401d>;
};

&i2c1 {
	clocks = <&versal_clk 99>;
	power-domains = <&versal_firmware 0x1822401e>;
};

&lpd_dma_chan0 {
	clocks = <&versal_clk 81>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x18224035>;
};

&lpd_dma_chan1 {
	clocks = <&versal_clk 81>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x18224036>;
};

&lpd_dma_chan2 {
	clocks = <&versal_clk 81>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x18224037>;
};

&lpd_dma_chan3 {
	clocks = <&versal_clk 81>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x18224038>;
};

&lpd_dma_chan4 {
	clocks = <&versal_clk 81>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x18224039>;
};

&lpd_dma_chan5 {
	clocks = <&versal_clk 81>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x1822403a>;
};

&lpd_dma_chan6 {
	clocks = <&versal_clk 81>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x1822403b>;
};

&lpd_dma_chan7 {
	clocks = <&versal_clk 81>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x1822403c>;
};

&qspi {
	clocks = <&versal_clk 57>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x1822402b>;
};

&ospi {
	clocks = <&versal_clk 58>, <&versal_clk 82>;
};

&rtc {
	power-domains = <&versal_firmware 0x18224034>;
};

&serial0 {
	clocks = <&versal_clk 92>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x18224021>;
};

&serial1 {
	clocks = <&versal_clk 93>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x18224022>;
};

&sdhci0 {
	clocks = <&versal_clk 59>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x1822402e>;
};

&sdhci1 {
	clocks = <&versal_clk 60>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x1822402f>;
};

&spi0 {
	clocks = <&versal_clk 94>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x1822401b>;
};

&spi1 {
	clocks = <&versal_clk 95>, <&versal_clk 82>;
	power-domains = <&versal_firmware 0x1822401c>;
};

&usb0 {
	clocks = <&versal_clk 91>, <&versal_clk 104>;
	power-domains = <&versal_firmware 0x18224018>;
};

&watchdog {
	clocks = <&versal_clk 82>;
};
