Metadata-Version: 2.1
Name: chipscopy
Version: 2024.1.1717799899
Summary: Open-source project from Xilinx® that enables high-level control of Versal debug IP running in hardware
Home-page: https://github.com/Xilinx/chipscopy
License: Apache-2.0 AND EPL-2.0
Author: Xilinx ChipScope Team
Maintainer: Xilinx ChipScope Team
Requires-Python: >=3.8.3,<4.0
Classifier: License :: Other/Proprietary License
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3.9
Classifier: Programming Language :: Python :: 3.10
Classifier: Programming Language :: Python :: 3.11
Provides-Extra: core-addons
Provides-Extra: jupyter
Provides-Extra: pytcf
Requires-Dist: Click (>=8.1,<9.0)
Requires-Dist: PyQt5 (>=5.15,<6.0) ; extra == "core-addons"
Requires-Dist: antlr4-python3-runtime (==4.10)
Requires-Dist: importlib_metadata (>=6.8,<7.0)
Requires-Dist: ipympl (>=0.9.3,<0.10.0) ; extra == "core-addons"
Requires-Dist: ipywidgets (>=8.1,<9.0) ; extra == "jupyter"
Requires-Dist: kaleido (==0.1.0) ; (sys_platform == "linux") and (extra == "core-addons")
Requires-Dist: kaleido (==0.1.0.post1) ; (sys_platform == "win32") and (extra == "core-addons")
Requires-Dist: loguru (>=0.7,<0.8)
Requires-Dist: matplotlib (>=3.7,<4.0) ; extra == "core-addons"
Requires-Dist: more-itertools (>=10.1,<11.0)
Requires-Dist: notebook (>=7.0,<8.0) ; extra == "jupyter"
Requires-Dist: pandas (>=1.5) ; extra == "core-addons"
Requires-Dist: plotly (>=5.16,<6.0) ; extra == "core-addons"
Requires-Dist: pytcf (>=0.0.8,<0.0.9) ; extra == "pytcf"
Requires-Dist: requests (>=2.0.0)
Requires-Dist: rich (>=13.5,<14.0)
Requires-Dist: typing_extensions (>=4.7,<5.0)
Project-URL: Bug Tracker, https://github.com/Xilinx/chipscopy/issues
Project-URL: Documentation, https://xilinx.github.io/chipscopy/
Project-URL: Repository, https://github.com/Xilinx/chipscopy
Description-Content-Type: text/markdown

# 🐍 ChipScoPy README

[![](https://img.shields.io/badge/code%20style-black-000000.svg)](https://github.com/psf/black)

![](https://raw.githubusercontent.com/Xilinx/chipscopy/master/docs/images/chipscopy_logo_head_right_transparent_background.png)

ChipScoPy is an open-source project from Xilinx® that enables high-level control of Versal debug IP running in hardware.
Using a simple Python API, developers can control and communicate with ChipScope® debug IP such as the Integrated Logic
Analyzer (ILA), Virtual IO (VIO), device memory access, and more.

ChipScoPy communicates with Versal devices. It does not work with older devices such as Ultrascale+ and 7-Series devices.

**We recommend using Python 3.8, 3.9, 3.10, or 3.11 with ChipScoPy.**

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![](https://raw.githubusercontent.com/Xilinx/chipscopy/master/docs/images/chipscopy_overview.png)

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[ChipScoPy Overview](https://xilinx.github.io/chipscopy/2024.1/overview.html)

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[System Requirements](https://xilinx.github.io/chipscopy/2024.1/system_requirements.html)

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[ChipScoPy Installation](https://xilinx.github.io/chipscopy/2024.1/chipscopy_installation.html)

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[ChipScoPy Examples](https://github.com/Xilinx/chipscopy/tree/master/chipscopy/examples)

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[FAQ](https://github.com/Xilinx/chipscopy/blob/master/FAQ.md)

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[API Documentation](https://xilinx.github.io/chipscopy/)

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Copyright (C) 2021-2022, Xilinx, Inc.

Copyright (C) 2022-2024, Advanced Micro Devices, Inc.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

