##
# Copyright (c) 2021 Xilinx, Inc.
# 
# Permission is hereby granted, free of charge, to any person obtaining a copy of this software and 
# associated documentation files (the "Software"), to deal in the Software without restriction, including 
# without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 
# copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to 
# the following conditions: 
# 
# The above copyright notice and this permission notice shall be included in all copies or substantial 
# portions of the Software. 
# 
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT 
# LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
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# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# 
#
##
Module_Name	Name	Address	Access_Type	Reset_Value	Description
CRL	RST_CPU_R5	0xff5e0300	rw	0x00000017	RPU MPCore Software Resets
CRL	RST_LPD_ADMA	0xff5e0304	rw	0x00000001	LPD DMA Software Reset (aka RST_ADMA)
CRL	RST_GEM0	0xff5e0308	rw	0x00000001	GEM 0 Software Reset
CRL	RST_GEM1	0xff5e030c	rw	0x00000001	GEM 1 Software Reset
CRL	RST_USB_2	0xff5e0314	rw	0x00000001	USB 2.0 Software Reset (aka RST_USB0)
CRL	RST_UART0	0xff5e0318	rw	0x00000001	UART 0 Software Reset
CRL	RST_UART1	0xff5e031c	rw	0x00000001	UART 1 Software Reset
CRL	RST_SPI0	0xff5e0320	rw	0x00000001	SPI 0 Software Reset
CRL	RST_SPI1	0xff5e0324	rw	0x00000001	SPI 1 Software Reset
CRL	RST_CAN0	0xff5e0328	rw	0x00000001	CAN 0 Software Reset
CRL	RST_CAN1	0xff5e032c	rw	0x00000001	CAN 1 Software Reset
CRL	RST_LPD_I2C0	0xff5e0330	rw	0x00000001	I2C 0 Software Reset (aka RST_I2C0)
CRL	RST_LPD_I2C1	0xff5e0334	rw	0x00000001	I2C 1 Software Reset (aka RST_I2C1)
CRL	RST_DBG_LPD	0xff5e0338	rw	0x00000033	LPD Debug Software Resets
CRL	RST_GPIO	0xff5e033c	rw	0x00000001	LPD GPIO Software Reset
CRL	RST_TTC	0xff5e0344	rw	0x0000000f	TTC Software Reset
CRL	RST_TIMESTAMP	0xff5e0348	rw	0x00000001	System Counter Reset (SCNTR unit)
CRL	RST_LPD_SWDT	0xff5e034c	rw	0x00000001	LPD System Watchdog Timer Software Reset (aka RST_SWDT)
CRL	RST_OCM 	0xff5e0350	rw	0x00000000	OCM Software Reset
CRL	RST_IPI	0xff5e0354	rw	0x00000000	IPI Software Reset
CRL	RST_FPD	0xff5e0360	rw	0x00000003	PS FPD Software Reset
CRL	RST_XRAM	0xff5e0364	rw	0x00000002	Accelerator RAM (XRAM) Reset Control (aka RST_OCM2)
CRL	PSM_RST_MODE	0xff5e0370	rw	0x00000001	PSM Reset Mode & Wakeup CSRs
CRF	RST_APU	0xfd1a0300	rw	0x00000d03	APU CPUs and MPCore Resets
CRF	RST_DBG_FPD	0xfd1a030c	rw	0x00000001	SoC Debug Reset Control
CRF	RST_FPD_SWDT	0xfd1a0314	rw	0x00000001	FPD System Watchdog Timer Reset Control
CRF	RST_SYSMON	0xfd1a0318	rw	0x00000000	FPD SysMon Reset Control
CRP	RST_QSPI	0xf1260300	rw	0x00000001	QSPI Controller Reset
CRP	RST_OSPI	0xf1260304	rw	0x00000001	OSPI Controller Reset
CRP	RST_SDIO0	0xf1260308	rw	0x00000001	SD/eMMC0 Controller Reset
CRP	RST_SDIO1	0xf126030c	rw	0x00000001	SD/eMMC1 Controller Reset
CRP	RST_I2C	0xf1260314	rw	0x00000001	PMC I2C Controller Reset
CRP	RST_GPIO	0xf1260318	rw	0x00000001	PMC_GPIO Controller Reset
CRP	RST_PS	0xf126031c	rw	0x00000046	PMC, PS, and PL Subsystem Resets
CRP	RST_NONPS	0xf1260320	rw	0x00000077	NoC/NPI/SoC Resets
CRP	RST_SBI	0xf1260324	rw	0x00000001	SBI Reset
CRP	RST_PDMA	0xf1260328	rw	0x00000003	PMC DMA Resets
CRP	RST_SYSMON	0xf126032c	rw	0x00000000	SysMon Reset
CRP	RST_PL	0xf1260330	rw	0x0000000f	PL Reset Outputs
CRP	RST_USB	0xf1260334	rw	0x00000001	USB 2.0 Controller PHY Reset
CRP	RST_DBG	0xf1260400	rw	0x00000003	Debug Reset
