This design is targeted for xczu29dr board (part number: xczu29dr-ffvf1760-2-e)

Zynq UltraScale+ Design Summary

Device	xczu29dr
SpeedGrade	-2
Part	xczu29dr-ffvf1760-2-e
Description	Zynq UltraScale+ PS Configuration Report
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction	Drive Strength(mA)
MIO 0	Quad SPI Flash	sclk_out	cmos	fast	pullup	out	12
MIO 1	Quad SPI Flash	miso_mo1	cmos	fast	pullup	in	12
MIO 2			cmos	fast	pullup		12
MIO 3			cmos	fast	pullup		12
MIO 4	Quad SPI Flash	mosi_mi0	cmos	fast	pullup	out	12
MIO 5	Quad SPI Flash	n_ss_out	cmos	fast	pullup	out	12
MIO 6	Feedback Clk	clk_for_lpbk	cmos	fast	pullup	out	12
MIO 7			cmos	fast	pullup		12
MIO 8			cmos	fast	pullup		12
MIO 9			cmos	fast	pullup		12
MIO 10			cmos	fast	pullup		12
MIO 11			cmos	fast	pullup		12
MIO 12			cmos	fast	pullup		12
MIO 13			cmos	fast	pullup		12
MIO 14			cmos	fast	pullup		12
MIO 15			cmos	fast	pullup		12
MIO 16			cmos	fast	pullup		12
MIO 17			cmos	fast	pullup		12
MIO 18			cmos	fast	pullup		12
MIO 19			cmos	fast	pullup		12
MIO 20			cmos	fast	pullup		12
MIO 21			cmos	fast	pullup		12
MIO 22			cmos	fast	pullup		12
MIO 23			cmos	fast	pullup		12
MIO 24			cmos	fast	pullup		12
MIO 25			cmos	fast	pullup		12
MIO 26			cmos	fast	pullup		12
MIO 27			cmos	fast	pullup		12
MIO 28			cmos	fast	pullup		12
MIO 29			cmos	fast	pullup		12
MIO 30			cmos	fast	pullup		12
MIO 31			cmos	fast	pullup		12
MIO 32			cmos	fast	pullup		12
MIO 33			cmos	fast	pullup		12
MIO 34	UART 0	rxd	cmos	fast	pullup	in	12
MIO 35	UART 0	txd	cmos	fast	pullup	out	12
MIO 36			cmos	fast	pullup		12
MIO 37			cmos	fast	pullup		12
MIO 38			cmos	fast	pullup		12
MIO 39	SD 1	sdio1_data_out[4]	cmos	fast	pullup	inout	12
MIO 40	SD 1	sdio1_data_out[5]	cmos	fast	pullup	inout	12
MIO 41	SD 1	sdio1_data_out[6]	cmos	fast	pullup	inout	12
MIO 42	SD 1	sdio1_data_out[7]	cmos	fast	pullup	inout	12
MIO 43	SD 1	sdio1_bus_pow	cmos	fast	pullup	out	12
MIO 44	SD 1	sdio1_wp	cmos	fast	pullup	in	12
MIO 45	SD 1	sdio1_cd_n	cmos	fast	pullup	in	12
MIO 46	SD 1	sdio1_data_out[0]	cmos	fast	pullup	inout	12
MIO 47	SD 1	sdio1_data_out[1]	cmos	fast	pullup	inout	12
MIO 48	SD 1	sdio1_data_out[2]	cmos	fast	pullup	inout	12
MIO 49	SD 1	sdio1_data_out[3]	cmos	fast	pullup	inout	12
MIO 50	SD 1	sdio1_cmd_out	cmos	fast	pullup	inout	12
MIO 51	SD 1	sdio1_clk_out	cmos	fast	pullup	out	12
MIO 52	USB 0	ulpi_clk_in	cmos	fast	pullup	in	12
MIO 53	USB 0	ulpi_dir	cmos	fast	pullup	in	12
MIO 54	USB 0	ulpi_tx_data[2]	cmos	fast	pullup	inout	12
MIO 55	USB 0	ulpi_nxt	cmos	fast	pullup	in	12
MIO 56	USB 0	ulpi_tx_data[0]	cmos	fast	pullup	inout	12
MIO 57	USB 0	ulpi_tx_data[1]	cmos	fast	pullup	inout	12
MIO 58	USB 0	ulpi_stp	cmos	fast	pullup	out	12
MIO 59	USB 0	ulpi_tx_data[3]	cmos	fast	pullup	inout	12
MIO 60	USB 0	ulpi_tx_data[4]	cmos	fast	pullup	inout	12
MIO 61	USB 0	ulpi_tx_data[5]	cmos	fast	pullup	inout	12
MIO 62	USB 0	ulpi_tx_data[6]	cmos	fast	pullup	inout	12
MIO 63	USB 0	ulpi_tx_data[7]	cmos	fast	pullup	inout	12
MIO 64			cmos	fast	pullup		12
MIO 65			cmos	fast	pullup		12
MIO 66			cmos	fast	pullup		12
MIO 67			cmos	fast	pullup		12
MIO 68			cmos	fast	pullup		12
MIO 69			cmos	fast	pullup		12
MIO 70			cmos	fast	pullup		12
MIO 71			cmos	fast	pullup		12
MIO 72			cmos	fast	pullup		12
MIO 73			cmos	fast	pullup		12
MIO 74			cmos	fast	pullup		12
MIO 75			cmos	fast	pullup		12
MIO 76			cmos	fast	pullup		12
MIO 77			cmos	fast	pullup		12

PS Clocks information

PSS REF CLK : 33.333

Name	Source	Input Frequency (MHz)
APLL	PSS_REF_CLK	2400.000
DPLL	PSS_REF_CLK	2133.333
VPLL	PSS_REF_CLK	2366.667
RPLL	PSS_REF_CLK	2333.333
IOPLL	PSS_REF_CLK	2333.333

Peripheral	Source	Actual Frequency (MHz)
GEM1 freq (MHz)	IOPLL	125.000000
USB0 freq (MHz)	IOPLL	250.000000
QSPI freq (MHz)	IOPLL	125.000000
SDIO1 freq (MHz)	IOPLL	187.500000
UART0 freq (MHz)	IOPLL	100.000000
I2C0 freq (MHz)	IOPLL	100.000000
CPU_R5 freq (MHz)	IOPLL	500.000000
IOU_SWITCH freq (MHz)	IOPLL	250.000000
LPD_SWITCH freq (MHz)	IOPLL	500.000000
LPD_LSBUS freq (MHz)	IOPLL	100.000000
GEM_TSU freq (MHz)	IOPLL	250.000000
TIMESTAMP freq (MHz)	IOPLL	100.000000
PSU__CRL_APB__USB3_REF_CTRL__freqmhz	IOPLL	20.000000
PCAP freq (MHz)	IOPLL	187.500000
DBG_LPD freq (MHz)	IOPLL	250.000000
ADMA freq (MHz)	IOPLL	500.000000
PL0 freq (MHz)	IOPLL	100.000000
PL1 freq (MHz)	IOPLL	375.000000
PL2 freq (MHz)	IOPLL	125.000000
PL3 freq (MHz)	IOPLL	375.000000
AMS freq (MHz)	IOPLL	51.724136
ACPU freq (MHz)	APLL	1200.000000
DBG FPD freq (MHz)	IOPLL	250.000000
DDR_CTRL freq MHz)	DPLL	533.333313
GDMA freq (MHz)	APLL	600.000000
DPDMA freq (MHz)	APLL	600.000000
TOPSW_MAIN freq (MHz)	DPLL	533.333313
TOPSW_LSBUS freq (MHz)	IOPLL	100.000000
DBG TSTMP freq (MHz)	IOPLL	250.000000

DDR Memory information

Parameter name	Value	Description
ENABLE	1	Enable the PS DDR Controller
DDR Interface freq (MHz)	1067	--
MEMORY TYPE	DDR 3	Type of memory interface
DM DBI	Components
BUS WIDTH	64 Bit	Data width of DDR interface, not including ECC data width
ECC	Disabled	Enables error correction code support
SPEED BIN	DDR3_2133N	Speed Bin
CL	14	Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL	10	CAS write latency setting in memory clock cycles
DDR AL	0	Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD	14	tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP	14	Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC	47.06	Row cycle time (ns)
T RAS MIN	33	Minimum number of memory clock cycles required between an Active and Precharge command
T FAW	30.0	Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH	16 Bits	Width of individual DRAM components
DEVICE CAPACITY	4096 MBits	Storage capacity of individual DRAM components
BG ADDR COUNT	NA	Number of bank group address pins
RANK ADDR COUNT	0	Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT	3	Number of bank address pins
ROW ADDR COUNT	15	Number of row address pins
COL ADDR COUNT	10	Number of column address bits
C_DDR_RAM_HIGHADDR	0x7FFFFFFF	--

GT lanes information

Protocol

GT lane#

Ref Clk Sel

Ref freq (MHz)