
#include "pmu-events/pmu-events.h"
#include "util/header.h"
#include "util/pmu.h"
#include <string.h>
#include <stddef.h>

struct compact_pmu_event {
  int offset;
};

static const char *const big_c_string =
/* offset=0 */ "\000\000metrics\000BP misp flush L3 topdown metric\000bp_misp_flush\000TopDownL3\000\000\000\000\000\000\000\000(BR_MIS_PRED * 5) / CPU_CYCLES\000BP misp flush L3 topdown metric\000"
/* offset=136 */ "\000\000metrics\000Backend Bound L1 topdown metric\000backend_bound\000TopDownL1\000\000\000\000\000\000\000\0001 - (frontend_bound + bad_speculation + retiring)\000Backend Bound L1 topdown metric\000"
/* offset=291 */ "\000\000metrics\000Bad Speculation L1 topdown metric\000bad_speculation\000TopDownL1\000\000\000\000\000\000\000\000(INST_SPEC - INST_RETIRED) / (4 * CPU_CYCLES)\000Bad Speculation L1 topdown metric\000"
/* offset=448 */ "\000\000metrics\000Branch mispredicts L2 topdown metric\000branch_mispredicts\000TopDownL2\000\000\000\000\000\000\000\000(bad_speculation * BR_MIS_PRED) / (BR_MIS_PRED + armv8_pmuv3_0@event\\=0x2013@)\000Branch mispredicts L2 topdown metric\000"
/* offset=647 */ "\000\000metrics\000Core bound L2 topdown metric\000core_bound\000TopDownL2\000\000\000\000\000\000\000\000(EXE_STALL_CYCLE - (MEM_STALL_ANYLOAD + armv8_pmuv3_0@event\\=0x7005@)) / CPU_CYCLES\000Core bound L2 topdown metric\000"
/* offset=827 */ "\000\000metrics\000Divider L3 topdown metric\000divider\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x7002@ / CPU_CYCLES\000Divider L3 topdown metric\000"
/* offset=956 */ "\000\000metrics\000EXE ports util L3 topdown metric\000exe_ports_util\000TopDownL3\000\000\000\000\000\000\000\000core_bound - divider - fsu_stall\000EXE ports util L3 topdown metric\000"
/* offset=1097 */ "\000\000metrics\000FSU stall L3 topdown metric\000fsu_stall\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x7003@ / CPU_CYCLES\000FSU stall L3 topdown metric\000"
/* offset=1232 */ "\000\000metrics\000Fetch bandwidth bound L2 topdown metric\000fetch_bandwidth_bound\000TopDownL2\000\000\000\000\000\000\000\000frontend_bound - fetch_latency_bound\000Fetch bandwidth bound L2 topdown metric\000"
/* offset=1398 */ "\000\000metrics\000Fetch latency bound L2 topdown metric\000fetch_latency_bound\000TopDownL2\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x201d@ / CPU_CYCLES\000Fetch latency bound L2 topdown metric\000"
/* offset=1563 */ "\000\000metrics\000Frontend bound L1 topdown metric\000frontend_bound\000TopDownL1\000\000\000\000\000\000\000\000FETCH_BUBBLE / (4 * CPU_CYCLES)\000Frontend bound L1 topdown metric\000"
/* offset=1703 */ "\000\000metrics\000Idle by icache miss L3 topdown metric\000idle_by_icache_miss\000TopDownL3\000\000\000\000\000\000\000\000(((L2I_CACHE - L2I_CACHE_REFILL) * 15) + (L2I_CACHE_REFILL * 100)) / CPU_CYCLES\000Idle by icache miss L3 topdown metric\000"
/* offset=1906 */ "\000\000metrics\000Idle by itlb miss L3 topdown metric\000idle_by_itlb_miss\000TopDownL3\000\000\000\000\000\000\000\000(((L2I_TLB - L2I_TLB_REFILL) * 15) + (L2I_TLB_REFILL * 100)) / CPU_CYCLES\000Idle by itlb miss L3 topdown metric\000"
/* offset=2097 */ "\000\000metrics\000Indirect branch L3 topdown metric\000indirect_branch\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x1010@ / BR_MIS_PRED\000Indirect branch L3 topdown metric\000"
/* offset=2251 */ "\000\000metrics\000L1 bound L3 topdown metric\000l1_bound\000TopDownL3\000\000\000\000\000\000\000\000(MEM_STALL_ANYLOAD - MEM_STALL_L1MISS) / CPU_CYCLES\000L1 bound L3 topdown metric\000"
/* offset=2393 */ "\000\000metrics\000L2 bound L3 topdown metric\000l2_bound\000TopDownL3\000\000\000\000\000\000\000\000(MEM_STALL_L1MISS - MEM_STALL_L2MISS) / CPU_CYCLES\000L2 bound L3 topdown metric\000"
/* offset=2534 */ "\000\000metrics\000Machine clears L2 topdown metric\000machine_clears\000TopDownL2\000\000\000\000\000\000\000\000bad_speculation - branch_mispredicts\000Machine clears L2 topdown metric\000"
/* offset=2679 */ "\000\000metrics\000Mem bound L3 topdown metric\000mem_bound\000TopDownL3\000\000\000\000\000\000\000\000MEM_STALL_L2MISS / CPU_CYCLES\000Mem bound L3 topdown metric\000"
/* offset=2802 */ "\000\000metrics\000Memory bound L2 topdown metric\000memory_bound\000TopDownL2\000\000\000\000\000\000\000\000(MEM_STALL_ANYLOAD + armv8_pmuv3_0@event\\=0x7005@) / CPU_CYCLES\000Memory bound L2 topdown metric\000"
/* offset=2968 */ "\000\000metrics\000Nuke flush L3 topdown metric\000nuke_flush\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x2012@ / armv8_pmuv3_0@event\\=0x2013@\000Nuke flush L3 topdown metric\000"
/* offset=3124 */ "\000\000metrics\000OOO flush L3 topdown metric\000ooo_flush\000TopDownL3\000\000\000\000\000\000\000\000(armv8_pmuv3_0@event\\=0x2013@ * 5) / CPU_CYCLES\000OOO flush L3 topdown metric\000"
/* offset=3265 */ "\000\000metrics\000Other branch L3 topdown metric\000other_branch\000TopDownL3\000\000\000\000\000\000\000\000(BR_MIS_PRED - armv8_pmuv3_0@event\\=0x1010@ - armv8_pmuv3_0@event\\=0x1013@ - armv8_pmuv3_0@event\\=0x1016@ - armv8_pmuv3_0@event\\=0x100d@) / BR_MIS_PRED\000Other branch L3 topdown metric\000"
/* offset=3519 */ "\000\000metrics\000Other flush L3 topdown metric\000other_flush\000TopDownL3\000\000\000\000\000\000\000\0001 - nuke_flush\000Other flush L3 topdown metric\000"
/* offset=3633 */ "\000\000metrics\000PC buffer stall L3 topdown metric\000pc_buffer_stall\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x2005@ / CPU_CYCLES\000PC buffer stall L3 topdown metric\000"
/* offset=3786 */ "\000\000metrics\000Pop branch L3 topdown metric\000pop_branch\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x100d@ / BR_MIS_PRED\000Pop branch L3 topdown metric\000"
/* offset=3925 */ "\000\000metrics\000Ptag stall L3 topdown metric\000ptag_stall\000TopDownL3\000\000\000\000\000\000\000\000(armv8_pmuv3_0@event\\=0x2006@ + armv8_pmuv3_0@event\\=0x2007@ + armv8_pmuv3_0@event\\=0x2008@) / CPU_CYCLES\000Ptag stall L3 topdown metric\000"
/* offset=4127 */ "\000\000metrics\000Push branch L3 topdown metric\000push_branch\000TopDownL3\000\000\000\000\000\000\000\000(armv8_pmuv3_0@event\\=0x1013@ + armv8_pmuv3_0@event\\=0x1016@) / BR_MIS_PRED\000Push branch L3 topdown metric\000"
/* offset=4302 */ "\000\000metrics\000Retiring L1 topdown metric\000retiring\000TopDownL1\000\000\000\000\000\000\000\000INST_RETIRED / (CPU_CYCLES * 4)\000Retiring L1 topdown metric\000"
/* offset=4424 */ "\000\000metrics\000Rob stall L3 topdown metric\000rob_stall\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x2004@ / CPU_CYCLES\000Rob stall L3 topdown metric\000"
/* offset=4559 */ "\000\000metrics\000SaveOpQ stall L3 topdown metric\000saveopq_stall\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x201e@ / CPU_CYCLES\000SaveOpQ stall L3 topdown metric\000"
/* offset=4706 */ "\000\000metrics\000Static predictor flush L3 topdown metric\000sp_flush\000TopDownL3\000\000\000\000\000\000\000\000(armv8_pmuv3_0@event\\=0x1001@ * 5) / CPU_CYCLES\000Static predictor flush L3 topdown metric\000"
/* offset=4872 */ "\000\000metrics\000Store bound L3 topdown metric\000store_bound\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x7005@ / CPU_CYCLES\000Store bound L3 topdown metric\000"
/* offset=5013 */ "\000\000metrics\000Sync stall L3 topdown metric\000sync_stall\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x2010@ / CPU_CYCLES\000Sync stall L3 topdown metric\000"
/* offset=5151 */ "\000\000metrics\000\000CPI\000\000\000\000\000\000\000\000\0001 / IPC\000\000"
/* offset=5183 */ "\000\000metrics\000\000DCache_L2_All\000\000\000\000\000\000\000\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000"
/* offset=5257 */ "\000\000metrics\000\000DCache_L2_All_Hits\000\000\000\000\000\000\000\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000"
/* offset=5361 */ "\000\000metrics\000\000DCache_L2_All_Miss\000\000\000\000\000\000\000\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000"
/* offset=5505 */ "\000\000metrics\000\000DCache_L2_Hits\000\000\000\000\000\000\000\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000"
/* offset=5583 */ "\000\000metrics\000\000DCache_L2_Misses\000\000\000\000\000\000\000\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000"
/* offset=5663 */ "\000\000metrics\000\000Frontend_Bound_SMT\000\000\000\000\000\000\000\000\000idq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))\000\000"
/* offset=5849 */ "\000\000metrics\000\000IPC\000group1\000\000\000\000\000\000\000\000inst_retired.any / cpu_clk_unhalted.thread\000\000"
/* offset=5922 */ "\000\000metrics\000\000L1D_Cache_Fill_BW\000\000\000\000\000\000\000\000\00064 * l1d.replacement / 1000000000 / duration_time\000\000"
/* offset=6010 */ "\000\000metrics\000\000M1\000\000\000\000\000\000\000\000\000ipc + M2\000\000"
/* offset=6042 */ "\000\000metrics\000\000M2\000\000\000\000\000\000\000\000\000ipc + M1\000\000"
/* offset=6074 */ "\000\000metrics\000\000M3\000\000\000\000\000\000\000\000\0001/M3\000\000"
/* offset=6102 */ "\000\000metrics\000\000cache_miss_cycles\000group1\000\000\000\000\000\000\000\000(dcache_miss_cpi + icache_miss_cycles)\000\000"
/* offset=6185 */ "\000\000metrics\000\000dcache_miss_cpi\000\000\000\000\000\000\000\000\000l1d\\-loads\\-misses / inst_retired.any\000\000"
/* offset=6259 */ "\000\000metrics\000\000icache_miss_cycles\000\000\000\000\000\000\000\000\000l1i\\-loads\\-misses / inst_retired.any\000\000"
/* offset=6336 */ "\000hisi_sicl,cpa\000uncore cpa\000Average bandwidth of CPA Port 0. Unit: hisi_sicl,cpa \000cpa_p0_avg_bw\000CPA\000\000\0000x00000030\000\000\000\000\000(cpa_p0_wr_dat * 64 + cpa_p0_rd_dat_64b * 64 + cpa_p0_rd_dat_32b * 32) / cpa_cycles\000\000"
/* offset=6536 */ "\000hisi_sicl,cpa\000uncore cpa\000Average bandwidth of CPA Port 1. Unit: hisi_sicl,cpa \000cpa_p1_avg_bw\000CPA\000\000\0000x00000030\000\000\000\000\000(cpa_p1_wr_dat * 64 + cpa_p1_rd_dat_64b * 64 + cpa_p1_rd_dat_32b * 32) / cpa_cycles\000\000"
/* offset=6736 */ "\000imx8_ddr\000metrics\000bytes all masters read from ddr based on read-cycles event. Unit: imx8_ddr \000imx8mm_ddr_read.all\000\000\000\000i.MX8MM\000\000\0009.765625e-4KB\000\000imx8mm_ddr.read_cycles * 4 * 4\000\000"
/* offset=6910 */ "\000imx8_ddr\000metrics\000bytes all masters read from ddr based on read-cycles event. Unit: imx8_ddr \000imx8mn_ddr_read.all\000\000\000\000i.MX8MN\000\000\0009.765625e-4KB\000\000imx8mn_ddr.read_cycles * 4 * 2\000\000"
/* offset=7084 */ "\000imx8_ddr\000metrics\000bytes all masters read from ddr based on read-cycles event. Unit: imx8_ddr \000imx8mq_ddr_read.all\000\000\000\000i.MX8MQ\000\000\0009.765625e-4KB\000\000imx8mq_ddr.read_cycles * 4 * 4\000\000"
/* offset=7258 */ "\000imx8_ddr\000metrics\000bytes all masters write to ddr based on write-cycles event. Unit: imx8_ddr \000imx8mm_ddr_write.all\000\000\000\000i.MX8MM\000\000\0009.765625e-4KB\000\000imx8mm_ddr.write_cycles * 4 * 4\000\000"
/* offset=7434 */ "\000imx8_ddr\000metrics\000bytes all masters write to ddr based on write-cycles event. Unit: imx8_ddr \000imx8mn_ddr_write.all\000\000\000\000i.MX8MN\000\000\0009.765625e-4KB\000\000imx8mn_ddr.write_cycles * 4 * 2\000\000"
/* offset=7610 */ "\000imx8_ddr\000metrics\000bytes all masters write to ddr based on write-cycles event. Unit: imx8_ddr \000imx8mq_ddr_write.all\000\000\000\000i.MX8MQ\000\000\0009.765625e-4KB\000\000imx8mq_ddr.write_cycles * 4 * 4\000\000"
/* offset=7786 */ "\000imx8_ddr\000metrics\000bytes of a53 core read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.a53\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0000@\000\000"
/* offset=7958 */ "\000imx8_ddr\000metrics\000bytes of a53 core write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.a53\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0000@\000\000"
/* offset=8131 */ "\000imx8_ddr\000metrics\000bytes of all masters read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.all\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0xffff\\,axi_id\\=0x0000@\000\000"
/* offset=8306 */ "\000imx8_ddr\000metrics\000bytes of all masters write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.all\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0xffff\\,axi_id\\=0x0000@\000\000"
/* offset=8482 */ "\000imx8_ddr\000metrics\000bytes of audio dsp read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.audio_dsp\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0041@\000\000"
/* offset=8661 */ "\000imx8_ddr\000metrics\000bytes of audio dsp write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.audio_dsp\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0041@\000\000"
/* offset=8841 */ "\000imx8_ddr\000metrics\000bytes of audio sdma2_burst read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.audio_sdma2_burst\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0063@\000\000"
/* offset=9036 */ "\000imx8_ddr\000metrics\000bytes of audio sdma2_burst write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.audio_sdma2_burst\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0063@\000\000"
/* offset=9232 */ "\000imx8_ddr\000metrics\000bytes of audio sdma2_per read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.audio_sdma2_per\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0062@\000\000"
/* offset=9423 */ "\000imx8_ddr\000metrics\000bytes of audio sdma2_per write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.audio_sdma2_per\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0062@\000\000"
/* offset=9615 */ "\000imx8_ddr\000metrics\000bytes of audio sdma3_burst read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.audio_sdma3_burst\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0065@\000\000"
/* offset=9810 */ "\000imx8_ddr\000metrics\000bytes of audio sdma3_burst write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.audio_sdma3_burst\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0065@\000\000"
/* offset=10006 */ "\000imx8_ddr\000metrics\000bytes of audio sdma3_per read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.audio_sdma3_per\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0064@\000\000"
/* offset=10197 */ "\000imx8_ddr\000metrics\000bytes of audio sdma3_per write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.audio_sdma3_per\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0064@\000\000"
/* offset=10389 */ "\000imx8_ddr\000metrics\000bytes of audio sdma_pif read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.audio_sdma_pif\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0066@\000\000"
/* offset=10578 */ "\000imx8_ddr\000metrics\000bytes of audio sdma_pif write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.audio_sdma_pif\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0066@\000\000"
/* offset=10768 */ "\000imx8_ddr\000metrics\000bytes of display dewarp read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.dewarp\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x006f@\000\000"
/* offset=10949 */ "\000imx8_ddr\000metrics\000bytes of display dewarp write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.dewarp\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x006f@\000\000"
/* offset=11131 */ "\000imx8_ddr\000metrics\000bytes of display isi1 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.isi1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x006a@\000\000"
/* offset=11308 */ "\000imx8_ddr\000metrics\000bytes of display isi1 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.isi1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x006a@\000\000"
/* offset=11486 */ "\000imx8_ddr\000metrics\000bytes of display isi2 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.isi2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x006b@\000\000"
/* offset=11663 */ "\000imx8_ddr\000metrics\000bytes of display isi2 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.isi2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x006b@\000\000"
/* offset=11841 */ "\000imx8_ddr\000metrics\000bytes of display isi3 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.isi3\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x006c@\000\000"
/* offset=12018 */ "\000imx8_ddr\000metrics\000bytes of display isi3 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.isi3\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x006c@\000\000"
/* offset=12196 */ "\000imx8_ddr\000metrics\000bytes of display isp1 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.isp1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x006d@\000\000"
/* offset=12373 */ "\000imx8_ddr\000metrics\000bytes of display isp1 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.isp1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x006d@\000\000"
/* offset=12551 */ "\000imx8_ddr\000metrics\000bytes of display isp2 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.isp2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x006e@\000\000"
/* offset=12728 */ "\000imx8_ddr\000metrics\000bytes of display isp2 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.isp2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x006e@\000\000"
/* offset=12906 */ "\000imx8_ddr\000metrics\000bytes of display lcdif1 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.lcdif1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0068@\000\000"
/* offset=13087 */ "\000imx8_ddr\000metrics\000bytes of display lcdif1 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.lcdif1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0068@\000\000"
/* offset=13269 */ "\000imx8_ddr\000metrics\000bytes of display lcdif2 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.lcdif2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0069@\000\000"
/* offset=13450 */ "\000imx8_ddr\000metrics\000bytes of display lcdif2 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.lcdif2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0069@\000\000"
/* offset=13632 */ "\000imx8_ddr\000metrics\000bytes of gpu 2d read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.2d\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0071@\000\000"
/* offset=13801 */ "\000imx8_ddr\000metrics\000bytes of gpu 2d write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.2d\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0071@\000\000"
/* offset=13971 */ "\000imx8_ddr\000metrics\000bytes of gpu 3d read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.3d\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0070@\000\000"
/* offset=14140 */ "\000imx8_ddr\000metrics\000bytes of gpu 3d write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.3d\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0070@\000\000"
/* offset=14310 */ "\000imx8_ddr\000metrics\000bytes of hdmi_tx hrv_mwr read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.hdmi_hrv_mwr\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0074@\000\000"
/* offset=14498 */ "\000imx8_ddr\000metrics\000bytes of hdmi_tx hrv_mwr write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.hdmi_hrv_mwr\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0074@\000\000"
/* offset=14687 */ "\000imx8_ddr\000metrics\000bytes of hdmi_tx lcdif read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.hdmi_lcdif\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0075@\000\000"
/* offset=14871 */ "\000imx8_ddr\000metrics\000bytes of hdmi_tx lcdif write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.hdmi_lcdif\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0075@\000\000"
/* offset=15056 */ "\000imx8_ddr\000metrics\000bytes of hdmi_tx tx_hdcp read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.hdmi_hdcp\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0076@\000\000"
/* offset=15241 */ "\000imx8_ddr\000metrics\000bytes of hdmi_tx tx_hdcp write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.hdmi_hdcp\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0076@\000\000"
/* offset=15427 */ "\000imx8_ddr\000metrics\000bytes of hsio pci read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.pci\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x007a@\000\000"
/* offset=15599 */ "\000imx8_ddr\000metrics\000bytes of hsio pci write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.pci\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x007a@\000\000"
/* offset=15772 */ "\000imx8_ddr\000metrics\000bytes of hsio usb1 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.usb1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0078@\000\000"
/* offset=15946 */ "\000imx8_ddr\000metrics\000bytes of hsio usb1 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.usb1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0078@\000\000"
/* offset=16121 */ "\000imx8_ddr\000metrics\000bytes of hsio usb2 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.usb2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0079@\000\000"
/* offset=16295 */ "\000imx8_ddr\000metrics\000bytes of hsio usb2 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.usb2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0079@\000\000"
/* offset=16470 */ "\000imx8_ddr\000metrics\000bytes of npu read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.npu\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0073@\000\000"
/* offset=16637 */ "\000imx8_ddr\000metrics\000bytes of npu write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.npu\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0073@\000\000"
/* offset=16805 */ "\000imx8_ddr\000metrics\000bytes of supermix(m7) core read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.supermix\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x000f\\,axi_id\\=0x0020@\000\000"
/* offset=16991 */ "\000imx8_ddr\000metrics\000bytes of supermix(m7) write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.supermix\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x000f\\,axi_id\\=0x0020@\000\000"
/* offset=17173 */ "\000imx8_ddr\000metrics\000bytes of vpu1 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.vpu1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x007c@\000\000"
/* offset=17342 */ "\000imx8_ddr\000metrics\000bytes of vpu1 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.vpu1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x007c@\000\000"
/* offset=17512 */ "\000imx8_ddr\000metrics\000bytes of vpu2 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.vpu2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x007d@\000\000"
/* offset=17681 */ "\000imx8_ddr\000metrics\000bytes of vpu2 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.vpu2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x007d@\000\000"
/* offset=17851 */ "\000imx8_ddr\000metrics\000bytes of vpu3 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.vpu3\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x007e@\000\000"
/* offset=18020 */ "\000imx8_ddr\000metrics\000bytes of vpu3 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.vpu3\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x007e@\000\000"
/* offset=18190 */ "_0inst_commit\000\000other\000This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only\000\000\000event=0x190\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only\000"
/* offset=18460 */ "_1inst_commit\000\000other\000This event counts every cycle that one instruction is committed\000\000\000event=0x191\000\000\000\000\000\000\000\000This event counts every cycle that one instruction is committed\000"
/* offset=18630 */ "_2inst_commit\000\000other\000This event counts every cycle that two instructions are committed\000\000\000event=0x192\000\000\000\000\000\000\000\000This event counts every cycle that two instructions are committed\000"
/* offset=18804 */ "_3inst_commit\000\000other\000This event counts every cycle that three instructions are committed\000\000\000event=0x193\000\000\000\000\000\000\000\000This event counts every cycle that three instructions are committed\000"
/* offset=18982 */ "_4inst_commit\000\000other\000This event counts every cycle that four instructions are committed\000\000\000event=0x194\000\000\000\000\000\000\000\000This event counts every cycle that four instructions are committed\000"
/* offset=19158 */ "act_cmd\000hisi_sccl,ddrc\000uncore ddrc\000DDRC active commands. Unit: hisi_sccl,ddrc \000\000\000config=0x5\000\000\000\000\000\000\000\000DDRC active commands\000"
/* offset=19278 */ "agu_dep_stall\000\000pipeline\000Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU\000\000\000event=0xe5\000\000\000\000\000\000\000\000\000"
/* offset=19434 */ "ase_inst_spec\000\000instruction\000ASE operations speculatively executed\000\000\000event=0x8005\000\000\000\000\000\000\000\000ASE operations speculatively executed\000"
/* offset=19559 */ "ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000"
/* offset=19721 */ "ase_sve_int16_spec\000\000instruction\000Advanced SIMD and SVE 16-bit integer operations speculatively executed\000\000\000event=0x80e7\000\000\000\000\000\000\000\000Advanced SIMD and SVE 16-bit integer operations speculatively executed\000"
/* offset=19917 */ "ase_sve_int32_spec\000\000instruction\000Advanced SIMD and SVE 32-bit integer operations speculatively executed\000\000\000event=0x80eb\000\000\000\000\000\000\000\000Advanced SIMD and SVE 32-bit integer operations speculatively executed\000"
/* offset=20113 */ "ase_sve_int64_spec\000\000instruction\000Advanced SIMD and SVE 64-bit integer operations speculatively executed\000\000\000event=0x80ef\000\000\000\000\000\000\000\000Advanced SIMD and SVE 64-bit integer operations speculatively executed\000"
/* offset=20309 */ "ase_sve_int8_spec\000\000instruction\000Advanced SIMD and SVE 8-bit integer operations speculatively executed\000\000\000event=0x80e3\000\000\000\000\000\000\000\000Advanced SIMD and SVE 8-bit integer operations speculatively executed\000"
/* offset=20502 */ "ase_sve_int_spec\000\000sve\000Advanced SIMD and SVE integer Operations speculatively executed\000\000\000event=0x8043\000\000\000\000\000\000\000\000Advanced SIMD and SVE integer Operations speculatively executed\000"
/* offset=20674 */ "ase_sve_ld_multi_spec\000\000sve\000Advanced SIMD and SVE contiguous load multiple vector Operations speculatively executed\000\000\000event=0x80a5\000\000\000\000\000\000\000\000Advanced SIMD and SVE contiguous load multiple vector Operations speculatively executed\000"
/* offset=20899 */ "ase_sve_ld_spec\000\000sve\000Advanced SIMD and SVE load Operations speculatively executed\000\000\000event=0x8085\000\000\000\000\000\000\000\000Advanced SIMD and SVE load Operations speculatively executed\000"
/* offset=21064 */ "ase_sve_st_multi_spec\000\000sve\000Advanced SIMD and SVE contiguous store multiple vector Operations speculatively executed\000\000\000event=0x80a6\000\000\000\000\000\000\000\000Advanced SIMD and SVE contiguous store multiple vector Operations speculatively executed\000"
/* offset=21291 */ "ase_sve_st_spec\000\000sve\000Advanced SIMD and SVE store Operations speculatively executed\000\000\000event=0x8086\000\000\000\000\000\000\000\000Advanced SIMD and SVE store Operations speculatively executed\000"
/* offset=21458 */ "back_invalid\000hisi_sccl,l3c\000uncore l3c\000Count of the number of L3C back invalid operations. Unit: hisi_sccl,l3c \000\000\000config=0x29\000\000\000\000\000\000\000\000Count of the number of L3C back invalid operations\000"
/* offset=21641 */ "base_ld_reg_spec\000\000sve\000General-purpose register load Operations speculatively executed\000\000\000event=0x8089\000\000\000\000\000\000\000\000General-purpose register load Operations speculatively executed\000"
/* offset=21813 */ "base_st_reg_spec\000\000sve\000General-purpose register store Operations speculatively executed\000\000\000event=0x808a\000\000\000\000\000\000\000\000General-purpose register store Operations speculatively executed\000"
/* offset=21987 */ "bc_ld_spec\000\000instruction\000This event counts architecturally executed SIMD broadcast floating-point load operations\000\000\000event=0x11a\000\000\000\000\000\000\000\000This event counts architecturally executed SIMD broadcast floating-point load operations\000"
/* offset=22210 */ "bi_num\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x23\000\000\000\000\000\000\000\000\000"
/* offset=22285 */ "biu_ext_mem_req\000\000memory\000External memory request\000\000\000event=0xc1\000\000\000\000\000\000\000\000External memory request\000"
/* offset=22377 */ "biu_ext_mem_req_nc\000\000memory\000External memory request to non-cacheable memory\000\000\000event=0xc2\000\000\000\000\000\000\000\000External memory request to non-cacheable memory\000"
/* offset=22520 */ "bp_l1_btb_correct\000\000branch\000L1 BTB Correction\000\000\000event=0x8a\000\000\000\000\000\000\000\000\000"
/* offset=22585 */ "bp_l2_btb_correct\000\000branch\000L2 BTB Correction\000\000\000event=0x8b\000\000\000\000\000\000\000\000\000"
/* offset=22650 */ "br_comp_wait\000\000other\000This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction\000\000\000event=0x18b\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction\000"
/* offset=22953 */ "br_cond\000\000branch\000Conditional branch executed\000\000\000event=0xc9\000\000\000\000\000\000\000\000\000"
/* offset=23018 */ "br_cond_mis_pred\000\000branch\000Conditional branch mis-predicted.This event counts when any branch which can be predicted by the conditional predictor is retired, and has mis-predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches which correctly predicted the condition but mis-predicted on the address do not count this event\000\000\000event=0xcc\000\000\000\000\000\000\000\000Conditional branch mis-predicted.This event counts when any branch which can be predicted by the conditional predictor is retired, and has mis-predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches which correctly predicted the condition but mis-predicted on the address do not count this event\000"
/* offset=23823 */ "br_cond_mis_pred\000\000branch\000Conditional branch mispredicted. This event counts when any branch that the conditional predictor can predict is retired and has mispredicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches that correctly predict the condition but mispredict the address do not count\000\000\000event=0xcc\000\000\000\000\000\000\000\000Conditional branch mispredicted. This event counts when any branch that the conditional predictor can predict is retired and has mispredicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches that correctly predict the condition but mispredict the address do not count\000"
/* offset=24566 */ "br_cond_mispred\000\000branch\000Conditional branch mispredicted\000\000\000event=0xcc\000\000\000\000\000\000\000\000\000"
/* offset=24643 */ "br_cond_pred\000\000branch\000Predicted conditional branch executed. This event counts when any branch that the conditional predictor can predict is retired. This event still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off\000\000\000event=0xc9\000\000\000\000\000\000\000\000Predicted conditional branch executed. This event counts when any branch that the conditional predictor can predict is retired. This event still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off\000"
/* offset=25158 */ "br_cond_pred\000\000branch\000Predicted conditional branch executed.This event counts when any branch which can be predicted by the conditional predictor is retired. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xc9\000\000\000\000\000\000\000\000Predicted conditional branch executed.This event counts when any branch which can be predicted by the conditional predictor is retired. This event still counts when branch prediction is disabled due to the MMU being off\000"
/* offset=25639 */ "br_immed_retired\000\000instruction\000Instruction architecturally executed, immediate branch\000\000\000event=0xd\000\000\000\000\000\000\000\000Instruction architecturally executed, immediate branch\000"
/* offset=25798 */ "br_immed_spec\000\000branch\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000"
/* offset=25936 */ "br_immed_spec\000\000instruction\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000"
/* offset=26079 */ "br_indirect_addr_mis_pred\000\000branch\000Indirect branch mis-predicted due to address mis-compare.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xcb\000\000\000\000\000\000\000\000Indirect branch mis-predicted due to address mis-compare.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000"
/* offset=26761 */ "br_indirect_addr_mis_pred\000\000branch\000Indirect branch mispredicted due to address miscompare. This event counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xcb\000\000\000\000\000\000\000\000Indirect branch mispredicted due to address miscompare. This event counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000"
/* offset=27417 */ "br_indirect_addr_pred\000\000branch\000Indirect branch with predicted address executed. This event counts when any indirect branch that the BTAC can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xcd\000\000\000\000\000\000\000\000Indirect branch with predicted address executed. This event counts when any indirect branch that the BTAC can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000"
/* offset=27995 */ "br_indirect_addr_pred\000\000branch\000Indirect branch with predicted address executed.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xcd\000\000\000\000\000\000\000\000Indirect branch with predicted address executed.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000"
/* offset=28587 */ "br_indirect_mis_pred\000\000branch\000Indirect branch mis-predicted.This event counts when any indirect branch which can be predicted by the BTAC is retired, and has mispredicted for either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xca\000\000\000\000\000\000\000\000Indirect branch mis-predicted.This event counts when any indirect branch which can be predicted by the BTAC is retired, and has mispredicted for either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off\000"
/* offset=29168 */ "br_indirect_mis_pred\000\000branch\000Indirect branch mispredicted. This event counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired and has mispredicted either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xca\000\000\000\000\000\000\000\000Indirect branch mispredicted. This event counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired and has mispredicted either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off\000"
/* offset=29781 */ "br_indirect_mispred\000\000branch\000Indirect branch mispredicted\000\000\000event=0xca\000\000\000\000\000\000\000\000\000"
/* offset=29859 */ "br_indirect_mispred_addr\000\000branch\000Indirect branch mispredicted because of address miscompare\000\000\000event=0xcb\000\000\000\000\000\000\000\000\000"
/* offset=29972 */ "br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000"
/* offset=30111 */ "br_indirect_spec\000\000instruction\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000"
/* offset=30255 */ "br_mis_pred\000\000branch\000Branch mispredicted\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000"
/* offset=30375 */ "br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000"
/* offset=30535 */ "br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000This event counts any predictable branch instruction which is mispredicted either due to dynamic misprediction or because the MMU is off and the branches are statically predicted not taken\000"
/* offset=30824 */ "br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000Instruction architecturally executed, mispredicted branch\000"
/* offset=30993 */ "br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush\000"
/* offset=31216 */ "br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000"
/* offset=31336 */ "br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000This event counts all predictable branches\000"
/* offset=31457 */ "br_pred\000\000branch\000Predictable branch\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000"
/* offset=31554 */ "br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000Instruction architecturally executed, branch\000"
/* offset=31688 */ "br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches\000"
/* offset=31890 */ "br_return_addr_mis_pred\000\000branch\000Procedure return mis-predicted due to address mis-compare.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xcf\000\000\000\000\000\000\000\000Procedure return mis-predicted due to address mis-compare.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000"
/* offset=32572 */ "br_return_addr_mis_pred\000\000branch\000Procedure return mispredicted due to address miscompare. This event counts when any procedure return that the call-return stack can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xcf\000\000\000\000\000\000\000\000Procedure return mispredicted due to address miscompare. This event counts when any procedure return that the call-return stack can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000"
/* offset=33256 */ "br_return_addr_pred\000\000branch\000Procedure return with predicted address executed. This event counts when any procedure return that the call-return stack can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xce\000\000\000\000\000\000\000\000Procedure return with predicted address executed. This event counts when any procedure return that the call-return stack can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000"
/* offset=33862 */ "br_return_addr_pred\000\000branch\000Procedure return with predicted address executed.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xce\000\000\000\000\000\000\000\000Procedure return with predicted address executed.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000"
/* offset=34454 */ "br_return_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, procedure return\000\000\000event=0xe\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, procedure return\000"
/* offset=34668 */ "br_return_spec\000\000branch\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000"
/* offset=34807 */ "br_return_spec\000\000instruction\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000"
/* offset=34951 */ "btb_mis_pred\000\000cache\000BTB misprediction\000\000\000event=0x102\000\000\000\000\000\000\000\000Branch target buffer misprediction\000"
/* offset=35045 */ "bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000"
/* offset=35129 */ "bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000This event counts for every beat of data transferred over the data channels between the core and the SCU. If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD and BUS_ACCESS_WR\000"
/* offset=35467 */ "bus_access_normal\000\000bus\000Bus access, Normal\000\000\000event=0x64\000\000\000\000\000\000\000\000Bus access, Normal\000"
/* offset=35548 */ "bus_access_not_shared\000\000bus\000Bus access, not Normal, Cacheable, Shareable\000\000\000event=0x63\000\000\000\000\000\000\000\000Bus access, not Normal, Cacheable, Shareable\000"
/* offset=35685 */ "bus_access_periph\000\000bus\000Bus access, peripheral\000\000\000event=0x65\000\000\000\000\000\000\000\000Bus access, peripheral\000"
/* offset=35774 */ "bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000"
/* offset=35845 */ "bus_access_rd\000\000core imp def\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000"
/* offset=35925 */ "bus_access_shared\000\000bus\000Bus access, Normal, Cacheable, Shareable\000\000\000event=0x62\000\000\000\000\000\000\000\000Bus access, Normal, Cacheable, Shareable\000"
/* offset=36050 */ "bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000"
/* offset=36123 */ "bus_access_wr\000\000core imp def\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000"
/* offset=36205 */ "bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000"
/* offset=36261 */ "bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000This event duplicates CPU_CYCLES\000"
/* offset=36340 */ "bus_read_total_mem\000\000bus\000This event counts read transactions from measured CMG local memory to measured CMG\000\000\000event=0x316\000\000\000\000\000\000\000\000This event counts read transactions from measured CMG local memory to measured CMG\000"
/* offset=36551 */ "bus_read_total_pci\000\000bus\000This event counts read transactions from PCI controller to measured CMG\000\000\000event=0x315\000\000\000\000\000\000\000\000This event counts read transactions from PCI controller to measured CMG\000"
/* offset=36740 */ "bus_read_total_tofu\000\000bus\000This event counts read transactions from tofu controller to measured CMG\000\000\000event=0x314\000\000\000\000\000\000\000\000This event counts read transactions from tofu controller to measured CMG\000"
/* offset=36932 */ "bus_write_total_cmg0\000\000bus\000This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0\000\000\000event=0x318\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0\000"
/* offset=37163 */ "bus_write_total_cmg1\000\000bus\000This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1\000\000\000event=0x319\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1\000"
/* offset=37394 */ "bus_write_total_cmg2\000\000bus\000This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2\000\000\000event=0x31a\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2\000"
/* offset=37625 */ "bus_write_total_cmg3\000\000bus\000This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3\000\000\000event=0x31b\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3\000"
/* offset=37856 */ "bus_write_total_mem\000\000bus\000This event counts write transactions from measured CMG to measured CMG local memory\000\000\000event=0x31e\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to measured CMG local memory\000"
/* offset=38070 */ "bus_write_total_pci\000\000bus\000This event counts write transactions from measured CMG to PCI controller\000\000\000event=0x31d\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to PCI controller\000"
/* offset=38262 */ "bus_write_total_tofu\000\000bus\000This event counts write transactions from measured CMG to tofu controller\000\000\000event=0x31c\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to tofu controller\000"
/* offset=38457 */ "bx_stall\000\000pipeline\000BX stalled\000\000\000event=0x10c\000\000\000\000\000\000\000\000BX Op non-issue\000"
/* offset=38524 */ "cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000"
/* offset=38744 */ "cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state\000"
/* offset=38994 */ "cid_write_retired\000\000instruction\000Write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000"
/* offset=39149 */ "cnt_cycles\000\000bus\000Constant frequency cycles\000\000\000event=0x4004\000\000\000\000\000\000\000\000Constant frequency cycles.  The counter increments at a constant frequency equal to the rate of increment of the system counter, CNTPCT_EL0\000"
/* offset=39353 */ "cp15_utlb_refill\000\000cache\000Level 1 CP15 TLB refill\000\000\000event=0xe8\000\000\000\000\000\000\000\000Level 1 CP15 TLB refill\000"
/* offset=39445 */ "cpa_cycles\000hisi_sicl,cpa\000uncore cpa\000count of CPA cycles. Unit: hisi_sicl,cpa \000\000\000config=0\000\0000x00000030\000\000\000\000\000\000\000"
/* offset=39552 */ "cpa_p0_rd_dat\000hisi_sicl,cpa\000uncore cpa\000Number of read ops transmitted by the P0 port. Unit: hisi_sicl,cpa \000\000\000config=0xe2\000\0000x00000030\000\000\000\000\000\000\000"
/* offset=39691 */ "cpa_p0_rd_dat_32b\000hisi_sicl,cpa\000uncore cpa\000Number of read ops transmitted by the P0 port which size is 32 bytes. Unit: hisi_sicl,cpa \000\000\000config=0x84\000\0000x00000030\000\000\000\000\000\000\000"
/* offset=39857 */ "cpa_p0_rd_dat_64b\000hisi_sicl,cpa\000uncore cpa\000Number of read ops transmitted by the P0 port which size is 64 bytes. Unit: hisi_sicl,cpa \000\000\000config=0x83\000\0000x00000030\000\000\000\000\000\000\000"
/* offset=40023 */ "cpa_p0_wr_dat\000hisi_sicl,cpa\000uncore cpa\000Number of write ops transmitted by the P0 port. Unit: hisi_sicl,cpa \000\000\000config=0xe1\000\0000x00000030\000\000\000\000\000\000\000"
/* offset=40163 */ "cpa_p1_rd_dat\000hisi_sicl,cpa\000uncore cpa\000Number of read ops transmitted by the P1 port. Unit: hisi_sicl,cpa \000\000\000config=0x62\000\0000x00000030\000\000\000\000\000\000\000"
/* offset=40302 */ "cpa_p1_rd_dat_32b\000hisi_sicl,cpa\000uncore cpa\000Number of read ops transmitted by the P1 port which size is 32 bytes. Unit: hisi_sicl,cpa \000\000\000config=0x4\000\0000x00000030\000\000\000\000\000\000\000"
/* offset=40467 */ "cpa_p1_rd_dat_64b\000hisi_sicl,cpa\000uncore cpa\000Number of read ops transmitted by the P1 port which size is 64 bytes. Unit: hisi_sicl,cpa \000\000\000config=0x3\000\0000x00000030\000\000\000\000\000\000\000"
/* offset=40632 */ "cpa_p1_wr_dat\000hisi_sicl,cpa\000uncore cpa\000Number of write ops transmitted by the P1 port. Unit: hisi_sicl,cpa \000\000\000config=0x61\000\0000x00000030\000\000\000\000\000\000\000"
/* offset=40772 */ "cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000"
/* offset=40820 */ "cpu_cycles\000\000bus\000The number of core clock cycles\000\000\000event=0x11\000\000\000\000\000\000\000\000The number of core clock cycles\000"
/* offset=40920 */ "cpu_cycles\000\000clock\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000The number of core clock cycles\000"
/* offset=40996 */ "cpu_cycles\000\000cycle\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000"
/* offset=41046 */ "crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000"
/* offset=41211 */ "cti_trigout4\000\000trace\000Cross-trigger Interface output trigger 4\000\000\000event=0x4018\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 4\000"
/* offset=41335 */ "cti_trigout5\000\000trace\000Cross-trigger Interface output trigger 5 \000\000\000event=0x4019\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 5 \000"
/* offset=41461 */ "cti_trigout6\000\000trace\000Cross-trigger Interface output trigger 6\000\000\000event=0x401a\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 6\000"
/* offset=41585 */ "cti_trigout7\000\000trace\000Cross-trigger Interface output trigger 7\000\000\000event=0x401b\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 7\000"
/* offset=41709 */ "d_lsu_slot_full\000\000pipeline\000Duration for which all slots in the Load-Store Unit (LSU) are busy\000\000\000event=0xd3\000\000\000\000\000\000\000\000Duration for which all slots in the Load-Store Unit (LSU) are busy\000"
/* offset=41889 */ "d_lsu_slot_full\000\000pipeline\000Duration for which all slots in the Load-Store Unit are busy\000\000\000event=0xd3\000\000\000\000\000\000\000\000Duration for which all slots in the Load-Store Unit are busy\000"
/* offset=42057 */ "dcache_self_hit_vipt\000\000cache\000Data cache hit in itself due to VIPT aliasing\000\000\000event=0xec\000\000\000\000\000\000\000\000Data cache hit in itself due to VIPT aliasing\000"
/* offset=42197 */ "dczva_spec\000\000instruction\000This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction\000\000\000event=0x9f\000\000\000\000\000\000\000\000This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction\000"
/* offset=42441 */ "de_iq_full\000\000pipeline\000Duration for which all slots in the Data Engine issue queue are busy\000\000\000event=0xda\000\000\000\000\000\000\000\000Duration for which all slots in the Data Engine issue queue are busy\000"
/* offset=42620 */ "de_iq_full\000\000pipeline\000Duration for which all slots in the data engine issue queue are busy. This event is set every time that the data engine rename has at least one valid instruction, excluding No Operations (NOPs), that cannot move to the issue stage because accpt_instr is LOW\000\000\000event=0xda\000\000\000\000\000\000\000\000Duration for which all slots in the data engine issue queue are busy. This event is set every time that the data engine rename has at least one valid instruction, excluding No Operations (NOPs), that cannot move to the issue stage because accpt_instr is LOW\000"
/* offset=43177 */ "decode_dep_stall\000\000pipeline\000Cycles the DPU IQ is empty and there is a pre-decode error being processed\000\000\000event=0xe3\000\000\000\000\000\000\000\000\000"
/* offset=43300 */ "decode_stall\000\000pipeline\000Decode starved\000\000\000event=0x108\000\000\000\000\000\000\000\000Decode starved for instruction cycle\000"
/* offset=43396 */ "dispatch_blocked.any\000\000other\000Memory cluster signals to block micro-op dispatch for any reason\000\000\000event=0x9,period=200000,umask=0x20\000\000\000\000\000\000\000\000\000"
/* offset=43534 */ "dispatch_stall\000\000pipeline\000Dispatch stalled\000\000\000event=0x109\000\000\000\000\000\000\000\000Op dispatch stalled cycle\000"
/* offset=43623 */ "dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000"
/* offset=43737 */ "dp_iq_full\000\000pipeline\000Duration for which all slots in the data processing issue queue are busy. This event counts the cycles where all slots in the DP0 and DP1 IQs are full with micro-operations waiting for issuing, and the despatch stage is not empty\000\000\000event=0xd9\000\000\000\000\000\000\000\000Duration for which all slots in the data processing issue queue are busy. This event counts the cycles where all slots in the DP0 and DP1 IQs are full with micro-operations waiting for issuing, and the despatch stage is not empty\000"
/* offset=44238 */ "dp_iq_full\000\000pipeline\000Duration for which all slots in the data processing issue queue are busy\000\000\000event=0xd9\000\000\000\000\000\000\000\000Duration for which all slots in the data processing issue queue are busy\000"
/* offset=44425 */ "dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000"
/* offset=44582 */ "dpu_br_cond_mis\000\000dpu\000Instruction retired, conditional branch, mispredicted\000\000\000event=0xea\000\000\000\000\000\000\000\000Instruction retired, conditional branch, mispredicted\000"
/* offset=44731 */ "dpu_br_cond_retired\000\000instruction\000Instruction retired, conditional branch\000\000\000event=0xe8\000\000\000\000\000\000\000\000Instruction retired, conditional branch\000"
/* offset=44864 */ "dpu_br_ind_mis\000\000dpu\000Instruction retired, indirect branch, mispredicted\000\000\000event=0xe9\000\000\000\000\000\000\000\000Instruction retired, indirect branch, mispredicted\000"
/* offset=45006 */ "dpu_mem_err_dcu\000\000dpu\000Memory error (any type) from DCU\000\000\000event=0xec\000\000\000\000\000\000\000\000Memory error (any type) from DCU\000"
/* offset=45113 */ "dpu_mem_err_ifu\000\000dpu\000Memory error (any type) from IFU\000\000\000event=0xeb\000\000\000\000\000\000\000\000Memory error (any type) from IFU\000"
/* offset=45220 */ "dpu_mem_err_tlb\000\000dpu\000Memory error (any type) from TLB\000\000\000event=0xed\000\000\000\000\000\000\000\000Memory error (any type) from TLB\000"
/* offset=45327 */ "dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000"
/* offset=45441 */ "dtb_miss\000\000cache\000DTB miss\000\000\000event=0x104\000\000\000\000\000\000\000\000DTB miss\000"
/* offset=45496 */ "dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000Access to data TLB causes a translation table walk\000"
/* offset=45635 */ "dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000This event counts on any data access which causes L2D_TLB_REFILL to count\000"
/* offset=45797 */ "ea_core\000\000other\000This event counts energy consumption per cycle of core\000\000\000event=0x1e0\000\000\000\000\000\000\000\000This event counts energy consumption per cycle of core\000"
/* offset=45943 */ "ea_l2\000\000cache\000This event counts energy consumption per cycle of L2 cache\000\000\000event=0x3e0\000\000\000\000\000\000\000\000This event counts energy consumption per cycle of L2 cache\000"
/* offset=46095 */ "ea_memory\000\000memory\000This event counts energy consumption per cycle of CMG local memory\000\000\000event=0x3e8\000\000\000\000\000\000\000\000This event counts energy consumption per cycle of CMG local memory\000"
/* offset=46268 */ "eaga_val\000\000pipeline\000This event counts valid cycles of EAGA pipeline\000\000\000event=0x1a0\000\000\000\000\000\000\000\000This event counts valid cycles of EAGA pipeline\000"
/* offset=46404 */ "eagb_val\000\000pipeline\000This event counts valid cycles of EAGB pipeline\000\000\000event=0x1a1\000\000\000\000\000\000\000\000This event counts valid cycles of EAGB pipeline\000"
/* offset=46540 */ "edir-hit\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x43\000\000\000\000\000\000\000\000\000"
/* offset=46617 */ "edir-home-migrate\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x4d\000\000\000\000\000\000\000\000\000"
/* offset=46703 */ "edir-lookup\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x41\000\000\000\000\000\000\000\000\000"
/* offset=46783 */ "effective_inst_spec\000\000instruction\000This event counts architecturally executed instructions, excluding the MOVPRFX instruction\000\000\000event=0x121\000\000\000\000\000\000\000\000This event counts architecturally executed instructions, excluding the MOVPRFX instruction\000"
/* offset=47019 */ "eist_trans\000\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000\000\000event=0x3a,period=200000,umask=0x0\000\000\000\000\000\000\000\000\000"
/* offset=47150 */ "etm_ext_out0\000\000etm\000ETM trace unit output 0\000\000\000event=0xde\000\000\000\000\000\000\000\000ETM trace unit output 0\000"
/* offset=47236 */ "etm_ext_out1\000\000etm\000ETM trace unit output 1\000\000\000event=0xdf\000\000\000\000\000\000\000\000ETM trace unit output 1\000"
/* offset=47322 */ "eu_comp_wait\000\000other\000This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction\000\000\000event=0x189\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction\000"
/* offset=47675 */ "event-hyphen\000uncore_cbox\000uncore\000UNC_CBO_HYPHEN. Unit: uncore_cbox \000\000\000event=0xe0,umask=0x00\000\000\000\000\000\000\000\000UNC_CBO_HYPHEN\000"
/* offset=47788 */ "event-two-hyph\000uncore_cbox\000uncore\000UNC_CBO_TWO_HYPH. Unit: uncore_cbox \000\000\000event=0xc0,umask=0x00\000\000\000\000\000\000\000\000UNC_CBO_TWO_HYPH\000"
/* offset=47907 */ "exa_val\000\000pipeline\000This event counts valid cycles of EXA pipeline\000\000\000event=0x1a2\000\000\000\000\000\000\000\000This event counts valid cycles of EXA pipeline\000"
/* offset=48040 */ "exb_val\000\000pipeline\000This event counts valid cycles of EXB pipeline\000\000\000event=0x1a3\000\000\000\000\000\000\000\000This event counts valid cycles of EXB pipeline\000"
/* offset=48173 */ "exc_dabort\000\000core imp def\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000"
/* offset=48296 */ "exc_dabort\000\000exception\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000"
/* offset=48416 */ "exc_fiq\000\000core imp def\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000"
/* offset=48500 */ "exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000"
/* offset=48581 */ "exc_fiq\000\000other\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000"
/* offset=48658 */ "exc_hvc\000\000core imp def\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000"
/* offset=48766 */ "exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000"
/* offset=48871 */ "exc_irq\000\000core imp def\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000"
/* offset=48955 */ "exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000"
/* offset=49036 */ "exc_irq\000\000other\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000"
/* offset=49113 */ "exc_pabort\000\000core imp def\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000"
/* offset=49228 */ "exc_pabort\000\000exception\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000"
/* offset=49340 */ "exc_return\000\000exception\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000"
/* offset=49535 */ "exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000"
/* offset=49732 */ "exc_smc\000\000core imp def\000Exception taken, Secure Monitor Call\000\000\000event=0x88\000\000\000\000\000\000\000\000Exception taken, Secure Monitor Call\000"
/* offset=49848 */ "exc_smc\000\000exception\000Exception taken, Secure Monitor Call\000\000\000event=0x88\000\000\000\000\000\000\000\000Exception taken, Secure Monitor Call\000"
/* offset=49961 */ "exc_svc\000\000core imp def\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000"
/* offset=50069 */ "exc_svc\000\000exception\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000"
/* offset=50174 */ "exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000"
/* offset=50246 */ "exc_trap_dabort\000\000core imp def\000Exception taken, Data Abort or SError not taken locally\000\000\000event=0x8c\000\000\000\000\000\000\000\000Exception taken, Data Abort or SError not taken locally\000"
/* offset=50408 */ "exc_trap_dabort\000\000exception\000Exception taken, Data Abort or SError not taken locally\000\000\000event=0x8c\000\000\000\000\000\000\000\000Exception taken, Data Abort or SError not taken locally\000"
/* offset=50567 */ "exc_trap_fiq\000\000core imp def\000Exception taken, FIQ not taken locally\000\000\000event=0x8f\000\000\000\000\000\000\000\000Exception taken, FIQ not taken locally\000"
/* offset=50692 */ "exc_trap_fiq\000\000exception\000Exception taken, FIQ not taken locally\000\000\000event=0x8f\000\000\000\000\000\000\000\000Exception taken, FIQ not taken locally\000"
/* offset=50814 */ "exc_trap_hyp\000\000exception\000Number of Traps to hypervisor\000\000\000event=0xdc\000\000\000\000\000\000\000\000Number of Traps to hypervisor\000"
/* offset=50918 */ "exc_trap_hyp\000\000exception\000Number of traps to hypervisor. This event counts the number of exception traps taken to EL2, excluding HVC instructions. This event is set every time that an exception is executed because of a decoded trap to the hypervisor. CCFAIL exceptions and traps caused by HVC instructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1\000\000\000event=0xdc\000\000\000\000\000\000\000\000Number of traps to hypervisor. This event counts the number of exception traps taken to EL2, excluding HVC instructions. This event is set every time that an exception is executed because of a decoded trap to the hypervisor. CCFAIL exceptions and traps caused by HVC instructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1\000"
/* offset=51700 */ "exc_trap_irq\000\000core imp def\000Exception taken, IRQ not taken locally\000\000\000event=0x8e\000\000\000\000\000\000\000\000Exception taken, IRQ not taken locally\000"
/* offset=51825 */ "exc_trap_irq\000\000exception\000Exception taken, IRQ not taken locally\000\000\000event=0x8e\000\000\000\000\000\000\000\000Exception taken, IRQ not taken locally\000"
/* offset=51947 */ "exc_trap_other\000\000core imp def\000Exception taken, Other traps not taken locally\000\000\000event=0x8d\000\000\000\000\000\000\000\000Exception taken, Other traps not taken locally\000"
/* offset=52090 */ "exc_trap_other\000\000exception\000Exception taken, Other traps not taken locally\000\000\000event=0x8d\000\000\000\000\000\000\000\000Exception taken, Other traps not taken locally\000"
/* offset=52230 */ "exc_trap_pabort\000\000core imp def\000Exception taken, Instruction Abort not taken locally\000\000\000event=0x8b\000\000\000\000\000\000\000\000Exception taken, Instruction Abort not taken locally\000"
/* offset=52386 */ "exc_trap_pabort\000\000exception\000Exception taken, Instruction Abort not taken locally\000\000\000event=0x8b\000\000\000\000\000\000\000\000Exception taken, Instruction Abort not taken locally\000"
/* offset=52539 */ "exc_undef\000\000core imp def\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000"
/* offset=52653 */ "exc_undef\000\000exception\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000"
/* offset=52764 */ "exe_stall_cycle\000\000core imp def\000Cycles of that the number of issue ups are less than 4\000\000\000event=0x7001\000\000\000\000\000\000\000\000Cycles of that the number of issuing micro operations are less than 4\000"
/* offset=52941 */ "ext_mem_req\000\000memory\000External memory request\000\000\000event=0xc0\000\000\000\000\000\000\000\000\000"
/* offset=53006 */ "ext_mem_req_nc\000\000memory\000Non-cacheable external memory request\000\000\000event=0xc1\000\000\000\000\000\000\000\000\000"
/* offset=53088 */ "ext_snoop\000\000cache\000SCU Snooped data from another CPU for this CPU\000\000\000event=0xc8\000\000\000\000\000\000\000\000\000"
/* offset=53173 */ "fetch_bubble\000\000core imp def\000Instructions can receive, but not send\000\000\000event=0x2014\000\000\000\000\000\000\000\000Instructions can receive, but not send\000"
/* offset=53300 */ "fl_comp_wait\000\000other\000This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction\000\000\000event=0x18a\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction\000"
/* offset=53629 */ "fla_val\000\000pipeline\000This event counts valid cycles of FLA pipeline\000\000\000event=0x1a4\000\000\000\000\000\000\000\000This event counts valid cycles of FLA pipeline\000"
/* offset=53762 */ "fla_val_prd_cnt\000\000pipeline\000This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1\000\000\000event=0x1b4\000\000\000\000\000\000\000\000This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1\000"
/* offset=54109 */ "flb_val\000\000pipeline\000This event counts valid cycles of FLB pipeline\000\000\000event=0x1a5\000\000\000\000\000\000\000\000This event counts valid cycles of FLB pipeline\000"
/* offset=54242 */ "flb_val_prd_cnt\000\000pipeline\000This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1\000\000\000event=0x1b5\000\000\000\000\000\000\000\000This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1\000"
/* offset=54589 */ "flux_rcmd\000hisi_sccl,ddrc\000uncore ddrc\000DDRC read commands. Unit: hisi_sccl,ddrc \000\000\000config=0x3\000\000\000\000\000\000\000\000DDRC read commands\000"
/* offset=54707 */ "flux_rd\000hisi_sccl,ddrc\000uncore ddrc\000DDRC total read operations. Unit: hisi_sccl,ddrc \000\000\000config=0x1\000\000\000\000\000\000\000\000DDRC total read operations\000"
/* offset=54839 */ "flux_wcmd\000hisi_sccl,ddrc\000uncore ddrc\000DDRC write commands. Unit: hisi_sccl,ddrc \000\000\000config=0x2\000\000\000\000\000\000\000\000DDRC write commands\000"
/* offset=54959 */ "flux_wr\000hisi_sccl,ddrc\000uncore ddrc\000DDRC total write operations. Unit: hisi_sccl,ddrc \000\000\000config=0\000\000\000\000\000\000\000\000DDRC total write operations\000"
/* offset=55091 */ "fp_cvt_spec\000\000sve\000floating-point convert Operations speculatively executed\000\000\000event=0x8038\000\000\000\000\000\000\000\000floating-point convert Operations speculatively executed\000"
/* offset=55244 */ "fp_dp_fixed_ops_spec\000\000sve\000Non-scalable double-precision floating-point element Operations speculatively executed\000\000\000event=0x80c7\000\000\000\000\000\000\000\000Non-scalable double-precision floating-point element Operations speculatively executed\000"
/* offset=55466 */ "fp_dp_scale_ops_spec\000\000sve\000Scalable double-precision floating-point element Operations speculatively executed\000\000\000event=0x80c6\000\000\000\000\000\000\000\000Scalable double-precision floating-point element Operations speculatively executed\000"
/* offset=55680 */ "fp_dp_spec\000\000instruction\000Floating-point double-precision operations speculatively executed\000\000\000event=0x801c\000\000\000\000\000\000\000\000Floating-point double-precision operations speculatively executed\000"
/* offset=55858 */ "fp_fixed_ops_spec\000\000instruction\000Non-scalable floating-point element Operations speculatively executed\000\000\000event=0x80c1\000\000\000\000\000\000\000\000Non-scalable floating-point element Operations speculatively executed\000"
/* offset=56051 */ "fp_fixed_ops_spec\000\000sve\000Non-scalable floating-point element Operations speculatively executed\000\000\000event=0x80c1\000\000\000\000\000\000\000\000Non-scalable floating-point element Operations speculatively executed\000"
/* offset=56236 */ "fp_fma_spec\000\000sve\000Floating-point FMA Operations speculatively executed\000\000\000event=0x8028\000\000\000\000\000\000\000\000Floating-point FMA Operations speculatively executed\000"
/* offset=56381 */ "fp_hp_fixed_ops_spec\000\000sve\000Non-scalable half-precision floating-point element Operations speculatively executed\000\000\000event=0x80c3\000\000\000\000\000\000\000\000Non-scalable half-precision floating-point element Operations speculatively executed\000"
/* offset=56599 */ "fp_hp_scale_ops_spec\000\000sve\000Scalable half-precision floating-point element Operations speculatively executed\000\000\000event=0x80c2\000\000\000\000\000\000\000\000Scalable half-precision floating-point element Operations speculatively executed\000"
/* offset=56809 */ "fp_hp_spec\000\000instruction\000Floating-point half-precision operations speculatively executed\000\000\000event=0x8014\000\000\000\000\000\000\000\000Floating-point half-precision operations speculatively executed\000"
/* offset=56983 */ "fp_ld_spec\000\000instruction\000This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers\000\000\000event=0x112\000\000\000\000\000\000\000\000This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers\000"
/* offset=57218 */ "fp_mv_spec\000\000instruction\000This event counts architecturally executed floating-point move operations\000\000\000event=0x105\000\000\000\000\000\000\000\000This event counts architecturally executed floating-point move operations\000"
/* offset=57411 */ "fp_recpe_spec\000\000sve\000Floating-point reciprocal estimate Operations speculatively executed\000\000\000event=0x8034\000\000\000\000\000\000\000\000Floating-point reciprocal estimate Operations speculatively executed\000"
/* offset=57590 */ "fp_scale_ops_spec\000\000instruction\000Scalable floating-point element Operations speculatively executed\000\000\000event=0x80c0\000\000\000\000\000\000\000\000Scalable floating-point element Operations speculatively executed\000"
/* offset=57775 */ "fp_scale_ops_spec\000\000sve\000Scalable floating-point element Operations speculatively executed\000\000\000event=0x80c0\000\000\000\000\000\000\000\000Scalable floating-point element Operations speculatively executed\000"
/* offset=57952 */ "fp_sp_fixed_ops_spec\000\000sve\000Non-scalable single-precision floating-point element Operations speculatively executed\000\000\000event=0x80c5\000\000\000\000\000\000\000\000Non-scalable single-precision floating-point element Operations speculatively executed\000"
/* offset=58174 */ "fp_sp_scale_ops_spec\000\000sve\000Scalable single-precision floating-point element Operations speculatively executed\000\000\000event=0x80c4\000\000\000\000\000\000\000\000Scalable single-precision floating-point element Operations speculatively executed\000"
/* offset=58388 */ "fp_sp_spec\000\000instruction\000Floating-point single-precision operations speculatively executed\000\000\000event=0x8018\000\000\000\000\000\000\000\000Floating-point single-precision operations speculatively executed\000"
/* offset=58566 */ "fp_spec\000\000sve\000Floating-point Operations speculatively executed\000\000\000event=0x8010\000\000\000\000\000\000\000\000Floating-point Operations speculatively executed\000"
/* offset=58699 */ "fp_st_spec\000\000instruction\000This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers\000\000\000event=0x113\000\000\000\000\000\000\000\000This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers\000"
/* offset=58936 */ "fsu_clock_off_cycles\000\000clock\000FSU clocking gated off cycle\000\000\000event=0x101\000\000\000\000\000\000\000\000FSU clocking gated off cycle\000"
/* offset=59043 */ "fx_stall\000\000pipeline\000FX stalled\000\000\000event=0x10f\000\000\000\000\000\000\000\000FX Op non-issue\000"
/* offset=59110 */ "hit_on_prf\000\000core imp def\000Hit on prefetched data\000\000\000event=0x6014\000\000\000\000\000\000\000\000Hit on prefetched data\000"
/* offset=59203 */ "i_btac_ram_rd\000\000cache\000Number of ways read in the instruction BTAC RAM\000\000\000event=0xc4\000\000\000\000\000\000\000\000Number of ways read in the instruction BTAC RAM\000"
/* offset=59340 */ "i_data_ram_rd\000\000cache\000Number of ways read in the instruction cache - Data RAM\000\000\000event=0xc3\000\000\000\000\000\000\000\000Number of ways read in the instruction cache - Data RAM\000"
/* offset=59493 */ "i_tag_ram_rd\000\000cache\000Number of ways read in the instruction cache - Tag RAM\000\000\000event=0xc2\000\000\000\000\000\000\000\000Number of ways read in the instruction cache - Tag RAM\000"
/* offset=59643 */ "ic_dep_stall\000\000pipeline\000Cycles the DPU IQ is empty and there is an instruction cache miss being processed\000\000\000event=0xe1\000\000\000\000\000\000\000\000\000"
/* offset=59769 */ "iel_spec\000\000instruction\000This event counts architecturally executed inter-element manipulation operations\000\000\000event=0x109\000\000\000\000\000\000\000\000This event counts architecturally executed inter-element manipulation operations\000"
/* offset=59974 */ "if_is_stall\000\000core imp def\000Instruction fetch stall cycles\000\000\000event=0x1044\000\000\000\000\000\000\000\000Instruction fetch stall cycles\000"
/* offset=60084 */ "ifu_all_thrds_rdy\000\000ifu\000This thread and the other thread both ready for scheduling in if0\000\000\000event=0xdc\000\000\000\000\000\000\000\000This thread and the other thread both ready for scheduling in if0\000"
/* offset=60259 */ "ifu_flushed_excl_tlb_miss\000\000ifu\000Thread flushed due to reasons other than TLB miss\000\000\000event=0xdb\000\000\000\000\000\000\000\000Thread flushed due to reasons other than TLB miss\000"
/* offset=60410 */ "ifu_flushed_tlb_miss\000\000ifu\000Thread flushed due to TLB miss\000\000\000event=0xda\000\000\000\000\000\000\000\000Thread flushed due to TLB miss\000"
/* offset=60518 */ "ifu_goto_idle\000\000ifu\000The thread moved from an active state to an inactive state (long-term sleep state, causing deallocation of some resources)\000\000\000event=0xe0\000\000\000\000\000\000\000\000The thread moved from an active state to an inactive state (long-term sleep state, causing deallocation of some resources)\000"
/* offset=60803 */ "ifu_ic_lf_sp\000\000ifu\000I-Cache Speculative line fill\000\000\000event=0xe4\000\000\000\000\000\000\000\000I-Cache Speculative line fill\000"
/* offset=60901 */ "ifu_ic_lookup_under_miss\000\000ifu\000I-Cache lookup under miss from other thread\000\000\000event=0xe1\000\000\000\000\000\000\000\000I-Cache lookup under miss from other thread\000"
/* offset=61039 */ "ifu_ic_miss_under_miss\000\000ifu\000I-Cache miss under miss from other thread\000\000\000event=0xe2\000\000\000\000\000\000\000\000I-Cache miss under miss from other thread\000"
/* offset=61171 */ "ifu_ic_miss_wait\000\000ifu\000I-Cache miss on an access from the prefetch block\000\000\000event=0xd0\000\000\000\000\000\000\000\000I-Cache miss on an access from the prefetch block\000"
/* offset=61313 */ "ifu_instr_pushed\000\000ifu\000This thread pushed an instruction into the IQ\000\000\000event=0xe3\000\000\000\000\000\000\000\000This thread pushed an instruction into the IQ\000"
/* offset=61447 */ "ifu_iutlb_miss_wait\000\000ifu\000Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l ITLB miss\000\000\000event=0xd1\000\000\000\000\000\000\000\000Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l ITLB miss\000"
/* offset=61666 */ "ifu_micro_caddr_mispred\000\000ifu\000Micro-predictor address mispredict, with respect to if3/if4 predictor\000\000\000event=0xd3\000\000\000\000\000\000\000\000Micro-predictor address mispredict, with respect to if3/if4 predictor\000"
/* offset=61855 */ "ifu_micro_cond_mispred\000\000ifu\000Micro-predictor conditional/direction mispredict, with respect to. if3/if4 predictor\000\000\000event=0xd2\000\000\000\000\000\000\000\000Micro-predictor conditional/direction mispredict, with respect to. if3/if4 predictor\000"
/* offset=62073 */ "ifu_micro_correction\000\000ifu\000Micro-predictor correction\000\000\000event=0xd7\000\000\000\000\000\000\000\000Micro-predictor correction\000"
/* offset=62173 */ "ifu_micro_hit\000\000ifu\000Micro-predictor hit with immediate redirect\000\000\000event=0xd4\000\000\000\000\000\000\000\000Micro-predictor hit with immediate redirect\000"
/* offset=62300 */ "ifu_micro_neg_hit\000\000ifu\000Micro-predictor negative cache hit\000\000\000event=0xd6\000\000\000\000\000\000\000\000Micro-predictor negative cache hit\000"
/* offset=62413 */ "ifu_micro_no_instr1\000\000ifu\000A 2nd instruction could have been pushed but was not because it was nonsequential\000\000\000event=0xd8\000\000\000\000\000\000\000\000A 2nd instruction could have been pushed but was not because it was nonsequential\000"
/* offset=62622 */ "ifu_micro_no_pred\000\000ifu\000Micro-predictor miss\000\000\000event=0xd9\000\000\000\000\000\000\000\000Micro-predictor miss\000"
/* offset=62707 */ "ifu_not_rdy_for_arb\000\000ifu\000This thread was not arbitrated because it was not ready for scheduling. For example, due to a cache miss or TLB miss\000\000\000event=0xdf\000\000\000\000\000\000\000\000This thread was not arbitrated because it was not ready for scheduling. For example, due to a cache miss or TLB miss\000"
/* offset=62986 */ "ifu_win_arb_other_act\000\000ifu\000This thread was arbitrated when the other thread was also active, but not necessarily ready. For example, waiting for I-Cache or TLB\000\000\000event=0xde\000\000\000\000\000\000\000\000This thread was arbitrated when the other thread was also active, but not necessarily ready. For example, waiting for I-Cache or TLB\000"
/* offset=63299 */ "ifu_win_arb_other_rdy\000\000ifu\000This thread was arbitrated when the other thread was also ready for scheduling\000\000\000event=0xdd\000\000\000\000\000\000\000\000This thread was arbitrated when the other thread was also ready for scheduling\000"
/* offset=63504 */ "imx8mm_ddr.cycles\000imx8_ddr\000ddrc\000ddr cycles event. Unit: imx8_ddr \000\000\000event=0\000\000i.MX8MM\000\000\000\000\000\000\000"
/* offset=63595 */ "imx8mm_ddr.read\000imx8_ddr\000ddrc\000ddr read event. Unit: imx8_ddr \000\000\000event=0x35\000\000i.MX8MM\000\000\000\000\000\000\000"
/* offset=63685 */ "imx8mm_ddr.read_cycles\000imx8_ddr\000ddrc\000ddr read-cycles event. Unit: imx8_ddr \000\000\000event=0x2a\000\000i.MX8MM\000\000\000\000\000\000\000"
/* offset=63789 */ "imx8mm_ddr.write\000imx8_ddr\000ddrc\000ddr write event. Unit: imx8_ddr \000\000\000event=0x38\000\000i.MX8MM\000\000\000\000\000\000\000"
/* offset=63881 */ "imx8mm_ddr.write_cycles\000imx8_ddr\000ddrc\000ddr write-cycles event. Unit: imx8_ddr \000\000\000event=0x2b\000\000i.MX8MM\000\000\000\000\000\000\000"
/* offset=63987 */ "imx8mn_ddr.cycles\000imx8_ddr\000ddrc\000ddr cycles event. Unit: imx8_ddr \000\000\000event=0\000\000i.MX8MN\000\000\000\000\000\000\000"
/* offset=64078 */ "imx8mn_ddr.read\000imx8_ddr\000ddrc\000ddr read event. Unit: imx8_ddr \000\000\000event=0x35\000\000i.MX8MN\000\000\000\000\000\000\000"
/* offset=64168 */ "imx8mn_ddr.read_cycles\000imx8_ddr\000ddrc\000ddr read-cycles event. Unit: imx8_ddr \000\000\000event=0x2a\000\000i.MX8MN\000\000\000\000\000\000\000"
/* offset=64272 */ "imx8mn_ddr.write\000imx8_ddr\000ddrc\000ddr write event. Unit: imx8_ddr \000\000\000event=0x38\000\000i.MX8MN\000\000\000\000\000\000\000"
/* offset=64364 */ "imx8mn_ddr.write_cycles\000imx8_ddr\000ddrc\000ddr write-cycles event. Unit: imx8_ddr \000\000\000event=0x2b\000\000i.MX8MN\000\000\000\000\000\000\000"
/* offset=64470 */ "imx8mp_ddr.cycles\000imx8_ddr\000ddrc\000ddr cycles event. Unit: imx8_ddr \000\000\000event=0\000\000i.MX8MP\000\000\000\000\000\000\000"
/* offset=64561 */ "imx8mp_ddr.read\000imx8_ddr\000ddrc\000ddr read event. Unit: imx8_ddr \000\000\000event=0x35\000\000i.MX8MP\000\000\000\000\000\000\000"
/* offset=64651 */ "imx8mp_ddr.read_cycles\000imx8_ddr\000ddrc\000ddr read-cycles event. Unit: imx8_ddr \000\000\000event=0x2a\000\000i.MX8MP\000\000\000\000\000\000\000"
/* offset=64755 */ "imx8mp_ddr.write\000imx8_ddr\000ddrc\000ddr write event. Unit: imx8_ddr \000\000\000event=0x38\000\000i.MX8MP\000\000\000\000\000\000\000"
/* offset=64847 */ "imx8mp_ddr.write_cycles\000imx8_ddr\000ddrc\000ddr write-cycles event. Unit: imx8_ddr \000\000\000event=0x2b\000\000i.MX8MP\000\000\000\000\000\000\000"
/* offset=64953 */ "imx8mq_ddr.cycles\000imx8_ddr\000ddrc\000ddr cycles event. Unit: imx8_ddr \000\000\000event=0\000\000i.MX8MQ\000\000\000\000\000\000\000"
/* offset=65044 */ "imx8mq_ddr.read\000imx8_ddr\000ddrc\000ddr read event. Unit: imx8_ddr \000\000\000event=0x35\000\000i.MX8MQ\000\000\000\000\000\000\000"
/* offset=65134 */ "imx8mq_ddr.read_cycles\000imx8_ddr\000ddrc\000ddr read-cycles event. Unit: imx8_ddr \000\000\000event=0x2a\000\000i.MX8MQ\000\000\000\000\000\000\000"
/* offset=65238 */ "imx8mq_ddr.write\000imx8_ddr\000ddrc\000ddr write event. Unit: imx8_ddr \000\000\000event=0x38\000\000i.MX8MQ\000\000\000\000\000\000\000"
/* offset=65330 */ "imx8mq_ddr.write_cycles\000imx8_ddr\000ddrc\000ddr write-cycles event. Unit: imx8_ddr \000\000\000event=0x2b\000\000i.MX8MQ\000\000\000\000\000\000\000"
/* offset=65436 */ "inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000"
/* offset=65555 */ "inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000This event counts all retired instructions, including those that fail their condition check\000"
/* offset=65729 */ "inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000"
/* offset=65838 */ "iq_is_empty\000\000core imp def\000Instruction queue is empty\000\000\000event=0x1043\000\000\000\000\000\000\000\000Instruction queue is empty\000"
/* offset=65940 */ "ireg_spec\000\000instruction\000This event counts architecturally executed inter-register manipulation operations\000\000\000event=0x10a\000\000\000\000\000\000\000\000This event counts architecturally executed inter-register manipulation operations\000"
/* offset=66148 */ "isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000"
/* offset=66262 */ "itb_miss\000\000cache\000ITB miss\000\000\000event=0x103\000\000\000\000\000\000\000\000ITB miss\000"
/* offset=66317 */ "itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000Access to instruction TLB that causes a translation table walk\000"
/* offset=66480 */ "itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000This event counts on any instruction access which causes L2D_TLB_REFILL to count\000"
/* offset=66661 */ "iutlb_dep_stall\000\000pipeline\000Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed\000\000\000event=0xe2\000\000\000\000\000\000\000\000\000"
/* offset=66794 */ "ixa_stall\000\000pipeline\000IXA stalled\000\000\000event=0x10a\000\000\000\000\000\000\000\000IXA Op non-issue\000"
/* offset=66864 */ "ixb_stall\000\000pipeline\000IXB stalled\000\000\000event=0x10b\000\000\000\000\000\000\000\000IXB Op non-issue\000"
/* offset=66934 */ "l1_miss_wait\000\000cache\000This event counts outstanding L1D cache miss requests per cycle\000\000\000event=0x208\000\000\000\000\000\000\000\000This event counts outstanding L1D cache miss requests per cycle\000"
/* offset=67103 */ "l1_pipe0_comp\000\000pipeline\000This event counts completed requests in L1D cache pipeline#0\000\000\000event=0x260\000\000\000\000\000\000\000\000This event counts completed requests in L1D cache pipeline#0\000"
/* offset=67270 */ "l1_pipe0_comp_prd_cnt\000\000pipeline\000This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1\000\000\000event=0x2b8\000\000\000\000\000\000\000\000This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1\000"
/* offset=67639 */ "l1_pipe0_val\000\000pipeline\000This event counts valid cycles of L1D cache pipeline#0\000\000\000event=0x240\000\000\000\000\000\000\000\000This event counts valid cycles of L1D cache pipeline#0\000"
/* offset=67793 */ "l1_pipe0_val_iu_not_sec0\000\000pipeline\000This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0\000\000\000event=0x2a0\000\000\000\000\000\000\000\000This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0\000"
/* offset=68019 */ "l1_pipe0_val_iu_tag_adrs_pfe\000\000pipeline\000This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1\000\000\000event=0x251\000\000\000\000\000\000\000\000This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1\000"
/* offset=68261 */ "l1_pipe0_val_iu_tag_adrs_sce\000\000pipeline\000This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1\000\000\000event=0x250\000\000\000\000\000\000\000\000This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1\000"
/* offset=68503 */ "l1_pipe1_comp\000\000pipeline\000This event counts completed requests in L1D cache pipeline#1\000\000\000event=0x261\000\000\000\000\000\000\000\000This event counts completed requests in L1D cache pipeline#1\000"
/* offset=68670 */ "l1_pipe1_comp_prd_cnt\000\000pipeline\000This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1\000\000\000event=0x2b9\000\000\000\000\000\000\000\000This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1\000"
/* offset=69039 */ "l1_pipe1_val\000\000pipeline\000This event counts valid cycles of L1D cache pipeline#1\000\000\000event=0x241\000\000\000\000\000\000\000\000This event counts valid cycles of L1D cache pipeline#1\000"
/* offset=69193 */ "l1_pipe1_val_iu_not_sec0\000\000pipeline\000This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0\000\000\000event=0x2a1\000\000\000\000\000\000\000\000This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0\000"
/* offset=69419 */ "l1_pipe1_val_iu_tag_adrs_pfe\000\000pipeline\000This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1\000\000\000event=0x253\000\000\000\000\000\000\000\000This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1\000"
/* offset=69661 */ "l1_pipe1_val_iu_tag_adrs_sce\000\000pipeline\000This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1\000\000\000event=0x252\000\000\000\000\000\000\000\000This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1\000"
/* offset=69903 */ "l1_pipe_abort_stld_intlk\000\000pipeline\000This event counts aborted requests in L1D pipelines that due to store-load interlock\000\000\000event=0x274\000\000\000\000\000\000\000\000This event counts aborted requests in L1D pipelines that due to store-load interlock\000"
/* offset=70129 */ "l1_pipe_comp_gather_0flow\000\000pipeline\000This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0\000\000\000event=0x2b2\000\000\000\000\000\000\000\000This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0\000"
/* offset=70450 */ "l1_pipe_comp_gather_1flow\000\000pipeline\000This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined\000\000\000event=0x2b1\000\000\000\000\000\000\000\000This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined\000"
/* offset=70773 */ "l1_pipe_comp_gather_2flow\000\000pipeline\000This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined\000\000\000event=0x2b0\000\000\000\000\000\000\000\000This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined\000"
/* offset=71106 */ "l1_pipe_comp_scatter_1flow\000\000pipeline\000This event counts the number of flows of the scatter instructions\000\000\000event=0x2b3\000\000\000\000\000\000\000\000This event counts the number of flows of the scatter instructions\000"
/* offset=71296 */ "l1_stage2_tlb_refill\000\000cache\000L1 stage 2 TLB refill\000\000\000event=0x111\000\000\000\000\000\000\000\000Level 1 stage 2 TLB refill\000"
/* offset=71394 */ "l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000"
/* offset=71482 */ "l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000This event counts any load or store operation or page table walk access which looks up in the L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL event causes this event to count\000"
/* offset=71751 */ "l1d_cache_allocate\000\000cache\000Level 1 data cache allocation without refill\000\000\000event=0x1f\000\000\000\000\000\000\000\000Level 1 data cache allocation without refill\000"
/* offset=71887 */ "l1d_cache_err\000\000other\000L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable\000\000\000event=0xd1\000\000\000\000\000\000\000\000\000"
/* offset=72009 */ "l1d_cache_inval\000\000cache\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000"
/* offset=72116 */ "l1d_cache_inval\000\000core imp def\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000"
/* offset=72230 */ "l1d_cache_late_miss\000\000cache\000L1D cache late miss\000\000\000event=0x105\000\000\000\000\000\000\000\000Level 1 data cache late miss\000"
/* offset=72327 */ "l1d_cache_lmiss_rd\000\000cache\000Level 1 data cache long-latency read miss\000\000\000event=0x39\000\000\000\000\000\000\000\000Level 1 data cache long-latency read miss.  The counter counts each memory read access counted by L1D_CACHE that incurs additional latency because it returns data from outside the Level 1 data or unified cache of this processing element\000"
/* offset=72652 */ "l1d_cache_prefetch\000\000cache\000L1D cache prefetch\000\000\000event=0x106\000\000\000\000\000\000\000\000Level 1 data cache prefetch request\000"
/* offset=72754 */ "l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000"
/* offset=72862 */ "l1d_cache_rd\000\000core imp def\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000"
/* offset=72977 */ "l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000"
/* offset=73072 */ "l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000This event counts any load or store operation or page table walk access which causes data to be read from outside the L1, including accesses which do not allocate into L1\000"
/* offset=73312 */ "l1d_cache_refill_dm\000\000cache\000This event counts L1D_CACHE_REFILL caused by demand access\000\000\000event=0x200\000\000\000\000\000\000\000\000This event counts L1D_CACHE_REFILL caused by demand access\000"
/* offset=73478 */ "l1d_cache_refill_hwprf\000\000cache\000This event counts L1D_CACHE_REFILL caused by hardware prefetch\000\000\000event=0x202\000\000\000\000\000\000\000\000This event counts L1D_CACHE_REFILL caused by hardware prefetch\000"
/* offset=73655 */ "l1d_cache_refill_inner\000\000cache\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000"
/* offset=73775 */ "l1d_cache_refill_inner\000\000core imp def\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000"
/* offset=73902 */ "l1d_cache_refill_outer\000\000cache\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000"
/* offset=74022 */ "l1d_cache_refill_outer\000\000core imp def\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000"
/* offset=74149 */ "l1d_cache_refill_prefetch\000\000cache\000L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that cause an allocation into the L1 data cache\000\000\000event=0xc2\000\000\000\000\000\000\000\000L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that cause an allocation into the L1 data cache\000"
/* offset=74478 */ "l1d_cache_refill_prefetch\000\000cache\000Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache\000\000\000event=0xc2\000\000\000\000\000\000\000\000Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache\000"
/* offset=74813 */ "l1d_cache_refill_prf\000\000cache\000This event counts L1D_CACHE_REFILL caused by software or hardware prefetch\000\000\000event=0x49\000\000\000\000\000\000\000\000This event counts L1D_CACHE_REFILL caused by software or hardware prefetch\000"
/* offset=75011 */ "l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000"
/* offset=75126 */ "l1d_cache_refill_rd\000\000core imp def\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000"
/* offset=75248 */ "l1d_cache_refill_wr\000\000cache\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000"
/* offset=75365 */ "l1d_cache_refill_wr\000\000core imp def\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000"
/* offset=75489 */ "l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000"
/* offset=75615 */ "l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000This event counts any write-back of data from the L1 data cache to L2 or L3. This counts both victim line evictions and snoops, including cache maintenance operations\000"
/* offset=75865 */ "l1d_cache_wb_clean\000\000cache\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000"
/* offset=76010 */ "l1d_cache_wb_clean\000\000core imp def\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000"
/* offset=76162 */ "l1d_cache_wb_victim\000\000cache\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000"
/* offset=76289 */ "l1d_cache_wb_victim\000\000core imp def\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000"
/* offset=76423 */ "l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000"
/* offset=76533 */ "l1d_cache_wr\000\000core imp def\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000"
/* offset=76650 */ "l1d_pref_line_fill\000\000cache\000Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache\000\000\000event=0xc3\000\000\000\000\000\000\000\000Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache\000"
/* offset=76972 */ "l1d_tlb\000\000cache\000Attributable Level 1 data or unified TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access\000"
/* offset=77103 */ "l1d_tlb\000\000cache\000L1D TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000This event counts any load or store operation which accesses the data L1 TLB\000"
/* offset=77230 */ "l1d_tlb\000\000cache\000Level 1 data TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000This event counts any load or store operation which accesses the data L1 TLB. If both a load and a store are executed on a cycle, this event counts twice. This event counts regardless of whether the MMU is enabled\000"
/* offset=77503 */ "l1d_tlb_rd\000\000cache\000L1D tlb access, read\000\000\000event=0x4e\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, read\000"
/* offset=77616 */ "l1d_tlb_rd\000\000core imp def\000L1D tlb access, read\000\000\000event=0x4e\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, read\000"
/* offset=77736 */ "l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000"
/* offset=77851 */ "l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000This event counts any refill of the data L1 TLB from the L2 TLB. This includes refills that result in a translation fault\000"
/* offset=78051 */ "l1d_tlb_refill_rd\000\000cache\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000"
/* offset=78160 */ "l1d_tlb_refill_rd\000\000core imp def\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000"
/* offset=78276 */ "l1d_tlb_refill_wr\000\000cache\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000"
/* offset=78387 */ "l1d_tlb_refill_wr\000\000core imp def\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000"
/* offset=78505 */ "l1d_tlb_wr\000\000cache\000L1D tlb access, write\000\000\000event=0x4f\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, write\000"
/* offset=78620 */ "l1d_tlb_wr\000\000core imp def\000L1D tlb access, write\000\000\000event=0x4f\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, write\000"
/* offset=78742 */ "l1d_ws_mode\000\000cache\000L1 data cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L1 data cache\000\000\000event=0xc5\000\000\000\000\000\000\000\000L1 data cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L1 data cache\000"
/* offset=79107 */ "l1d_ws_mode\000\000cache\000L1D is in write stream mode\000\000\000event=0xc7\000\000\000\000\000\000\000\000L1D is in write stream mode\000"
/* offset=79202 */ "l1d_ws_mode\000\000cache\000Level 1 data cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L1 D-cache\000\000\000event=0xc5\000\000\000\000\000\000\000\000Level 1 data cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L1 D-cache\000"
/* offset=79563 */ "l1d_ws_mode_enter\000\000cache\000L1D entering write stream mode\000\000\000event=0xc6\000\000\000\000\000\000\000\000L1D entering write stream mode\000"
/* offset=79670 */ "l1d_ws_mode_entry\000\000cache\000L1 data cache entering write streaming mode. This event counts for each entry into write streaming mode\000\000\000event=0xc4\000\000\000\000\000\000\000\000L1 data cache entering write streaming mode. This event counts for each entry into write streaming mode\000"
/* offset=79923 */ "l1d_ws_mode_entry\000\000cache\000Level 1 data cache entering write streaming mode.This event counts for each entry into write-streaming mode\000\000\000event=0xc4\000\000\000\000\000\000\000\000Level 1 data cache entering write streaming mode.This event counts for each entry into write-streaming mode\000"
/* offset=80184 */ "l1hwpf_inj_alloc_pf\000\000other\000This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher\000\000\000event=0x231\000\000\000\000\000\000\000\000This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher\000"
/* offset=80448 */ "l1hwpf_inj_noalloc_pf\000\000other\000This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher\000\000\000event=0x232\000\000\000\000\000\000\000\000This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher\000"
/* offset=80722 */ "l1hwpf_stream_pf\000\000other\000This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher\000\000\000event=0x230\000\000\000\000\000\000\000\000This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher\000"
/* offset=80951 */ "l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000"
/* offset=81080 */ "l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Level 1 instruction cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which accesses the L1 instruction cache or L0 Macro-op cache\000"
/* offset=81331 */ "l1i_cache_err\000\000other\000L1 Instruction Cache (data or tag) memory error\000\000\000event=0xd0\000\000\000\000\000\000\000\000\000"
/* offset=81421 */ "l1i_cache_lmiss\000\000cache\000Level 1 instruction cache long-latency read miss\000\000\000event=0x4006\000\000\000\000\000\000\000\000Level 1 instruction cache long-latency read miss.  If the L1I_CACHE_RD event is implemented, the counter counts each access counted by L1I_CACHE_RD that incurs additional latency because it returns instructions from outside of the Level 1 instruction cache of this PE.  If the L1I_CACHE_RD event is not implemented, the counter counts each access counted by L1I_CACHE that incurs additional latency because it returns instructions from outside the Level 1 instruction cache of this PE.  The event indicates to software that the access missed in the Level 1 instruction cache and might have a significant performance impact due to the additional latency, compared to the latency of an access that hits in the Level 1 instruction cache\000"
/* offset=82249 */ "l1i_cache_prf\000\000core imp def\000L1I cache prefetch access count\000\000\000event=0x102e\000\000\000\000\000\000\000\000Level 1 instruction cache prefetch access count\000"
/* offset=82379 */ "l1i_cache_prf_refill\000\000core imp def\000L1I cache miss due to prefetch access count\000\000\000event=0x102f\000\000\000\000\000\000\000\000Level 1 instruction cache miss due to prefetch access count\000"
/* offset=82540 */ "l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000"
/* offset=82649 */ "l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000This event counts any instruction fetch which misses in the cache\000"
/* offset=82791 */ "l1i_miss_wait\000\000cache\000This event counts outstanding L1I cache miss requests per cycle\000\000\000event=0x209\000\000\000\000\000\000\000\000This event counts outstanding L1I cache miss requests per cycle\000"
/* offset=82961 */ "l1i_pipe_comp\000\000pipeline\000This event counts completed requests in L1I cache pipeline\000\000\000event=0x268\000\000\000\000\000\000\000\000This event counts completed requests in L1I cache pipeline\000"
/* offset=83124 */ "l1i_pipe_val\000\000pipeline\000This event counts valid cycles of L1I cache pipeline\000\000\000event=0x269\000\000\000\000\000\000\000\000This event counts valid cycles of L1I cache pipeline\000"
/* offset=83274 */ "l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB access\000"
/* offset=83397 */ "l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000This event counts any instruction fetch which accesses the instruction L1 TLB\000"
/* offset=83554 */ "l1i_tlb\000\000cache\000Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000This event counts any instruction fetch which accesses the instruction L1 TLB.This event counts regardless of whether the MMU is enabled\000"
/* offset=83757 */ "l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000"
/* offset=83886 */ "l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000This event counts any refill of the instruction L1 TLB from the L2 TLB. This includes refills that result in a translation fault\000"
/* offset=84100 */ "l1pld_tlb\000\000cache\000Level 1 preload TLB access. This event only counts software and hardware prefetches at Level 1. This event counts all accesses to the preload data micro TLB, that is L1 prefetcher and preload instructions. This event does not take into account whether the MMU is enabled or not\000\000\000event=0xeb\000\000\000\000\000\000\000\000Level 1 preload TLB access. This event only counts software and hardware prefetches at Level 1. This event counts all accesses to the preload data micro TLB, that is L1 prefetcher and preload instructions. This event does not take into account whether the MMU is enabled or not\000"
/* offset=84693 */ "l1pld_tlb_refill\000\000cache\000Level 1 PLD TLB refill\000\000\000event=0xe7\000\000\000\000\000\000\000\000Level 1 PLD TLB refill\000"
/* offset=84783 */ "l2_l1d_cache_wb_unatt\000\000cache\000Unattributable Level 1 data cache write-back. This event occurs when a requestor outside the PE makes a coherency request that results in writeback\000\000\000event=0xf0\000\000\000\000\000\000\000\000Unattributable Level 1 data cache write-back. This event occurs when a requestor outside the PE makes a coherency request that results in writeback\000"
/* offset=85128 */ "l2_l2d_cache_rd_unatt\000\000cache\000Unattributable Level 2 data cache access, read. This event occurs when a requestor outside the PE makes a coherency request that results in level 2 data cache read access\000\000\000event=0xf2\000\000\000\000\000\000\000\000Unattributable Level 2 data cache access, read. This event occurs when a requestor outside the PE makes a coherency request that results in level 2 data cache read access\000"
/* offset=85519 */ "l2_l2d_cache_unatt\000\000cache\000Unattributable Level 2 data cache access. This event occurs when a requestor outside the PE makes a coherency request that results in level 2 data cache access\000\000\000event=0xf1\000\000\000\000\000\000\000\000Unattributable Level 2 data cache access. This event occurs when a requestor outside the PE makes a coherency request that results in level 2 data cache access\000"
/* offset=85885 */ "l2_l3d_cache_alloc_unatt\000\000cache\000Unattributable Level 3 data or unified cache allocation without refill. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 cache allocate without refill\000\000\000event=0xf5\000\000\000\000\000\000\000\000Unattributable Level 3 data or unified cache allocation without refill. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 cache allocate without refill\000"
/* offset=86341 */ "l2_l3d_cache_rd_unatt\000\000cache\000Unattributable Level 3 data cache access, read. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 data cache read access\000\000\000event=0xf4\000\000\000\000\000\000\000\000Unattributable Level 3 data cache access, read. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 data cache read access\000"
/* offset=86732 */ "l2_l3d_cache_refill_unatt\000\000cache\000Unattributable Level 3 data or unified cache refill. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 cache refill\000\000\000event=0xf6\000\000\000\000\000\000\000\000Unattributable Level 3 data or unified cache refill. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 cache refill\000"
/* offset=87117 */ "l2_l3d_cache_unatt\000\000cache\000Unattributable Level 3 data cache access. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 data cache read access\000\000\000event=0xf3\000\000\000\000\000\000\000\000Unattributable Level 3 data cache access. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 data cache read access\000"
/* offset=87493 */ "l2_miss_count\000\000cache\000This event counts the number of times of L2 cache miss\000\000\000event=0x309\000\000\000\000\000\000\000\000This event counts the number of times of L2 cache miss\000"
/* offset=87645 */ "l2_miss_wait\000\000cache\000This event counts outstanding L2 cache miss requests per cycle\000\000\000event=0x308\000\000\000\000\000\000\000\000This event counts outstanding L2 cache miss requests per cycle\000"
/* offset=87812 */ "l2_pipe_comp_all\000\000pipeline\000This event counts completed requests in L2 cache pipeline\000\000\000event=0x350\000\000\000\000\000\000\000\000This event counts completed requests in L2 cache pipeline\000"
/* offset=87976 */ "l2_pipe_comp_pf_l2mib_mch\000\000pipeline\000This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access\000\000\000event=0x370\000\000\000\000\000\000\000\000This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access\000"
/* offset=88279 */ "l2_pipe_val\000\000pipeline\000This event counts valid cycles of L2 cache pipeline\000\000\000event=0x330\000\000\000\000\000\000\000\000This event counts valid cycles of L2 cache pipeline\000"
/* offset=88426 */ "l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000"
/* offset=88515 */ "l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000This event counts any transaction from L1 which looks up in the L2 cache, and any write-back from the L1 to the L2. Snoops from outside the core and cache maintenance operations are not counted\000"
/* offset=88772 */ "l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000Attributable Level 2 data cache allocation without refill\000"
/* offset=88934 */ "l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000This event counts any full cache line write into the L2 cache which does not cause a linefill, including write-backs from L1 to L2 and full-line writes which do not allocate into L1\000"
/* offset=89220 */ "l2d_cache_inval\000\000cache\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000"
/* offset=89327 */ "l2d_cache_inval\000\000core imp def\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000"
/* offset=89441 */ "l2d_cache_lmiss_rd\000\000cache\000Level 2 data cache long-latency read miss\000\000\000event=0x4009\000\000\000\000\000\000\000\000Level 2 data cache long-latency read miss.  The counter counts each memory read access counted by L2D_CACHE that incurs additional latency because it returns data from outside the Level 2 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 2 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 2 data or unified cache\000"
/* offset=89994 */ "l2d_cache_mibmch_prf\000\000cache\000This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access\000\000\000event=0x326\000\000\000\000\000\000\000\000This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access\000"
/* offset=90289 */ "l2d_cache_prefetch\000\000cache\000L2D cache prefetch\000\000\000event=0x107\000\000\000\000\000\000\000\000Level 2 data cache prefetch request\000"
/* offset=90391 */ "l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000"
/* offset=90499 */ "l2d_cache_rd\000\000core imp def\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000"
/* offset=90614 */ "l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted\000"
/* offset=90863 */ "l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000"
/* offset=90947 */ "l2d_cache_refill_dm\000\000cache\000This event counts L2D_CACHE_REFILL caused by demand access\000\000\000event=0x300\000\000\000\000\000\000\000\000This event counts L2D_CACHE_REFILL caused by demand access\000"
/* offset=91113 */ "l2d_cache_refill_hwprf\000\000cache\000This event counts L2D_CACHE_REFILL caused by hardware prefetch\000\000\000event=0x302\000\000\000\000\000\000\000\000This event counts L2D_CACHE_REFILL caused by hardware prefetch\000"
/* offset=91290 */ "l2d_cache_refill_prefetch\000\000cache\000L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event does not count. If the complex is configured without a per-complex L2 cache, this event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. If neither a per-complex cache or a cluster cache is configured, this event is not implemented\000\000\000event=0xc1\000\000\000\000\000\000\000\000L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event does not count. If the complex is configured without a per-complex L2 cache, this event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. If neither a per-complex cache or a cluster cache is configured, this event is not implemented\000"
/* offset=92059 */ "l2d_cache_refill_prefetch\000\000cache\000Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented\000\000\000event=0xc1\000\000\000\000\000\000\000\000Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented\000"
/* offset=92852 */ "l2d_cache_refill_prf\000\000cache\000This event counts L2D_CACHE_REFILL caused by software or hardware prefetch\000\000\000event=0x59\000\000\000\000\000\000\000\000This event counts L2D_CACHE_REFILL caused by software or hardware prefetch\000"
/* offset=93050 */ "l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000"
/* offset=93165 */ "l2d_cache_refill_rd\000\000core imp def\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000"
/* offset=93287 */ "l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000"
/* offset=93404 */ "l2d_cache_refill_wr\000\000core imp def\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000"
/* offset=93528 */ "l2d_cache_stash_dropped\000\000cache\000L2 cache stash dropped. This event counts on each stash request that is received from the interconnect or the Accelerator Coherency Port (ACP), that targets L2 cache and is dropped due to lack of buffer space to hold the request\000\000\000event=0xd6\000\000\000\000\000\000\000\000L2 cache stash dropped. This event counts on each stash request that is received from the interconnect or the Accelerator Coherency Port (ACP), that targets L2 cache and is dropped due to lack of buffer space to hold the request\000"
/* offset=94037 */ "l2d_cache_stash_dropped\000\000cache\000Level 2 cache stash dropped. This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request. L2 and L3 cache events (L2D_CACHE*, L3D_CACHE*) The behavior of these events depends on the configuration of the core. If the private L2 cache is present, the L2D_CACHE* events count the activity in the private L2 cache, and the L3D_CACHE* events count the activity in the DSU L3 cache (if present). If the private L2 cache is not present but the DSU L3 cache is present, the L2D_CACHE* events count activity in the DSU L3 cache and the L3D_CACHE* events do not count. The L2D_CACHE_WB, L2D_CACHE_WR and L2D_CACHE_REFILL_WR events do not count in this configuration. If neither the private L2 cache nor the DSU L3 cache are present, neither the L2D_CACHE* or L3D_CACHE* events will count\000\000\000event=0xf7\000\000\000\000\000\000\000\000Level 2 cache stash dropped. This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request. L2 and L3 cache events (L2D_CACHE*, L3D_CACHE*) The behavior of these events depends on the configuration of the core. If the private L2 cache is present, the L2D_CACHE* events count the activity in the private L2 cache, and the L3D_CACHE* events count the activity in the DSU L3 cache (if present). If the private L2 cache is not present but the DSU L3 cache is present, the L2D_CACHE* events count activity in the DSU L3 cache and the L3D_CACHE* events do not count. The L2D_CACHE_WB, L2D_CACHE_WR and L2D_CACHE_REFILL_WR events do not count in this configuration. If neither the private L2 cache nor the DSU L3 cache are present, neither the L2D_CACHE* or L3D_CACHE* events will count\000"
/* offset=95854 */ "l2d_cache_stash_dropped\000\000cache\000Level 2 cache stash dropped.This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request\000\000\000event=0xd6\000\000\000\000\000\000\000\000Level 2 cache stash dropped.This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request\000"
/* offset=96291 */ "l2d_cache_swap_local\000\000cache\000This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch\000\000\000event=0x396\000\000\000\000\000\000\000\000This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch\000"
/* offset=96586 */ "l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000"
/* offset=96712 */ "l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000This event counts any write-back of data from the L2 cache to outside the core. This includes snoops to the L2 which return data, regardless of whether they cause an invalidation. Invalidations from the L2 which do not write data outside of the core and snoops which return data from the L1 are not counted\000"
/* offset=97102 */ "l2d_cache_wb_clean\000\000cache\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000"
/* offset=97247 */ "l2d_cache_wb_clean\000\000core imp def\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000"
/* offset=97399 */ "l2d_cache_wb_victim\000\000cache\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000"
/* offset=97526 */ "l2d_cache_wb_victim\000\000core imp def\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000"
/* offset=97660 */ "l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000"
/* offset=97770 */ "l2d_cache_wr\000\000core imp def\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000"
/* offset=97887 */ "l2d_l2walk_tlb\000\000cache\000Level 2 TLB level-2 walk cache access.This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled\000\000\000event=0xd2\000\000\000\000\000\000\000\000Level 2 TLB level-2 walk cache access.This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled\000"
/* offset=98481 */ "l2d_l2walk_tlb_refill\000\000cache\000Level 2 TLB level-2 walk cache refill.This event does not count if the MMU is disabled\000\000\000event=0xd3\000\000\000\000\000\000\000\000Level 2 TLB level-2 walk cache refill.This event does not count if the MMU is disabled\000"
/* offset=98704 */ "l2d_llwalk_tlb\000\000cache\000Level 2 TLB last-level walk cache access.This event does not count if the MMU is disabled\000\000\000event=0xd0\000\000\000\000\000\000\000\000Level 2 TLB last-level walk cache access.This event does not count if the MMU is disabled\000"
/* offset=98926 */ "l2d_llwalk_tlb_refill\000\000cache\000Level 2 TLB last-level walk cache refill.This event does not count if the MMU is disabled\000\000\000event=0xd1\000\000\000\000\000\000\000\000Level 2 TLB last-level walk cache refill.This event does not count if the MMU is disabled\000"
/* offset=99155 */ "l2d_pref_line_fill\000\000cache\000Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3_PREF_LINE_FILL. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented\000\000\000event=0xc4\000\000\000\000\000\000\000\000Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3_PREF_LINE_FILL. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented\000"
/* offset=99925 */ "l2d_s2_tlb\000\000cache\000L2 TLB IPA cache access. This event counts on each access to the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 translation is disabled, this event does not count\000\000\000event=0xd4\000\000\000\000\000\000\000\000L2 TLB IPA cache access. This event counts on each access to the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 translation is disabled, this event does not count\000"
/* offset=100457 */ "l2d_s2_tlb\000\000cache\000Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count\000\000\000event=0xd4\000\000\000\000\000\000\000\000Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count\000"
/* offset=100991 */ "l2d_s2_tlb_refill\000\000cache\000L2 TLB IPA cache refill. This event counts on each refill of the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 translation is disabled, this event does not count\000\000\000event=0xd5\000\000\000\000\000\000\000\000L2 TLB IPA cache refill. This event counts on each refill of the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 translation is disabled, this event does not count\000"
/* offset=101572 */ "l2d_s2_tlb_refill\000\000cache\000Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count\000\000\000event=0xd5\000\000\000\000\000\000\000\000Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count\000"
/* offset=102157 */ "l2d_swap_dm\000\000cache\000This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch\000\000\000event=0x325\000\000\000\000\000\000\000\000This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch\000"
/* offset=102443 */ "l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access\000"
/* offset=102574 */ "l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000This event counts on any access to the L2 TLB (caused by a refill of any of the L1 TLBs). This event does not count if the MMU is disabled\000"
/* offset=102796 */ "l2d_tlb_access\000\000cache\000L2D TLB access\000\000\000event=0x34\000\000\000\000\000\000\000\000Level 2 access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count\000"
/* offset=102985 */ "l2d_tlb_rd\000\000cache\000L2D cache access, read\000\000\000event=0x5e\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, read\000"
/* offset=103100 */ "l2d_tlb_rd\000\000core imp def\000L2D cache access, read\000\000\000event=0x5e\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, read\000"
/* offset=103222 */ "l2d_tlb_refill\000\000cache\000Attributable L2 data or unified TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000This event counts on anyrefill of the L2 TLB, caused by either an instruction or data access.This event does not count if the MMU is disabled\000"
/* offset=103449 */ "l2d_tlb_refill\000\000cache\000Attributable Level 2 data TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000Attributable Level 2 data TLB refill\000"
/* offset=103565 */ "l2d_tlb_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x5c\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, read\000"
/* offset=103687 */ "l2d_tlb_refill_rd\000\000core imp def\000L2D cache refill, read\000\000\000event=0x5c\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, read\000"
/* offset=103816 */ "l2d_tlb_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x5d\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, write\000"
/* offset=103940 */ "l2d_tlb_refill_wr\000\000core imp def\000L2D cache refill, write\000\000\000event=0x5d\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, write\000"
/* offset=104071 */ "l2d_tlb_wr\000\000cache\000L2D cache access, write\000\000\000event=0x5f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, write\000"
/* offset=104188 */ "l2d_tlb_wr\000\000core imp def\000L2D cache access, write\000\000\000event=0x5f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, write\000"
/* offset=104312 */ "l2d_walk_tlb\000\000cache\000L2 TLB walk cache access. This event does not count if the MMU is disabled\000\000\000event=0xd0\000\000\000\000\000\000\000\000L2 TLB walk cache access. This event does not count if the MMU is disabled\000"
/* offset=104502 */ "l2d_walk_tlb_refill\000\000cache\000L2 TLB walk cache refill. This event does not count if the MMU is disabled\000\000\000event=0xd1\000\000\000\000\000\000\000\000L2 TLB walk cache refill. This event does not count if the MMU is disabled\000"
/* offset=104699 */ "l2d_ws_mode\000\000cache\000L2 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L2 cache\000\000\000event=0xc3\000\000\000\000\000\000\000\000L2 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L2 cache\000"
/* offset=105044 */ "l2d_ws_mode\000\000cache\000Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache\000\000\000event=0xc3\000\000\000\000\000\000\000\000Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache\000"
/* offset=105393 */ "l2d_ws_mode\000\000cache\000Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache\000\000\000event=0xc8\000\000\000\000\000\000\000\000Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache\000"
/* offset=105742 */ "l2hwpf_inj_alloc_pf\000\000other\000This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher\000\000\000event=0x234\000\000\000\000\000\000\000\000This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher\000"
/* offset=106004 */ "l2hwpf_inj_noalloc_pf\000\000other\000This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher\000\000\000event=0x235\000\000\000\000\000\000\000\000This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher\000"
/* offset=106276 */ "l2hwpf_other\000\000other\000This event counts prefetch requests to L2 cache generated by the other causes\000\000\000event=0x236\000\000\000\000\000\000\000\000This event counts prefetch requests to L2 cache generated by the other causes\000"
/* offset=106473 */ "l2hwpf_stream_pf\000\000other\000This event counts streaming prefetch requests to L2 cache generated by hardware prefecher\000\000\000event=0x233\000\000\000\000\000\000\000\000This event counts streaming prefetch requests to L2 cache generated by hardware prefecher\000"
/* offset=106698 */ "l2i_tlb\000\000cache\000Attributable Level 2 instruction TLB access\000\000\000event=0x30\000\000\000\000\000\000\000\000Attributable Level 2 instruction TLB access\000"
/* offset=106821 */ "l2i_tlb_access\000\000cache\000L2I TLB access\000\000\000event=0x35\000\000\000\000\000\000\000\000Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count\000"
/* offset=107024 */ "l2i_tlb_refill\000\000cache\000Attributable Level 2 instruction TLB refill\000\000\000event=0x2e\000\000\000\000\000\000\000\000Attributable Level 2 instruction TLB refill\000"
/* offset=107154 */ "l2pld_tlb\000\000cache\000Level 2 preload and MMU prefetcher TLB access. This event only counts software and hardware prefetches at Level 2\000\000\000event=0xe8\000\000\000\000\000\000\000\000Level 2 preload and MMU prefetcher TLB access. This event only counts software and hardware prefetches at Level 2\000"
/* offset=107419 */ "l3_cache_rd\000\000cache\000L3 cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 3 cache access, read\000"
/* offset=107520 */ "l3_pref_line_fill\000\000cache\000Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to distinguish between both hardware and software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented\000\000\000event=0xc5\000\000\000\000\000\000\000\000Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to distinguish between both hardware and software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented\000"
/* offset=108575 */ "l3d_cache\000\000cache\000Attributable Level 3 data cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000Attributable Level 3 data cache access\000"
/* offset=108690 */ "l3d_cache\000\000cache\000Attributable Level 3 unified cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000This event counts for any cacheable read transaction returning datafrom the SCU, or for any cacheable write to the SCU\000"
/* offset=108888 */ "l3d_cache_allocate\000\000cache\000Allocation without refill\000\000\000event=0x29\000\000\000\000\000\000\000\000This event counts any full cache line write into the L3 cache which does not cause a linefill, including write-backs from L2 to L3 and full-line writes which do not allocate into L2\000"
/* offset=109142 */ "l3d_cache_allocate\000\000cache\000Attributable Level 3 data cache allocation without refill\000\000\000event=0x29\000\000\000\000\000\000\000\000Attributable Level 3 data cache allocation without refill\000"
/* offset=109304 */ "l3d_cache_lmiss_rd\000\000cache\000Level 3 data cache long-latency read miss\000\000\000event=0x400b\000\000\000\000\000\000\000\000Level 3 data cache long-latency read miss.  The counter counts each memory read access counted by L3D_CACHE that incurs additional latency because it returns data from outside the Level 3 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 3 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 3 data or unified cache\000"
/* offset=109857 */ "l3d_cache_rd\000\000cache\000Attributable Level 3 data or unified cache access, read\000\000\000event=0xa0\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache access, read\000"
/* offset=110009 */ "l3d_cache_refill\000\000cache\000Attributable Level 3 data cache refill\000\000\000event=0x2a\000\000\000\000\000\000\000\000Attributable Level 3 data cache refill\000"
/* offset=110131 */ "l3d_cache_refill\000\000cache\000Attributable Level 3 unified cache refill\000\000\000event=0x2a\000\000\000\000\000\000\000\000This event counts for any cacheable read transaction returning datafrom the SCU for which the data source was outside the cluster. Transactions such as ReadUnique are counted here as 'read' transactions, even though they can be generated by store instructions\000"
/* offset=110477 */ "l3d_cache_refill_prefetch\000\000cache\000Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to both distinguish hardware vs software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented\000\000\000event=0xc0\000\000\000\000\000\000\000\000Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to both distinguish hardware vs software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented\000"
/* offset=111522 */ "l3d_cache_refill_rd\000\000cache\000Attributable Level 3 data or unified cache refill, read\000\000\000event=0xa2\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache refill, read\000"
/* offset=111681 */ "l3d_ws_mode\000\000cache\000L3 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L3 cache\000\000\000event=0xc7\000\000\000\000\000\000\000\000L3 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L3 cache\000"
/* offset=112026 */ "l3d_ws_mode\000\000cache\000Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache\000\000\000event=0xc9\000\000\000\000\000\000\000\000Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache\000"
/* offset=112375 */ "l3d_ws_mode\000\000cache\000Level 3 cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache\000\000\000event=0xc7\000\000\000\000\000\000\000\000Level 3 cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache\000"
/* offset=112722 */ "ld_align_lat\000\000memory\000Load with additional latency from alignment\000\000\000event=0x4021\000\000\000\000\000\000\000\000Load with additional latency from alignment\000"
/* offset=112853 */ "ld_comp_wait\000\000other\000This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access\000\000\000event=0x184\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access\000"
/* offset=113248 */ "ld_comp_wait_ex\000\000other\000This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access\000\000\000event=0x185\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access\000"
/* offset=113632 */ "ld_comp_wait_l1_miss\000\000other\000This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access\000\000\000event=0x182\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access\000"
/* offset=113991 */ "ld_comp_wait_l1_miss_ex\000\000other\000This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access\000\000\000event=0x183\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access\000"
/* offset=114339 */ "ld_comp_wait_l2_miss\000\000other\000This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access\000\000\000event=0x180\000\000\000\000\000\000\000\000This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access\000"
/* offset=114690 */ "ld_comp_wait_l2_miss_ex\000\000other\000This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access\000\000\000event=0x181\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access\000"
/* offset=115034 */ "ld_comp_wait_pfp_busy\000\000other\000This event counts every cycle that no instruction was committed due to the lack of an available prefetch port\000\000\000event=0x186\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed due to the lack of an available prefetch port\000"
/* offset=115304 */ "ld_comp_wait_pfp_busy_ex\000\000other\000This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation\000\000\000event=0x187\000\000\000\000\000\000\000\000This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation\000"
/* offset=115517 */ "ld_comp_wait_pfp_busy_swpf\000\000other\000This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction\000\000\000event=0x188\000\000\000\000\000\000\000\000This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction\000"
/* offset=115744 */ "ld_dep_stall\000\000pipeline\000Cycles there is a stall in the Wr stage because of a load miss\000\000\000event=0xe7\000\000\000\000\000\000\000\000\000"
/* offset=115851 */ "ld_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, load\000\000\000event=0x6\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, load\000"
/* offset=116034 */ "ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000"
/* offset=116153 */ "ldrex_spec\000\000instruction\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000"
/* offset=116311 */ "ldrex_spec\000\000intrinsic\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000"
/* offset=116467 */ "ldst_align_lat\000\000memory\000Access with additional latency from alignment\000\000\000event=0x4020\000\000\000\000\000\000\000\000Access with additional latency from alignment\000"
/* offset=116604 */ "ldst_spec\000\000instruction\000Operation speculatively executed, load or store\000\000\000event=0x72\000\000\000\000\000\000\000\000Operation speculatively executed, load or store\000"
/* offset=116743 */ "lf_stall\000\000pipeline\000A linefill caused an instruction side stall\000\000\000event=0xc0\000\000\000\000\000\000\000\000A linefill caused an instruction side stall\000"
/* offset=116870 */ "ll_cache_miss_rd\000\000cache\000Last level cache miss, read\000\000\000event=0x37\000\000\000\000\000\000\000\000Last level cache miss, read\000"
/* offset=116970 */ "ll_cache_rd\000\000cache\000Attributable Last level cache memory read\000\000\000event=0x36\000\000\000\000\000\000\000\000Attributable Last level cache memory read\000"
/* offset=117093 */ "ll_ws_mode\000\000cache\000Last level cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the system cache\000\000\000event=0xc8\000\000\000\000\000\000\000\000Last level cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the system cache\000"
/* offset=117461 */ "ls_iq_full\000\000pipeline\000Duration for which all slots in the load-store issue queue are busy. This event counts the cycles where all slots in the LS IQs are full with micro-operations waiting for issuing, and the dispatch stage is not empty\000\000\000event=0xd8\000\000\000\000\000\000\000\000Duration for which all slots in the load-store issue queue are busy. This event counts the cycles where all slots in the LS IQs are full with micro-operations waiting for issuing, and the dispatch stage is not empty\000"
/* offset=117934 */ "ls_iq_full\000\000pipeline\000Duration for which all slots in the load-store issue queue are busy\000\000\000event=0xd8\000\000\000\000\000\000\000\000Duration for which all slots in the load-store issue queue are busy\000"
/* offset=118111 */ "lx_stall\000\000pipeline\000LX stalled\000\000\000event=0x10d\000\000\000\000\000\000\000\000LX Op non-issue\000"
/* offset=118178 */ "mediated_num\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x32\000\000\000\000\000\000\000\000\000"
/* offset=118259 */ "mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000"
/* offset=118336 */ "mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000This event counts memory accesses due to load or store instructions. This event counts the sum of MEM_ACCESS_RD and MEM_ACCESS_WR\000"
/* offset=118524 */ "mem_access_checked\000\000memory\000Checked data memory access\000\000\000event=0x4024\000\000\000\000\000\000\000\000Checked data memory access\000"
/* offset=118627 */ "mem_access_checked_rd\000\000memory\000Checked data memory access, read\000\000\000event=0x4025\000\000\000\000\000\000\000\000Checked data memory access, read\000"
/* offset=118745 */ "mem_access_checked_wr\000\000memory\000Checked data memory access, write\000\000\000event=0x4026\000\000\000\000\000\000\000\000Checked data memory access, write\000"
/* offset=118865 */ "mem_access_rd\000\000core imp def\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000"
/* offset=118963 */ "mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000"
/* offset=119055 */ "mem_access_wr\000\000core imp def\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000"
/* offset=119155 */ "mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000"
/* offset=119249 */ "mem_stall_anyload\000\000core imp def\000No any micro operation is issued and meanwhile any load operation is not resolved\000\000\000event=0x7004\000\000\000\000\000\000\000\000No any micro operation is issued and meanwhile any load operation is not resolved\000"
/* offset=119467 */ "mem_stall_l1miss\000\000core imp def\000No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill\000\000\000event=0x7006\000\000\000\000\000\000\000\000No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill\000"
/* offset=119752 */ "mem_stall_l2miss\000\000core imp def\000No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache\000\000\000event=0x7007\000\000\000\000\000\000\000\000No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache\000"
/* offset=120089 */ "memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000"
/* offset=120171 */ "memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs\000"
/* offset=120341 */ "memory_error\000\000memory\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs\000"
/* offset=120508 */ "mmu_ptw\000\000mmu\000Duration of a translation table walk handled by the MMU\000\000\000event=0xe0\000\000\000\000\000\000\000\000Duration of a translation table walk handled by the MMU\000"
/* offset=120653 */ "mmu_ptw_cp15\000\000mmu\000Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA to PA operations)\000\000\000event=0xe6\000\000\000\000\000\000\000\000Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA to PA operations)\000"
/* offset=120915 */ "mmu_ptw_cp15\000\000mmu\000Duration of a translation table walk requested by an address translation operation\000\000\000event=0xe6\000\000\000\000\000\000\000\000Duration of a translation table walk requested by an address translation operation\000"
/* offset=121119 */ "mmu_ptw_iside\000\000mmu\000Duration of a translation table walk requested by the Instruction Side\000\000\000event=0xe4\000\000\000\000\000\000\000\000Duration of a translation table walk requested by the Instruction Side\000"
/* offset=121300 */ "mmu_ptw_iside\000\000mmu\000Duration of a translation table walk requested by the instruction side\000\000\000event=0xe4\000\000\000\000\000\000\000\000Duration of a translation table walk requested by the instruction side\000"
/* offset=121481 */ "mmu_ptw_lsu\000\000mmu\000Duration of a translation table walk requested by the LSU\000\000\000event=0xe3\000\000\000\000\000\000\000\000Duration of a translation table walk requested by the LSU\000"
/* offset=121634 */ "mmu_ptw_pld\000\000mmu\000Duration of a translation table walk requested by a Preload instruction or Prefetch request\000\000\000event=0xe5\000\000\000\000\000\000\000\000Duration of a translation table walk requested by a Preload instruction or Prefetch request\000"
/* offset=121855 */ "mmu_ptw_st1\000\000mmu\000Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1\000\000\000event=0xe1\000\000\000\000\000\000\000\000Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1\000"
/* offset=122172 */ "mmu_ptw_st1\000\000mmu\000Duration of a Stage 1 translation table walk handled by the MMU\000\000\000event=0xe1\000\000\000\000\000\000\000\000Duration of a Stage 1 translation table walk handled by the MMU\000"
/* offset=122337 */ "mmu_ptw_st2\000\000mmu\000Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1\000\000\000event=0xe2\000\000\000\000\000\000\000\000Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1\000"
/* offset=122654 */ "mmu_ptw_st2\000\000mmu\000Duration of a Stage 2 translation table walk handled by the MMU\000\000\000event=0xe2\000\000\000\000\000\000\000\000Duration of a Stage 2 translation table walk handled by the MMU\000"
/* offset=122819 */ "nop_spec\000\000instruction\000Speculatively executed, NOP\000\000\000event=0x100\000\000\000\000\000\000\000\000Operation speculatively executed, NOP\000"
/* offset=122928 */ "op_retired\000\000instruction\000Micro-operation architecturally executed\000\000\000event=0x3a\000\000\000\000\000\000\000\000Micro-operation architecturally executed.  The counter counts each operation counted by OP_SPEC that would be executed in a simple sequential execution of the program\000"
/* offset=123180 */ "op_spec\000\000instruction\000Micro-operation speculatively executed\000\000\000event=0x3b\000\000\000\000\000\000\000\000Micro-operation speculatively executed.  The counter counts the number of operations executed by the processing element, including those that are executed speculatively and would not be executed in a simple sequential execution of the program\000"
/* offset=123503 */ "other_interlock_stall\000\000pipeline\000Cycles there is an interlock other than  Advanced SIMD/Floating-point instructions or load/store instruction\000\000\000event=0xe4\000\000\000\000\000\000\000\000\000"
/* offset=123665 */ "other_iq_dep_stall\000\000pipeline\000Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error\000\000\000event=0xe0\000\000\000\000\000\000\000\000\000"
/* offset=123842 */ "page_walk_l0_stage1_hit\000\000cache\000Page walk, L0 stage-1 hit\000\000\000event=0x112\000\000\000\000\000\000\000\000Page walk cache level-0 stage-1 hit\000"
/* offset=123956 */ "page_walk_l1_stage1_hit\000\000cache\000Page walk, L1 stage-1 hit\000\000\000event=0x113\000\000\000\000\000\000\000\000Page walk cache level-1 stage-1 hit\000"
/* offset=124070 */ "page_walk_l1_stage2_hit\000\000cache\000Page walk, L1 stage-2 hit\000\000\000event=0x115\000\000\000\000\000\000\000\000Page walk cache level-1 stage-2 hit\000"
/* offset=124184 */ "page_walk_l2_stage1_hit\000\000cache\000Page walk, L2 stage-1 hit\000\000\000event=0x114\000\000\000\000\000\000\000\000Page walk cache level-2 stage-1 hit\000"
/* offset=124298 */ "page_walk_l2_stage2_hit\000\000cache\000Page walk, L2 stage-2 hit\000\000\000event=0x116\000\000\000\000\000\000\000\000Page walk cache level-2 stage-2 hit\000"
/* offset=124412 */ "pc_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, software change of the PC\000\000\000event=0xc\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, software change of the PC\000"
/* offset=124643 */ "pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000"
/* offset=124810 */ "pld_utlb_refill\000\000cache\000Level 1 PLD TLB refill\000\000\000event=0xe7\000\000\000\000\000\000\000\000Level 1 PLD TLB refill\000"
/* offset=124899 */ "pldtlb_walk\000\000cache\000Prefetch access to unified TLB that caused a page table walk. This event counts software and hardware prefetches\000\000\000event=0xec\000\000\000\000\000\000\000\000Prefetch access to unified TLB that caused a page table walk. This event counts software and hardware prefetches\000"
/* offset=125164 */ "pmu_hovfs\000\000pmu\000PMU overflow, counters reserved for use by EL2\000\000\000event=0x400f\000\000\000\000\000\000\000\000PMU overflow, counters reserved for use by EL2\000"
/* offset=125295 */ "pmu_ovfs\000\000pmu\000PMU overflow, counters accessible to EL1 and EL0\000\000\000event=0x400d\000\000\000\000\000\000\000\000PMU overflow, counters accessible to EL1 and EL0\000"
/* offset=125429 */ "post_index_spec\000\000instruction\000This event counts architecturally executed operations that uses 'post-index' as its addressing mode\000\000\000event=0x124\000\000\000\000\000\000\000\000This event counts architecturally executed operations that uses 'post-index' as its addressing mode\000"
/* offset=125679 */ "prd_spec\000\000instruction\000This event counts architecturally executed operations that using predicate register\000\000\000event=0x108\000\000\000\000\000\000\000\000This event counts architecturally executed operations that using predicate register\000"
/* offset=125890 */ "pre_cmd\000hisi_sccl,ddrc\000uncore ddrc\000DDRC precharge commands. Unit: hisi_sccl,ddrc \000\000\000config=0x4\000\000\000\000\000\000\000\000DDRC precharge commands\000"
/* offset=126016 */ "pre_decode_err\000\000other\000Pre-decode error\000\000\000event=0xc6\000\000\000\000\000\000\000\000\000"
/* offset=126076 */ "pre_index_spec\000\000instruction\000This event counts architecturally executed operations that uses 'pre-index' as its addressing mode\000\000\000event=0x123\000\000\000\000\000\000\000\000This event counts architecturally executed operations that uses 'pre-index' as its addressing mode\000"
/* offset=126323 */ "predecode_error\000\000exception\000Predecode error\000\000\000event=0xc6\000\000\000\000\000\000\000\000Predecode error\000"
/* offset=126402 */ "prefetch_drop\000hisi_sccl,l3c\000uncore l3c\000Count of the number of prefetch drops from this L3C. Unit: hisi_sccl,l3c \000\000\000config=0x42\000\000\000\000\000\000\000\000Count of the number of prefetch drops from this L3C\000"
/* offset=126588 */ "prefetch_linefill\000\000cache\000Linefill because of prefetch\000\000\000event=0xc2\000\000\000\000\000\000\000\000\000"
/* offset=126663 */ "prefetch_linefill_drop\000\000cache\000Instruction Cache Throttle occurred\000\000\000event=0xc3\000\000\000\000\000\000\000\000\000"
/* offset=126750 */ "prf_req\000\000core imp def\000Prefetch request from LSU\000\000\000event=0x6013\000\000\000\000\000\000\000\000Prefetch request from LSU\000"
/* offset=126846 */ "prf_spec\000\000sve\000Prefetch Operations speculatively executed\000\000\000event=0x8087\000\000\000\000\000\000\000\000Prefetch Operations speculatively executed\000"
/* offset=126968 */ "prx_val\000\000pipeline\000This event counts valid cycles of PRX pipeline\000\000\000event=0x1a6\000\000\000\000\000\000\000\000This event counts valid cycles of PRX pipeline\000"
/* offset=127101 */ "ptw_stall\000\000pipeline\000A translation table walk caused an instruction side stall\000\000\000event=0xc1\000\000\000\000\000\000\000\000A translation table walk caused an instruction side stall\000"
/* offset=127257 */ "rc_ld_spec\000\000instruction\000Release consistency operation speculatively executed, Load-Acquire\000\000\000event=0x90\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Load-Acquire\000"
/* offset=127435 */ "rc_st_spec\000\000instruction\000Release consistency operation speculatively executed, Store-Release\000\000\000event=0x91\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Store-Release\000"
/* offset=127615 */ "rd_cpipe\000hisi_sccl,l3c\000uncore l3c\000Total read accesses. Unit: hisi_sccl,l3c \000\000\000config=0\000\000\000\000\000\000\000\000Total read accesses\000"
/* offset=127729 */ "rd_ddr_128b\000hisi_sccl,hha\000uncore hha\000The number of read operations sent by HHA to DDRC which size is 128 bytes. Unit: hisi_sccl,hha \000\000\000config=0x1e\000\000\000\000\000\000\000\000The number of read operations sent by HHA to DDRC which size is 128 bytes\000"
/* offset=127957 */ "rd_ddr_64b\000hisi_sccl,hha\000uncore hha\000The number of read operations sent by HHA to DDRC which size is 64 bytes. Unit: hisi_sccl,hha \000\000\000config=0x1c\000\000\000\000\000\000\000\000The number of read operations sent by HHA to DDRC which size is 64bytes\000"
/* offset=128181 */ "rd_hit_cpipe\000hisi_sccl,l3c\000uncore l3c\000Total read hits. Unit: hisi_sccl,l3c \000\000\000config=0x2\000\000\000\000\000\000\000\000Total read hits\000"
/* offset=128293 */ "rd_hit_spipe\000hisi_sccl,l3c\000uncore l3c\000Count of the number of read lines that hits in spipe of this L3C. Unit: hisi_sccl,l3c \000\000\000config=0x22\000\000\000\000\000\000\000\000Count of the number of read lines that hits in spipe of this L3C\000"
/* offset=128504 */ "rd_spipe\000hisi_sccl,l3c\000uncore l3c\000Count of the number of read lines that come from this cluster of CPU core in spipe. Unit: hisi_sccl,l3c \000\000\000config=0x20\000\000\000\000\000\000\000\000Count of the number of read lines that come from this cluster of CPU core in spipe\000"
/* offset=128747 */ "read_alloc\000\000cache\000Read allocate mode\000\000\000event=0xc5\000\000\000\000\000\000\000\000\000"
/* offset=128805 */ "read_alloc_enter\000\000cache\000Entering read allocate mode\000\000\000event=0xc4\000\000\000\000\000\000\000\000\000"
/* offset=128878 */ "remote_access\000\000memory\000Access to another socket in a multi-socket system\000\000\000event=0x31\000\000\000\000\000\000\000\000Access to another socket in a multi-socket system\000"
/* offset=129020 */ "remote_access_rd\000\000memory\000Attributable memory read access to another socket in a multi-socket system\000\000\000event=0x38\000\000\000\000\000\000\000\000Attributable memory read access to another socket in a multi-socket system\000"
/* offset=129215 */ "retry_cpu\000hisi_sccl,l3c\000uncore l3c\000Count of the number of retry that L3C suppresses the CPU operations. Unit: hisi_sccl,l3c \000\000\000config=0x40\000\000\000\000\000\000\000\000Count of the number of retry that L3C suppresses the CPU operations\000"
/* offset=129429 */ "retry_ring\000hisi_sccl,l3c\000uncore l3c\000Count of the number of retry that L3C suppresses the ring operations. Unit: hisi_sccl,l3c \000\000\000config=0x41\000\000\000\000\000\000\000\000Count of the number of retry that L3C suppresses the ring operations\000"
/* offset=129646 */ "rnk_chg\000hisi_sccl,ddrc\000uncore ddrc\000DDRC rank commands. Unit: hisi_sccl,ddrc \000\000\000config=0x6\000\000\000\000\000\000\000\000DDRC rank commands\000"
/* offset=129762 */ "rob_empty\000\000other\000This event counts every cycle that no instruction was committed because the CSE is empty\000\000\000event=0x18c\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the CSE is empty\000"
/* offset=129978 */ "rob_empty_stq_busy\000\000other\000This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full\000\000\000event=0x18d\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full\000"
/* offset=130267 */ "rw_chg\000hisi_sccl,ddrc\000uncore ddrc\000DDRC read and write changes. Unit: hisi_sccl,ddrc \000\000\000config=0x7\000\000\000\000\000\000\000\000DDRC read and write changes\000"
/* offset=130400 */ "rx_ccix\000hisi_sccl,hha\000uncore hha\000Count of the number of operations that HHA has received from CCIX. Unit: hisi_sccl,hha \000\000\000config=0x3\000\000\000\000\000\000\000\000Count of the number of operations that HHA has received from CCIX\000"
/* offset=130607 */ "rx_ops_num\000hisi_sccl,hha\000uncore hha\000The number of all operations received by the HHA. Unit: hisi_sccl,hha \000\000\000config=0\000\000\000\000\000\000\000\000The number of all operations received by the HHA\000"
/* offset=130781 */ "rx_outer\000hisi_sccl,hha\000uncore hha\000The number of all operations received by the HHA from another socket. Unit: hisi_sccl,hha \000\000\000config=0x1\000\000\000\000\000\000\000\000The number of all operations received by the HHA from another socket\000"
/* offset=130995 */ "rx_sccl\000hisi_sccl,hha\000uncore hha\000The number of all operations received by the HHA from another SCCL in this socket. Unit: hisi_sccl,hha \000\000\000config=0x2\000\000\000\000\000\000\000\000The number of all operations received by the HHA from another SCCL in this socket\000"
/* offset=131234 */ "rx_snprsp_outer\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x3c\000\000\000\000\000\000\000\000\000"
/* offset=131318 */ "rx_snprspdata\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x38\000\000\000\000\000\000\000\000\000"
/* offset=131400 */ "rx_wbi\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x4\000\000\000\000\000\000\000\000\000"
/* offset=131474 */ "rx_wbip\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x5\000\000\000\000\000\000\000\000\000"
/* offset=131549 */ "rx_wtistash\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x11\000\000\000\000\000\000\000\000\000"
/* offset=131629 */ "sample_collision\000\000spe\000Sample collided with previous sample\000\000\000event=0x4003\000\000\000\000\000\000\000\000Sample collided with previous sample\000"
/* offset=131747 */ "sample_feed\000\000spe\000Sample Taken\000\000\000event=0x4001\000\000\000\000\000\000\000\000Sample Taken\000"
/* offset=131812 */ "sample_filtrate\000\000spe\000Sample Taken and not removed by filtering\000\000\000event=0x4002\000\000\000\000\000\000\000\000Sample Taken and not removed by filtering\000"
/* offset=131939 */ "sample_pop\000\000spe\000Sample Population\000\000\000event=0x4000\000\000\000\000\000\000\000\000Sample Population\000"
/* offset=132013 */ "sdir-hit\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x42\000\000\000\000\000\000\000\000\000"
/* offset=132090 */ "sdir-home-migrate\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x4c\000\000\000\000\000\000\000\000\000"
/* offset=132176 */ "sdir-lookup\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x40\000\000\000\000\000\000\000\000\000"
/* offset=132256 */ "segment_reg_loads.any\000\000other\000Number of segment register loads\000\000\000event=0x6,period=200000,umask=0x80\000\000\000\000\000\000\000\000\000"
/* offset=132363 */ "simd_dep_stall\000\000pipeline\000Cycles there is an interlock for an Advanced SIMD/Floating-point operation\000\000\000event=0xe6\000\000\000\000\000\000\000\000\000"
/* offset=132484 */ "simd_inst_retired\000\000sve\000SIMD Instruction architecturally executed\000\000\000event=0x8000\000\000\000\000\000\000\000\000SIMD Instruction architecturally executed\000"
/* offset=132613 */ "single_movprfx_commit\000\000other\000This event counts every cycle that only the MOVPRFX instruction is committed\000\000\000event=0x199\000\000\000\000\000\000\000\000This event counts every cycle that only the MOVPRFX instruction is committed\000"
/* offset=132817 */ "spill_num\000hisi_sccl,hha\000uncore hha\000Count of the number of spill operations that the HHA has sent. Unit: hisi_sccl,hha \000\000\000config=0x20\000\000\000\000\000\000\000\000Count of the number of spill operations that the HHA has sent\000"
/* offset=133019 */ "spill_success\000hisi_sccl,hha\000uncore hha\000Count of the number of successful spill operations that the HHA has sent. Unit: hisi_sccl,hha \000\000\000config=0x21\000\000\000\000\000\000\000\000Count of the number of successful spill operations that the HHA has sent\000"
/* offset=133247 */ "st_align_lat\000\000memory\000Store with additional latency from alignment\000\000\000event=0x4022\000\000\000\000\000\000\000\000Store with additional latency from alignment\000"
/* offset=133380 */ "st_dep_stall\000\000pipeline\000Cycles there is a stall in the Wr stage because of a store\000\000\000event=0xe8\000\000\000\000\000\000\000\000\000"
/* offset=133483 */ "st_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, store\000\000\000event=0x7\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, store\000"
/* offset=133668 */ "st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000"
/* offset=133789 */ "stall\000\000pipeline\000No operation sent for execution\000\000\000event=0x3c\000\000\000\000\000\000\000\000No operation sent for execution.  The counter counts every attributable cycle on which no attributable instruction or operation was sent for execution on this processing element\000"
/* offset=134035 */ "stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000No operation issued due to the backend\000"
/* offset=134157 */ "stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000The counter counts on any cycle fetched instructions are not dispatched due to resource constraints\000"
/* offset=134340 */ "stall_backend_ilock\000\000pipeline\000No operation issued due to the backend interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded\000\000\000event=0xe4\000\000\000\000\000\000\000\000No operation issued due to the backend interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded\000"
/* offset=134804 */ "stall_backend_ilock\000\000pipeline\000No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded\000\000\000event=0xe4\000\000\000\000\000\000\000\000No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded\000"
/* offset=135266 */ "stall_backend_ilock_addr\000\000pipeline\000No operation issued due to the backend, address interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock on an address operand. This type of interlock is caused by a load/store instruction waiting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded\000\000\000event=0xe5\000\000\000\000\000\000\000\000No operation issued due to the backend, address interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock on an address operand. This type of interlock is caused by a load/store instruction waiting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded\000"
/* offset=136005 */ "stall_backend_ilock_agu\000\000pipeline\000No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded\000\000\000event=0xe5\000\000\000\000\000\000\000\000No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded\000"
/* offset=136669 */ "stall_backend_ilock_fpu\000\000pipeline\000No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded\000\000\000event=0xe6\000\000\000\000\000\000\000\000No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded\000"
/* offset=137245 */ "stall_backend_ilock_vpu\000\000pipeline\000No operation issued due to the backend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an interlock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded\000\000\000event=0xe6\000\000\000\000\000\000\000\000No operation issued due to the backend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an interlock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded\000"
/* offset=137801 */ "stall_backend_ld\000\000pipeline\000No operation issued due to the backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load\000\000\000event=0xe7\000\000\000\000\000\000\000\000No operation issued due to the backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load\000"
/* offset=138106 */ "stall_backend_ld\000\000pipeline\000No operation issued due to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load\000\000\000event=0xe7\000\000\000\000\000\000\000\000No operation issued due to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load\000"
/* offset=138397 */ "stall_backend_ld_cache\000\000pipeline\000No operation issued due to the backend, load, cache miss. This event counts every cycle where there is a stall in the Wr stage due to a load that is waiting on data. The event counts for stalls that are caused by missing the cache or where the data is Non-cacheable\000\000\000event=0xe9\000\000\000\000\000\000\000\000No operation issued due to the backend, load, cache miss. This event counts every cycle where there is a stall in the Wr stage due to a load that is waiting on data. The event counts for stalls that are caused by missing the cache or where the data is Non-cacheable\000"
/* offset=138982 */ "stall_backend_ld_cache\000\000pipeline\000No operation issued due to the backend, load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)\000\000\000event=0xe9\000\000\000\000\000\000\000\000No operation issued due to the backend, load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)\000"
/* offset=139453 */ "stall_backend_ld_tlb\000\000pipeline\000No operation issued due to the backend, load, TLB miss. This event counts every cycle where there is a stall in the Wr stage due to a load that misses in the L1 TLB\000\000\000event=0xea\000\000\000\000\000\000\000\000No operation issued due to the backend, load, TLB miss. This event counts every cycle where there is a stall in the Wr stage due to a load that misses in the L1 TLB\000"
/* offset=139834 */ "stall_backend_ld_tlb\000\000pipeline\000No operation issued due to the backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load which has missed in the L1 TLB\000\000\000event=0xea\000\000\000\000\000\000\000\000No operation issued due to the backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load which has missed in the L1 TLB\000"
/* offset=140211 */ "stall_backend_mem\000\000pipeline\000Memory stall cycles\000\000\000event=0x4005\000\000\000\000\000\000\000\000Memory stall cycles.  The counter counts each cycle counted by STALL_BACKEND where there is a cache miss in the last level of cache within the processing element clock domain\000"
/* offset=140456 */ "stall_backend_st\000\000pipeline\000No operation issued due to the backend, store. This event counts every cycle where there is a stall in the Wr stage due to a store\000\000\000event=0xe8\000\000\000\000\000\000\000\000No operation issued due to the backend, store. This event counts every cycle where there is a stall in the Wr stage due to a store\000"
/* offset=140765 */ "stall_backend_st\000\000pipeline\000No operation issued due to the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store\000\000\000event=0xe8\000\000\000\000\000\000\000\000No operation issued due to the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store\000"
/* offset=141060 */ "stall_backend_st_stb\000\000pipeline\000No operation issued due to the backend, store, STB full.This event counts every cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full\000\000\000event=0xeb\000\000\000\000\000\000\000\000No operation issued due to the backend, store, STB full.This event counts every cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full\000"
/* offset=141465 */ "stall_backend_st_stb\000\000pipeline\000No operation issued due to the backend, store, Store Buffer (STB) full. This event counts every cycle where there is a stall in the Wr stage because of a store operation that is waiting due to the STB being full\000\000\000event=0xeb\000\000\000\000\000\000\000\000No operation issued due to the backend, store, Store Buffer (STB) full. This event counts every cycle where there is a stall in the Wr stage because of a store operation that is waiting due to the STB being full\000"
/* offset=141940 */ "stall_backend_st_tlb\000\000pipeline\000No operation issued due to the backend, store, TLB miss. This event counts every cycle where there is a stall in the Wr stage because of a store operation that has missed in the L1 TLB\000\000\000event=0xec\000\000\000\000\000\000\000\000No operation issued due to the backend, store, TLB miss. This event counts every cycle where there is a stall in the Wr stage because of a store operation that has missed in the L1 TLB\000"
/* offset=142361 */ "stall_backend_st_tlb\000\000pipeline\000No operation issued due to the backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a store which has missed in the L1 TLB\000\000\000event=0xec\000\000\000\000\000\000\000\000No operation issued due to the backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a store which has missed in the L1 TLB\000"
/* offset=142742 */ "stall_backend_vpu_hazard\000\000pipeline\000No operation issued due to the backend, VPU hazard. This event counts every cycle where the core stalls due to contention for the VPU with the other core\000\000\000event=0xed\000\000\000\000\000\000\000\000No operation issued due to the backend, VPU hazard. This event counts every cycle where the core stalls due to contention for the VPU with the other core\000"
/* offset=143105 */ "stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000No operation issued because of the frontend\000"
/* offset=143238 */ "stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000The counter counts on any cycle when there are no fetched instructions available to dispatch\000"
/* offset=143420 */ "stall_frontend_cache\000\000pipeline\000No operation issued due to the frontend, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue is empty and there is an instruction cache miss being processed\000\000\000event=0xe1\000\000\000\000\000\000\000\000No operation issued due to the frontend, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue is empty and there is an instruction cache miss being processed\000"
/* offset=143873 */ "stall_frontend_cache\000\000pipeline\000No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed\000\000\000event=0xe1\000\000\000\000\000\000\000\000No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed\000"
/* offset=144238 */ "stall_frontend_pderr\000\000pipeline\000No operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed\000\000\000event=0xe3\000\000\000\000\000\000\000\000No operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed\000"
/* offset=144601 */ "stall_frontend_pderr\000\000pipeline\000No operation issued due to the frontend, pre-decode error\000\000\000event=0xe3\000\000\000\000\000\000\000\000No operation issued due to the frontend, pre-decode error\000"
/* offset=144768 */ "stall_frontend_tlb\000\000pipeline\000No operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty and there is an instruction L1 TLB miss being processed\000\000\000event=0xe2\000\000\000\000\000\000\000\000No operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty and there is an instruction L1 TLB miss being processed\000"
/* offset=145171 */ "stall_frontend_tlb\000\000pipeline\000No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed\000\000\000event=0xe2\000\000\000\000\000\000\000\000No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed\000"
/* offset=145532 */ "stall_sb_full\000\000pipeline\000Data Write operation that stalls the pipeline because the store buffer is full\000\000\000event=0xc7\000\000\000\000\000\000\000\000\000"
/* offset=145656 */ "stall_slot\000\000pipeline\000No operation sent for execution on a slot\000\000\000event=0x3f\000\000\000\000\000\000\000\000No operation sent for execution on a slot.  The counter counts on each attributable cycle the number of instruction or operation slots that were not occupied by an instruction or operation attributable to the processing element\000"
/* offset=145967 */ "stall_slot_backend\000\000pipeline\000No operation sent for execution on a slot due to the backend\000\000\000event=0x3d\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the backend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because the backend is unable to accept it\000"
/* offset=146292 */ "stall_slot_backend_ilock\000\000pipeline\000Issue slot not issued due to interlock. For each cycle, this event counts each dispatch slot that does not issue due to an interlock\000\000\000event=0xee\000\000\000\000\000\000\000\000Issue slot not issued due to interlock. For each cycle, this event counts each dispatch slot that does not issue due to an interlock\000"
/* offset=146613 */ "stall_slot_frontend\000\000pipeline\000No operation sent for execution on a slot due to the frontend\000\000\000event=0x3e\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the frontend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because there was no attributable instruction or operation available to issue from the processing element from the frontend for the slot\000"
/* offset=147035 */ "stb_stall\000\000cache\000Merge in the store buffer\000\000\000event=0xc0\000\000\000\000\000\000\000\000Merge in the store buffer\000"
/* offset=147124 */ "strex_fail_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000"
/* offset=147297 */ "strex_fail_spec\000\000intrinsic\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000"
/* offset=147468 */ "strex_pass_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX pass\000\000\000event=0x6d\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX pass\000"
/* offset=147641 */ "strex_pass_spec\000\000intrinsic\000Exclusive operation speculatively executed, STREX or STX pass\000\000\000event=0x6d\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX pass\000"
/* offset=147812 */ "strex_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX\000\000\000event=0x6f\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX\000"
/* offset=147970 */ "strex_spec\000\000intrinsic\000Exclusive operation speculatively executed, STREX or STX\000\000\000event=0x6f\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX\000"
/* offset=148126 */ "sve_inst_retired\000\000instruction\000Instruction architecturally executed, SVE\000\000\000event=0x8002\000\000\000\000\000\000\000\000Instruction architecturally executed, SVE\000"
/* offset=148262 */ "sve_inst_retired\000\000sve\000Instruction architecturally executed, SVE\000\000\000event=0x8002\000\000\000\000\000\000\000\000Instruction architecturally executed, SVE\000"
/* offset=148390 */ "sve_inst_spec\000\000instruction\000SVE operations speculatively executed\000\000\000event=0x8006\000\000\000\000\000\000\000\000SVE operations speculatively executed\000"
/* offset=148515 */ "sve_ld_gather_spec\000\000sve\000SVE gather-load Operations speculatively executed\000\000\000event=0x80ad\000\000\000\000\000\000\000\000SVE gather-load Operations speculatively executed\000"
/* offset=148661 */ "sve_ldff_fault_spec\000\000instruction\000SVE first-fault load operations speculatively executed which set FFR bit to 0\000\000\000event=0x80bd\000\000\000\000\000\000\000\000SVE first-fault load operations speculatively executed which set FFR bit to 0\000"
/* offset=148872 */ "sve_ldff_spec\000\000instruction\000SVE First-fault load Operations speculatively executed\000\000\000event=0x80bc\000\000\000\000\000\000\000\000SVE First-fault load Operations speculatively executed\000"
/* offset=149031 */ "sve_ldff_spec\000\000sve\000SVE First-fault load Operations speculatively executed\000\000\000event=0x80bc\000\000\000\000\000\000\000\000SVE First-fault load Operations speculatively executed\000"
/* offset=149182 */ "sve_ldr_preg_spec\000\000sve\000SVE load predicate register Operations speculatively executed\000\000\000event=0x8095\000\000\000\000\000\000\000\000SVE load predicate register Operations speculatively executed\000"
/* offset=149351 */ "sve_ldr_reg_spec\000\000sve\000SVE unpredicated load register Operations speculatively executed\000\000\000event=0x8091\000\000\000\000\000\000\000\000SVE unpredicated load register Operations speculatively executed\000"
/* offset=149525 */ "sve_math_spec\000\000sve\000SVE Math accelerator Operations speculatively executed\000\000\000event=0x800e\000\000\000\000\000\000\000\000SVE Math accelerator Operations speculatively executed\000"
/* offset=149676 */ "sve_movprfx_spec\000\000sve\000SVE MOVPRFX Operations speculatively executed\000\000\000event=0x807c\000\000\000\000\000\000\000\000SVE MOVPRFX Operations speculatively executed\000"
/* offset=149812 */ "sve_movprfx_u_spec\000\000sve\000SVE MOVPRFX unfused Operations speculatively executed\000\000\000event=0x807f\000\000\000\000\000\000\000\000SVE MOVPRFX unfused Operations speculatively executed\000"
/* offset=149966 */ "sve_pred_empty_spec\000\000instruction\000SVE predicated operations with no active predicates speculatively executed\000\000\000event=0x8075\000\000\000\000\000\000\000\000SVE predicated operations with no active predicates speculatively executed\000"
/* offset=150171 */ "sve_pred_full_spec\000\000instruction\000SVE predicated operations speculatively executed with all active predicates\000\000\000event=0x8076\000\000\000\000\000\000\000\000SVE predicated operations speculatively executed with all active predicates\000"
/* offset=150377 */ "sve_pred_not_full_spec\000\000instruction\000SVE predicated operations with empty or partially active predicates\000\000\000event=0x8079\000\000\000\000\000\000\000\000SVE predicated operations with empty or partially active predicates\000"
/* offset=150571 */ "sve_pred_partial_spec\000\000instruction\000SVE predicated operations speculatively executed with partially active predicates\000\000\000event=0x8077\000\000\000\000\000\000\000\000SVE predicated operations speculatively executed with partially active predicates\000"
/* offset=150792 */ "sve_pred_spec\000\000instruction\000SVE predicated Operations speculatively executed\000\000\000event=0x8074\000\000\000\000\000\000\000\000SVE predicated Operations speculatively executed\000"
/* offset=150939 */ "sve_pred_spec\000\000sve\000SVE predicated Operations speculatively executed\000\000\000event=0x8074\000\000\000\000\000\000\000\000SVE predicated Operations speculatively executed\000"
/* offset=151078 */ "sve_prf_contig_spec\000\000sve\000SVE contiguous prefetch element Operations speculatively executed\000\000\000event=0x809f\000\000\000\000\000\000\000\000SVE contiguous prefetch element Operations speculatively executed\000"
/* offset=151257 */ "sve_prf_gather_spec\000\000sve\000SVE gather-prefetch Operations speculatively executed\000\000\000event=0x80af\000\000\000\000\000\000\000\000SVE gather-prefetch Operations speculatively executed\000"
/* offset=151412 */ "sve_st_scatter_spec\000\000sve\000SVE scatter-store Operations speculatively executed\000\000\000event=0x80ae\000\000\000\000\000\000\000\000SVE scatter-store Operations speculatively executed\000"
/* offset=151563 */ "sve_str_preg_spec\000\000sve\000SVE store predicate register Operations speculatively executed\000\000\000event=0x8096\000\000\000\000\000\000\000\000SVE store predicate register Operations speculatively executed\000"
/* offset=151734 */ "sve_str_reg_spec\000\000sve\000SVE unpredicated store register Operations speculatively executed\000\000\000event=0x8092\000\000\000\000\000\000\000\000SVE unpredicated store register Operations speculatively executed\000"
/* offset=151910 */ "sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000"
/* offset=152116 */ "sw_incr\000\000instruction\000Software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, software increment\000"
/* offset=152230 */ "sx_stall\000\000pipeline\000SX stalled\000\000\000event=0x10e\000\000\000\000\000\000\000\000SX Op non-issue\000"
/* offset=152297 */ "sys_ccn_pmu.read_cycles\000uncore_sys_ccn_pmu\000uncore\000ccn read-cycles event. Unit: uncore_sys_ccn_pmu \000\000\000config=0x2c\000\0000x01\000\000\000\000\000\000\000"
/* offset=152422 */ "sys_ddr_pmu.write_cycles\000uncore_sys_ddr_pmu\000uncore\000ddr write-cycles event. Unit: uncore_sys_ddr_pmu \000\000\000event=0x2b\000\000v8\000\000\000\000\000\000\000"
/* offset=152546 */ "tlb_access\000\000cache\000Level 2 TLB access\000\000\000event=0xea\000\000\000\000\000\000\000\000Level 2 TLB access\000"
/* offset=152622 */ "tlb_err\000\000other\000TLB memory error\000\000\000event=0xd2\000\000\000\000\000\000\000\000\000"
/* offset=152675 */ "tlb_l2tlb_l2walk_access\000\000cache\000Level 2 TLB level-2 walk cache access. This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled\000\000\000event=0xcc\000\000\000\000\000\000\000\000Level 2 TLB level-2 walk cache access. This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled\000"
/* offset=153280 */ "tlb_l2tlb_l2walk_refill\000\000cache\000Level 2 TLB level-2 walk cache refill. This event does not count if the MMU is disabled\000\000\000event=0xcd\000\000\000\000\000\000\000\000Level 2 TLB level-2 walk cache refill. This event does not count if the MMU is disabled\000"
/* offset=153507 */ "tlb_l2tlb_llwalk_access\000\000cache\000Level 2 TLB last-level walk cache access. This event does not count if the MMU is disabled\000\000\000event=0xca\000\000\000\000\000\000\000\000Level 2 TLB last-level walk cache access. This event does not count if the MMU is disabled\000"
/* offset=153740 */ "tlb_l2tlb_llwalk_refill\000\000cache\000Level 2 TLB last-level walk cache refill. This event does not count if the MMU is disabled\000\000\000event=0xcb\000\000\000\000\000\000\000\000Level 2 TLB last-level walk cache refill. This event does not count if the MMU is disabled\000"
/* offset=153973 */ "tlb_l2tlb_s2_access\000\000cache\000Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count\000\000\000event=0xce\000\000\000\000\000\000\000\000Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count\000"
/* offset=154516 */ "tlb_l2tlb_s2_refill\000\000cache\000Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count\000\000\000event=0xcf\000\000\000\000\000\000\000\000Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count\000"
/* offset=155103 */ "tlb_miss\000\000cache\000Level 2 TLB miss\000\000\000event=0xeb\000\000\000\000\000\000\000\000Level 2 TLB miss\000"
/* offset=155173 */ "trb_trig\000\000trace\000Trace buffer Trigger Event\000\000\000event=0x400e\000\000\000\000\000\000\000\000Trace buffer Trigger Event\000"
/* offset=155265 */ "trb_wrap\000\000trace\000Trace buffer current write pointer wrapped\000\000\000event=0x400c\000\000\000\000\000\000\000\000Trace buffer current write pointer wrapped\000"
/* offset=155389 */ "trcextout0\000\000trace\000PE Trace Unit external output 0\000\000\000event=0x4010\000\000\000\000\000\000\000\000PE Trace Unit external output 0\000"
/* offset=155493 */ "trcextout1\000\000trace\000PE Trace Unit external output 1\000\000\000event=0x4011\000\000\000\000\000\000\000\000PE Trace Unit external output 1\000"
/* offset=155597 */ "trcextout2\000\000trace\000PE Trace Unit external output 2\000\000\000event=0x4012\000\000\000\000\000\000\000\000PE Trace Unit external output 2\000"
/* offset=155701 */ "trcextout3\000\000trace\000PE Trace Unit external output 3\000\000\000event=0x4013\000\000\000\000\000\000\000\000PE Trace Unit external output 3\000"
/* offset=155805 */ "ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000"
/* offset=156015 */ "ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state\000"
/* offset=156249 */ "tx_snp_ccix\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x35\000\000\000\000\000\000\000\000\000"
/* offset=156329 */ "tx_snp_num\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x33\000\000\000\000\000\000\000\000\000"
/* offset=156408 */ "tx_snp_outer\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x34\000\000\000\000\000\000\000\000\000"
/* offset=156489 */ "unaligned_ld_spec\000\000core imp def\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000"
/* offset=156587 */ "unaligned_ld_spec\000\000memory\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000"
/* offset=156679 */ "unaligned_ldst_retired\000\000memory\000Instruction architecturally executed, condition code check pass, unaligned\000\000\000event=0xf\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, unaligned\000"
/* offset=156879 */ "unaligned_ldst_spec\000\000core imp def\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000"
/* offset=156967 */ "unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000"
/* offset=157049 */ "unaligned_st_spec\000\000core imp def\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000"
/* offset=157149 */ "unaligned_st_spec\000\000memory\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000"
/* offset=157243 */ "unc_cbo_xsnp_response.miss_eviction\000uncore_cbox\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core. Unit: uncore_cbox \000\000\000event=0x22,umask=0x81\000\000\000\000\000\000\000\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000"
/* offset=157511 */ "uncore_hisi_ddrc.flux_wcmd\000hisi_sccl,ddrc\000uncore\000DDRC write commands. Unit: hisi_sccl,ddrc \000\000\000event=0x2\000\000\000\000\000\000\000\000DDRC write commands\000"
/* offset=157642 */ "uncore_hisi_l3c.rd_hit_cpipe\000hisi_sccl,l3c\000uncore\000Total read hits. Unit: hisi_sccl,l3c \000\000\000event=0x7\000\000\000\000\000\000\000\000Total read hits\000"
/* offset=157765 */ "uncore_imc.cache_hits\000uncore_imc\000uncore\000Total cache hits. Unit: uncore_imc \000\000\000event=0x34\000\000\000\000\000\000\000\000Total cache hits\000"
/* offset=157878 */ "uncore_imc_free_running.cache_miss\000uncore_imc_free_running\000uncore\000Total cache misses. Unit: uncore_imc_free_running \000\000\000event=0x12\000\000\000\000\000\000\000\000Total cache misses\000"
/* offset=158034 */ "uop_only_commit\000\000other\000This event counts every cycle that only any micro-operations are committed\000\000\000event=0x198\000\000\000\000\000\000\000\000This event counts every cycle that only any micro-operations are committed\000"
/* offset=158228 */ "uop_spec\000\000sve\000Microarchitectural operation, Operations speculatively executed\000\000\000event=0x8008\000\000\000\000\000\000\000\000Microarchitectural operation, Operations speculatively executed\000"
/* offset=158392 */ "uop_split\000\000other\000This event counts the occurrence count of the micro-operation split\000\000\000event=0x139\000\000\000\000\000\000\000\000This event counts the occurrence count of the micro-operation split\000"
/* offset=158566 */ "utlb_flush\000\000cache\000Level 1 TLB flush\000\000\000event=0xe9\000\000\000\000\000\000\000\000Level 1 TLB flush\000"
/* offset=158640 */ "vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000"
/* offset=158804 */ "victim_num\000hisi_sccl,l3c\000uncore l3c\000l3c precharge commands. Unit: hisi_sccl,l3c \000\000\000config=0x4\000\000\000\000\000\000\000\000l3c precharge commands\000"
/* offset=158928 */ "wait_cycles\000\000clock\000Wait state cycle\000\000\000event=0x110\000\000\000\000\000\000\000\000Wait state cycle\000"
/* offset=159002 */ "wfe_wfi_cycle\000\000other\000This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction\000\000\000event=0x18e\000\000\000\000\000\000\000\000This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction\000"
/* offset=159230 */ "wr_cpipe\000hisi_sccl,l3c\000uncore l3c\000Total write accesses. Unit: hisi_sccl,l3c \000\000\000config=0x1\000\000\000\000\000\000\000\000Total write accesses\000"
/* offset=159348 */ "wr_ddr_128b\000hisi_sccl,hha\000uncore hha\000The number of write operations sent by HHA to DDRC which size is 128 bytes. Unit: hisi_sccl,hha \000\000\000config=0x1f\000\000\000\000\000\000\000\000The number of write operations sent by HHA to DDRC which size is 128 bytes\000"
/* offset=159578 */ "wr_ddr_64b\000hisi_sccl,hha\000uncore hha\000The number of write operations sent by HHA to DDRC which size is 64 bytes. Unit: hisi_sccl,hha \000\000\000config=0x1d\000\000\000\000\000\000\000\000The number of write operations sent by HHA to DDRC which size is 64 bytes\000"
/* offset=159805 */ "wr_hit_cpipe\000hisi_sccl,l3c\000uncore l3c\000Total write hits. Unit: hisi_sccl,l3c \000\000\000config=0x3\000\000\000\000\000\000\000\000Total write hits\000"
/* offset=159919 */ "wr_hit_spipe\000hisi_sccl,l3c\000uncore l3c\000Count of the number of write lines that hits in spipe of this L3C. Unit: hisi_sccl,l3c \000\000\000config=0x23\000\000\000\000\000\000\000\000Count of the number of write lines that hits in spipe of this L3C\000"
/* offset=160132 */ "wr_spipe\000hisi_sccl,l3c\000uncore l3c\000Count of the number of write lines that come from this cluster of CPU core in spipe. Unit: hisi_sccl,l3c \000\000\000config=0x21\000\000\000\000\000\000\000\000Count of the number of write lines that come from this cluster of CPU core in spipe\000"
;

static const struct compact_pmu_event pme_hisilicon_hip09_sys[] = {
{ 6336 }, /* \000hisi_sicl,cpa\000uncore cpa\000Average bandwidth of CPA Port 0. Unit: hisi_sicl,cpa \000cpa_p0_avg_bw\000CPA\000\000\0000x00000030\000\000\000\000\000(cpa_p0_wr_dat * 64 + cpa_p0_rd_dat_64b * 64 + cpa_p0_rd_dat_32b * 32) / cpa_cycles\000\000 */
{ 6536 }, /* \000hisi_sicl,cpa\000uncore cpa\000Average bandwidth of CPA Port 1. Unit: hisi_sicl,cpa \000cpa_p1_avg_bw\000CPA\000\000\0000x00000030\000\000\000\000\000(cpa_p1_wr_dat * 64 + cpa_p1_rd_dat_64b * 64 + cpa_p1_rd_dat_32b * 32) / cpa_cycles\000\000 */
{ 39445 }, /* cpa_cycles\000hisi_sicl,cpa\000uncore cpa\000count of CPA cycles. Unit: hisi_sicl,cpa \000\000\000config=0\000\0000x00000030\000\000\000\000\000\000\000 */
{ 39552 }, /* cpa_p0_rd_dat\000hisi_sicl,cpa\000uncore cpa\000Number of read ops transmitted by the P0 port. Unit: hisi_sicl,cpa \000\000\000config=0xe2\000\0000x00000030\000\000\000\000\000\000\000 */
{ 39691 }, /* cpa_p0_rd_dat_32b\000hisi_sicl,cpa\000uncore cpa\000Number of read ops transmitted by the P0 port which size is 32 bytes. Unit: hisi_sicl,cpa \000\000\000config=0x84\000\0000x00000030\000\000\000\000\000\000\000 */
{ 39857 }, /* cpa_p0_rd_dat_64b\000hisi_sicl,cpa\000uncore cpa\000Number of read ops transmitted by the P0 port which size is 64 bytes. Unit: hisi_sicl,cpa \000\000\000config=0x83\000\0000x00000030\000\000\000\000\000\000\000 */
{ 40023 }, /* cpa_p0_wr_dat\000hisi_sicl,cpa\000uncore cpa\000Number of write ops transmitted by the P0 port. Unit: hisi_sicl,cpa \000\000\000config=0xe1\000\0000x00000030\000\000\000\000\000\000\000 */
{ 40163 }, /* cpa_p1_rd_dat\000hisi_sicl,cpa\000uncore cpa\000Number of read ops transmitted by the P1 port. Unit: hisi_sicl,cpa \000\000\000config=0x62\000\0000x00000030\000\000\000\000\000\000\000 */
{ 40302 }, /* cpa_p1_rd_dat_32b\000hisi_sicl,cpa\000uncore cpa\000Number of read ops transmitted by the P1 port which size is 32 bytes. Unit: hisi_sicl,cpa \000\000\000config=0x4\000\0000x00000030\000\000\000\000\000\000\000 */
{ 40467 }, /* cpa_p1_rd_dat_64b\000hisi_sicl,cpa\000uncore cpa\000Number of read ops transmitted by the P1 port which size is 64 bytes. Unit: hisi_sicl,cpa \000\000\000config=0x3\000\0000x00000030\000\000\000\000\000\000\000 */
{ 40632 }, /* cpa_p1_wr_dat\000hisi_sicl,cpa\000uncore cpa\000Number of write ops transmitted by the P1 port. Unit: hisi_sicl,cpa \000\000\000config=0x61\000\0000x00000030\000\000\000\000\000\000\000 */
};

static const struct compact_pmu_event pme_hisilicon_hip08[] = {
{ 52764 }, /* exe_stall_cycle\000\000core imp def\000Cycles of that the number of issue ups are less than 4\000\000\000event=0x7001\000\000\000\000\000\000\000\000Cycles of that the number of issuing micro operations are less than 4\000 */
{ 53173 }, /* fetch_bubble\000\000core imp def\000Instructions can receive, but not send\000\000\000event=0x2014\000\000\000\000\000\000\000\000Instructions can receive, but not send\000 */
{ 59110 }, /* hit_on_prf\000\000core imp def\000Hit on prefetched data\000\000\000event=0x6014\000\000\000\000\000\000\000\000Hit on prefetched data\000 */
{ 59974 }, /* if_is_stall\000\000core imp def\000Instruction fetch stall cycles\000\000\000event=0x1044\000\000\000\000\000\000\000\000Instruction fetch stall cycles\000 */
{ 65838 }, /* iq_is_empty\000\000core imp def\000Instruction queue is empty\000\000\000event=0x1043\000\000\000\000\000\000\000\000Instruction queue is empty\000 */
{ 72116 }, /* l1d_cache_inval\000\000core imp def\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000 */
{ 72862 }, /* l1d_cache_rd\000\000core imp def\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 75126 }, /* l1d_cache_refill_rd\000\000core imp def\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75365 }, /* l1d_cache_refill_wr\000\000core imp def\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 76010 }, /* l1d_cache_wb_clean\000\000core imp def\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000 */
{ 76289 }, /* l1d_cache_wb_victim\000\000core imp def\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000 */
{ 76533 }, /* l1d_cache_wr\000\000core imp def\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 77616 }, /* l1d_tlb_rd\000\000core imp def\000L1D tlb access, read\000\000\000event=0x4e\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, read\000 */
{ 78160 }, /* l1d_tlb_refill_rd\000\000core imp def\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000 */
{ 78387 }, /* l1d_tlb_refill_wr\000\000core imp def\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000 */
{ 78620 }, /* l1d_tlb_wr\000\000core imp def\000L1D tlb access, write\000\000\000event=0x4f\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, write\000 */
{ 82249 }, /* l1i_cache_prf\000\000core imp def\000L1I cache prefetch access count\000\000\000event=0x102e\000\000\000\000\000\000\000\000Level 1 instruction cache prefetch access count\000 */
{ 82379 }, /* l1i_cache_prf_refill\000\000core imp def\000L1I cache miss due to prefetch access count\000\000\000event=0x102f\000\000\000\000\000\000\000\000Level 1 instruction cache miss due to prefetch access count\000 */
{ 89327 }, /* l2d_cache_inval\000\000core imp def\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000 */
{ 90499 }, /* l2d_cache_rd\000\000core imp def\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 93165 }, /* l2d_cache_refill_rd\000\000core imp def\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93404 }, /* l2d_cache_refill_wr\000\000core imp def\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 97247 }, /* l2d_cache_wb_clean\000\000core imp def\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000 */
{ 97526 }, /* l2d_cache_wb_victim\000\000core imp def\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000 */
{ 97770 }, /* l2d_cache_wr\000\000core imp def\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 119249 }, /* mem_stall_anyload\000\000core imp def\000No any micro operation is issued and meanwhile any load operation is not resolved\000\000\000event=0x7004\000\000\000\000\000\000\000\000No any micro operation is issued and meanwhile any load operation is not resolved\000 */
{ 119467 }, /* mem_stall_l1miss\000\000core imp def\000No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill\000\000\000event=0x7006\000\000\000\000\000\000\000\000No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill\000 */
{ 119752 }, /* mem_stall_l2miss\000\000core imp def\000No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache\000\000\000event=0x7007\000\000\000\000\000\000\000\000No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache\000 */
{ 126750 }, /* prf_req\000\000core imp def\000Prefetch request from LSU\000\000\000event=0x6013\000\000\000\000\000\000\000\000Prefetch request from LSU\000 */
{ 136 }, /* \000\000metrics\000Backend Bound L1 topdown metric\000backend_bound\000TopDownL1\000\000\000\000\000\000\000\0001 - (frontend_bound + bad_speculation + retiring)\000Backend Bound L1 topdown metric\000 */
{ 291 }, /* \000\000metrics\000Bad Speculation L1 topdown metric\000bad_speculation\000TopDownL1\000\000\000\000\000\000\000\000(INST_SPEC - INST_RETIRED) / (4 * CPU_CYCLES)\000Bad Speculation L1 topdown metric\000 */
{ 0 }, /* \000\000metrics\000BP misp flush L3 topdown metric\000bp_misp_flush\000TopDownL3\000\000\000\000\000\000\000\000(BR_MIS_PRED * 5) / CPU_CYCLES\000BP misp flush L3 topdown metric\000 */
{ 448 }, /* \000\000metrics\000Branch mispredicts L2 topdown metric\000branch_mispredicts\000TopDownL2\000\000\000\000\000\000\000\000(bad_speculation * BR_MIS_PRED) / (BR_MIS_PRED + armv8_pmuv3_0@event\\=0x2013@)\000Branch mispredicts L2 topdown metric\000 */
{ 647 }, /* \000\000metrics\000Core bound L2 topdown metric\000core_bound\000TopDownL2\000\000\000\000\000\000\000\000(EXE_STALL_CYCLE - (MEM_STALL_ANYLOAD + armv8_pmuv3_0@event\\=0x7005@)) / CPU_CYCLES\000Core bound L2 topdown metric\000 */
{ 827 }, /* \000\000metrics\000Divider L3 topdown metric\000divider\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x7002@ / CPU_CYCLES\000Divider L3 topdown metric\000 */
{ 956 }, /* \000\000metrics\000EXE ports util L3 topdown metric\000exe_ports_util\000TopDownL3\000\000\000\000\000\000\000\000core_bound - divider - fsu_stall\000EXE ports util L3 topdown metric\000 */
{ 1232 }, /* \000\000metrics\000Fetch bandwidth bound L2 topdown metric\000fetch_bandwidth_bound\000TopDownL2\000\000\000\000\000\000\000\000frontend_bound - fetch_latency_bound\000Fetch bandwidth bound L2 topdown metric\000 */
{ 1398 }, /* \000\000metrics\000Fetch latency bound L2 topdown metric\000fetch_latency_bound\000TopDownL2\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x201d@ / CPU_CYCLES\000Fetch latency bound L2 topdown metric\000 */
{ 1563 }, /* \000\000metrics\000Frontend bound L1 topdown metric\000frontend_bound\000TopDownL1\000\000\000\000\000\000\000\000FETCH_BUBBLE / (4 * CPU_CYCLES)\000Frontend bound L1 topdown metric\000 */
{ 1097 }, /* \000\000metrics\000FSU stall L3 topdown metric\000fsu_stall\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x7003@ / CPU_CYCLES\000FSU stall L3 topdown metric\000 */
{ 1703 }, /* \000\000metrics\000Idle by icache miss L3 topdown metric\000idle_by_icache_miss\000TopDownL3\000\000\000\000\000\000\000\000(((L2I_CACHE - L2I_CACHE_REFILL) * 15) + (L2I_CACHE_REFILL * 100)) / CPU_CYCLES\000Idle by icache miss L3 topdown metric\000 */
{ 1906 }, /* \000\000metrics\000Idle by itlb miss L3 topdown metric\000idle_by_itlb_miss\000TopDownL3\000\000\000\000\000\000\000\000(((L2I_TLB - L2I_TLB_REFILL) * 15) + (L2I_TLB_REFILL * 100)) / CPU_CYCLES\000Idle by itlb miss L3 topdown metric\000 */
{ 2097 }, /* \000\000metrics\000Indirect branch L3 topdown metric\000indirect_branch\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x1010@ / BR_MIS_PRED\000Indirect branch L3 topdown metric\000 */
{ 2251 }, /* \000\000metrics\000L1 bound L3 topdown metric\000l1_bound\000TopDownL3\000\000\000\000\000\000\000\000(MEM_STALL_ANYLOAD - MEM_STALL_L1MISS) / CPU_CYCLES\000L1 bound L3 topdown metric\000 */
{ 2393 }, /* \000\000metrics\000L2 bound L3 topdown metric\000l2_bound\000TopDownL3\000\000\000\000\000\000\000\000(MEM_STALL_L1MISS - MEM_STALL_L2MISS) / CPU_CYCLES\000L2 bound L3 topdown metric\000 */
{ 2534 }, /* \000\000metrics\000Machine clears L2 topdown metric\000machine_clears\000TopDownL2\000\000\000\000\000\000\000\000bad_speculation - branch_mispredicts\000Machine clears L2 topdown metric\000 */
{ 2679 }, /* \000\000metrics\000Mem bound L3 topdown metric\000mem_bound\000TopDownL3\000\000\000\000\000\000\000\000MEM_STALL_L2MISS / CPU_CYCLES\000Mem bound L3 topdown metric\000 */
{ 2802 }, /* \000\000metrics\000Memory bound L2 topdown metric\000memory_bound\000TopDownL2\000\000\000\000\000\000\000\000(MEM_STALL_ANYLOAD + armv8_pmuv3_0@event\\=0x7005@) / CPU_CYCLES\000Memory bound L2 topdown metric\000 */
{ 2968 }, /* \000\000metrics\000Nuke flush L3 topdown metric\000nuke_flush\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x2012@ / armv8_pmuv3_0@event\\=0x2013@\000Nuke flush L3 topdown metric\000 */
{ 3124 }, /* \000\000metrics\000OOO flush L3 topdown metric\000ooo_flush\000TopDownL3\000\000\000\000\000\000\000\000(armv8_pmuv3_0@event\\=0x2013@ * 5) / CPU_CYCLES\000OOO flush L3 topdown metric\000 */
{ 3265 }, /* \000\000metrics\000Other branch L3 topdown metric\000other_branch\000TopDownL3\000\000\000\000\000\000\000\000(BR_MIS_PRED - armv8_pmuv3_0@event\\=0x1010@ - armv8_pmuv3_0@event\\=0x1013@ - armv8_pmuv3_0@event\\=0x1016@ - armv8_pmuv3_0@event\\=0x100d@) / BR_MIS_PRED\000Other branch L3 topdown metric\000 */
{ 3519 }, /* \000\000metrics\000Other flush L3 topdown metric\000other_flush\000TopDownL3\000\000\000\000\000\000\000\0001 - nuke_flush\000Other flush L3 topdown metric\000 */
{ 3633 }, /* \000\000metrics\000PC buffer stall L3 topdown metric\000pc_buffer_stall\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x2005@ / CPU_CYCLES\000PC buffer stall L3 topdown metric\000 */
{ 3786 }, /* \000\000metrics\000Pop branch L3 topdown metric\000pop_branch\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x100d@ / BR_MIS_PRED\000Pop branch L3 topdown metric\000 */
{ 3925 }, /* \000\000metrics\000Ptag stall L3 topdown metric\000ptag_stall\000TopDownL3\000\000\000\000\000\000\000\000(armv8_pmuv3_0@event\\=0x2006@ + armv8_pmuv3_0@event\\=0x2007@ + armv8_pmuv3_0@event\\=0x2008@) / CPU_CYCLES\000Ptag stall L3 topdown metric\000 */
{ 4127 }, /* \000\000metrics\000Push branch L3 topdown metric\000push_branch\000TopDownL3\000\000\000\000\000\000\000\000(armv8_pmuv3_0@event\\=0x1013@ + armv8_pmuv3_0@event\\=0x1016@) / BR_MIS_PRED\000Push branch L3 topdown metric\000 */
{ 4302 }, /* \000\000metrics\000Retiring L1 topdown metric\000retiring\000TopDownL1\000\000\000\000\000\000\000\000INST_RETIRED / (CPU_CYCLES * 4)\000Retiring L1 topdown metric\000 */
{ 4424 }, /* \000\000metrics\000Rob stall L3 topdown metric\000rob_stall\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x2004@ / CPU_CYCLES\000Rob stall L3 topdown metric\000 */
{ 4559 }, /* \000\000metrics\000SaveOpQ stall L3 topdown metric\000saveopq_stall\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x201e@ / CPU_CYCLES\000SaveOpQ stall L3 topdown metric\000 */
{ 4706 }, /* \000\000metrics\000Static predictor flush L3 topdown metric\000sp_flush\000TopDownL3\000\000\000\000\000\000\000\000(armv8_pmuv3_0@event\\=0x1001@ * 5) / CPU_CYCLES\000Static predictor flush L3 topdown metric\000 */
{ 4872 }, /* \000\000metrics\000Store bound L3 topdown metric\000store_bound\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x7005@ / CPU_CYCLES\000Store bound L3 topdown metric\000 */
{ 5013 }, /* \000\000metrics\000Sync stall L3 topdown metric\000sync_stall\000TopDownL3\000\000\000\000\000\000\000\000armv8_pmuv3_0@event\\=0x2010@ / CPU_CYCLES\000Sync stall L3 topdown metric\000 */
{ 19158 }, /* act_cmd\000hisi_sccl,ddrc\000uncore ddrc\000DDRC active commands. Unit: hisi_sccl,ddrc \000\000\000config=0x5\000\000\000\000\000\000\000\000DDRC active commands\000 */
{ 54589 }, /* flux_rcmd\000hisi_sccl,ddrc\000uncore ddrc\000DDRC read commands. Unit: hisi_sccl,ddrc \000\000\000config=0x3\000\000\000\000\000\000\000\000DDRC read commands\000 */
{ 54707 }, /* flux_rd\000hisi_sccl,ddrc\000uncore ddrc\000DDRC total read operations. Unit: hisi_sccl,ddrc \000\000\000config=0x1\000\000\000\000\000\000\000\000DDRC total read operations\000 */
{ 54839 }, /* flux_wcmd\000hisi_sccl,ddrc\000uncore ddrc\000DDRC write commands. Unit: hisi_sccl,ddrc \000\000\000config=0x2\000\000\000\000\000\000\000\000DDRC write commands\000 */
{ 54959 }, /* flux_wr\000hisi_sccl,ddrc\000uncore ddrc\000DDRC total write operations. Unit: hisi_sccl,ddrc \000\000\000config=0\000\000\000\000\000\000\000\000DDRC total write operations\000 */
{ 125890 }, /* pre_cmd\000hisi_sccl,ddrc\000uncore ddrc\000DDRC precharge commands. Unit: hisi_sccl,ddrc \000\000\000config=0x4\000\000\000\000\000\000\000\000DDRC precharge commands\000 */
{ 129646 }, /* rnk_chg\000hisi_sccl,ddrc\000uncore ddrc\000DDRC rank commands. Unit: hisi_sccl,ddrc \000\000\000config=0x6\000\000\000\000\000\000\000\000DDRC rank commands\000 */
{ 130267 }, /* rw_chg\000hisi_sccl,ddrc\000uncore ddrc\000DDRC read and write changes. Unit: hisi_sccl,ddrc \000\000\000config=0x7\000\000\000\000\000\000\000\000DDRC read and write changes\000 */
{ 22210 }, /* bi_num\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x23\000\000\000\000\000\000\000\000\000 */
{ 46540 }, /* edir-hit\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x43\000\000\000\000\000\000\000\000\000 */
{ 46617 }, /* edir-home-migrate\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x4d\000\000\000\000\000\000\000\000\000 */
{ 46703 }, /* edir-lookup\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x41\000\000\000\000\000\000\000\000\000 */
{ 118178 }, /* mediated_num\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x32\000\000\000\000\000\000\000\000\000 */
{ 127729 }, /* rd_ddr_128b\000hisi_sccl,hha\000uncore hha\000The number of read operations sent by HHA to DDRC which size is 128 bytes. Unit: hisi_sccl,hha \000\000\000config=0x1e\000\000\000\000\000\000\000\000The number of read operations sent by HHA to DDRC which size is 128 bytes\000 */
{ 127957 }, /* rd_ddr_64b\000hisi_sccl,hha\000uncore hha\000The number of read operations sent by HHA to DDRC which size is 64 bytes. Unit: hisi_sccl,hha \000\000\000config=0x1c\000\000\000\000\000\000\000\000The number of read operations sent by HHA to DDRC which size is 64bytes\000 */
{ 130400 }, /* rx_ccix\000hisi_sccl,hha\000uncore hha\000Count of the number of operations that HHA has received from CCIX. Unit: hisi_sccl,hha \000\000\000config=0x3\000\000\000\000\000\000\000\000Count of the number of operations that HHA has received from CCIX\000 */
{ 130607 }, /* rx_ops_num\000hisi_sccl,hha\000uncore hha\000The number of all operations received by the HHA. Unit: hisi_sccl,hha \000\000\000config=0\000\000\000\000\000\000\000\000The number of all operations received by the HHA\000 */
{ 130781 }, /* rx_outer\000hisi_sccl,hha\000uncore hha\000The number of all operations received by the HHA from another socket. Unit: hisi_sccl,hha \000\000\000config=0x1\000\000\000\000\000\000\000\000The number of all operations received by the HHA from another socket\000 */
{ 130995 }, /* rx_sccl\000hisi_sccl,hha\000uncore hha\000The number of all operations received by the HHA from another SCCL in this socket. Unit: hisi_sccl,hha \000\000\000config=0x2\000\000\000\000\000\000\000\000The number of all operations received by the HHA from another SCCL in this socket\000 */
{ 131234 }, /* rx_snprsp_outer\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x3c\000\000\000\000\000\000\000\000\000 */
{ 131318 }, /* rx_snprspdata\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x38\000\000\000\000\000\000\000\000\000 */
{ 131400 }, /* rx_wbi\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x4\000\000\000\000\000\000\000\000\000 */
{ 131474 }, /* rx_wbip\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x5\000\000\000\000\000\000\000\000\000 */
{ 131549 }, /* rx_wtistash\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x11\000\000\000\000\000\000\000\000\000 */
{ 132013 }, /* sdir-hit\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x42\000\000\000\000\000\000\000\000\000 */
{ 132090 }, /* sdir-home-migrate\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x4c\000\000\000\000\000\000\000\000\000 */
{ 132176 }, /* sdir-lookup\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x40\000\000\000\000\000\000\000\000\000 */
{ 132817 }, /* spill_num\000hisi_sccl,hha\000uncore hha\000Count of the number of spill operations that the HHA has sent. Unit: hisi_sccl,hha \000\000\000config=0x20\000\000\000\000\000\000\000\000Count of the number of spill operations that the HHA has sent\000 */
{ 133019 }, /* spill_success\000hisi_sccl,hha\000uncore hha\000Count of the number of successful spill operations that the HHA has sent. Unit: hisi_sccl,hha \000\000\000config=0x21\000\000\000\000\000\000\000\000Count of the number of successful spill operations that the HHA has sent\000 */
{ 156249 }, /* tx_snp_ccix\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x35\000\000\000\000\000\000\000\000\000 */
{ 156329 }, /* tx_snp_num\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x33\000\000\000\000\000\000\000\000\000 */
{ 156408 }, /* tx_snp_outer\000hisi_sccl,hha\000uncore hha\000Unit: hisi_sccl,hha \000\000\000config=0x34\000\000\000\000\000\000\000\000\000 */
{ 159348 }, /* wr_ddr_128b\000hisi_sccl,hha\000uncore hha\000The number of write operations sent by HHA to DDRC which size is 128 bytes. Unit: hisi_sccl,hha \000\000\000config=0x1f\000\000\000\000\000\000\000\000The number of write operations sent by HHA to DDRC which size is 128 bytes\000 */
{ 159578 }, /* wr_ddr_64b\000hisi_sccl,hha\000uncore hha\000The number of write operations sent by HHA to DDRC which size is 64 bytes. Unit: hisi_sccl,hha \000\000\000config=0x1d\000\000\000\000\000\000\000\000The number of write operations sent by HHA to DDRC which size is 64 bytes\000 */
{ 21458 }, /* back_invalid\000hisi_sccl,l3c\000uncore l3c\000Count of the number of L3C back invalid operations. Unit: hisi_sccl,l3c \000\000\000config=0x29\000\000\000\000\000\000\000\000Count of the number of L3C back invalid operations\000 */
{ 126402 }, /* prefetch_drop\000hisi_sccl,l3c\000uncore l3c\000Count of the number of prefetch drops from this L3C. Unit: hisi_sccl,l3c \000\000\000config=0x42\000\000\000\000\000\000\000\000Count of the number of prefetch drops from this L3C\000 */
{ 127615 }, /* rd_cpipe\000hisi_sccl,l3c\000uncore l3c\000Total read accesses. Unit: hisi_sccl,l3c \000\000\000config=0\000\000\000\000\000\000\000\000Total read accesses\000 */
{ 128181 }, /* rd_hit_cpipe\000hisi_sccl,l3c\000uncore l3c\000Total read hits. Unit: hisi_sccl,l3c \000\000\000config=0x2\000\000\000\000\000\000\000\000Total read hits\000 */
{ 128293 }, /* rd_hit_spipe\000hisi_sccl,l3c\000uncore l3c\000Count of the number of read lines that hits in spipe of this L3C. Unit: hisi_sccl,l3c \000\000\000config=0x22\000\000\000\000\000\000\000\000Count of the number of read lines that hits in spipe of this L3C\000 */
{ 128504 }, /* rd_spipe\000hisi_sccl,l3c\000uncore l3c\000Count of the number of read lines that come from this cluster of CPU core in spipe. Unit: hisi_sccl,l3c \000\000\000config=0x20\000\000\000\000\000\000\000\000Count of the number of read lines that come from this cluster of CPU core in spipe\000 */
{ 129215 }, /* retry_cpu\000hisi_sccl,l3c\000uncore l3c\000Count of the number of retry that L3C suppresses the CPU operations. Unit: hisi_sccl,l3c \000\000\000config=0x40\000\000\000\000\000\000\000\000Count of the number of retry that L3C suppresses the CPU operations\000 */
{ 129429 }, /* retry_ring\000hisi_sccl,l3c\000uncore l3c\000Count of the number of retry that L3C suppresses the ring operations. Unit: hisi_sccl,l3c \000\000\000config=0x41\000\000\000\000\000\000\000\000Count of the number of retry that L3C suppresses the ring operations\000 */
{ 158804 }, /* victim_num\000hisi_sccl,l3c\000uncore l3c\000l3c precharge commands. Unit: hisi_sccl,l3c \000\000\000config=0x4\000\000\000\000\000\000\000\000l3c precharge commands\000 */
{ 159230 }, /* wr_cpipe\000hisi_sccl,l3c\000uncore l3c\000Total write accesses. Unit: hisi_sccl,l3c \000\000\000config=0x1\000\000\000\000\000\000\000\000Total write accesses\000 */
{ 159805 }, /* wr_hit_cpipe\000hisi_sccl,l3c\000uncore l3c\000Total write hits. Unit: hisi_sccl,l3c \000\000\000config=0x3\000\000\000\000\000\000\000\000Total write hits\000 */
{ 159919 }, /* wr_hit_spipe\000hisi_sccl,l3c\000uncore l3c\000Count of the number of write lines that hits in spipe of this L3C. Unit: hisi_sccl,l3c \000\000\000config=0x23\000\000\000\000\000\000\000\000Count of the number of write lines that hits in spipe of this L3C\000 */
{ 160132 }, /* wr_spipe\000hisi_sccl,l3c\000uncore l3c\000Count of the number of write lines that come from this cluster of CPU core in spipe. Unit: hisi_sccl,l3c \000\000\000config=0x21\000\000\000\000\000\000\000\000Count of the number of write lines that come from this cluster of CPU core in spipe\000 */
};

static const struct compact_pmu_event pme_cavium_thunderx2[] = {
{ 35845 }, /* bus_access_rd\000\000core imp def\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36123 }, /* bus_access_wr\000\000core imp def\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 48173 }, /* exc_dabort\000\000core imp def\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000 */
{ 48416 }, /* exc_fiq\000\000core imp def\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48658 }, /* exc_hvc\000\000core imp def\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 48871 }, /* exc_irq\000\000core imp def\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 49113 }, /* exc_pabort\000\000core imp def\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000 */
{ 49732 }, /* exc_smc\000\000core imp def\000Exception taken, Secure Monitor Call\000\000\000event=0x88\000\000\000\000\000\000\000\000Exception taken, Secure Monitor Call\000 */
{ 49961 }, /* exc_svc\000\000core imp def\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000 */
{ 50246 }, /* exc_trap_dabort\000\000core imp def\000Exception taken, Data Abort or SError not taken locally\000\000\000event=0x8c\000\000\000\000\000\000\000\000Exception taken, Data Abort or SError not taken locally\000 */
{ 50567 }, /* exc_trap_fiq\000\000core imp def\000Exception taken, FIQ not taken locally\000\000\000event=0x8f\000\000\000\000\000\000\000\000Exception taken, FIQ not taken locally\000 */
{ 51700 }, /* exc_trap_irq\000\000core imp def\000Exception taken, IRQ not taken locally\000\000\000event=0x8e\000\000\000\000\000\000\000\000Exception taken, IRQ not taken locally\000 */
{ 51947 }, /* exc_trap_other\000\000core imp def\000Exception taken, Other traps not taken locally\000\000\000event=0x8d\000\000\000\000\000\000\000\000Exception taken, Other traps not taken locally\000 */
{ 52230 }, /* exc_trap_pabort\000\000core imp def\000Exception taken, Instruction Abort not taken locally\000\000\000event=0x8b\000\000\000\000\000\000\000\000Exception taken, Instruction Abort not taken locally\000 */
{ 52539 }, /* exc_undef\000\000core imp def\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000 */
{ 72116 }, /* l1d_cache_inval\000\000core imp def\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000 */
{ 72862 }, /* l1d_cache_rd\000\000core imp def\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 73775 }, /* l1d_cache_refill_inner\000\000core imp def\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000 */
{ 74022 }, /* l1d_cache_refill_outer\000\000core imp def\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000 */
{ 75126 }, /* l1d_cache_refill_rd\000\000core imp def\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75365 }, /* l1d_cache_refill_wr\000\000core imp def\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 76010 }, /* l1d_cache_wb_clean\000\000core imp def\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000 */
{ 76289 }, /* l1d_cache_wb_victim\000\000core imp def\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000 */
{ 76533 }, /* l1d_cache_wr\000\000core imp def\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 77616 }, /* l1d_tlb_rd\000\000core imp def\000L1D tlb access, read\000\000\000event=0x4e\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, read\000 */
{ 78160 }, /* l1d_tlb_refill_rd\000\000core imp def\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000 */
{ 78387 }, /* l1d_tlb_refill_wr\000\000core imp def\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000 */
{ 78620 }, /* l1d_tlb_wr\000\000core imp def\000L1D tlb access, write\000\000\000event=0x4f\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, write\000 */
{ 103100 }, /* l2d_tlb_rd\000\000core imp def\000L2D cache access, read\000\000\000event=0x5e\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, read\000 */
{ 103687 }, /* l2d_tlb_refill_rd\000\000core imp def\000L2D cache refill, read\000\000\000event=0x5c\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, read\000 */
{ 103940 }, /* l2d_tlb_refill_wr\000\000core imp def\000L2D cache refill, write\000\000\000event=0x5d\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, write\000 */
{ 104188 }, /* l2d_tlb_wr\000\000core imp def\000L2D cache access, write\000\000\000event=0x5f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, write\000 */
{ 118865 }, /* mem_access_rd\000\000core imp def\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119055 }, /* mem_access_wr\000\000core imp def\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 156489 }, /* unaligned_ld_spec\000\000core imp def\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000 */
{ 156879 }, /* unaligned_ldst_spec\000\000core imp def\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 157049 }, /* unaligned_st_spec\000\000core imp def\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000 */
};

static const struct compact_pmu_event pme_freescale_imx8mq_sys[] = {
{ 64953 }, /* imx8mq_ddr.cycles\000imx8_ddr\000ddrc\000ddr cycles event. Unit: imx8_ddr \000\000\000event=0\000\000i.MX8MQ\000\000\000\000\000\000\000 */
{ 65044 }, /* imx8mq_ddr.read\000imx8_ddr\000ddrc\000ddr read event. Unit: imx8_ddr \000\000\000event=0x35\000\000i.MX8MQ\000\000\000\000\000\000\000 */
{ 65134 }, /* imx8mq_ddr.read_cycles\000imx8_ddr\000ddrc\000ddr read-cycles event. Unit: imx8_ddr \000\000\000event=0x2a\000\000i.MX8MQ\000\000\000\000\000\000\000 */
{ 65238 }, /* imx8mq_ddr.write\000imx8_ddr\000ddrc\000ddr write event. Unit: imx8_ddr \000\000\000event=0x38\000\000i.MX8MQ\000\000\000\000\000\000\000 */
{ 65330 }, /* imx8mq_ddr.write_cycles\000imx8_ddr\000ddrc\000ddr write-cycles event. Unit: imx8_ddr \000\000\000event=0x2b\000\000i.MX8MQ\000\000\000\000\000\000\000 */
{ 7084 }, /* \000imx8_ddr\000metrics\000bytes all masters read from ddr based on read-cycles event. Unit: imx8_ddr \000imx8mq_ddr_read.all\000\000\000\000i.MX8MQ\000\000\0009.765625e-4KB\000\000imx8mq_ddr.read_cycles * 4 * 4\000\000 */
{ 7610 }, /* \000imx8_ddr\000metrics\000bytes all masters write to ddr based on write-cycles event. Unit: imx8_ddr \000imx8mq_ddr_write.all\000\000\000\000i.MX8MQ\000\000\0009.765625e-4KB\000\000imx8mq_ddr.write_cycles * 4 * 4\000\000 */
};

static const struct compact_pmu_event pme_freescale_imx8mp_sys[] = {
{ 64470 }, /* imx8mp_ddr.cycles\000imx8_ddr\000ddrc\000ddr cycles event. Unit: imx8_ddr \000\000\000event=0\000\000i.MX8MP\000\000\000\000\000\000\000 */
{ 64561 }, /* imx8mp_ddr.read\000imx8_ddr\000ddrc\000ddr read event. Unit: imx8_ddr \000\000\000event=0x35\000\000i.MX8MP\000\000\000\000\000\000\000 */
{ 64651 }, /* imx8mp_ddr.read_cycles\000imx8_ddr\000ddrc\000ddr read-cycles event. Unit: imx8_ddr \000\000\000event=0x2a\000\000i.MX8MP\000\000\000\000\000\000\000 */
{ 64755 }, /* imx8mp_ddr.write\000imx8_ddr\000ddrc\000ddr write event. Unit: imx8_ddr \000\000\000event=0x38\000\000i.MX8MP\000\000\000\000\000\000\000 */
{ 64847 }, /* imx8mp_ddr.write_cycles\000imx8_ddr\000ddrc\000ddr write-cycles event. Unit: imx8_ddr \000\000\000event=0x2b\000\000i.MX8MP\000\000\000\000\000\000\000 */
{ 13632 }, /* \000imx8_ddr\000metrics\000bytes of gpu 2d read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.2d\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0071@\000\000 */
{ 13971 }, /* \000imx8_ddr\000metrics\000bytes of gpu 3d read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.3d\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0070@\000\000 */
{ 7786 }, /* \000imx8_ddr\000metrics\000bytes of a53 core read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.a53\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0000@\000\000 */
{ 8131 }, /* \000imx8_ddr\000metrics\000bytes of all masters read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.all\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0xffff\\,axi_id\\=0x0000@\000\000 */
{ 8482 }, /* \000imx8_ddr\000metrics\000bytes of audio dsp read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.audio_dsp\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0041@\000\000 */
{ 8841 }, /* \000imx8_ddr\000metrics\000bytes of audio sdma2_burst read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.audio_sdma2_burst\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0063@\000\000 */
{ 9232 }, /* \000imx8_ddr\000metrics\000bytes of audio sdma2_per read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.audio_sdma2_per\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0062@\000\000 */
{ 9615 }, /* \000imx8_ddr\000metrics\000bytes of audio sdma3_burst read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.audio_sdma3_burst\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0065@\000\000 */
{ 10006 }, /* \000imx8_ddr\000metrics\000bytes of audio sdma3_per read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.audio_sdma3_per\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0064@\000\000 */
{ 10389 }, /* \000imx8_ddr\000metrics\000bytes of audio sdma_pif read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.audio_sdma_pif\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0066@\000\000 */
{ 10768 }, /* \000imx8_ddr\000metrics\000bytes of display dewarp read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.dewarp\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x006f@\000\000 */
{ 15056 }, /* \000imx8_ddr\000metrics\000bytes of hdmi_tx tx_hdcp read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.hdmi_hdcp\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0076@\000\000 */
{ 14310 }, /* \000imx8_ddr\000metrics\000bytes of hdmi_tx hrv_mwr read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.hdmi_hrv_mwr\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0074@\000\000 */
{ 14687 }, /* \000imx8_ddr\000metrics\000bytes of hdmi_tx lcdif read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.hdmi_lcdif\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0075@\000\000 */
{ 11131 }, /* \000imx8_ddr\000metrics\000bytes of display isi1 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.isi1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x006a@\000\000 */
{ 11486 }, /* \000imx8_ddr\000metrics\000bytes of display isi2 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.isi2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x006b@\000\000 */
{ 11841 }, /* \000imx8_ddr\000metrics\000bytes of display isi3 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.isi3\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x006c@\000\000 */
{ 12196 }, /* \000imx8_ddr\000metrics\000bytes of display isp1 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.isp1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x006d@\000\000 */
{ 12551 }, /* \000imx8_ddr\000metrics\000bytes of display isp2 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.isp2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x006e@\000\000 */
{ 12906 }, /* \000imx8_ddr\000metrics\000bytes of display lcdif1 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.lcdif1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0068@\000\000 */
{ 13269 }, /* \000imx8_ddr\000metrics\000bytes of display lcdif2 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.lcdif2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0069@\000\000 */
{ 16470 }, /* \000imx8_ddr\000metrics\000bytes of npu read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.npu\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0073@\000\000 */
{ 15427 }, /* \000imx8_ddr\000metrics\000bytes of hsio pci read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.pci\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x007a@\000\000 */
{ 16805 }, /* \000imx8_ddr\000metrics\000bytes of supermix(m7) core read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.supermix\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x000f\\,axi_id\\=0x0020@\000\000 */
{ 15772 }, /* \000imx8_ddr\000metrics\000bytes of hsio usb1 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.usb1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0078@\000\000 */
{ 16121 }, /* \000imx8_ddr\000metrics\000bytes of hsio usb2 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.usb2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x0079@\000\000 */
{ 17173 }, /* \000imx8_ddr\000metrics\000bytes of vpu1 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.vpu1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x007c@\000\000 */
{ 17512 }, /* \000imx8_ddr\000metrics\000bytes of vpu2 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.vpu2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x007d@\000\000 */
{ 17851 }, /* \000imx8_ddr\000metrics\000bytes of vpu3 read from ddr. Unit: imx8_ddr \000imx8mp_ddr_read.vpu3\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-read\\,axi_mask\\=0x0000\\,axi_id\\=0x007e@\000\000 */
{ 13801 }, /* \000imx8_ddr\000metrics\000bytes of gpu 2d write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.2d\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0071@\000\000 */
{ 14140 }, /* \000imx8_ddr\000metrics\000bytes of gpu 3d write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.3d\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0070@\000\000 */
{ 7958 }, /* \000imx8_ddr\000metrics\000bytes of a53 core write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.a53\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0000@\000\000 */
{ 8306 }, /* \000imx8_ddr\000metrics\000bytes of all masters write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.all\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0xffff\\,axi_id\\=0x0000@\000\000 */
{ 8661 }, /* \000imx8_ddr\000metrics\000bytes of audio dsp write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.audio_dsp\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0041@\000\000 */
{ 9036 }, /* \000imx8_ddr\000metrics\000bytes of audio sdma2_burst write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.audio_sdma2_burst\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0063@\000\000 */
{ 9423 }, /* \000imx8_ddr\000metrics\000bytes of audio sdma2_per write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.audio_sdma2_per\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0062@\000\000 */
{ 9810 }, /* \000imx8_ddr\000metrics\000bytes of audio sdma3_burst write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.audio_sdma3_burst\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0065@\000\000 */
{ 10197 }, /* \000imx8_ddr\000metrics\000bytes of audio sdma3_per write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.audio_sdma3_per\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0064@\000\000 */
{ 10578 }, /* \000imx8_ddr\000metrics\000bytes of audio sdma_pif write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.audio_sdma_pif\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0066@\000\000 */
{ 10949 }, /* \000imx8_ddr\000metrics\000bytes of display dewarp write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.dewarp\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x006f@\000\000 */
{ 15241 }, /* \000imx8_ddr\000metrics\000bytes of hdmi_tx tx_hdcp write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.hdmi_hdcp\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0076@\000\000 */
{ 14498 }, /* \000imx8_ddr\000metrics\000bytes of hdmi_tx hrv_mwr write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.hdmi_hrv_mwr\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0074@\000\000 */
{ 14871 }, /* \000imx8_ddr\000metrics\000bytes of hdmi_tx lcdif write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.hdmi_lcdif\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0075@\000\000 */
{ 11308 }, /* \000imx8_ddr\000metrics\000bytes of display isi1 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.isi1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x006a@\000\000 */
{ 11663 }, /* \000imx8_ddr\000metrics\000bytes of display isi2 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.isi2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x006b@\000\000 */
{ 12018 }, /* \000imx8_ddr\000metrics\000bytes of display isi3 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.isi3\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x006c@\000\000 */
{ 12373 }, /* \000imx8_ddr\000metrics\000bytes of display isp1 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.isp1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x006d@\000\000 */
{ 12728 }, /* \000imx8_ddr\000metrics\000bytes of display isp2 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.isp2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x006e@\000\000 */
{ 13087 }, /* \000imx8_ddr\000metrics\000bytes of display lcdif1 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.lcdif1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0068@\000\000 */
{ 13450 }, /* \000imx8_ddr\000metrics\000bytes of display lcdif2 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.lcdif2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0069@\000\000 */
{ 16637 }, /* \000imx8_ddr\000metrics\000bytes of npu write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.npu\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0073@\000\000 */
{ 15599 }, /* \000imx8_ddr\000metrics\000bytes of hsio pci write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.pci\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x007a@\000\000 */
{ 16991 }, /* \000imx8_ddr\000metrics\000bytes of supermix(m7) write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.supermix\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x000f\\,axi_id\\=0x0020@\000\000 */
{ 15946 }, /* \000imx8_ddr\000metrics\000bytes of hsio usb1 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.usb1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0078@\000\000 */
{ 16295 }, /* \000imx8_ddr\000metrics\000bytes of hsio usb2 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.usb2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x0079@\000\000 */
{ 17342 }, /* \000imx8_ddr\000metrics\000bytes of vpu1 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.vpu1\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x007c@\000\000 */
{ 17681 }, /* \000imx8_ddr\000metrics\000bytes of vpu2 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.vpu2\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x007d@\000\000 */
{ 18020 }, /* \000imx8_ddr\000metrics\000bytes of vpu3 write to ddr. Unit: imx8_ddr \000imx8mp_ddr_write.vpu3\000\000\000\000i.MX8MP\000\000\0009.765625e-4KB\000\000imx8_ddr0@axid\\-write\\,axi_mask\\=0x0000\\,axi_id\\=0x007e@\000\000 */
};

static const struct compact_pmu_event pme_freescale_imx8mn_sys[] = {
{ 63987 }, /* imx8mn_ddr.cycles\000imx8_ddr\000ddrc\000ddr cycles event. Unit: imx8_ddr \000\000\000event=0\000\000i.MX8MN\000\000\000\000\000\000\000 */
{ 64078 }, /* imx8mn_ddr.read\000imx8_ddr\000ddrc\000ddr read event. Unit: imx8_ddr \000\000\000event=0x35\000\000i.MX8MN\000\000\000\000\000\000\000 */
{ 64168 }, /* imx8mn_ddr.read_cycles\000imx8_ddr\000ddrc\000ddr read-cycles event. Unit: imx8_ddr \000\000\000event=0x2a\000\000i.MX8MN\000\000\000\000\000\000\000 */
{ 64272 }, /* imx8mn_ddr.write\000imx8_ddr\000ddrc\000ddr write event. Unit: imx8_ddr \000\000\000event=0x38\000\000i.MX8MN\000\000\000\000\000\000\000 */
{ 64364 }, /* imx8mn_ddr.write_cycles\000imx8_ddr\000ddrc\000ddr write-cycles event. Unit: imx8_ddr \000\000\000event=0x2b\000\000i.MX8MN\000\000\000\000\000\000\000 */
{ 6910 }, /* \000imx8_ddr\000metrics\000bytes all masters read from ddr based on read-cycles event. Unit: imx8_ddr \000imx8mn_ddr_read.all\000\000\000\000i.MX8MN\000\000\0009.765625e-4KB\000\000imx8mn_ddr.read_cycles * 4 * 2\000\000 */
{ 7434 }, /* \000imx8_ddr\000metrics\000bytes all masters write to ddr based on write-cycles event. Unit: imx8_ddr \000imx8mn_ddr_write.all\000\000\000\000i.MX8MN\000\000\0009.765625e-4KB\000\000imx8mn_ddr.write_cycles * 4 * 2\000\000 */
};

static const struct compact_pmu_event pme_freescale_imx8mm_sys[] = {
{ 63504 }, /* imx8mm_ddr.cycles\000imx8_ddr\000ddrc\000ddr cycles event. Unit: imx8_ddr \000\000\000event=0\000\000i.MX8MM\000\000\000\000\000\000\000 */
{ 63595 }, /* imx8mm_ddr.read\000imx8_ddr\000ddrc\000ddr read event. Unit: imx8_ddr \000\000\000event=0x35\000\000i.MX8MM\000\000\000\000\000\000\000 */
{ 63685 }, /* imx8mm_ddr.read_cycles\000imx8_ddr\000ddrc\000ddr read-cycles event. Unit: imx8_ddr \000\000\000event=0x2a\000\000i.MX8MM\000\000\000\000\000\000\000 */
{ 63789 }, /* imx8mm_ddr.write\000imx8_ddr\000ddrc\000ddr write event. Unit: imx8_ddr \000\000\000event=0x38\000\000i.MX8MM\000\000\000\000\000\000\000 */
{ 63881 }, /* imx8mm_ddr.write_cycles\000imx8_ddr\000ddrc\000ddr write-cycles event. Unit: imx8_ddr \000\000\000event=0x2b\000\000i.MX8MM\000\000\000\000\000\000\000 */
{ 6736 }, /* \000imx8_ddr\000metrics\000bytes all masters read from ddr based on read-cycles event. Unit: imx8_ddr \000imx8mm_ddr_read.all\000\000\000\000i.MX8MM\000\000\0009.765625e-4KB\000\000imx8mm_ddr.read_cycles * 4 * 4\000\000 */
{ 7258 }, /* \000imx8_ddr\000metrics\000bytes all masters write to ddr based on write-cycles event. Unit: imx8_ddr \000imx8mm_ddr_write.all\000\000\000\000i.MX8MM\000\000\0009.765625e-4KB\000\000imx8mm_ddr.write_cycles * 4 * 4\000\000 */
};

static const struct compact_pmu_event pme_ampere_emag[] = {
{ 25798 }, /* br_immed_spec\000\000branch\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30255 }, /* br_mis_pred\000\000branch\000Branch mispredicted\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31457 }, /* br_pred\000\000branch\000Predictable branch\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 34668 }, /* br_return_spec\000\000branch\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35467 }, /* bus_access_normal\000\000bus\000Bus access, Normal\000\000\000event=0x64\000\000\000\000\000\000\000\000Bus access, Normal\000 */
{ 35548 }, /* bus_access_not_shared\000\000bus\000Bus access, not Normal, Cacheable, Shareable\000\000\000event=0x63\000\000\000\000\000\000\000\000Bus access, not Normal, Cacheable, Shareable\000 */
{ 35685 }, /* bus_access_periph\000\000bus\000Bus access, peripheral\000\000\000event=0x65\000\000\000\000\000\000\000\000Bus access, peripheral\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 35925 }, /* bus_access_shared\000\000bus\000Bus access, Normal, Cacheable, Shareable\000\000\000event=0x62\000\000\000\000\000\000\000\000Bus access, Normal, Cacheable, Shareable\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 34951 }, /* btb_mis_pred\000\000cache\000BTB misprediction\000\000\000event=0x102\000\000\000\000\000\000\000\000Branch target buffer misprediction\000 */
{ 45441 }, /* dtb_miss\000\000cache\000DTB miss\000\000\000event=0x104\000\000\000\000\000\000\000\000DTB miss\000 */
{ 66262 }, /* itb_miss\000\000cache\000ITB miss\000\000\000event=0x103\000\000\000\000\000\000\000\000ITB miss\000 */
{ 71296 }, /* l1_stage2_tlb_refill\000\000cache\000L1 stage 2 TLB refill\000\000\000event=0x111\000\000\000\000\000\000\000\000Level 1 stage 2 TLB refill\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72009 }, /* l1d_cache_inval\000\000cache\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000 */
{ 72230 }, /* l1d_cache_late_miss\000\000cache\000L1D cache late miss\000\000\000event=0x105\000\000\000\000\000\000\000\000Level 1 data cache late miss\000 */
{ 72652 }, /* l1d_cache_prefetch\000\000cache\000L1D cache prefetch\000\000\000event=0x106\000\000\000\000\000\000\000\000Level 1 data cache prefetch request\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 75011 }, /* l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 77103 }, /* l1d_tlb\000\000cache\000L1D TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000This event counts any load or store operation which accesses the data L1 TLB\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 78051 }, /* l1d_tlb_refill_rd\000\000cache\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000 */
{ 78276 }, /* l1d_tlb_refill_wr\000\000cache\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83397 }, /* l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000This event counts any instruction fetch which accesses the instruction L1 TLB\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 89220 }, /* l2d_cache_inval\000\000cache\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000 */
{ 90289 }, /* l2d_cache_prefetch\000\000cache\000L2D cache prefetch\000\000\000event=0x107\000\000\000\000\000\000\000\000Level 2 data cache prefetch request\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 93050 }, /* l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93287 }, /* l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97102 }, /* l2d_cache_wb_clean\000\000cache\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000 */
{ 97399 }, /* l2d_cache_wb_victim\000\000cache\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 102796 }, /* l2d_tlb_access\000\000cache\000L2D TLB access\000\000\000event=0x34\000\000\000\000\000\000\000\000Level 2 access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count\000 */
{ 106821 }, /* l2i_tlb_access\000\000cache\000L2I TLB access\000\000\000event=0x35\000\000\000\000\000\000\000\000Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count\000 */
{ 123842 }, /* page_walk_l0_stage1_hit\000\000cache\000Page walk, L0 stage-1 hit\000\000\000event=0x112\000\000\000\000\000\000\000\000Page walk cache level-0 stage-1 hit\000 */
{ 123956 }, /* page_walk_l1_stage1_hit\000\000cache\000Page walk, L1 stage-1 hit\000\000\000event=0x113\000\000\000\000\000\000\000\000Page walk cache level-1 stage-1 hit\000 */
{ 124070 }, /* page_walk_l1_stage2_hit\000\000cache\000Page walk, L1 stage-2 hit\000\000\000event=0x115\000\000\000\000\000\000\000\000Page walk cache level-1 stage-2 hit\000 */
{ 124184 }, /* page_walk_l2_stage1_hit\000\000cache\000Page walk, L2 stage-1 hit\000\000\000event=0x114\000\000\000\000\000\000\000\000Page walk cache level-2 stage-1 hit\000 */
{ 124298 }, /* page_walk_l2_stage2_hit\000\000cache\000Page walk, L2 stage-2 hit\000\000\000event=0x116\000\000\000\000\000\000\000\000Page walk cache level-2 stage-2 hit\000 */
{ 40920 }, /* cpu_cycles\000\000clock\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000The number of core clock cycles\000 */
{ 58936 }, /* fsu_clock_off_cycles\000\000clock\000FSU clocking gated off cycle\000\000\000event=0x101\000\000\000\000\000\000\000\000FSU clocking gated off cycle\000 */
{ 158928 }, /* wait_cycles\000\000clock\000Wait state cycle\000\000\000event=0x110\000\000\000\000\000\000\000\000Wait state cycle\000 */
{ 48296 }, /* exc_dabort\000\000exception\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48766 }, /* exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 49228 }, /* exc_pabort\000\000exception\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000 */
{ 49340 }, /* exc_return\000\000exception\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 50069 }, /* exc_svc\000\000exception\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 50408 }, /* exc_trap_dabort\000\000exception\000Exception taken, Data Abort or SError not taken locally\000\000\000event=0x8c\000\000\000\000\000\000\000\000Exception taken, Data Abort or SError not taken locally\000 */
{ 50692 }, /* exc_trap_fiq\000\000exception\000Exception taken, FIQ not taken locally\000\000\000event=0x8f\000\000\000\000\000\000\000\000Exception taken, FIQ not taken locally\000 */
{ 51825 }, /* exc_trap_irq\000\000exception\000Exception taken, IRQ not taken locally\000\000\000event=0x8e\000\000\000\000\000\000\000\000Exception taken, IRQ not taken locally\000 */
{ 52090 }, /* exc_trap_other\000\000exception\000Exception taken, Other traps not taken locally\000\000\000event=0x8d\000\000\000\000\000\000\000\000Exception taken, Other traps not taken locally\000 */
{ 52386 }, /* exc_trap_pabort\000\000exception\000Exception taken, Instruction Abort not taken locally\000\000\000event=0x8b\000\000\000\000\000\000\000\000Exception taken, Instruction Abort not taken locally\000 */
{ 52653 }, /* exc_undef\000\000exception\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 30993 }, /* br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush\000 */
{ 31688 }, /* br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches\000 */
{ 38994 }, /* cid_write_retired\000\000instruction\000Write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 43623 }, /* dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 45327 }, /* dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116604 }, /* ldst_spec\000\000instruction\000Operation speculatively executed, load or store\000\000\000event=0x72\000\000\000\000\000\000\000\000Operation speculatively executed, load or store\000 */
{ 122819 }, /* nop_spec\000\000instruction\000Speculatively executed, NOP\000\000\000event=0x100\000\000\000\000\000\000\000\000Operation speculatively executed, NOP\000 */
{ 124643 }, /* pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000 */
{ 127257 }, /* rc_ld_spec\000\000instruction\000Release consistency operation speculatively executed, Load-Acquire\000\000\000event=0x90\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Load-Acquire\000 */
{ 127435 }, /* rc_st_spec\000\000instruction\000Release consistency operation speculatively executed, Store-Release\000\000\000event=0x91\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Store-Release\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 152116 }, /* sw_incr\000\000instruction\000Software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, software increment\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 116311 }, /* ldrex_spec\000\000intrinsic\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000 */
{ 147297 }, /* strex_fail_spec\000\000intrinsic\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000 */
{ 147641 }, /* strex_pass_spec\000\000intrinsic\000Exclusive operation speculatively executed, STREX or STX pass\000\000\000event=0x6d\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX pass\000 */
{ 147970 }, /* strex_spec\000\000intrinsic\000Exclusive operation speculatively executed, STREX or STX\000\000\000event=0x6f\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 120341 }, /* memory_error\000\000memory\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs\000 */
{ 156587 }, /* unaligned_ld_spec\000\000memory\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000 */
{ 156967 }, /* unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 157149 }, /* unaligned_st_spec\000\000memory\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000 */
{ 38457 }, /* bx_stall\000\000pipeline\000BX stalled\000\000\000event=0x10c\000\000\000\000\000\000\000\000BX Op non-issue\000 */
{ 43300 }, /* decode_stall\000\000pipeline\000Decode starved\000\000\000event=0x108\000\000\000\000\000\000\000\000Decode starved for instruction cycle\000 */
{ 43534 }, /* dispatch_stall\000\000pipeline\000Dispatch stalled\000\000\000event=0x109\000\000\000\000\000\000\000\000Op dispatch stalled cycle\000 */
{ 59043 }, /* fx_stall\000\000pipeline\000FX stalled\000\000\000event=0x10f\000\000\000\000\000\000\000\000FX Op non-issue\000 */
{ 66794 }, /* ixa_stall\000\000pipeline\000IXA stalled\000\000\000event=0x10a\000\000\000\000\000\000\000\000IXA Op non-issue\000 */
{ 66864 }, /* ixb_stall\000\000pipeline\000IXB stalled\000\000\000event=0x10b\000\000\000\000\000\000\000\000IXB Op non-issue\000 */
{ 118111 }, /* lx_stall\000\000pipeline\000LX stalled\000\000\000event=0x10d\000\000\000\000\000\000\000\000LX Op non-issue\000 */
{ 152230 }, /* sx_stall\000\000pipeline\000SX stalled\000\000\000event=0x10e\000\000\000\000\000\000\000\000SX Op non-issue\000 */
};

static const struct compact_pmu_event pme_fujitsu_a64fx[] = {
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 36340 }, /* bus_read_total_mem\000\000bus\000This event counts read transactions from measured CMG local memory to measured CMG\000\000\000event=0x316\000\000\000\000\000\000\000\000This event counts read transactions from measured CMG local memory to measured CMG\000 */
{ 36551 }, /* bus_read_total_pci\000\000bus\000This event counts read transactions from PCI controller to measured CMG\000\000\000event=0x315\000\000\000\000\000\000\000\000This event counts read transactions from PCI controller to measured CMG\000 */
{ 36740 }, /* bus_read_total_tofu\000\000bus\000This event counts read transactions from tofu controller to measured CMG\000\000\000event=0x314\000\000\000\000\000\000\000\000This event counts read transactions from tofu controller to measured CMG\000 */
{ 36932 }, /* bus_write_total_cmg0\000\000bus\000This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0\000\000\000event=0x318\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to CMG0, if measured CMG is not CMG0\000 */
{ 37163 }, /* bus_write_total_cmg1\000\000bus\000This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1\000\000\000event=0x319\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to CMG1, if measured CMG is not CMG1\000 */
{ 37394 }, /* bus_write_total_cmg2\000\000bus\000This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2\000\000\000event=0x31a\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to CMG2, if measured CMG is not CMG2\000 */
{ 37625 }, /* bus_write_total_cmg3\000\000bus\000This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3\000\000\000event=0x31b\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to CMG3, if measured CMG is not CMG3\000 */
{ 37856 }, /* bus_write_total_mem\000\000bus\000This event counts write transactions from measured CMG to measured CMG local memory\000\000\000event=0x31e\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to measured CMG local memory\000 */
{ 38070 }, /* bus_write_total_pci\000\000bus\000This event counts write transactions from measured CMG to PCI controller\000\000\000event=0x31d\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to PCI controller\000 */
{ 38262 }, /* bus_write_total_tofu\000\000bus\000This event counts write transactions from measured CMG to tofu controller\000\000\000event=0x31c\000\000\000\000\000\000\000\000This event counts write transactions from measured CMG to tofu controller\000 */
{ 45943 }, /* ea_l2\000\000cache\000This event counts energy consumption per cycle of L2 cache\000\000\000event=0x3e0\000\000\000\000\000\000\000\000This event counts energy consumption per cycle of L2 cache\000 */
{ 66934 }, /* l1_miss_wait\000\000cache\000This event counts outstanding L1D cache miss requests per cycle\000\000\000event=0x208\000\000\000\000\000\000\000\000This event counts outstanding L1D cache miss requests per cycle\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 73312 }, /* l1d_cache_refill_dm\000\000cache\000This event counts L1D_CACHE_REFILL caused by demand access\000\000\000event=0x200\000\000\000\000\000\000\000\000This event counts L1D_CACHE_REFILL caused by demand access\000 */
{ 73478 }, /* l1d_cache_refill_hwprf\000\000cache\000This event counts L1D_CACHE_REFILL caused by hardware prefetch\000\000\000event=0x202\000\000\000\000\000\000\000\000This event counts L1D_CACHE_REFILL caused by hardware prefetch\000 */
{ 74813 }, /* l1d_cache_refill_prf\000\000cache\000This event counts L1D_CACHE_REFILL caused by software or hardware prefetch\000\000\000event=0x49\000\000\000\000\000\000\000\000This event counts L1D_CACHE_REFILL caused by software or hardware prefetch\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 82791 }, /* l1i_miss_wait\000\000cache\000This event counts outstanding L1I cache miss requests per cycle\000\000\000event=0x209\000\000\000\000\000\000\000\000This event counts outstanding L1I cache miss requests per cycle\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 87493 }, /* l2_miss_count\000\000cache\000This event counts the number of times of L2 cache miss\000\000\000event=0x309\000\000\000\000\000\000\000\000This event counts the number of times of L2 cache miss\000 */
{ 87645 }, /* l2_miss_wait\000\000cache\000This event counts outstanding L2 cache miss requests per cycle\000\000\000event=0x308\000\000\000\000\000\000\000\000This event counts outstanding L2 cache miss requests per cycle\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 89994 }, /* l2d_cache_mibmch_prf\000\000cache\000This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access\000\000\000event=0x326\000\000\000\000\000\000\000\000This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 90947 }, /* l2d_cache_refill_dm\000\000cache\000This event counts L2D_CACHE_REFILL caused by demand access\000\000\000event=0x300\000\000\000\000\000\000\000\000This event counts L2D_CACHE_REFILL caused by demand access\000 */
{ 91113 }, /* l2d_cache_refill_hwprf\000\000cache\000This event counts L2D_CACHE_REFILL caused by hardware prefetch\000\000\000event=0x302\000\000\000\000\000\000\000\000This event counts L2D_CACHE_REFILL caused by hardware prefetch\000 */
{ 92852 }, /* l2d_cache_refill_prf\000\000cache\000This event counts L2D_CACHE_REFILL caused by software or hardware prefetch\000\000\000event=0x59\000\000\000\000\000\000\000\000This event counts L2D_CACHE_REFILL caused by software or hardware prefetch\000 */
{ 96291 }, /* l2d_cache_swap_local\000\000cache\000This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch\000\000\000event=0x396\000\000\000\000\000\000\000\000This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 102157 }, /* l2d_swap_dm\000\000cache\000This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch\000\000\000event=0x325\000\000\000\000\000\000\000\000This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch\000 */
{ 102443 }, /* l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access\000 */
{ 103449 }, /* l2d_tlb_refill\000\000cache\000Attributable Level 2 data TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000Attributable Level 2 data TLB refill\000 */
{ 106698 }, /* l2i_tlb\000\000cache\000Attributable Level 2 instruction TLB access\000\000\000event=0x30\000\000\000\000\000\000\000\000Attributable Level 2 instruction TLB access\000 */
{ 107024 }, /* l2i_tlb_refill\000\000cache\000Attributable Level 2 instruction TLB refill\000\000\000event=0x2e\000\000\000\000\000\000\000\000Attributable Level 2 instruction TLB refill\000 */
{ 40996 }, /* cpu_cycles\000\000cycle\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 48296 }, /* exc_dabort\000\000exception\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48766 }, /* exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 49228 }, /* exc_pabort\000\000exception\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000 */
{ 49848 }, /* exc_smc\000\000exception\000Exception taken, Secure Monitor Call\000\000\000event=0x88\000\000\000\000\000\000\000\000Exception taken, Secure Monitor Call\000 */
{ 50069 }, /* exc_svc\000\000exception\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 52653 }, /* exc_undef\000\000exception\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 21987 }, /* bc_ld_spec\000\000instruction\000This event counts architecturally executed SIMD broadcast floating-point load operations\000\000\000event=0x11a\000\000\000\000\000\000\000\000This event counts architecturally executed SIMD broadcast floating-point load operations\000 */
{ 25936 }, /* br_immed_spec\000\000instruction\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 30111 }, /* br_indirect_spec\000\000instruction\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 34807 }, /* br_return_spec\000\000instruction\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 42197 }, /* dczva_spec\000\000instruction\000This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction\000\000\000event=0x9f\000\000\000\000\000\000\000\000This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction\000 */
{ 43623 }, /* dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 45327 }, /* dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000 */
{ 46783 }, /* effective_inst_spec\000\000instruction\000This event counts architecturally executed instructions, excluding the MOVPRFX instruction\000\000\000event=0x121\000\000\000\000\000\000\000\000This event counts architecturally executed instructions, excluding the MOVPRFX instruction\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 56983 }, /* fp_ld_spec\000\000instruction\000This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers\000\000\000event=0x112\000\000\000\000\000\000\000\000This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers\000 */
{ 57218 }, /* fp_mv_spec\000\000instruction\000This event counts architecturally executed floating-point move operations\000\000\000event=0x105\000\000\000\000\000\000\000\000This event counts architecturally executed floating-point move operations\000 */
{ 58699 }, /* fp_st_spec\000\000instruction\000This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers\000\000\000event=0x113\000\000\000\000\000\000\000\000This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers\000 */
{ 59769 }, /* iel_spec\000\000instruction\000This event counts architecturally executed inter-element manipulation operations\000\000\000event=0x109\000\000\000\000\000\000\000\000This event counts architecturally executed inter-element manipulation operations\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 65940 }, /* ireg_spec\000\000instruction\000This event counts architecturally executed inter-register manipulation operations\000\000\000event=0x10a\000\000\000\000\000\000\000\000This event counts architecturally executed inter-register manipulation operations\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116153 }, /* ldrex_spec\000\000instruction\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000 */
{ 116604 }, /* ldst_spec\000\000instruction\000Operation speculatively executed, load or store\000\000\000event=0x72\000\000\000\000\000\000\000\000Operation speculatively executed, load or store\000 */
{ 124643 }, /* pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000 */
{ 125429 }, /* post_index_spec\000\000instruction\000This event counts architecturally executed operations that uses 'post-index' as its addressing mode\000\000\000event=0x124\000\000\000\000\000\000\000\000This event counts architecturally executed operations that uses 'post-index' as its addressing mode\000 */
{ 125679 }, /* prd_spec\000\000instruction\000This event counts architecturally executed operations that using predicate register\000\000\000event=0x108\000\000\000\000\000\000\000\000This event counts architecturally executed operations that using predicate register\000 */
{ 126076 }, /* pre_index_spec\000\000instruction\000This event counts architecturally executed operations that uses 'pre-index' as its addressing mode\000\000\000event=0x123\000\000\000\000\000\000\000\000This event counts architecturally executed operations that uses 'pre-index' as its addressing mode\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 147812 }, /* strex_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX\000\000\000event=0x6f\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 46095 }, /* ea_memory\000\000memory\000This event counts energy consumption per cycle of CMG local memory\000\000\000event=0x3e8\000\000\000\000\000\000\000\000This event counts energy consumption per cycle of CMG local memory\000 */
{ 18190 }, /* _0inst_commit\000\000other\000This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only\000\000\000event=0x190\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only\000 */
{ 18460 }, /* _1inst_commit\000\000other\000This event counts every cycle that one instruction is committed\000\000\000event=0x191\000\000\000\000\000\000\000\000This event counts every cycle that one instruction is committed\000 */
{ 18630 }, /* _2inst_commit\000\000other\000This event counts every cycle that two instructions are committed\000\000\000event=0x192\000\000\000\000\000\000\000\000This event counts every cycle that two instructions are committed\000 */
{ 18804 }, /* _3inst_commit\000\000other\000This event counts every cycle that three instructions are committed\000\000\000event=0x193\000\000\000\000\000\000\000\000This event counts every cycle that three instructions are committed\000 */
{ 18982 }, /* _4inst_commit\000\000other\000This event counts every cycle that four instructions are committed\000\000\000event=0x194\000\000\000\000\000\000\000\000This event counts every cycle that four instructions are committed\000 */
{ 22650 }, /* br_comp_wait\000\000other\000This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction\000\000\000event=0x18b\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction\000 */
{ 45797 }, /* ea_core\000\000other\000This event counts energy consumption per cycle of core\000\000\000event=0x1e0\000\000\000\000\000\000\000\000This event counts energy consumption per cycle of core\000 */
{ 47322 }, /* eu_comp_wait\000\000other\000This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction\000\000\000event=0x189\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction\000 */
{ 53300 }, /* fl_comp_wait\000\000other\000This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction\000\000\000event=0x18a\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction\000 */
{ 80184 }, /* l1hwpf_inj_alloc_pf\000\000other\000This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher\000\000\000event=0x231\000\000\000\000\000\000\000\000This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher\000 */
{ 80448 }, /* l1hwpf_inj_noalloc_pf\000\000other\000This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher\000\000\000event=0x232\000\000\000\000\000\000\000\000This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher\000 */
{ 80722 }, /* l1hwpf_stream_pf\000\000other\000This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher\000\000\000event=0x230\000\000\000\000\000\000\000\000This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher\000 */
{ 105742 }, /* l2hwpf_inj_alloc_pf\000\000other\000This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher\000\000\000event=0x234\000\000\000\000\000\000\000\000This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher\000 */
{ 106004 }, /* l2hwpf_inj_noalloc_pf\000\000other\000This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher\000\000\000event=0x235\000\000\000\000\000\000\000\000This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher\000 */
{ 106276 }, /* l2hwpf_other\000\000other\000This event counts prefetch requests to L2 cache generated by the other causes\000\000\000event=0x236\000\000\000\000\000\000\000\000This event counts prefetch requests to L2 cache generated by the other causes\000 */
{ 106473 }, /* l2hwpf_stream_pf\000\000other\000This event counts streaming prefetch requests to L2 cache generated by hardware prefecher\000\000\000event=0x233\000\000\000\000\000\000\000\000This event counts streaming prefetch requests to L2 cache generated by hardware prefecher\000 */
{ 112853 }, /* ld_comp_wait\000\000other\000This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access\000\000\000event=0x184\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access\000 */
{ 113248 }, /* ld_comp_wait_ex\000\000other\000This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access\000\000\000event=0x185\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access\000 */
{ 113632 }, /* ld_comp_wait_l1_miss\000\000other\000This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access\000\000\000event=0x182\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access\000 */
{ 113991 }, /* ld_comp_wait_l1_miss_ex\000\000other\000This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access\000\000\000event=0x183\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access\000 */
{ 114339 }, /* ld_comp_wait_l2_miss\000\000other\000This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access\000\000\000event=0x180\000\000\000\000\000\000\000\000This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access\000 */
{ 114690 }, /* ld_comp_wait_l2_miss_ex\000\000other\000This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access\000\000\000event=0x181\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access\000 */
{ 115034 }, /* ld_comp_wait_pfp_busy\000\000other\000This event counts every cycle that no instruction was committed due to the lack of an available prefetch port\000\000\000event=0x186\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed due to the lack of an available prefetch port\000 */
{ 115304 }, /* ld_comp_wait_pfp_busy_ex\000\000other\000This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation\000\000\000event=0x187\000\000\000\000\000\000\000\000This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation\000 */
{ 115517 }, /* ld_comp_wait_pfp_busy_swpf\000\000other\000This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction\000\000\000event=0x188\000\000\000\000\000\000\000\000This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction\000 */
{ 129762 }, /* rob_empty\000\000other\000This event counts every cycle that no instruction was committed because the CSE is empty\000\000\000event=0x18c\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the CSE is empty\000 */
{ 129978 }, /* rob_empty_stq_busy\000\000other\000This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full\000\000\000event=0x18d\000\000\000\000\000\000\000\000This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full\000 */
{ 132613 }, /* single_movprfx_commit\000\000other\000This event counts every cycle that only the MOVPRFX instruction is committed\000\000\000event=0x199\000\000\000\000\000\000\000\000This event counts every cycle that only the MOVPRFX instruction is committed\000 */
{ 158034 }, /* uop_only_commit\000\000other\000This event counts every cycle that only any micro-operations are committed\000\000\000event=0x198\000\000\000\000\000\000\000\000This event counts every cycle that only any micro-operations are committed\000 */
{ 158392 }, /* uop_split\000\000other\000This event counts the occurrence count of the micro-operation split\000\000\000event=0x139\000\000\000\000\000\000\000\000This event counts the occurrence count of the micro-operation split\000 */
{ 159002 }, /* wfe_wfi_cycle\000\000other\000This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction\000\000\000event=0x18e\000\000\000\000\000\000\000\000This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction\000 */
{ 46268 }, /* eaga_val\000\000pipeline\000This event counts valid cycles of EAGA pipeline\000\000\000event=0x1a0\000\000\000\000\000\000\000\000This event counts valid cycles of EAGA pipeline\000 */
{ 46404 }, /* eagb_val\000\000pipeline\000This event counts valid cycles of EAGB pipeline\000\000\000event=0x1a1\000\000\000\000\000\000\000\000This event counts valid cycles of EAGB pipeline\000 */
{ 47907 }, /* exa_val\000\000pipeline\000This event counts valid cycles of EXA pipeline\000\000\000event=0x1a2\000\000\000\000\000\000\000\000This event counts valid cycles of EXA pipeline\000 */
{ 48040 }, /* exb_val\000\000pipeline\000This event counts valid cycles of EXB pipeline\000\000\000event=0x1a3\000\000\000\000\000\000\000\000This event counts valid cycles of EXB pipeline\000 */
{ 53629 }, /* fla_val\000\000pipeline\000This event counts valid cycles of FLA pipeline\000\000\000event=0x1a4\000\000\000\000\000\000\000\000This event counts valid cycles of FLA pipeline\000 */
{ 53762 }, /* fla_val_prd_cnt\000\000pipeline\000This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1\000\000\000event=0x1b4\000\000\000\000\000\000\000\000This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 16 when all bits are 1\000 */
{ 54109 }, /* flb_val\000\000pipeline\000This event counts valid cycles of FLB pipeline\000\000\000event=0x1a5\000\000\000\000\000\000\000\000This event counts valid cycles of FLB pipeline\000 */
{ 54242 }, /* flb_val_prd_cnt\000\000pipeline\000This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1\000\000\000event=0x1b5\000\000\000\000\000\000\000\000This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 16 when all bits are 1\000 */
{ 67103 }, /* l1_pipe0_comp\000\000pipeline\000This event counts completed requests in L1D cache pipeline#0\000\000\000event=0x260\000\000\000\000\000\000\000\000This event counts completed requests in L1D cache pipeline#0\000 */
{ 67270 }, /* l1_pipe0_comp_prd_cnt\000\000pipeline\000This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1\000\000\000event=0x2b8\000\000\000\000\000\000\000\000This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 16 when all bits are 1\000 */
{ 67639 }, /* l1_pipe0_val\000\000pipeline\000This event counts valid cycles of L1D cache pipeline#0\000\000\000event=0x240\000\000\000\000\000\000\000\000This event counts valid cycles of L1D cache pipeline#0\000 */
{ 67793 }, /* l1_pipe0_val_iu_not_sec0\000\000pipeline\000This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0\000\000\000event=0x2a0\000\000\000\000\000\000\000\000This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0\000 */
{ 68019 }, /* l1_pipe0_val_iu_tag_adrs_pfe\000\000pipeline\000This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1\000\000\000event=0x251\000\000\000\000\000\000\000\000This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1\000 */
{ 68261 }, /* l1_pipe0_val_iu_tag_adrs_sce\000\000pipeline\000This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1\000\000\000event=0x250\000\000\000\000\000\000\000\000This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1\000 */
{ 68503 }, /* l1_pipe1_comp\000\000pipeline\000This event counts completed requests in L1D cache pipeline#1\000\000\000event=0x261\000\000\000\000\000\000\000\000This event counts completed requests in L1D cache pipeline#1\000 */
{ 68670 }, /* l1_pipe1_comp_prd_cnt\000\000pipeline\000This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1\000\000\000event=0x2b9\000\000\000\000\000\000\000\000This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 16 when all bits are 1\000 */
{ 69039 }, /* l1_pipe1_val\000\000pipeline\000This event counts valid cycles of L1D cache pipeline#1\000\000\000event=0x241\000\000\000\000\000\000\000\000This event counts valid cycles of L1D cache pipeline#1\000 */
{ 69193 }, /* l1_pipe1_val_iu_not_sec0\000\000pipeline\000This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0\000\000\000event=0x2a1\000\000\000\000\000\000\000\000This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0\000 */
{ 69419 }, /* l1_pipe1_val_iu_tag_adrs_pfe\000\000pipeline\000This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1\000\000\000event=0x253\000\000\000\000\000\000\000\000This event counts requests in L1D cache pipeline#1 that its pfe bit of tagged address is 1\000 */
{ 69661 }, /* l1_pipe1_val_iu_tag_adrs_sce\000\000pipeline\000This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1\000\000\000event=0x252\000\000\000\000\000\000\000\000This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1\000 */
{ 69903 }, /* l1_pipe_abort_stld_intlk\000\000pipeline\000This event counts aborted requests in L1D pipelines that due to store-load interlock\000\000\000event=0x274\000\000\000\000\000\000\000\000This event counts aborted requests in L1D pipelines that due to store-load interlock\000 */
{ 70129 }, /* l1_pipe_comp_gather_0flow\000\000pipeline\000This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0\000\000\000event=0x2b2\000\000\000\000\000\000\000\000This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0\000 */
{ 70450 }, /* l1_pipe_comp_gather_1flow\000\000pipeline\000This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined\000\000\000event=0x2b1\000\000\000\000\000\000\000\000This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined\000 */
{ 70773 }, /* l1_pipe_comp_gather_2flow\000\000pipeline\000This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined\000\000\000event=0x2b0\000\000\000\000\000\000\000\000This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined\000 */
{ 71106 }, /* l1_pipe_comp_scatter_1flow\000\000pipeline\000This event counts the number of flows of the scatter instructions\000\000\000event=0x2b3\000\000\000\000\000\000\000\000This event counts the number of flows of the scatter instructions\000 */
{ 82961 }, /* l1i_pipe_comp\000\000pipeline\000This event counts completed requests in L1I cache pipeline\000\000\000event=0x268\000\000\000\000\000\000\000\000This event counts completed requests in L1I cache pipeline\000 */
{ 83124 }, /* l1i_pipe_val\000\000pipeline\000This event counts valid cycles of L1I cache pipeline\000\000\000event=0x269\000\000\000\000\000\000\000\000This event counts valid cycles of L1I cache pipeline\000 */
{ 87812 }, /* l2_pipe_comp_all\000\000pipeline\000This event counts completed requests in L2 cache pipeline\000\000\000event=0x350\000\000\000\000\000\000\000\000This event counts completed requests in L2 cache pipeline\000 */
{ 87976 }, /* l2_pipe_comp_pf_l2mib_mch\000\000pipeline\000This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access\000\000\000event=0x370\000\000\000\000\000\000\000\000This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access\000 */
{ 88279 }, /* l2_pipe_val\000\000pipeline\000This event counts valid cycles of L2 cache pipeline\000\000\000event=0x330\000\000\000\000\000\000\000\000This event counts valid cycles of L2 cache pipeline\000 */
{ 126968 }, /* prx_val\000\000pipeline\000This event counts valid cycles of PRX pipeline\000\000\000event=0x1a6\000\000\000\000\000\000\000\000This event counts valid cycles of PRX pipeline\000 */
{ 134035 }, /* stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000No operation issued due to the backend\000 */
{ 143105 }, /* stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000No operation issued because of the frontend\000 */
{ 20502 }, /* ase_sve_int_spec\000\000sve\000Advanced SIMD and SVE integer Operations speculatively executed\000\000\000event=0x8043\000\000\000\000\000\000\000\000Advanced SIMD and SVE integer Operations speculatively executed\000 */
{ 20674 }, /* ase_sve_ld_multi_spec\000\000sve\000Advanced SIMD and SVE contiguous load multiple vector Operations speculatively executed\000\000\000event=0x80a5\000\000\000\000\000\000\000\000Advanced SIMD and SVE contiguous load multiple vector Operations speculatively executed\000 */
{ 20899 }, /* ase_sve_ld_spec\000\000sve\000Advanced SIMD and SVE load Operations speculatively executed\000\000\000event=0x8085\000\000\000\000\000\000\000\000Advanced SIMD and SVE load Operations speculatively executed\000 */
{ 21064 }, /* ase_sve_st_multi_spec\000\000sve\000Advanced SIMD and SVE contiguous store multiple vector Operations speculatively executed\000\000\000event=0x80a6\000\000\000\000\000\000\000\000Advanced SIMD and SVE contiguous store multiple vector Operations speculatively executed\000 */
{ 21291 }, /* ase_sve_st_spec\000\000sve\000Advanced SIMD and SVE store Operations speculatively executed\000\000\000event=0x8086\000\000\000\000\000\000\000\000Advanced SIMD and SVE store Operations speculatively executed\000 */
{ 21641 }, /* base_ld_reg_spec\000\000sve\000General-purpose register load Operations speculatively executed\000\000\000event=0x8089\000\000\000\000\000\000\000\000General-purpose register load Operations speculatively executed\000 */
{ 21813 }, /* base_st_reg_spec\000\000sve\000General-purpose register store Operations speculatively executed\000\000\000event=0x808a\000\000\000\000\000\000\000\000General-purpose register store Operations speculatively executed\000 */
{ 55091 }, /* fp_cvt_spec\000\000sve\000floating-point convert Operations speculatively executed\000\000\000event=0x8038\000\000\000\000\000\000\000\000floating-point convert Operations speculatively executed\000 */
{ 55244 }, /* fp_dp_fixed_ops_spec\000\000sve\000Non-scalable double-precision floating-point element Operations speculatively executed\000\000\000event=0x80c7\000\000\000\000\000\000\000\000Non-scalable double-precision floating-point element Operations speculatively executed\000 */
{ 55466 }, /* fp_dp_scale_ops_spec\000\000sve\000Scalable double-precision floating-point element Operations speculatively executed\000\000\000event=0x80c6\000\000\000\000\000\000\000\000Scalable double-precision floating-point element Operations speculatively executed\000 */
{ 56051 }, /* fp_fixed_ops_spec\000\000sve\000Non-scalable floating-point element Operations speculatively executed\000\000\000event=0x80c1\000\000\000\000\000\000\000\000Non-scalable floating-point element Operations speculatively executed\000 */
{ 56236 }, /* fp_fma_spec\000\000sve\000Floating-point FMA Operations speculatively executed\000\000\000event=0x8028\000\000\000\000\000\000\000\000Floating-point FMA Operations speculatively executed\000 */
{ 56381 }, /* fp_hp_fixed_ops_spec\000\000sve\000Non-scalable half-precision floating-point element Operations speculatively executed\000\000\000event=0x80c3\000\000\000\000\000\000\000\000Non-scalable half-precision floating-point element Operations speculatively executed\000 */
{ 56599 }, /* fp_hp_scale_ops_spec\000\000sve\000Scalable half-precision floating-point element Operations speculatively executed\000\000\000event=0x80c2\000\000\000\000\000\000\000\000Scalable half-precision floating-point element Operations speculatively executed\000 */
{ 57411 }, /* fp_recpe_spec\000\000sve\000Floating-point reciprocal estimate Operations speculatively executed\000\000\000event=0x8034\000\000\000\000\000\000\000\000Floating-point reciprocal estimate Operations speculatively executed\000 */
{ 57775 }, /* fp_scale_ops_spec\000\000sve\000Scalable floating-point element Operations speculatively executed\000\000\000event=0x80c0\000\000\000\000\000\000\000\000Scalable floating-point element Operations speculatively executed\000 */
{ 57952 }, /* fp_sp_fixed_ops_spec\000\000sve\000Non-scalable single-precision floating-point element Operations speculatively executed\000\000\000event=0x80c5\000\000\000\000\000\000\000\000Non-scalable single-precision floating-point element Operations speculatively executed\000 */
{ 58174 }, /* fp_sp_scale_ops_spec\000\000sve\000Scalable single-precision floating-point element Operations speculatively executed\000\000\000event=0x80c4\000\000\000\000\000\000\000\000Scalable single-precision floating-point element Operations speculatively executed\000 */
{ 58566 }, /* fp_spec\000\000sve\000Floating-point Operations speculatively executed\000\000\000event=0x8010\000\000\000\000\000\000\000\000Floating-point Operations speculatively executed\000 */
{ 126846 }, /* prf_spec\000\000sve\000Prefetch Operations speculatively executed\000\000\000event=0x8087\000\000\000\000\000\000\000\000Prefetch Operations speculatively executed\000 */
{ 132484 }, /* simd_inst_retired\000\000sve\000SIMD Instruction architecturally executed\000\000\000event=0x8000\000\000\000\000\000\000\000\000SIMD Instruction architecturally executed\000 */
{ 148262 }, /* sve_inst_retired\000\000sve\000Instruction architecturally executed, SVE\000\000\000event=0x8002\000\000\000\000\000\000\000\000Instruction architecturally executed, SVE\000 */
{ 148515 }, /* sve_ld_gather_spec\000\000sve\000SVE gather-load Operations speculatively executed\000\000\000event=0x80ad\000\000\000\000\000\000\000\000SVE gather-load Operations speculatively executed\000 */
{ 149031 }, /* sve_ldff_spec\000\000sve\000SVE First-fault load Operations speculatively executed\000\000\000event=0x80bc\000\000\000\000\000\000\000\000SVE First-fault load Operations speculatively executed\000 */
{ 149182 }, /* sve_ldr_preg_spec\000\000sve\000SVE load predicate register Operations speculatively executed\000\000\000event=0x8095\000\000\000\000\000\000\000\000SVE load predicate register Operations speculatively executed\000 */
{ 149351 }, /* sve_ldr_reg_spec\000\000sve\000SVE unpredicated load register Operations speculatively executed\000\000\000event=0x8091\000\000\000\000\000\000\000\000SVE unpredicated load register Operations speculatively executed\000 */
{ 149525 }, /* sve_math_spec\000\000sve\000SVE Math accelerator Operations speculatively executed\000\000\000event=0x800e\000\000\000\000\000\000\000\000SVE Math accelerator Operations speculatively executed\000 */
{ 149676 }, /* sve_movprfx_spec\000\000sve\000SVE MOVPRFX Operations speculatively executed\000\000\000event=0x807c\000\000\000\000\000\000\000\000SVE MOVPRFX Operations speculatively executed\000 */
{ 149812 }, /* sve_movprfx_u_spec\000\000sve\000SVE MOVPRFX unfused Operations speculatively executed\000\000\000event=0x807f\000\000\000\000\000\000\000\000SVE MOVPRFX unfused Operations speculatively executed\000 */
{ 150939 }, /* sve_pred_spec\000\000sve\000SVE predicated Operations speculatively executed\000\000\000event=0x8074\000\000\000\000\000\000\000\000SVE predicated Operations speculatively executed\000 */
{ 151078 }, /* sve_prf_contig_spec\000\000sve\000SVE contiguous prefetch element Operations speculatively executed\000\000\000event=0x809f\000\000\000\000\000\000\000\000SVE contiguous prefetch element Operations speculatively executed\000 */
{ 151257 }, /* sve_prf_gather_spec\000\000sve\000SVE gather-prefetch Operations speculatively executed\000\000\000event=0x80af\000\000\000\000\000\000\000\000SVE gather-prefetch Operations speculatively executed\000 */
{ 151412 }, /* sve_st_scatter_spec\000\000sve\000SVE scatter-store Operations speculatively executed\000\000\000event=0x80ae\000\000\000\000\000\000\000\000SVE scatter-store Operations speculatively executed\000 */
{ 151563 }, /* sve_str_preg_spec\000\000sve\000SVE store predicate register Operations speculatively executed\000\000\000event=0x8096\000\000\000\000\000\000\000\000SVE store predicate register Operations speculatively executed\000 */
{ 151734 }, /* sve_str_reg_spec\000\000sve\000SVE unpredicated store register Operations speculatively executed\000\000\000event=0x8092\000\000\000\000\000\000\000\000SVE unpredicated store register Operations speculatively executed\000 */
{ 158228 }, /* uop_spec\000\000sve\000Microarchitectural operation, Operations speculatively executed\000\000\000event=0x8008\000\000\000\000\000\000\000\000Microarchitectural operation, Operations speculatively executed\000 */
};

static const struct compact_pmu_event pme_arm_cortex_a55[] = {
{ 23018 }, /* br_cond_mis_pred\000\000branch\000Conditional branch mis-predicted.This event counts when any branch which can be predicted by the conditional predictor is retired, and has mis-predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches which correctly predicted the condition but mis-predicted on the address do not count this event\000\000\000event=0xcc\000\000\000\000\000\000\000\000Conditional branch mis-predicted.This event counts when any branch which can be predicted by the conditional predictor is retired, and has mis-predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches which correctly predicted the condition but mis-predicted on the address do not count this event\000 */
{ 25158 }, /* br_cond_pred\000\000branch\000Predicted conditional branch executed.This event counts when any branch which can be predicted by the conditional predictor is retired. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xc9\000\000\000\000\000\000\000\000Predicted conditional branch executed.This event counts when any branch which can be predicted by the conditional predictor is retired. This event still counts when branch prediction is disabled due to the MMU being off\000 */
{ 25798 }, /* br_immed_spec\000\000branch\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 26079 }, /* br_indirect_addr_mis_pred\000\000branch\000Indirect branch mis-predicted due to address mis-compare.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xcb\000\000\000\000\000\000\000\000Indirect branch mis-predicted due to address mis-compare.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000 */
{ 27995 }, /* br_indirect_addr_pred\000\000branch\000Indirect branch with predicted address executed.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xcd\000\000\000\000\000\000\000\000Indirect branch with predicted address executed.This event counts when any indirect branch which can be predicted by the BTAC is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000 */
{ 28587 }, /* br_indirect_mis_pred\000\000branch\000Indirect branch mis-predicted.This event counts when any indirect branch which can be predicted by the BTAC is retired, and has mispredicted for either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xca\000\000\000\000\000\000\000\000Indirect branch mis-predicted.This event counts when any indirect branch which can be predicted by the BTAC is retired, and has mispredicted for either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off\000 */
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 31890 }, /* br_return_addr_mis_pred\000\000branch\000Procedure return mis-predicted due to address mis-compare.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xcf\000\000\000\000\000\000\000\000Procedure return mis-predicted due to address mis-compare.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000 */
{ 33862 }, /* br_return_addr_pred\000\000branch\000Procedure return with predicted address executed.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xce\000\000\000\000\000\000\000\000Procedure return with predicted address executed.This event counts when any procedure return which can be predicted by the CRS is retired, was taken and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000 */
{ 34668 }, /* br_return_spec\000\000branch\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 45496 }, /* dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000Access to data TLB causes a translation table walk\000 */
{ 66317 }, /* itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000Access to instruction TLB that causes a translation table walk\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 73655 }, /* l1d_cache_refill_inner\000\000cache\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000 */
{ 73902 }, /* l1d_cache_refill_outer\000\000cache\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000 */
{ 74478 }, /* l1d_cache_refill_prefetch\000\000cache\000Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache\000\000\000event=0xc2\000\000\000\000\000\000\000\000Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache\000 */
{ 75011 }, /* l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75248 }, /* l1d_cache_refill_wr\000\000cache\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 76972 }, /* l1d_tlb\000\000cache\000Attributable Level 1 data or unified TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 79202 }, /* l1d_ws_mode\000\000cache\000Level 1 data cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L1 D-cache\000\000\000event=0xc5\000\000\000\000\000\000\000\000Level 1 data cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L1 D-cache\000 */
{ 79923 }, /* l1d_ws_mode_entry\000\000cache\000Level 1 data cache entering write streaming mode.This event counts for each entry into write-streaming mode\000\000\000event=0xc4\000\000\000\000\000\000\000\000Level 1 data cache entering write streaming mode.This event counts for each entry into write-streaming mode\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83274 }, /* l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB access\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 88772 }, /* l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000Attributable Level 2 data cache allocation without refill\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 92059 }, /* l2d_cache_refill_prefetch\000\000cache\000Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented\000\000\000event=0xc1\000\000\000\000\000\000\000\000Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented\000 */
{ 93050 }, /* l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93287 }, /* l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 95854 }, /* l2d_cache_stash_dropped\000\000cache\000Level 2 cache stash dropped.This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request\000\000\000event=0xd6\000\000\000\000\000\000\000\000Level 2 cache stash dropped.This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 97887 }, /* l2d_l2walk_tlb\000\000cache\000Level 2 TLB level-2 walk cache access.This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled\000\000\000event=0xd2\000\000\000\000\000\000\000\000Level 2 TLB level-2 walk cache access.This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled\000 */
{ 98481 }, /* l2d_l2walk_tlb_refill\000\000cache\000Level 2 TLB level-2 walk cache refill.This event does not count if the MMU is disabled\000\000\000event=0xd3\000\000\000\000\000\000\000\000Level 2 TLB level-2 walk cache refill.This event does not count if the MMU is disabled\000 */
{ 98704 }, /* l2d_llwalk_tlb\000\000cache\000Level 2 TLB last-level walk cache access.This event does not count if the MMU is disabled\000\000\000event=0xd0\000\000\000\000\000\000\000\000Level 2 TLB last-level walk cache access.This event does not count if the MMU is disabled\000 */
{ 98926 }, /* l2d_llwalk_tlb_refill\000\000cache\000Level 2 TLB last-level walk cache refill.This event does not count if the MMU is disabled\000\000\000event=0xd1\000\000\000\000\000\000\000\000Level 2 TLB last-level walk cache refill.This event does not count if the MMU is disabled\000 */
{ 100457 }, /* l2d_s2_tlb\000\000cache\000Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count\000\000\000event=0xd4\000\000\000\000\000\000\000\000Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count\000 */
{ 101572 }, /* l2d_s2_tlb_refill\000\000cache\000Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count\000\000\000event=0xd5\000\000\000\000\000\000\000\000Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count\000 */
{ 102443 }, /* l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access\000 */
{ 103449 }, /* l2d_tlb_refill\000\000cache\000Attributable Level 2 data TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000Attributable Level 2 data TLB refill\000 */
{ 105044 }, /* l2d_ws_mode\000\000cache\000Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache\000\000\000event=0xc3\000\000\000\000\000\000\000\000Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache\000 */
{ 108575 }, /* l3d_cache\000\000cache\000Attributable Level 3 data cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000Attributable Level 3 data cache access\000 */
{ 109142 }, /* l3d_cache_allocate\000\000cache\000Attributable Level 3 data cache allocation without refill\000\000\000event=0x29\000\000\000\000\000\000\000\000Attributable Level 3 data cache allocation without refill\000 */
{ 109857 }, /* l3d_cache_rd\000\000cache\000Attributable Level 3 data or unified cache access, read\000\000\000event=0xa0\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache access, read\000 */
{ 110009 }, /* l3d_cache_refill\000\000cache\000Attributable Level 3 data cache refill\000\000\000event=0x2a\000\000\000\000\000\000\000\000Attributable Level 3 data cache refill\000 */
{ 110477 }, /* l3d_cache_refill_prefetch\000\000cache\000Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to both distinguish hardware vs software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented\000\000\000event=0xc0\000\000\000\000\000\000\000\000Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to both distinguish hardware vs software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented\000 */
{ 111522 }, /* l3d_cache_refill_rd\000\000cache\000Attributable Level 3 data or unified cache refill, read\000\000\000event=0xa2\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache refill, read\000 */
{ 112375 }, /* l3d_ws_mode\000\000cache\000Level 3 cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache\000\000\000event=0xc7\000\000\000\000\000\000\000\000Level 3 cache write streaming mode.This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache\000 */
{ 116870 }, /* ll_cache_miss_rd\000\000cache\000Last level cache miss, read\000\000\000event=0x37\000\000\000\000\000\000\000\000Last level cache miss, read\000 */
{ 116970 }, /* ll_cache_rd\000\000cache\000Attributable Last level cache memory read\000\000\000event=0x36\000\000\000\000\000\000\000\000Attributable Last level cache memory read\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 120089 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000 */
{ 126323 }, /* predecode_error\000\000exception\000Predecode error\000\000\000event=0xc6\000\000\000\000\000\000\000\000Predecode error\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 25639 }, /* br_immed_retired\000\000instruction\000Instruction architecturally executed, immediate branch\000\000\000event=0xd\000\000\000\000\000\000\000\000Instruction architecturally executed, immediate branch\000 */
{ 30824 }, /* br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000Instruction architecturally executed, mispredicted branch\000 */
{ 31554 }, /* br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000Instruction architecturally executed, branch\000 */
{ 34454 }, /* br_return_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, procedure return\000\000\000event=0xe\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, procedure return\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 115851 }, /* ld_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, load\000\000\000event=0x6\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, load\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116604 }, /* ldst_spec\000\000instruction\000Operation speculatively executed, load or store\000\000\000event=0x72\000\000\000\000\000\000\000\000Operation speculatively executed, load or store\000 */
{ 124412 }, /* pc_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, software change of the PC\000\000\000event=0xc\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, software change of the PC\000 */
{ 124643 }, /* pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000 */
{ 133483 }, /* st_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, store\000\000\000event=0x7\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, store\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 129020 }, /* remote_access_rd\000\000memory\000Attributable memory read access to another socket in a multi-socket system\000\000\000event=0x38\000\000\000\000\000\000\000\000Attributable memory read access to another socket in a multi-socket system\000 */
{ 156679 }, /* unaligned_ldst_retired\000\000memory\000Instruction architecturally executed, condition code check pass, unaligned\000\000\000event=0xf\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, unaligned\000 */
{ 134035 }, /* stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000No operation issued due to the backend\000 */
{ 134804 }, /* stall_backend_ilock\000\000pipeline\000No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded\000\000\000event=0xe4\000\000\000\000\000\000\000\000No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded\000 */
{ 136005 }, /* stall_backend_ilock_agu\000\000pipeline\000No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded\000\000\000event=0xe5\000\000\000\000\000\000\000\000No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded\000 */
{ 136669 }, /* stall_backend_ilock_fpu\000\000pipeline\000No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded\000\000\000event=0xe6\000\000\000\000\000\000\000\000No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded\000 */
{ 138106 }, /* stall_backend_ld\000\000pipeline\000No operation issued due to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load\000\000\000event=0xe7\000\000\000\000\000\000\000\000No operation issued due to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load\000 */
{ 138982 }, /* stall_backend_ld_cache\000\000pipeline\000No operation issued due to the backend, load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)\000\000\000event=0xe9\000\000\000\000\000\000\000\000No operation issued due to the backend, load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)\000 */
{ 139834 }, /* stall_backend_ld_tlb\000\000pipeline\000No operation issued due to the backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load which has missed in the L1 TLB\000\000\000event=0xea\000\000\000\000\000\000\000\000No operation issued due to the backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load which has missed in the L1 TLB\000 */
{ 140765 }, /* stall_backend_st\000\000pipeline\000No operation issued due to the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store\000\000\000event=0xe8\000\000\000\000\000\000\000\000No operation issued due to the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store\000 */
{ 141060 }, /* stall_backend_st_stb\000\000pipeline\000No operation issued due to the backend, store, STB full.This event counts every cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full\000\000\000event=0xeb\000\000\000\000\000\000\000\000No operation issued due to the backend, store, STB full.This event counts every cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full\000 */
{ 142361 }, /* stall_backend_st_tlb\000\000pipeline\000No operation issued due to the backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a store which has missed in the L1 TLB\000\000\000event=0xec\000\000\000\000\000\000\000\000No operation issued due to the backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a store which has missed in the L1 TLB\000 */
{ 143105 }, /* stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000No operation issued because of the frontend\000 */
{ 143873 }, /* stall_frontend_cache\000\000pipeline\000No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed\000\000\000event=0xe1\000\000\000\000\000\000\000\000No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed\000 */
{ 144238 }, /* stall_frontend_pderr\000\000pipeline\000No operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed\000\000\000event=0xe3\000\000\000\000\000\000\000\000No operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed\000 */
{ 145171 }, /* stall_frontend_tlb\000\000pipeline\000No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed\000\000\000event=0xe2\000\000\000\000\000\000\000\000No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed\000 */
};

static const struct compact_pmu_event pme_arm_cortex_x1[] = {
{ 25798 }, /* br_immed_spec\000\000branch\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 34668 }, /* br_return_spec\000\000branch\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 39149 }, /* cnt_cycles\000\000bus\000Constant frequency cycles\000\000\000event=0x4004\000\000\000\000\000\000\000\000Constant frequency cycles.  The counter increments at a constant frequency equal to the rate of increment of the system counter, CNTPCT_EL0\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 45496 }, /* dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000Access to data TLB causes a translation table walk\000 */
{ 66317 }, /* itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000Access to instruction TLB that causes a translation table walk\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72009 }, /* l1d_cache_inval\000\000cache\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000 */
{ 72327 }, /* l1d_cache_lmiss_rd\000\000cache\000Level 1 data cache long-latency read miss\000\000\000event=0x39\000\000\000\000\000\000\000\000Level 1 data cache long-latency read miss.  The counter counts each memory read access counted by L1D_CACHE that incurs additional latency because it returns data from outside the Level 1 data or unified cache of this processing element\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 73655 }, /* l1d_cache_refill_inner\000\000cache\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000 */
{ 73902 }, /* l1d_cache_refill_outer\000\000cache\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000 */
{ 75011 }, /* l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75248 }, /* l1d_cache_refill_wr\000\000cache\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 75865 }, /* l1d_cache_wb_clean\000\000cache\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000 */
{ 76162 }, /* l1d_cache_wb_victim\000\000cache\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 76972 }, /* l1d_tlb\000\000cache\000Attributable Level 1 data or unified TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access\000 */
{ 77503 }, /* l1d_tlb_rd\000\000cache\000L1D tlb access, read\000\000\000event=0x4e\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, read\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 78051 }, /* l1d_tlb_refill_rd\000\000cache\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000 */
{ 78276 }, /* l1d_tlb_refill_wr\000\000cache\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000 */
{ 78505 }, /* l1d_tlb_wr\000\000cache\000L1D tlb access, write\000\000\000event=0x4f\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, write\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 81421 }, /* l1i_cache_lmiss\000\000cache\000Level 1 instruction cache long-latency read miss\000\000\000event=0x4006\000\000\000\000\000\000\000\000Level 1 instruction cache long-latency read miss.  If the L1I_CACHE_RD event is implemented, the counter counts each access counted by L1I_CACHE_RD that incurs additional latency because it returns instructions from outside of the Level 1 instruction cache of this PE.  If the L1I_CACHE_RD event is not implemented, the counter counts each access counted by L1I_CACHE that incurs additional latency because it returns instructions from outside the Level 1 instruction cache of this PE.  The event indicates to software that the access missed in the Level 1 instruction cache and might have a significant performance impact due to the additional latency, compared to the latency of an access that hits in the Level 1 instruction cache\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83274 }, /* l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB access\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 88772 }, /* l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000Attributable Level 2 data cache allocation without refill\000 */
{ 89220 }, /* l2d_cache_inval\000\000cache\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000 */
{ 89441 }, /* l2d_cache_lmiss_rd\000\000cache\000Level 2 data cache long-latency read miss\000\000\000event=0x4009\000\000\000\000\000\000\000\000Level 2 data cache long-latency read miss.  The counter counts each memory read access counted by L2D_CACHE that incurs additional latency because it returns data from outside the Level 2 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 2 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 2 data or unified cache\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 93050 }, /* l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93287 }, /* l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97102 }, /* l2d_cache_wb_clean\000\000cache\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000 */
{ 97399 }, /* l2d_cache_wb_victim\000\000cache\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 102443 }, /* l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access\000 */
{ 102985 }, /* l2d_tlb_rd\000\000cache\000L2D cache access, read\000\000\000event=0x5e\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, read\000 */
{ 103449 }, /* l2d_tlb_refill\000\000cache\000Attributable Level 2 data TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000Attributable Level 2 data TLB refill\000 */
{ 103565 }, /* l2d_tlb_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x5c\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, read\000 */
{ 103816 }, /* l2d_tlb_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x5d\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, write\000 */
{ 104071 }, /* l2d_tlb_wr\000\000cache\000L2D cache access, write\000\000\000event=0x5f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, write\000 */
{ 108575 }, /* l3d_cache\000\000cache\000Attributable Level 3 data cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000Attributable Level 3 data cache access\000 */
{ 109142 }, /* l3d_cache_allocate\000\000cache\000Attributable Level 3 data cache allocation without refill\000\000\000event=0x29\000\000\000\000\000\000\000\000Attributable Level 3 data cache allocation without refill\000 */
{ 109304 }, /* l3d_cache_lmiss_rd\000\000cache\000Level 3 data cache long-latency read miss\000\000\000event=0x400b\000\000\000\000\000\000\000\000Level 3 data cache long-latency read miss.  The counter counts each memory read access counted by L3D_CACHE that incurs additional latency because it returns data from outside the Level 3 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 3 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 3 data or unified cache\000 */
{ 109857 }, /* l3d_cache_rd\000\000cache\000Attributable Level 3 data or unified cache access, read\000\000\000event=0xa0\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache access, read\000 */
{ 110009 }, /* l3d_cache_refill\000\000cache\000Attributable Level 3 data cache refill\000\000\000event=0x2a\000\000\000\000\000\000\000\000Attributable Level 3 data cache refill\000 */
{ 116870 }, /* ll_cache_miss_rd\000\000cache\000Last level cache miss, read\000\000\000event=0x37\000\000\000\000\000\000\000\000Last level cache miss, read\000 */
{ 116970 }, /* ll_cache_rd\000\000cache\000Attributable Last level cache memory read\000\000\000event=0x36\000\000\000\000\000\000\000\000Attributable Last level cache memory read\000 */
{ 48296 }, /* exc_dabort\000\000exception\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48766 }, /* exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 49228 }, /* exc_pabort\000\000exception\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000 */
{ 49848 }, /* exc_smc\000\000exception\000Exception taken, Secure Monitor Call\000\000\000event=0x88\000\000\000\000\000\000\000\000Exception taken, Secure Monitor Call\000 */
{ 50069 }, /* exc_svc\000\000exception\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 50408 }, /* exc_trap_dabort\000\000exception\000Exception taken, Data Abort or SError not taken locally\000\000\000event=0x8c\000\000\000\000\000\000\000\000Exception taken, Data Abort or SError not taken locally\000 */
{ 50692 }, /* exc_trap_fiq\000\000exception\000Exception taken, FIQ not taken locally\000\000\000event=0x8f\000\000\000\000\000\000\000\000Exception taken, FIQ not taken locally\000 */
{ 51825 }, /* exc_trap_irq\000\000exception\000Exception taken, IRQ not taken locally\000\000\000event=0x8e\000\000\000\000\000\000\000\000Exception taken, IRQ not taken locally\000 */
{ 52090 }, /* exc_trap_other\000\000exception\000Exception taken, Other traps not taken locally\000\000\000event=0x8d\000\000\000\000\000\000\000\000Exception taken, Other traps not taken locally\000 */
{ 52386 }, /* exc_trap_pabort\000\000exception\000Exception taken, Instruction Abort not taken locally\000\000\000event=0x8b\000\000\000\000\000\000\000\000Exception taken, Instruction Abort not taken locally\000 */
{ 52653 }, /* exc_undef\000\000exception\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000 */
{ 120089 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 30824 }, /* br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000Instruction architecturally executed, mispredicted branch\000 */
{ 31554 }, /* br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000Instruction architecturally executed, branch\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 43623 }, /* dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 45327 }, /* dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116153 }, /* ldrex_spec\000\000instruction\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000 */
{ 122928 }, /* op_retired\000\000instruction\000Micro-operation architecturally executed\000\000\000event=0x3a\000\000\000\000\000\000\000\000Micro-operation architecturally executed.  The counter counts each operation counted by OP_SPEC that would be executed in a simple sequential execution of the program\000 */
{ 123180 }, /* op_spec\000\000instruction\000Micro-operation speculatively executed\000\000\000event=0x3b\000\000\000\000\000\000\000\000Micro-operation speculatively executed.  The counter counts the number of operations executed by the processing element, including those that are executed speculatively and would not be executed in a simple sequential execution of the program\000 */
{ 124643 }, /* pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000 */
{ 127257 }, /* rc_ld_spec\000\000instruction\000Release consistency operation speculatively executed, Load-Acquire\000\000\000event=0x90\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Load-Acquire\000 */
{ 127435 }, /* rc_st_spec\000\000instruction\000Release consistency operation speculatively executed, Store-Release\000\000\000event=0x91\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Store-Release\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 147124 }, /* strex_fail_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000 */
{ 147468 }, /* strex_pass_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX pass\000\000\000event=0x6d\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX pass\000 */
{ 147812 }, /* strex_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX\000\000\000event=0x6f\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 128878 }, /* remote_access\000\000memory\000Access to another socket in a multi-socket system\000\000\000event=0x31\000\000\000\000\000\000\000\000Access to another socket in a multi-socket system\000 */
{ 156587 }, /* unaligned_ld_spec\000\000memory\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000 */
{ 156967 }, /* unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 157149 }, /* unaligned_st_spec\000\000memory\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000 */
{ 133789 }, /* stall\000\000pipeline\000No operation sent for execution\000\000\000event=0x3c\000\000\000\000\000\000\000\000No operation sent for execution.  The counter counts every attributable cycle on which no attributable instruction or operation was sent for execution on this processing element\000 */
{ 134035 }, /* stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000No operation issued due to the backend\000 */
{ 140211 }, /* stall_backend_mem\000\000pipeline\000Memory stall cycles\000\000\000event=0x4005\000\000\000\000\000\000\000\000Memory stall cycles.  The counter counts each cycle counted by STALL_BACKEND where there is a cache miss in the last level of cache within the processing element clock domain\000 */
{ 143105 }, /* stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000No operation issued because of the frontend\000 */
{ 145656 }, /* stall_slot\000\000pipeline\000No operation sent for execution on a slot\000\000\000event=0x3f\000\000\000\000\000\000\000\000No operation sent for execution on a slot.  The counter counts on each attributable cycle the number of instruction or operation slots that were not occupied by an instruction or operation attributable to the processing element\000 */
{ 145967 }, /* stall_slot_backend\000\000pipeline\000No operation sent for execution on a slot due to the backend\000\000\000event=0x3d\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the backend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because the backend is unable to accept it\000 */
{ 146613 }, /* stall_slot_frontend\000\000pipeline\000No operation sent for execution on a slot due to the frontend\000\000\000event=0x3e\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the frontend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because there was no attributable instruction or operation available to issue from the processing element from the frontend for the slot\000 */
};

static const struct compact_pmu_event pme_arm_cortex_a76_n1[] = {
{ 30535 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000This event counts any predictable branch instruction which is mispredicted either due to dynamic misprediction or because the MMU is off and the branches are statically predicted not taken\000 */
{ 31336 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000This event counts all predictable branches\000 */
{ 35129 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000This event counts for every beat of data transferred over the data channels between the core and the SCU. If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD and BUS_ACCESS_WR\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36261 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000This event duplicates CPU_CYCLES\000 */
{ 40820 }, /* cpu_cycles\000\000bus\000The number of core clock cycles\000\000\000event=0x11\000\000\000\000\000\000\000\000The number of core clock cycles\000 */
{ 45635 }, /* dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000This event counts on any data access which causes L2D_TLB_REFILL to count\000 */
{ 66480 }, /* itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000This event counts on any instruction access which causes L2D_TLB_REFILL to count\000 */
{ 71482 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000This event counts any load or store operation or page table walk access which looks up in the L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL event causes this event to count\000 */
{ 72009 }, /* l1d_cache_inval\000\000cache\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 73072 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000This event counts any load or store operation or page table walk access which causes data to be read from outside the L1, including accesses which do not allocate into L1\000 */
{ 73655 }, /* l1d_cache_refill_inner\000\000cache\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000 */
{ 73902 }, /* l1d_cache_refill_outer\000\000cache\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000 */
{ 75011 }, /* l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75248 }, /* l1d_cache_refill_wr\000\000cache\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 75615 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000This event counts any write-back of data from the L1 data cache to L2 or L3. This counts both victim line evictions and snoops, including cache maintenance operations\000 */
{ 75865 }, /* l1d_cache_wb_clean\000\000cache\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000 */
{ 76162 }, /* l1d_cache_wb_victim\000\000cache\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 77230 }, /* l1d_tlb\000\000cache\000Level 1 data TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000This event counts any load or store operation which accesses the data L1 TLB. If both a load and a store are executed on a cycle, this event counts twice. This event counts regardless of whether the MMU is enabled\000 */
{ 77503 }, /* l1d_tlb_rd\000\000cache\000L1D tlb access, read\000\000\000event=0x4e\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, read\000 */
{ 77851 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000This event counts any refill of the data L1 TLB from the L2 TLB. This includes refills that result in a translation fault\000 */
{ 78051 }, /* l1d_tlb_refill_rd\000\000cache\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000 */
{ 78276 }, /* l1d_tlb_refill_wr\000\000cache\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000 */
{ 78505 }, /* l1d_tlb_wr\000\000cache\000L1D tlb access, write\000\000\000event=0x4f\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, write\000 */
{ 81080 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Level 1 instruction cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which accesses the L1 instruction cache or L0 Macro-op cache\000 */
{ 82649 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000This event counts any instruction fetch which misses in the cache\000 */
{ 83554 }, /* l1i_tlb\000\000cache\000Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000This event counts any instruction fetch which accesses the instruction L1 TLB.This event counts regardless of whether the MMU is enabled\000 */
{ 83886 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000This event counts any refill of the instruction L1 TLB from the L2 TLB. This includes refills that result in a translation fault\000 */
{ 88515 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000This event counts any transaction from L1 which looks up in the L2 cache, and any write-back from the L1 to the L2. Snoops from outside the core and cache maintenance operations are not counted\000 */
{ 88934 }, /* l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000This event counts any full cache line write into the L2 cache which does not cause a linefill, including write-backs from L1 to L2 and full-line writes which do not allocate into L1\000 */
{ 89220 }, /* l2d_cache_inval\000\000cache\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90614 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted\000 */
{ 93050 }, /* l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93287 }, /* l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 96712 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000This event counts any write-back of data from the L2 cache to outside the core. This includes snoops to the L2 which return data, regardless of whether they cause an invalidation. Invalidations from the L2 which do not write data outside of the core and snoops which return data from the L1 are not counted\000 */
{ 97102 }, /* l2d_cache_wb_clean\000\000cache\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000 */
{ 97399 }, /* l2d_cache_wb_victim\000\000cache\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 102574 }, /* l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000This event counts on any access to the L2 TLB (caused by a refill of any of the L1 TLBs). This event does not count if the MMU is disabled\000 */
{ 102985 }, /* l2d_tlb_rd\000\000cache\000L2D cache access, read\000\000\000event=0x5e\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, read\000 */
{ 103222 }, /* l2d_tlb_refill\000\000cache\000Attributable L2 data or unified TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000This event counts on anyrefill of the L2 TLB, caused by either an instruction or data access.This event does not count if the MMU is disabled\000 */
{ 103565 }, /* l2d_tlb_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x5c\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, read\000 */
{ 103816 }, /* l2d_tlb_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x5d\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, write\000 */
{ 104071 }, /* l2d_tlb_wr\000\000cache\000L2D cache access, write\000\000\000event=0x5f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, write\000 */
{ 108690 }, /* l3d_cache\000\000cache\000Attributable Level 3 unified cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000This event counts for any cacheable read transaction returning datafrom the SCU, or for any cacheable write to the SCU\000 */
{ 108888 }, /* l3d_cache_allocate\000\000cache\000Allocation without refill\000\000\000event=0x29\000\000\000\000\000\000\000\000This event counts any full cache line write into the L3 cache which does not cause a linefill, including write-backs from L2 to L3 and full-line writes which do not allocate into L2\000 */
{ 109857 }, /* l3d_cache_rd\000\000cache\000Attributable Level 3 data or unified cache access, read\000\000\000event=0xa0\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache access, read\000 */
{ 110131 }, /* l3d_cache_refill\000\000cache\000Attributable Level 3 unified cache refill\000\000\000event=0x2a\000\000\000\000\000\000\000\000This event counts for any cacheable read transaction returning datafrom the SCU for which the data source was outside the cluster. Transactions such as ReadUnique are counted here as 'read' transactions, even though they can be generated by store instructions\000 */
{ 116870 }, /* ll_cache_miss_rd\000\000cache\000Last level cache miss, read\000\000\000event=0x37\000\000\000\000\000\000\000\000Last level cache miss, read\000 */
{ 116970 }, /* ll_cache_rd\000\000cache\000Attributable Last level cache memory read\000\000\000event=0x36\000\000\000\000\000\000\000\000Attributable Last level cache memory read\000 */
{ 48296 }, /* exc_dabort\000\000exception\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48766 }, /* exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 49228 }, /* exc_pabort\000\000exception\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000 */
{ 49848 }, /* exc_smc\000\000exception\000Exception taken, Secure Monitor Call\000\000\000event=0x88\000\000\000\000\000\000\000\000Exception taken, Secure Monitor Call\000 */
{ 50069 }, /* exc_svc\000\000exception\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 50408 }, /* exc_trap_dabort\000\000exception\000Exception taken, Data Abort or SError not taken locally\000\000\000event=0x8c\000\000\000\000\000\000\000\000Exception taken, Data Abort or SError not taken locally\000 */
{ 50692 }, /* exc_trap_fiq\000\000exception\000Exception taken, FIQ not taken locally\000\000\000event=0x8f\000\000\000\000\000\000\000\000Exception taken, FIQ not taken locally\000 */
{ 51825 }, /* exc_trap_irq\000\000exception\000Exception taken, IRQ not taken locally\000\000\000event=0x8e\000\000\000\000\000\000\000\000Exception taken, IRQ not taken locally\000 */
{ 52090 }, /* exc_trap_other\000\000exception\000Exception taken, Other traps not taken locally\000\000\000event=0x8d\000\000\000\000\000\000\000\000Exception taken, Other traps not taken locally\000 */
{ 52386 }, /* exc_trap_pabort\000\000exception\000Exception taken, Instruction Abort not taken locally\000\000\000event=0x8b\000\000\000\000\000\000\000\000Exception taken, Instruction Abort not taken locally\000 */
{ 52653 }, /* exc_undef\000\000exception\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000 */
{ 120171 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 25936 }, /* br_immed_spec\000\000instruction\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 30111 }, /* br_indirect_spec\000\000instruction\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30993 }, /* br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush\000 */
{ 31688 }, /* br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches\000 */
{ 34807 }, /* br_return_spec\000\000instruction\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 38744 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 43623 }, /* dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 45327 }, /* dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 65555 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000This event counts all retired instructions, including those that fail their condition check\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116153 }, /* ldrex_spec\000\000instruction\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000 */
{ 116604 }, /* ldst_spec\000\000instruction\000Operation speculatively executed, load or store\000\000\000event=0x72\000\000\000\000\000\000\000\000Operation speculatively executed, load or store\000 */
{ 124643 }, /* pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000 */
{ 127257 }, /* rc_ld_spec\000\000instruction\000Release consistency operation speculatively executed, Load-Acquire\000\000\000event=0x90\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Load-Acquire\000 */
{ 127435 }, /* rc_st_spec\000\000instruction\000Release consistency operation speculatively executed, Store-Release\000\000\000event=0x91\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Store-Release\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 147124 }, /* strex_fail_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000 */
{ 147468 }, /* strex_pass_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX pass\000\000\000event=0x6d\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX pass\000 */
{ 147812 }, /* strex_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX\000\000\000event=0x6f\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 156015 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 118336 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000This event counts memory accesses due to load or store instructions. This event counts the sum of MEM_ACCESS_RD and MEM_ACCESS_WR\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 128878 }, /* remote_access\000\000memory\000Access to another socket in a multi-socket system\000\000\000event=0x31\000\000\000\000\000\000\000\000Access to another socket in a multi-socket system\000 */
{ 156587 }, /* unaligned_ld_spec\000\000memory\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000 */
{ 156967 }, /* unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 157149 }, /* unaligned_st_spec\000\000memory\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000 */
{ 134157 }, /* stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000The counter counts on any cycle fetched instructions are not dispatched due to resource constraints\000 */
{ 143238 }, /* stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000The counter counts on any cycle when there are no fetched instructions available to dispatch\000 */
};

static const struct compact_pmu_event pme_arm_cortex_a53[] = {
{ 22953 }, /* br_cond\000\000branch\000Conditional branch executed\000\000\000event=0xc9\000\000\000\000\000\000\000\000\000 */
{ 24566 }, /* br_cond_mispred\000\000branch\000Conditional branch mispredicted\000\000\000event=0xcc\000\000\000\000\000\000\000\000\000 */
{ 29781 }, /* br_indirect_mispred\000\000branch\000Indirect branch mispredicted\000\000\000event=0xca\000\000\000\000\000\000\000\000\000 */
{ 29859 }, /* br_indirect_mispred_addr\000\000branch\000Indirect branch mispredicted because of address miscompare\000\000\000event=0xcb\000\000\000\000\000\000\000\000\000 */
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 53088 }, /* ext_snoop\000\000cache\000SCU Snooped data from another CPU for this CPU\000\000\000event=0xc8\000\000\000\000\000\000\000\000\000 */
{ 126588 }, /* prefetch_linefill\000\000cache\000Linefill because of prefetch\000\000\000event=0xc2\000\000\000\000\000\000\000\000\000 */
{ 126663 }, /* prefetch_linefill_drop\000\000cache\000Instruction Cache Throttle occurred\000\000\000event=0xc3\000\000\000\000\000\000\000\000\000 */
{ 128747 }, /* read_alloc\000\000cache\000Read allocate mode\000\000\000event=0xc5\000\000\000\000\000\000\000\000\000 */
{ 128805 }, /* read_alloc_enter\000\000cache\000Entering read allocate mode\000\000\000event=0xc4\000\000\000\000\000\000\000\000\000 */
{ 52941 }, /* ext_mem_req\000\000memory\000External memory request\000\000\000event=0xc0\000\000\000\000\000\000\000\000\000 */
{ 53006 }, /* ext_mem_req_nc\000\000memory\000Non-cacheable external memory request\000\000\000event=0xc1\000\000\000\000\000\000\000\000\000 */
{ 48581 }, /* exc_fiq\000\000other\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 49036 }, /* exc_irq\000\000other\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 71887 }, /* l1d_cache_err\000\000other\000L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable\000\000\000event=0xd1\000\000\000\000\000\000\000\000\000 */
{ 81331 }, /* l1i_cache_err\000\000other\000L1 Instruction Cache (data or tag) memory error\000\000\000event=0xd0\000\000\000\000\000\000\000\000\000 */
{ 126016 }, /* pre_decode_err\000\000other\000Pre-decode error\000\000\000event=0xc6\000\000\000\000\000\000\000\000\000 */
{ 152622 }, /* tlb_err\000\000other\000TLB memory error\000\000\000event=0xd2\000\000\000\000\000\000\000\000\000 */
{ 19278 }, /* agu_dep_stall\000\000pipeline\000Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU\000\000\000event=0xe5\000\000\000\000\000\000\000\000\000 */
{ 43177 }, /* decode_dep_stall\000\000pipeline\000Cycles the DPU IQ is empty and there is a pre-decode error being processed\000\000\000event=0xe3\000\000\000\000\000\000\000\000\000 */
{ 59643 }, /* ic_dep_stall\000\000pipeline\000Cycles the DPU IQ is empty and there is an instruction cache miss being processed\000\000\000event=0xe1\000\000\000\000\000\000\000\000\000 */
{ 66661 }, /* iutlb_dep_stall\000\000pipeline\000Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed\000\000\000event=0xe2\000\000\000\000\000\000\000\000\000 */
{ 115744 }, /* ld_dep_stall\000\000pipeline\000Cycles there is a stall in the Wr stage because of a load miss\000\000\000event=0xe7\000\000\000\000\000\000\000\000\000 */
{ 123503 }, /* other_interlock_stall\000\000pipeline\000Cycles there is an interlock other than  Advanced SIMD/Floating-point instructions or load/store instruction\000\000\000event=0xe4\000\000\000\000\000\000\000\000\000 */
{ 123665 }, /* other_iq_dep_stall\000\000pipeline\000Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error\000\000\000event=0xe0\000\000\000\000\000\000\000\000\000 */
{ 132363 }, /* simd_dep_stall\000\000pipeline\000Cycles there is an interlock for an Advanced SIMD/Floating-point operation\000\000\000event=0xe6\000\000\000\000\000\000\000\000\000 */
{ 133380 }, /* st_dep_stall\000\000pipeline\000Cycles there is a stall in the Wr stage because of a store\000\000\000event=0xe8\000\000\000\000\000\000\000\000\000 */
{ 145532 }, /* stall_sb_full\000\000pipeline\000Data Write operation that stalls the pipeline because the store buffer is full\000\000\000event=0xc7\000\000\000\000\000\000\000\000\000 */
};

static const struct compact_pmu_event pme_arm_cortex_a510[] = {
{ 23823 }, /* br_cond_mis_pred\000\000branch\000Conditional branch mispredicted. This event counts when any branch that the conditional predictor can predict is retired and has mispredicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches that correctly predict the condition but mispredict the address do not count\000\000\000event=0xcc\000\000\000\000\000\000\000\000Conditional branch mispredicted. This event counts when any branch that the conditional predictor can predict is retired and has mispredicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches that correctly predict the condition but mispredict the address do not count\000 */
{ 24643 }, /* br_cond_pred\000\000branch\000Predicted conditional branch executed. This event counts when any branch that the conditional predictor can predict is retired. This event still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off\000\000\000event=0xc9\000\000\000\000\000\000\000\000Predicted conditional branch executed. This event counts when any branch that the conditional predictor can predict is retired. This event still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off\000 */
{ 25798 }, /* br_immed_spec\000\000branch\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 26761 }, /* br_indirect_addr_mis_pred\000\000branch\000Indirect branch mispredicted due to address miscompare. This event counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xcb\000\000\000\000\000\000\000\000Indirect branch mispredicted due to address miscompare. This event counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000 */
{ 27417 }, /* br_indirect_addr_pred\000\000branch\000Indirect branch with predicted address executed. This event counts when any indirect branch that the BTAC can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xcd\000\000\000\000\000\000\000\000Indirect branch with predicted address executed. This event counts when any indirect branch that the BTAC can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000 */
{ 29168 }, /* br_indirect_mis_pred\000\000branch\000Indirect branch mispredicted. This event counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired and has mispredicted either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xca\000\000\000\000\000\000\000\000Indirect branch mispredicted. This event counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired and has mispredicted either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off\000 */
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 32572 }, /* br_return_addr_mis_pred\000\000branch\000Procedure return mispredicted due to address miscompare. This event counts when any procedure return that the call-return stack can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xcf\000\000\000\000\000\000\000\000Procedure return mispredicted due to address miscompare. This event counts when any procedure return that the call-return stack can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off\000 */
{ 33256 }, /* br_return_addr_pred\000\000branch\000Procedure return with predicted address executed. This event counts when any procedure return that the call-return stack can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000\000\000event=0xce\000\000\000\000\000\000\000\000Procedure return with predicted address executed. This event counts when any procedure return that the call-return stack can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off\000 */
{ 34668 }, /* br_return_spec\000\000branch\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 45496 }, /* dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000Access to data TLB causes a translation table walk\000 */
{ 66317 }, /* itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000Access to instruction TLB that causes a translation table walk\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72327 }, /* l1d_cache_lmiss_rd\000\000cache\000Level 1 data cache long-latency read miss\000\000\000event=0x39\000\000\000\000\000\000\000\000Level 1 data cache long-latency read miss.  The counter counts each memory read access counted by L1D_CACHE that incurs additional latency because it returns data from outside the Level 1 data or unified cache of this processing element\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 73655 }, /* l1d_cache_refill_inner\000\000cache\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000 */
{ 73902 }, /* l1d_cache_refill_outer\000\000cache\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000 */
{ 74149 }, /* l1d_cache_refill_prefetch\000\000cache\000L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that cause an allocation into the L1 data cache\000\000\000event=0xc2\000\000\000\000\000\000\000\000L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that cause an allocation into the L1 data cache\000 */
{ 75011 }, /* l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75248 }, /* l1d_cache_refill_wr\000\000cache\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 76972 }, /* l1d_tlb\000\000cache\000Attributable Level 1 data or unified TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 78742 }, /* l1d_ws_mode\000\000cache\000L1 data cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L1 data cache\000\000\000event=0xc5\000\000\000\000\000\000\000\000L1 data cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L1 data cache\000 */
{ 79670 }, /* l1d_ws_mode_entry\000\000cache\000L1 data cache entering write streaming mode. This event counts for each entry into write streaming mode\000\000\000event=0xc4\000\000\000\000\000\000\000\000L1 data cache entering write streaming mode. This event counts for each entry into write streaming mode\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 81421 }, /* l1i_cache_lmiss\000\000cache\000Level 1 instruction cache long-latency read miss\000\000\000event=0x4006\000\000\000\000\000\000\000\000Level 1 instruction cache long-latency read miss.  If the L1I_CACHE_RD event is implemented, the counter counts each access counted by L1I_CACHE_RD that incurs additional latency because it returns instructions from outside of the Level 1 instruction cache of this PE.  If the L1I_CACHE_RD event is not implemented, the counter counts each access counted by L1I_CACHE that incurs additional latency because it returns instructions from outside the Level 1 instruction cache of this PE.  The event indicates to software that the access missed in the Level 1 instruction cache and might have a significant performance impact due to the additional latency, compared to the latency of an access that hits in the Level 1 instruction cache\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83274 }, /* l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB access\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 88772 }, /* l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000Attributable Level 2 data cache allocation without refill\000 */
{ 89441 }, /* l2d_cache_lmiss_rd\000\000cache\000Level 2 data cache long-latency read miss\000\000\000event=0x4009\000\000\000\000\000\000\000\000Level 2 data cache long-latency read miss.  The counter counts each memory read access counted by L2D_CACHE that incurs additional latency because it returns data from outside the Level 2 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 2 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 2 data or unified cache\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 91290 }, /* l2d_cache_refill_prefetch\000\000cache\000L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event does not count. If the complex is configured without a per-complex L2 cache, this event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. If neither a per-complex cache or a cluster cache is configured, this event is not implemented\000\000\000event=0xc1\000\000\000\000\000\000\000\000L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event does not count. If the complex is configured without a per-complex L2 cache, this event counts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. If neither a per-complex cache or a cluster cache is configured, this event is not implemented\000 */
{ 93050 }, /* l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93287 }, /* l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 93528 }, /* l2d_cache_stash_dropped\000\000cache\000L2 cache stash dropped. This event counts on each stash request that is received from the interconnect or the Accelerator Coherency Port (ACP), that targets L2 cache and is dropped due to lack of buffer space to hold the request\000\000\000event=0xd6\000\000\000\000\000\000\000\000L2 cache stash dropped. This event counts on each stash request that is received from the interconnect or the Accelerator Coherency Port (ACP), that targets L2 cache and is dropped due to lack of buffer space to hold the request\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 99925 }, /* l2d_s2_tlb\000\000cache\000L2 TLB IPA cache access. This event counts on each access to the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 translation is disabled, this event does not count\000\000\000event=0xd4\000\000\000\000\000\000\000\000L2 TLB IPA cache access. This event counts on each access to the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 translation is disabled, this event does not count\000 */
{ 100991 }, /* l2d_s2_tlb_refill\000\000cache\000L2 TLB IPA cache refill. This event counts on each refill of the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 translation is disabled, this event does not count\000\000\000event=0xd5\000\000\000\000\000\000\000\000L2 TLB IPA cache refill. This event counts on each refill of the IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 translation is disabled, this event does not count\000 */
{ 102443 }, /* l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access\000 */
{ 103449 }, /* l2d_tlb_refill\000\000cache\000Attributable Level 2 data TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000Attributable Level 2 data TLB refill\000 */
{ 104312 }, /* l2d_walk_tlb\000\000cache\000L2 TLB walk cache access. This event does not count if the MMU is disabled\000\000\000event=0xd0\000\000\000\000\000\000\000\000L2 TLB walk cache access. This event does not count if the MMU is disabled\000 */
{ 104502 }, /* l2d_walk_tlb_refill\000\000cache\000L2 TLB walk cache refill. This event does not count if the MMU is disabled\000\000\000event=0xd1\000\000\000\000\000\000\000\000L2 TLB walk cache refill. This event does not count if the MMU is disabled\000 */
{ 104699 }, /* l2d_ws_mode\000\000cache\000L2 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L2 cache\000\000\000event=0xc3\000\000\000\000\000\000\000\000L2 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L2 cache\000 */
{ 108575 }, /* l3d_cache\000\000cache\000Attributable Level 3 data cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000Attributable Level 3 data cache access\000 */
{ 109304 }, /* l3d_cache_lmiss_rd\000\000cache\000Level 3 data cache long-latency read miss\000\000\000event=0x400b\000\000\000\000\000\000\000\000Level 3 data cache long-latency read miss.  The counter counts each memory read access counted by L3D_CACHE that incurs additional latency because it returns data from outside the Level 3 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 3 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 3 data or unified cache\000 */
{ 109857 }, /* l3d_cache_rd\000\000cache\000Attributable Level 3 data or unified cache access, read\000\000\000event=0xa0\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache access, read\000 */
{ 111522 }, /* l3d_cache_refill_rd\000\000cache\000Attributable Level 3 data or unified cache refill, read\000\000\000event=0xa2\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache refill, read\000 */
{ 111681 }, /* l3d_ws_mode\000\000cache\000L3 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L3 cache\000\000\000event=0xc7\000\000\000\000\000\000\000\000L3 cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the L3 cache\000 */
{ 116870 }, /* ll_cache_miss_rd\000\000cache\000Last level cache miss, read\000\000\000event=0x37\000\000\000\000\000\000\000\000Last level cache miss, read\000 */
{ 116970 }, /* ll_cache_rd\000\000cache\000Attributable Last level cache memory read\000\000\000event=0x36\000\000\000\000\000\000\000\000Attributable Last level cache memory read\000 */
{ 117093 }, /* ll_ws_mode\000\000cache\000Last level cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the system cache\000\000\000event=0xc8\000\000\000\000\000\000\000\000Last level cache write streaming mode. This event counts for each cycle where the core is in write streaming mode and is not allocating writes into the system cache\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 120089 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 19721 }, /* ase_sve_int16_spec\000\000instruction\000Advanced SIMD and SVE 16-bit integer operations speculatively executed\000\000\000event=0x80e7\000\000\000\000\000\000\000\000Advanced SIMD and SVE 16-bit integer operations speculatively executed\000 */
{ 19917 }, /* ase_sve_int32_spec\000\000instruction\000Advanced SIMD and SVE 32-bit integer operations speculatively executed\000\000\000event=0x80eb\000\000\000\000\000\000\000\000Advanced SIMD and SVE 32-bit integer operations speculatively executed\000 */
{ 20113 }, /* ase_sve_int64_spec\000\000instruction\000Advanced SIMD and SVE 64-bit integer operations speculatively executed\000\000\000event=0x80ef\000\000\000\000\000\000\000\000Advanced SIMD and SVE 64-bit integer operations speculatively executed\000 */
{ 20309 }, /* ase_sve_int8_spec\000\000instruction\000Advanced SIMD and SVE 8-bit integer operations speculatively executed\000\000\000event=0x80e3\000\000\000\000\000\000\000\000Advanced SIMD and SVE 8-bit integer operations speculatively executed\000 */
{ 25639 }, /* br_immed_retired\000\000instruction\000Instruction architecturally executed, immediate branch\000\000\000event=0xd\000\000\000\000\000\000\000\000Instruction architecturally executed, immediate branch\000 */
{ 30824 }, /* br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000Instruction architecturally executed, mispredicted branch\000 */
{ 31554 }, /* br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000Instruction architecturally executed, branch\000 */
{ 34454 }, /* br_return_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, procedure return\000\000\000event=0xe\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, procedure return\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 55680 }, /* fp_dp_spec\000\000instruction\000Floating-point double-precision operations speculatively executed\000\000\000event=0x801c\000\000\000\000\000\000\000\000Floating-point double-precision operations speculatively executed\000 */
{ 56809 }, /* fp_hp_spec\000\000instruction\000Floating-point half-precision operations speculatively executed\000\000\000event=0x8014\000\000\000\000\000\000\000\000Floating-point half-precision operations speculatively executed\000 */
{ 58388 }, /* fp_sp_spec\000\000instruction\000Floating-point single-precision operations speculatively executed\000\000\000event=0x8018\000\000\000\000\000\000\000\000Floating-point single-precision operations speculatively executed\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 115851 }, /* ld_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, load\000\000\000event=0x6\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, load\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116604 }, /* ldst_spec\000\000instruction\000Operation speculatively executed, load or store\000\000\000event=0x72\000\000\000\000\000\000\000\000Operation speculatively executed, load or store\000 */
{ 122928 }, /* op_retired\000\000instruction\000Micro-operation architecturally executed\000\000\000event=0x3a\000\000\000\000\000\000\000\000Micro-operation architecturally executed.  The counter counts each operation counted by OP_SPEC that would be executed in a simple sequential execution of the program\000 */
{ 123180 }, /* op_spec\000\000instruction\000Micro-operation speculatively executed\000\000\000event=0x3b\000\000\000\000\000\000\000\000Micro-operation speculatively executed.  The counter counts the number of operations executed by the processing element, including those that are executed speculatively and would not be executed in a simple sequential execution of the program\000 */
{ 124412 }, /* pc_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, software change of the PC\000\000\000event=0xc\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, software change of the PC\000 */
{ 124643 }, /* pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000 */
{ 133483 }, /* st_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, store\000\000\000event=0x7\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, store\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 148126 }, /* sve_inst_retired\000\000instruction\000Instruction architecturally executed, SVE\000\000\000event=0x8002\000\000\000\000\000\000\000\000Instruction architecturally executed, SVE\000 */
{ 148390 }, /* sve_inst_spec\000\000instruction\000SVE operations speculatively executed\000\000\000event=0x8006\000\000\000\000\000\000\000\000SVE operations speculatively executed\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 112722 }, /* ld_align_lat\000\000memory\000Load with additional latency from alignment\000\000\000event=0x4021\000\000\000\000\000\000\000\000Load with additional latency from alignment\000 */
{ 116467 }, /* ldst_align_lat\000\000memory\000Access with additional latency from alignment\000\000\000event=0x4020\000\000\000\000\000\000\000\000Access with additional latency from alignment\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118524 }, /* mem_access_checked\000\000memory\000Checked data memory access\000\000\000event=0x4024\000\000\000\000\000\000\000\000Checked data memory access\000 */
{ 118627 }, /* mem_access_checked_rd\000\000memory\000Checked data memory access, read\000\000\000event=0x4025\000\000\000\000\000\000\000\000Checked data memory access, read\000 */
{ 118745 }, /* mem_access_checked_wr\000\000memory\000Checked data memory access, write\000\000\000event=0x4026\000\000\000\000\000\000\000\000Checked data memory access, write\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 129020 }, /* remote_access_rd\000\000memory\000Attributable memory read access to another socket in a multi-socket system\000\000\000event=0x38\000\000\000\000\000\000\000\000Attributable memory read access to another socket in a multi-socket system\000 */
{ 133247 }, /* st_align_lat\000\000memory\000Store with additional latency from alignment\000\000\000event=0x4022\000\000\000\000\000\000\000\000Store with additional latency from alignment\000 */
{ 133789 }, /* stall\000\000pipeline\000No operation sent for execution\000\000\000event=0x3c\000\000\000\000\000\000\000\000No operation sent for execution.  The counter counts every attributable cycle on which no attributable instruction or operation was sent for execution on this processing element\000 */
{ 134035 }, /* stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000No operation issued due to the backend\000 */
{ 134340 }, /* stall_backend_ilock\000\000pipeline\000No operation issued due to the backend interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded\000\000\000event=0xe4\000\000\000\000\000\000\000\000No operation issued due to the backend interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded\000 */
{ 135266 }, /* stall_backend_ilock_addr\000\000pipeline\000No operation issued due to the backend, address interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock on an address operand. This type of interlock is caused by a load/store instruction waiting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded\000\000\000event=0xe5\000\000\000\000\000\000\000\000No operation issued due to the backend, address interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock on an address operand. This type of interlock is caused by a load/store instruction waiting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded\000 */
{ 137245 }, /* stall_backend_ilock_vpu\000\000pipeline\000No operation issued due to the backend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an interlock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded\000\000\000event=0xe6\000\000\000\000\000\000\000\000No operation issued due to the backend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an interlock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded\000 */
{ 137801 }, /* stall_backend_ld\000\000pipeline\000No operation issued due to the backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load\000\000\000event=0xe7\000\000\000\000\000\000\000\000No operation issued due to the backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load\000 */
{ 138397 }, /* stall_backend_ld_cache\000\000pipeline\000No operation issued due to the backend, load, cache miss. This event counts every cycle where there is a stall in the Wr stage due to a load that is waiting on data. The event counts for stalls that are caused by missing the cache or where the data is Non-cacheable\000\000\000event=0xe9\000\000\000\000\000\000\000\000No operation issued due to the backend, load, cache miss. This event counts every cycle where there is a stall in the Wr stage due to a load that is waiting on data. The event counts for stalls that are caused by missing the cache or where the data is Non-cacheable\000 */
{ 139453 }, /* stall_backend_ld_tlb\000\000pipeline\000No operation issued due to the backend, load, TLB miss. This event counts every cycle where there is a stall in the Wr stage due to a load that misses in the L1 TLB\000\000\000event=0xea\000\000\000\000\000\000\000\000No operation issued due to the backend, load, TLB miss. This event counts every cycle where there is a stall in the Wr stage due to a load that misses in the L1 TLB\000 */
{ 140211 }, /* stall_backend_mem\000\000pipeline\000Memory stall cycles\000\000\000event=0x4005\000\000\000\000\000\000\000\000Memory stall cycles.  The counter counts each cycle counted by STALL_BACKEND where there is a cache miss in the last level of cache within the processing element clock domain\000 */
{ 140456 }, /* stall_backend_st\000\000pipeline\000No operation issued due to the backend, store. This event counts every cycle where there is a stall in the Wr stage due to a store\000\000\000event=0xe8\000\000\000\000\000\000\000\000No operation issued due to the backend, store. This event counts every cycle where there is a stall in the Wr stage due to a store\000 */
{ 141465 }, /* stall_backend_st_stb\000\000pipeline\000No operation issued due to the backend, store, Store Buffer (STB) full. This event counts every cycle where there is a stall in the Wr stage because of a store operation that is waiting due to the STB being full\000\000\000event=0xeb\000\000\000\000\000\000\000\000No operation issued due to the backend, store, Store Buffer (STB) full. This event counts every cycle where there is a stall in the Wr stage because of a store operation that is waiting due to the STB being full\000 */
{ 141940 }, /* stall_backend_st_tlb\000\000pipeline\000No operation issued due to the backend, store, TLB miss. This event counts every cycle where there is a stall in the Wr stage because of a store operation that has missed in the L1 TLB\000\000\000event=0xec\000\000\000\000\000\000\000\000No operation issued due to the backend, store, TLB miss. This event counts every cycle where there is a stall in the Wr stage because of a store operation that has missed in the L1 TLB\000 */
{ 142742 }, /* stall_backend_vpu_hazard\000\000pipeline\000No operation issued due to the backend, VPU hazard. This event counts every cycle where the core stalls due to contention for the VPU with the other core\000\000\000event=0xed\000\000\000\000\000\000\000\000No operation issued due to the backend, VPU hazard. This event counts every cycle where the core stalls due to contention for the VPU with the other core\000 */
{ 143105 }, /* stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000No operation issued because of the frontend\000 */
{ 143420 }, /* stall_frontend_cache\000\000pipeline\000No operation issued due to the frontend, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue is empty and there is an instruction cache miss being processed\000\000\000event=0xe1\000\000\000\000\000\000\000\000No operation issued due to the frontend, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue is empty and there is an instruction cache miss being processed\000 */
{ 144601 }, /* stall_frontend_pderr\000\000pipeline\000No operation issued due to the frontend, pre-decode error\000\000\000event=0xe3\000\000\000\000\000\000\000\000No operation issued due to the frontend, pre-decode error\000 */
{ 144768 }, /* stall_frontend_tlb\000\000pipeline\000No operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty and there is an instruction L1 TLB miss being processed\000\000\000event=0xe2\000\000\000\000\000\000\000\000No operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty and there is an instruction L1 TLB miss being processed\000 */
{ 145656 }, /* stall_slot\000\000pipeline\000No operation sent for execution on a slot\000\000\000event=0x3f\000\000\000\000\000\000\000\000No operation sent for execution on a slot.  The counter counts on each attributable cycle the number of instruction or operation slots that were not occupied by an instruction or operation attributable to the processing element\000 */
{ 145967 }, /* stall_slot_backend\000\000pipeline\000No operation sent for execution on a slot due to the backend\000\000\000event=0x3d\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the backend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because the backend is unable to accept it\000 */
{ 146292 }, /* stall_slot_backend_ilock\000\000pipeline\000Issue slot not issued due to interlock. For each cycle, this event counts each dispatch slot that does not issue due to an interlock\000\000\000event=0xee\000\000\000\000\000\000\000\000Issue slot not issued due to interlock. For each cycle, this event counts each dispatch slot that does not issue due to an interlock\000 */
{ 146613 }, /* stall_slot_frontend\000\000pipeline\000No operation sent for execution on a slot due to the frontend\000\000\000event=0x3e\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the frontend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because there was no attributable instruction or operation available to issue from the processing element from the frontend for the slot\000 */
{ 125164 }, /* pmu_hovfs\000\000pmu\000PMU overflow, counters reserved for use by EL2\000\000\000event=0x400f\000\000\000\000\000\000\000\000PMU overflow, counters reserved for use by EL2\000 */
{ 125295 }, /* pmu_ovfs\000\000pmu\000PMU overflow, counters accessible to EL1 and EL0\000\000\000event=0x400d\000\000\000\000\000\000\000\000PMU overflow, counters accessible to EL1 and EL0\000 */
{ 41211 }, /* cti_trigout4\000\000trace\000Cross-trigger Interface output trigger 4\000\000\000event=0x4018\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 4\000 */
{ 41335 }, /* cti_trigout5\000\000trace\000Cross-trigger Interface output trigger 5 \000\000\000event=0x4019\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 5 \000 */
{ 41461 }, /* cti_trigout6\000\000trace\000Cross-trigger Interface output trigger 6\000\000\000event=0x401a\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 6\000 */
{ 41585 }, /* cti_trigout7\000\000trace\000Cross-trigger Interface output trigger 7\000\000\000event=0x401b\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 7\000 */
{ 155173 }, /* trb_trig\000\000trace\000Trace buffer Trigger Event\000\000\000event=0x400e\000\000\000\000\000\000\000\000Trace buffer Trigger Event\000 */
{ 155265 }, /* trb_wrap\000\000trace\000Trace buffer current write pointer wrapped\000\000\000event=0x400c\000\000\000\000\000\000\000\000Trace buffer current write pointer wrapped\000 */
{ 155389 }, /* trcextout0\000\000trace\000PE Trace Unit external output 0\000\000\000event=0x4010\000\000\000\000\000\000\000\000PE Trace Unit external output 0\000 */
{ 155493 }, /* trcextout1\000\000trace\000PE Trace Unit external output 1\000\000\000event=0x4011\000\000\000\000\000\000\000\000PE Trace Unit external output 1\000 */
{ 155597 }, /* trcextout2\000\000trace\000PE Trace Unit external output 2\000\000\000event=0x4012\000\000\000\000\000\000\000\000PE Trace Unit external output 2\000 */
{ 155701 }, /* trcextout3\000\000trace\000PE Trace Unit external output 3\000\000\000event=0x4013\000\000\000\000\000\000\000\000PE Trace Unit external output 3\000 */
};

static const struct compact_pmu_event pme_arm_cortex_a75[] = {
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 45496 }, /* dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000Access to data TLB causes a translation table walk\000 */
{ 59203 }, /* i_btac_ram_rd\000\000cache\000Number of ways read in the instruction BTAC RAM\000\000\000event=0xc4\000\000\000\000\000\000\000\000Number of ways read in the instruction BTAC RAM\000 */
{ 59340 }, /* i_data_ram_rd\000\000cache\000Number of ways read in the instruction cache - Data RAM\000\000\000event=0xc3\000\000\000\000\000\000\000\000Number of ways read in the instruction cache - Data RAM\000 */
{ 59493 }, /* i_tag_ram_rd\000\000cache\000Number of ways read in the instruction cache - Tag RAM\000\000\000event=0xc2\000\000\000\000\000\000\000\000Number of ways read in the instruction cache - Tag RAM\000 */
{ 66317 }, /* itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000Access to instruction TLB that causes a translation table walk\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 71751 }, /* l1d_cache_allocate\000\000cache\000Level 1 data cache allocation without refill\000\000\000event=0x1f\000\000\000\000\000\000\000\000Level 1 data cache allocation without refill\000 */
{ 72009 }, /* l1d_cache_inval\000\000cache\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 75865 }, /* l1d_cache_wb_clean\000\000cache\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000 */
{ 76162 }, /* l1d_cache_wb_victim\000\000cache\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 76972 }, /* l1d_tlb\000\000cache\000Attributable Level 1 data or unified TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83274 }, /* l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB access\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 84100 }, /* l1pld_tlb\000\000cache\000Level 1 preload TLB access. This event only counts software and hardware prefetches at Level 1. This event counts all accesses to the preload data micro TLB, that is L1 prefetcher and preload instructions. This event does not take into account whether the MMU is enabled or not\000\000\000event=0xeb\000\000\000\000\000\000\000\000Level 1 preload TLB access. This event only counts software and hardware prefetches at Level 1. This event counts all accesses to the preload data micro TLB, that is L1 prefetcher and preload instructions. This event does not take into account whether the MMU is enabled or not\000 */
{ 84693 }, /* l1pld_tlb_refill\000\000cache\000Level 1 PLD TLB refill\000\000\000event=0xe7\000\000\000\000\000\000\000\000Level 1 PLD TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 88772 }, /* l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000Attributable Level 2 data cache allocation without refill\000 */
{ 89220 }, /* l2d_cache_inval\000\000cache\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97102 }, /* l2d_cache_wb_clean\000\000cache\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000 */
{ 97399 }, /* l2d_cache_wb_victim\000\000cache\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 102443 }, /* l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access\000 */
{ 103449 }, /* l2d_tlb_refill\000\000cache\000Attributable Level 2 data TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000Attributable Level 2 data TLB refill\000 */
{ 106698 }, /* l2i_tlb\000\000cache\000Attributable Level 2 instruction TLB access\000\000\000event=0x30\000\000\000\000\000\000\000\000Attributable Level 2 instruction TLB access\000 */
{ 107154 }, /* l2pld_tlb\000\000cache\000Level 2 preload and MMU prefetcher TLB access. This event only counts software and hardware prefetches at Level 2\000\000\000event=0xe8\000\000\000\000\000\000\000\000Level 2 preload and MMU prefetcher TLB access. This event only counts software and hardware prefetches at Level 2\000 */
{ 108575 }, /* l3d_cache\000\000cache\000Attributable Level 3 data cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000Attributable Level 3 data cache access\000 */
{ 109142 }, /* l3d_cache_allocate\000\000cache\000Attributable Level 3 data cache allocation without refill\000\000\000event=0x29\000\000\000\000\000\000\000\000Attributable Level 3 data cache allocation without refill\000 */
{ 109857 }, /* l3d_cache_rd\000\000cache\000Attributable Level 3 data or unified cache access, read\000\000\000event=0xa0\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache access, read\000 */
{ 110009 }, /* l3d_cache_refill\000\000cache\000Attributable Level 3 data cache refill\000\000\000event=0x2a\000\000\000\000\000\000\000\000Attributable Level 3 data cache refill\000 */
{ 111522 }, /* l3d_cache_refill_rd\000\000cache\000Attributable Level 3 data or unified cache refill, read\000\000\000event=0xa2\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache refill, read\000 */
{ 116870 }, /* ll_cache_miss_rd\000\000cache\000Last level cache miss, read\000\000\000event=0x37\000\000\000\000\000\000\000\000Last level cache miss, read\000 */
{ 116970 }, /* ll_cache_rd\000\000cache\000Attributable Last level cache memory read\000\000\000event=0x36\000\000\000\000\000\000\000\000Attributable Last level cache memory read\000 */
{ 124899 }, /* pldtlb_walk\000\000cache\000Prefetch access to unified TLB that caused a page table walk. This event counts software and hardware prefetches\000\000\000event=0xec\000\000\000\000\000\000\000\000Prefetch access to unified TLB that caused a page table walk. This event counts software and hardware prefetches\000 */
{ 152546 }, /* tlb_access\000\000cache\000Level 2 TLB access\000\000\000event=0xea\000\000\000\000\000\000\000\000Level 2 TLB access\000 */
{ 158566 }, /* utlb_flush\000\000cache\000Level 1 TLB flush\000\000\000event=0xe9\000\000\000\000\000\000\000\000Level 1 TLB flush\000 */
{ 47150 }, /* etm_ext_out0\000\000etm\000ETM trace unit output 0\000\000\000event=0xde\000\000\000\000\000\000\000\000ETM trace unit output 0\000 */
{ 47236 }, /* etm_ext_out1\000\000etm\000ETM trace unit output 1\000\000\000event=0xdf\000\000\000\000\000\000\000\000ETM trace unit output 1\000 */
{ 48766 }, /* exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 50918 }, /* exc_trap_hyp\000\000exception\000Number of traps to hypervisor. This event counts the number of exception traps taken to EL2, excluding HVC instructions. This event is set every time that an exception is executed because of a decoded trap to the hypervisor. CCFAIL exceptions and traps caused by HVC instructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1\000\000\000event=0xdc\000\000\000\000\000\000\000\000Number of traps to hypervisor. This event counts the number of exception traps taken to EL2, excluding HVC instructions. This event is set every time that an exception is executed because of a decoded trap to the hypervisor. CCFAIL exceptions and traps caused by HVC instructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1\000 */
{ 52653 }, /* exc_undef\000\000exception\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 25639 }, /* br_immed_retired\000\000instruction\000Instruction architecturally executed, immediate branch\000\000\000event=0xd\000\000\000\000\000\000\000\000Instruction architecturally executed, immediate branch\000 */
{ 31554 }, /* br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000Instruction architecturally executed, branch\000 */
{ 34454 }, /* br_return_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, procedure return\000\000\000event=0xe\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, procedure return\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 43623 }, /* dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 45327 }, /* dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116153 }, /* ldrex_spec\000\000instruction\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000 */
{ 116604 }, /* ldst_spec\000\000instruction\000Operation speculatively executed, load or store\000\000\000event=0x72\000\000\000\000\000\000\000\000Operation speculatively executed, load or store\000 */
{ 124412 }, /* pc_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, software change of the PC\000\000\000event=0xc\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, software change of the PC\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 147124 }, /* strex_fail_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000 */
{ 147468 }, /* strex_pass_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX pass\000\000\000event=0x6d\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX pass\000 */
{ 147812 }, /* strex_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX\000\000\000event=0x6f\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 129020 }, /* remote_access_rd\000\000memory\000Attributable memory read access to another socket in a multi-socket system\000\000\000event=0x38\000\000\000\000\000\000\000\000Attributable memory read access to another socket in a multi-socket system\000 */
{ 156967 }, /* unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 120508 }, /* mmu_ptw\000\000mmu\000Duration of a translation table walk handled by the MMU\000\000\000event=0xe0\000\000\000\000\000\000\000\000Duration of a translation table walk handled by the MMU\000 */
{ 120915 }, /* mmu_ptw_cp15\000\000mmu\000Duration of a translation table walk requested by an address translation operation\000\000\000event=0xe6\000\000\000\000\000\000\000\000Duration of a translation table walk requested by an address translation operation\000 */
{ 121300 }, /* mmu_ptw_iside\000\000mmu\000Duration of a translation table walk requested by the instruction side\000\000\000event=0xe4\000\000\000\000\000\000\000\000Duration of a translation table walk requested by the instruction side\000 */
{ 121481 }, /* mmu_ptw_lsu\000\000mmu\000Duration of a translation table walk requested by the LSU\000\000\000event=0xe3\000\000\000\000\000\000\000\000Duration of a translation table walk requested by the LSU\000 */
{ 121634 }, /* mmu_ptw_pld\000\000mmu\000Duration of a translation table walk requested by a Preload instruction or Prefetch request\000\000\000event=0xe5\000\000\000\000\000\000\000\000Duration of a translation table walk requested by a Preload instruction or Prefetch request\000 */
{ 121855 }, /* mmu_ptw_st1\000\000mmu\000Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1\000\000\000event=0xe1\000\000\000\000\000\000\000\000Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1\000 */
{ 122337 }, /* mmu_ptw_st2\000\000mmu\000Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1\000\000\000event=0xe2\000\000\000\000\000\000\000\000Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1\000 */
{ 41709 }, /* d_lsu_slot_full\000\000pipeline\000Duration for which all slots in the Load-Store Unit (LSU) are busy\000\000\000event=0xd3\000\000\000\000\000\000\000\000Duration for which all slots in the Load-Store Unit (LSU) are busy\000 */
{ 42620 }, /* de_iq_full\000\000pipeline\000Duration for which all slots in the data engine issue queue are busy. This event is set every time that the data engine rename has at least one valid instruction, excluding No Operations (NOPs), that cannot move to the issue stage because accpt_instr is LOW\000\000\000event=0xda\000\000\000\000\000\000\000\000Duration for which all slots in the data engine issue queue are busy. This event is set every time that the data engine rename has at least one valid instruction, excluding No Operations (NOPs), that cannot move to the issue stage because accpt_instr is LOW\000 */
{ 43737 }, /* dp_iq_full\000\000pipeline\000Duration for which all slots in the data processing issue queue are busy. This event counts the cycles where all slots in the DP0 and DP1 IQs are full with micro-operations waiting for issuing, and the despatch stage is not empty\000\000\000event=0xd9\000\000\000\000\000\000\000\000Duration for which all slots in the data processing issue queue are busy. This event counts the cycles where all slots in the DP0 and DP1 IQs are full with micro-operations waiting for issuing, and the despatch stage is not empty\000 */
{ 116743 }, /* lf_stall\000\000pipeline\000A linefill caused an instruction side stall\000\000\000event=0xc0\000\000\000\000\000\000\000\000A linefill caused an instruction side stall\000 */
{ 117461 }, /* ls_iq_full\000\000pipeline\000Duration for which all slots in the load-store issue queue are busy. This event counts the cycles where all slots in the LS IQs are full with micro-operations waiting for issuing, and the dispatch stage is not empty\000\000\000event=0xd8\000\000\000\000\000\000\000\000Duration for which all slots in the load-store issue queue are busy. This event counts the cycles where all slots in the LS IQs are full with micro-operations waiting for issuing, and the dispatch stage is not empty\000 */
{ 127101 }, /* ptw_stall\000\000pipeline\000A translation table walk caused an instruction side stall\000\000\000event=0xc1\000\000\000\000\000\000\000\000A translation table walk caused an instruction side stall\000 */
{ 134035 }, /* stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000No operation issued due to the backend\000 */
{ 143105 }, /* stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000No operation issued because of the frontend\000 */
};

static const struct compact_pmu_event pme_arm_cortex_x2[] = {
{ 25798 }, /* br_immed_spec\000\000branch\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 34668 }, /* br_return_spec\000\000branch\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 39149 }, /* cnt_cycles\000\000bus\000Constant frequency cycles\000\000\000event=0x4004\000\000\000\000\000\000\000\000Constant frequency cycles.  The counter increments at a constant frequency equal to the rate of increment of the system counter, CNTPCT_EL0\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 45496 }, /* dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000Access to data TLB causes a translation table walk\000 */
{ 66317 }, /* itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000Access to instruction TLB that causes a translation table walk\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72009 }, /* l1d_cache_inval\000\000cache\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000 */
{ 72327 }, /* l1d_cache_lmiss_rd\000\000cache\000Level 1 data cache long-latency read miss\000\000\000event=0x39\000\000\000\000\000\000\000\000Level 1 data cache long-latency read miss.  The counter counts each memory read access counted by L1D_CACHE that incurs additional latency because it returns data from outside the Level 1 data or unified cache of this processing element\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 73655 }, /* l1d_cache_refill_inner\000\000cache\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000 */
{ 73902 }, /* l1d_cache_refill_outer\000\000cache\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000 */
{ 75011 }, /* l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75248 }, /* l1d_cache_refill_wr\000\000cache\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 75865 }, /* l1d_cache_wb_clean\000\000cache\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000 */
{ 76162 }, /* l1d_cache_wb_victim\000\000cache\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 76972 }, /* l1d_tlb\000\000cache\000Attributable Level 1 data or unified TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access\000 */
{ 77503 }, /* l1d_tlb_rd\000\000cache\000L1D tlb access, read\000\000\000event=0x4e\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, read\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 78051 }, /* l1d_tlb_refill_rd\000\000cache\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000 */
{ 78276 }, /* l1d_tlb_refill_wr\000\000cache\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000 */
{ 78505 }, /* l1d_tlb_wr\000\000cache\000L1D tlb access, write\000\000\000event=0x4f\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, write\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 81421 }, /* l1i_cache_lmiss\000\000cache\000Level 1 instruction cache long-latency read miss\000\000\000event=0x4006\000\000\000\000\000\000\000\000Level 1 instruction cache long-latency read miss.  If the L1I_CACHE_RD event is implemented, the counter counts each access counted by L1I_CACHE_RD that incurs additional latency because it returns instructions from outside of the Level 1 instruction cache of this PE.  If the L1I_CACHE_RD event is not implemented, the counter counts each access counted by L1I_CACHE that incurs additional latency because it returns instructions from outside the Level 1 instruction cache of this PE.  The event indicates to software that the access missed in the Level 1 instruction cache and might have a significant performance impact due to the additional latency, compared to the latency of an access that hits in the Level 1 instruction cache\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83274 }, /* l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB access\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 88772 }, /* l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000Attributable Level 2 data cache allocation without refill\000 */
{ 89220 }, /* l2d_cache_inval\000\000cache\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000 */
{ 89441 }, /* l2d_cache_lmiss_rd\000\000cache\000Level 2 data cache long-latency read miss\000\000\000event=0x4009\000\000\000\000\000\000\000\000Level 2 data cache long-latency read miss.  The counter counts each memory read access counted by L2D_CACHE that incurs additional latency because it returns data from outside the Level 2 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 2 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 2 data or unified cache\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 93050 }, /* l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93287 }, /* l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97102 }, /* l2d_cache_wb_clean\000\000cache\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000 */
{ 97399 }, /* l2d_cache_wb_victim\000\000cache\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 102443 }, /* l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access\000 */
{ 102985 }, /* l2d_tlb_rd\000\000cache\000L2D cache access, read\000\000\000event=0x5e\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, read\000 */
{ 103449 }, /* l2d_tlb_refill\000\000cache\000Attributable Level 2 data TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000Attributable Level 2 data TLB refill\000 */
{ 103565 }, /* l2d_tlb_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x5c\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, read\000 */
{ 103816 }, /* l2d_tlb_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x5d\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, write\000 */
{ 104071 }, /* l2d_tlb_wr\000\000cache\000L2D cache access, write\000\000\000event=0x5f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, write\000 */
{ 108575 }, /* l3d_cache\000\000cache\000Attributable Level 3 data cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000Attributable Level 3 data cache access\000 */
{ 109142 }, /* l3d_cache_allocate\000\000cache\000Attributable Level 3 data cache allocation without refill\000\000\000event=0x29\000\000\000\000\000\000\000\000Attributable Level 3 data cache allocation without refill\000 */
{ 109304 }, /* l3d_cache_lmiss_rd\000\000cache\000Level 3 data cache long-latency read miss\000\000\000event=0x400b\000\000\000\000\000\000\000\000Level 3 data cache long-latency read miss.  The counter counts each memory read access counted by L3D_CACHE that incurs additional latency because it returns data from outside the Level 3 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 3 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 3 data or unified cache\000 */
{ 109857 }, /* l3d_cache_rd\000\000cache\000Attributable Level 3 data or unified cache access, read\000\000\000event=0xa0\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache access, read\000 */
{ 110009 }, /* l3d_cache_refill\000\000cache\000Attributable Level 3 data cache refill\000\000\000event=0x2a\000\000\000\000\000\000\000\000Attributable Level 3 data cache refill\000 */
{ 116870 }, /* ll_cache_miss_rd\000\000cache\000Last level cache miss, read\000\000\000event=0x37\000\000\000\000\000\000\000\000Last level cache miss, read\000 */
{ 116970 }, /* ll_cache_rd\000\000cache\000Attributable Last level cache memory read\000\000\000event=0x36\000\000\000\000\000\000\000\000Attributable Last level cache memory read\000 */
{ 48296 }, /* exc_dabort\000\000exception\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48766 }, /* exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 49228 }, /* exc_pabort\000\000exception\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000 */
{ 49848 }, /* exc_smc\000\000exception\000Exception taken, Secure Monitor Call\000\000\000event=0x88\000\000\000\000\000\000\000\000Exception taken, Secure Monitor Call\000 */
{ 50069 }, /* exc_svc\000\000exception\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 50408 }, /* exc_trap_dabort\000\000exception\000Exception taken, Data Abort or SError not taken locally\000\000\000event=0x8c\000\000\000\000\000\000\000\000Exception taken, Data Abort or SError not taken locally\000 */
{ 50692 }, /* exc_trap_fiq\000\000exception\000Exception taken, FIQ not taken locally\000\000\000event=0x8f\000\000\000\000\000\000\000\000Exception taken, FIQ not taken locally\000 */
{ 51825 }, /* exc_trap_irq\000\000exception\000Exception taken, IRQ not taken locally\000\000\000event=0x8e\000\000\000\000\000\000\000\000Exception taken, IRQ not taken locally\000 */
{ 52090 }, /* exc_trap_other\000\000exception\000Exception taken, Other traps not taken locally\000\000\000event=0x8d\000\000\000\000\000\000\000\000Exception taken, Other traps not taken locally\000 */
{ 52386 }, /* exc_trap_pabort\000\000exception\000Exception taken, Instruction Abort not taken locally\000\000\000event=0x8b\000\000\000\000\000\000\000\000Exception taken, Instruction Abort not taken locally\000 */
{ 52653 }, /* exc_undef\000\000exception\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000 */
{ 120089 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000 */
{ 19434 }, /* ase_inst_spec\000\000instruction\000ASE operations speculatively executed\000\000\000event=0x8005\000\000\000\000\000\000\000\000ASE operations speculatively executed\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 19721 }, /* ase_sve_int16_spec\000\000instruction\000Advanced SIMD and SVE 16-bit integer operations speculatively executed\000\000\000event=0x80e7\000\000\000\000\000\000\000\000Advanced SIMD and SVE 16-bit integer operations speculatively executed\000 */
{ 19917 }, /* ase_sve_int32_spec\000\000instruction\000Advanced SIMD and SVE 32-bit integer operations speculatively executed\000\000\000event=0x80eb\000\000\000\000\000\000\000\000Advanced SIMD and SVE 32-bit integer operations speculatively executed\000 */
{ 20113 }, /* ase_sve_int64_spec\000\000instruction\000Advanced SIMD and SVE 64-bit integer operations speculatively executed\000\000\000event=0x80ef\000\000\000\000\000\000\000\000Advanced SIMD and SVE 64-bit integer operations speculatively executed\000 */
{ 20309 }, /* ase_sve_int8_spec\000\000instruction\000Advanced SIMD and SVE 8-bit integer operations speculatively executed\000\000\000event=0x80e3\000\000\000\000\000\000\000\000Advanced SIMD and SVE 8-bit integer operations speculatively executed\000 */
{ 30824 }, /* br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000Instruction architecturally executed, mispredicted branch\000 */
{ 31554 }, /* br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000Instruction architecturally executed, branch\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 43623 }, /* dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 45327 }, /* dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 55680 }, /* fp_dp_spec\000\000instruction\000Floating-point double-precision operations speculatively executed\000\000\000event=0x801c\000\000\000\000\000\000\000\000Floating-point double-precision operations speculatively executed\000 */
{ 55858 }, /* fp_fixed_ops_spec\000\000instruction\000Non-scalable floating-point element Operations speculatively executed\000\000\000event=0x80c1\000\000\000\000\000\000\000\000Non-scalable floating-point element Operations speculatively executed\000 */
{ 56809 }, /* fp_hp_spec\000\000instruction\000Floating-point half-precision operations speculatively executed\000\000\000event=0x8014\000\000\000\000\000\000\000\000Floating-point half-precision operations speculatively executed\000 */
{ 57590 }, /* fp_scale_ops_spec\000\000instruction\000Scalable floating-point element Operations speculatively executed\000\000\000event=0x80c0\000\000\000\000\000\000\000\000Scalable floating-point element Operations speculatively executed\000 */
{ 58388 }, /* fp_sp_spec\000\000instruction\000Floating-point single-precision operations speculatively executed\000\000\000event=0x8018\000\000\000\000\000\000\000\000Floating-point single-precision operations speculatively executed\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116153 }, /* ldrex_spec\000\000instruction\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000 */
{ 122928 }, /* op_retired\000\000instruction\000Micro-operation architecturally executed\000\000\000event=0x3a\000\000\000\000\000\000\000\000Micro-operation architecturally executed.  The counter counts each operation counted by OP_SPEC that would be executed in a simple sequential execution of the program\000 */
{ 123180 }, /* op_spec\000\000instruction\000Micro-operation speculatively executed\000\000\000event=0x3b\000\000\000\000\000\000\000\000Micro-operation speculatively executed.  The counter counts the number of operations executed by the processing element, including those that are executed speculatively and would not be executed in a simple sequential execution of the program\000 */
{ 124643 }, /* pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000 */
{ 127257 }, /* rc_ld_spec\000\000instruction\000Release consistency operation speculatively executed, Load-Acquire\000\000\000event=0x90\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Load-Acquire\000 */
{ 127435 }, /* rc_st_spec\000\000instruction\000Release consistency operation speculatively executed, Store-Release\000\000\000event=0x91\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Store-Release\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 147124 }, /* strex_fail_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000 */
{ 147468 }, /* strex_pass_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX pass\000\000\000event=0x6d\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX pass\000 */
{ 147812 }, /* strex_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX\000\000\000event=0x6f\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX\000 */
{ 148390 }, /* sve_inst_spec\000\000instruction\000SVE operations speculatively executed\000\000\000event=0x8006\000\000\000\000\000\000\000\000SVE operations speculatively executed\000 */
{ 148661 }, /* sve_ldff_fault_spec\000\000instruction\000SVE first-fault load operations speculatively executed which set FFR bit to 0\000\000\000event=0x80bd\000\000\000\000\000\000\000\000SVE first-fault load operations speculatively executed which set FFR bit to 0\000 */
{ 148872 }, /* sve_ldff_spec\000\000instruction\000SVE First-fault load Operations speculatively executed\000\000\000event=0x80bc\000\000\000\000\000\000\000\000SVE First-fault load Operations speculatively executed\000 */
{ 149966 }, /* sve_pred_empty_spec\000\000instruction\000SVE predicated operations with no active predicates speculatively executed\000\000\000event=0x8075\000\000\000\000\000\000\000\000SVE predicated operations with no active predicates speculatively executed\000 */
{ 150171 }, /* sve_pred_full_spec\000\000instruction\000SVE predicated operations speculatively executed with all active predicates\000\000\000event=0x8076\000\000\000\000\000\000\000\000SVE predicated operations speculatively executed with all active predicates\000 */
{ 150377 }, /* sve_pred_not_full_spec\000\000instruction\000SVE predicated operations with empty or partially active predicates\000\000\000event=0x8079\000\000\000\000\000\000\000\000SVE predicated operations with empty or partially active predicates\000 */
{ 150571 }, /* sve_pred_partial_spec\000\000instruction\000SVE predicated operations speculatively executed with partially active predicates\000\000\000event=0x8077\000\000\000\000\000\000\000\000SVE predicated operations speculatively executed with partially active predicates\000 */
{ 150792 }, /* sve_pred_spec\000\000instruction\000SVE predicated Operations speculatively executed\000\000\000event=0x8074\000\000\000\000\000\000\000\000SVE predicated Operations speculatively executed\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 112722 }, /* ld_align_lat\000\000memory\000Load with additional latency from alignment\000\000\000event=0x4021\000\000\000\000\000\000\000\000Load with additional latency from alignment\000 */
{ 116467 }, /* ldst_align_lat\000\000memory\000Access with additional latency from alignment\000\000\000event=0x4020\000\000\000\000\000\000\000\000Access with additional latency from alignment\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118524 }, /* mem_access_checked\000\000memory\000Checked data memory access\000\000\000event=0x4024\000\000\000\000\000\000\000\000Checked data memory access\000 */
{ 118627 }, /* mem_access_checked_rd\000\000memory\000Checked data memory access, read\000\000\000event=0x4025\000\000\000\000\000\000\000\000Checked data memory access, read\000 */
{ 118745 }, /* mem_access_checked_wr\000\000memory\000Checked data memory access, write\000\000\000event=0x4026\000\000\000\000\000\000\000\000Checked data memory access, write\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 128878 }, /* remote_access\000\000memory\000Access to another socket in a multi-socket system\000\000\000event=0x31\000\000\000\000\000\000\000\000Access to another socket in a multi-socket system\000 */
{ 133247 }, /* st_align_lat\000\000memory\000Store with additional latency from alignment\000\000\000event=0x4022\000\000\000\000\000\000\000\000Store with additional latency from alignment\000 */
{ 156587 }, /* unaligned_ld_spec\000\000memory\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000 */
{ 156967 }, /* unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 157149 }, /* unaligned_st_spec\000\000memory\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000 */
{ 133789 }, /* stall\000\000pipeline\000No operation sent for execution\000\000\000event=0x3c\000\000\000\000\000\000\000\000No operation sent for execution.  The counter counts every attributable cycle on which no attributable instruction or operation was sent for execution on this processing element\000 */
{ 134035 }, /* stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000No operation issued due to the backend\000 */
{ 140211 }, /* stall_backend_mem\000\000pipeline\000Memory stall cycles\000\000\000event=0x4005\000\000\000\000\000\000\000\000Memory stall cycles.  The counter counts each cycle counted by STALL_BACKEND where there is a cache miss in the last level of cache within the processing element clock domain\000 */
{ 143105 }, /* stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000No operation issued because of the frontend\000 */
{ 145656 }, /* stall_slot\000\000pipeline\000No operation sent for execution on a slot\000\000\000event=0x3f\000\000\000\000\000\000\000\000No operation sent for execution on a slot.  The counter counts on each attributable cycle the number of instruction or operation slots that were not occupied by an instruction or operation attributable to the processing element\000 */
{ 145967 }, /* stall_slot_backend\000\000pipeline\000No operation sent for execution on a slot due to the backend\000\000\000event=0x3d\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the backend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because the backend is unable to accept it\000 */
{ 146613 }, /* stall_slot_frontend\000\000pipeline\000No operation sent for execution on a slot due to the frontend\000\000\000event=0x3e\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the frontend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because there was no attributable instruction or operation available to issue from the processing element from the frontend for the slot\000 */
{ 41211 }, /* cti_trigout4\000\000trace\000Cross-trigger Interface output trigger 4\000\000\000event=0x4018\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 4\000 */
{ 41335 }, /* cti_trigout5\000\000trace\000Cross-trigger Interface output trigger 5 \000\000\000event=0x4019\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 5 \000 */
{ 41461 }, /* cti_trigout6\000\000trace\000Cross-trigger Interface output trigger 6\000\000\000event=0x401a\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 6\000 */
{ 41585 }, /* cti_trigout7\000\000trace\000Cross-trigger Interface output trigger 7\000\000\000event=0x401b\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 7\000 */
{ 155265 }, /* trb_wrap\000\000trace\000Trace buffer current write pointer wrapped\000\000\000event=0x400c\000\000\000\000\000\000\000\000Trace buffer current write pointer wrapped\000 */
{ 155389 }, /* trcextout0\000\000trace\000PE Trace Unit external output 0\000\000\000event=0x4010\000\000\000\000\000\000\000\000PE Trace Unit external output 0\000 */
{ 155493 }, /* trcextout1\000\000trace\000PE Trace Unit external output 1\000\000\000event=0x4011\000\000\000\000\000\000\000\000PE Trace Unit external output 1\000 */
{ 155597 }, /* trcextout2\000\000trace\000PE Trace Unit external output 2\000\000\000event=0x4012\000\000\000\000\000\000\000\000PE Trace Unit external output 2\000 */
{ 155701 }, /* trcextout3\000\000trace\000PE Trace Unit external output 3\000\000\000event=0x4013\000\000\000\000\000\000\000\000PE Trace Unit external output 3\000 */
};

static const struct compact_pmu_event pme_arm_cortex_a57_a72[] = {
{ 25798 }, /* br_immed_spec\000\000branch\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 34668 }, /* br_return_spec\000\000branch\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35467 }, /* bus_access_normal\000\000bus\000Bus access, Normal\000\000\000event=0x64\000\000\000\000\000\000\000\000Bus access, Normal\000 */
{ 35548 }, /* bus_access_not_shared\000\000bus\000Bus access, not Normal, Cacheable, Shareable\000\000\000event=0x63\000\000\000\000\000\000\000\000Bus access, not Normal, Cacheable, Shareable\000 */
{ 35685 }, /* bus_access_periph\000\000bus\000Bus access, peripheral\000\000\000event=0x65\000\000\000\000\000\000\000\000Bus access, peripheral\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 35925 }, /* bus_access_shared\000\000bus\000Bus access, Normal, Cacheable, Shareable\000\000\000event=0x62\000\000\000\000\000\000\000\000Bus access, Normal, Cacheable, Shareable\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72009 }, /* l1d_cache_inval\000\000cache\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 75011 }, /* l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75248 }, /* l1d_cache_refill_wr\000\000cache\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 75865 }, /* l1d_cache_wb_clean\000\000cache\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000 */
{ 76162 }, /* l1d_cache_wb_victim\000\000cache\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 78051 }, /* l1d_tlb_refill_rd\000\000cache\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000 */
{ 78276 }, /* l1d_tlb_refill_wr\000\000cache\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 89220 }, /* l2d_cache_inval\000\000cache\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 93050 }, /* l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93287 }, /* l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97102 }, /* l2d_cache_wb_clean\000\000cache\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000 */
{ 97399 }, /* l2d_cache_wb_victim\000\000cache\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 48296 }, /* exc_dabort\000\000exception\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48766 }, /* exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 49228 }, /* exc_pabort\000\000exception\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000 */
{ 49848 }, /* exc_smc\000\000exception\000Exception taken, Secure Monitor Call\000\000\000event=0x88\000\000\000\000\000\000\000\000Exception taken, Secure Monitor Call\000 */
{ 50069 }, /* exc_svc\000\000exception\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 50408 }, /* exc_trap_dabort\000\000exception\000Exception taken, Data Abort or SError not taken locally\000\000\000event=0x8c\000\000\000\000\000\000\000\000Exception taken, Data Abort or SError not taken locally\000 */
{ 50692 }, /* exc_trap_fiq\000\000exception\000Exception taken, FIQ not taken locally\000\000\000event=0x8f\000\000\000\000\000\000\000\000Exception taken, FIQ not taken locally\000 */
{ 51825 }, /* exc_trap_irq\000\000exception\000Exception taken, IRQ not taken locally\000\000\000event=0x8e\000\000\000\000\000\000\000\000Exception taken, IRQ not taken locally\000 */
{ 52090 }, /* exc_trap_other\000\000exception\000Exception taken, Other traps not taken locally\000\000\000event=0x8d\000\000\000\000\000\000\000\000Exception taken, Other traps not taken locally\000 */
{ 52386 }, /* exc_trap_pabort\000\000exception\000Exception taken, Instruction Abort not taken locally\000\000\000event=0x8b\000\000\000\000\000\000\000\000Exception taken, Instruction Abort not taken locally\000 */
{ 52653 }, /* exc_undef\000\000exception\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000 */
{ 120089 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 43623 }, /* dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 45327 }, /* dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116153 }, /* ldrex_spec\000\000instruction\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000 */
{ 116604 }, /* ldst_spec\000\000instruction\000Operation speculatively executed, load or store\000\000\000event=0x72\000\000\000\000\000\000\000\000Operation speculatively executed, load or store\000 */
{ 124643 }, /* pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000 */
{ 127257 }, /* rc_ld_spec\000\000instruction\000Release consistency operation speculatively executed, Load-Acquire\000\000\000event=0x90\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Load-Acquire\000 */
{ 127435 }, /* rc_st_spec\000\000instruction\000Release consistency operation speculatively executed, Store-Release\000\000\000event=0x91\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Store-Release\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 147124 }, /* strex_fail_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000 */
{ 147468 }, /* strex_pass_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX pass\000\000\000event=0x6d\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX pass\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 156587 }, /* unaligned_ld_spec\000\000memory\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000 */
{ 156967 }, /* unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 157149 }, /* unaligned_st_spec\000\000memory\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000 */
};

static const struct compact_pmu_event pme_arm_cortex_a34[] = {
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 120089 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000 */
{ 25639 }, /* br_immed_retired\000\000instruction\000Instruction architecturally executed, immediate branch\000\000\000event=0xd\000\000\000\000\000\000\000\000Instruction architecturally executed, immediate branch\000 */
{ 34454 }, /* br_return_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, procedure return\000\000\000event=0xe\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, procedure return\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 115851 }, /* ld_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, load\000\000\000event=0x6\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, load\000 */
{ 124412 }, /* pc_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, software change of the PC\000\000\000event=0xc\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, software change of the PC\000 */
{ 133483 }, /* st_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, store\000\000\000event=0x7\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, store\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 156679 }, /* unaligned_ldst_retired\000\000memory\000Instruction architecturally executed, condition code check pass, unaligned\000\000\000event=0xf\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, unaligned\000 */
};

static const struct compact_pmu_event pme_arm_cortex_a78[] = {
{ 25798 }, /* br_immed_spec\000\000branch\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 34668 }, /* br_return_spec\000\000branch\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 39149 }, /* cnt_cycles\000\000bus\000Constant frequency cycles\000\000\000event=0x4004\000\000\000\000\000\000\000\000Constant frequency cycles.  The counter increments at a constant frequency equal to the rate of increment of the system counter, CNTPCT_EL0\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 45496 }, /* dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000Access to data TLB causes a translation table walk\000 */
{ 66317 }, /* itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000Access to instruction TLB that causes a translation table walk\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72009 }, /* l1d_cache_inval\000\000cache\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000 */
{ 72327 }, /* l1d_cache_lmiss_rd\000\000cache\000Level 1 data cache long-latency read miss\000\000\000event=0x39\000\000\000\000\000\000\000\000Level 1 data cache long-latency read miss.  The counter counts each memory read access counted by L1D_CACHE that incurs additional latency because it returns data from outside the Level 1 data or unified cache of this processing element\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 73655 }, /* l1d_cache_refill_inner\000\000cache\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000 */
{ 73902 }, /* l1d_cache_refill_outer\000\000cache\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000 */
{ 75011 }, /* l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75248 }, /* l1d_cache_refill_wr\000\000cache\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 75865 }, /* l1d_cache_wb_clean\000\000cache\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000 */
{ 76162 }, /* l1d_cache_wb_victim\000\000cache\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 76972 }, /* l1d_tlb\000\000cache\000Attributable Level 1 data or unified TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access\000 */
{ 77503 }, /* l1d_tlb_rd\000\000cache\000L1D tlb access, read\000\000\000event=0x4e\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, read\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 78051 }, /* l1d_tlb_refill_rd\000\000cache\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000 */
{ 78276 }, /* l1d_tlb_refill_wr\000\000cache\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000 */
{ 78505 }, /* l1d_tlb_wr\000\000cache\000L1D tlb access, write\000\000\000event=0x4f\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, write\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 81421 }, /* l1i_cache_lmiss\000\000cache\000Level 1 instruction cache long-latency read miss\000\000\000event=0x4006\000\000\000\000\000\000\000\000Level 1 instruction cache long-latency read miss.  If the L1I_CACHE_RD event is implemented, the counter counts each access counted by L1I_CACHE_RD that incurs additional latency because it returns instructions from outside of the Level 1 instruction cache of this PE.  If the L1I_CACHE_RD event is not implemented, the counter counts each access counted by L1I_CACHE that incurs additional latency because it returns instructions from outside the Level 1 instruction cache of this PE.  The event indicates to software that the access missed in the Level 1 instruction cache and might have a significant performance impact due to the additional latency, compared to the latency of an access that hits in the Level 1 instruction cache\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83274 }, /* l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB access\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 88772 }, /* l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000Attributable Level 2 data cache allocation without refill\000 */
{ 89220 }, /* l2d_cache_inval\000\000cache\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000 */
{ 89441 }, /* l2d_cache_lmiss_rd\000\000cache\000Level 2 data cache long-latency read miss\000\000\000event=0x4009\000\000\000\000\000\000\000\000Level 2 data cache long-latency read miss.  The counter counts each memory read access counted by L2D_CACHE that incurs additional latency because it returns data from outside the Level 2 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 2 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 2 data or unified cache\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 93050 }, /* l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93287 }, /* l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97102 }, /* l2d_cache_wb_clean\000\000cache\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000 */
{ 97399 }, /* l2d_cache_wb_victim\000\000cache\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 102443 }, /* l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access\000 */
{ 102985 }, /* l2d_tlb_rd\000\000cache\000L2D cache access, read\000\000\000event=0x5e\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, read\000 */
{ 103449 }, /* l2d_tlb_refill\000\000cache\000Attributable Level 2 data TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000Attributable Level 2 data TLB refill\000 */
{ 103565 }, /* l2d_tlb_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x5c\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, read\000 */
{ 103816 }, /* l2d_tlb_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x5d\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, write\000 */
{ 104071 }, /* l2d_tlb_wr\000\000cache\000L2D cache access, write\000\000\000event=0x5f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, write\000 */
{ 108575 }, /* l3d_cache\000\000cache\000Attributable Level 3 data cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000Attributable Level 3 data cache access\000 */
{ 109142 }, /* l3d_cache_allocate\000\000cache\000Attributable Level 3 data cache allocation without refill\000\000\000event=0x29\000\000\000\000\000\000\000\000Attributable Level 3 data cache allocation without refill\000 */
{ 109304 }, /* l3d_cache_lmiss_rd\000\000cache\000Level 3 data cache long-latency read miss\000\000\000event=0x400b\000\000\000\000\000\000\000\000Level 3 data cache long-latency read miss.  The counter counts each memory read access counted by L3D_CACHE that incurs additional latency because it returns data from outside the Level 3 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 3 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 3 data or unified cache\000 */
{ 109857 }, /* l3d_cache_rd\000\000cache\000Attributable Level 3 data or unified cache access, read\000\000\000event=0xa0\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache access, read\000 */
{ 110009 }, /* l3d_cache_refill\000\000cache\000Attributable Level 3 data cache refill\000\000\000event=0x2a\000\000\000\000\000\000\000\000Attributable Level 3 data cache refill\000 */
{ 116870 }, /* ll_cache_miss_rd\000\000cache\000Last level cache miss, read\000\000\000event=0x37\000\000\000\000\000\000\000\000Last level cache miss, read\000 */
{ 116970 }, /* ll_cache_rd\000\000cache\000Attributable Last level cache memory read\000\000\000event=0x36\000\000\000\000\000\000\000\000Attributable Last level cache memory read\000 */
{ 48296 }, /* exc_dabort\000\000exception\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48766 }, /* exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 49228 }, /* exc_pabort\000\000exception\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000 */
{ 49848 }, /* exc_smc\000\000exception\000Exception taken, Secure Monitor Call\000\000\000event=0x88\000\000\000\000\000\000\000\000Exception taken, Secure Monitor Call\000 */
{ 50069 }, /* exc_svc\000\000exception\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 50408 }, /* exc_trap_dabort\000\000exception\000Exception taken, Data Abort or SError not taken locally\000\000\000event=0x8c\000\000\000\000\000\000\000\000Exception taken, Data Abort or SError not taken locally\000 */
{ 50692 }, /* exc_trap_fiq\000\000exception\000Exception taken, FIQ not taken locally\000\000\000event=0x8f\000\000\000\000\000\000\000\000Exception taken, FIQ not taken locally\000 */
{ 51825 }, /* exc_trap_irq\000\000exception\000Exception taken, IRQ not taken locally\000\000\000event=0x8e\000\000\000\000\000\000\000\000Exception taken, IRQ not taken locally\000 */
{ 52090 }, /* exc_trap_other\000\000exception\000Exception taken, Other traps not taken locally\000\000\000event=0x8d\000\000\000\000\000\000\000\000Exception taken, Other traps not taken locally\000 */
{ 52386 }, /* exc_trap_pabort\000\000exception\000Exception taken, Instruction Abort not taken locally\000\000\000event=0x8b\000\000\000\000\000\000\000\000Exception taken, Instruction Abort not taken locally\000 */
{ 52653 }, /* exc_undef\000\000exception\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000 */
{ 120089 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 30824 }, /* br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000Instruction architecturally executed, mispredicted branch\000 */
{ 31554 }, /* br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000Instruction architecturally executed, branch\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 43623 }, /* dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 45327 }, /* dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116153 }, /* ldrex_spec\000\000instruction\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000 */
{ 122928 }, /* op_retired\000\000instruction\000Micro-operation architecturally executed\000\000\000event=0x3a\000\000\000\000\000\000\000\000Micro-operation architecturally executed.  The counter counts each operation counted by OP_SPEC that would be executed in a simple sequential execution of the program\000 */
{ 123180 }, /* op_spec\000\000instruction\000Micro-operation speculatively executed\000\000\000event=0x3b\000\000\000\000\000\000\000\000Micro-operation speculatively executed.  The counter counts the number of operations executed by the processing element, including those that are executed speculatively and would not be executed in a simple sequential execution of the program\000 */
{ 124643 }, /* pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000 */
{ 127257 }, /* rc_ld_spec\000\000instruction\000Release consistency operation speculatively executed, Load-Acquire\000\000\000event=0x90\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Load-Acquire\000 */
{ 127435 }, /* rc_st_spec\000\000instruction\000Release consistency operation speculatively executed, Store-Release\000\000\000event=0x91\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Store-Release\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 147124 }, /* strex_fail_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000 */
{ 147468 }, /* strex_pass_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX pass\000\000\000event=0x6d\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX pass\000 */
{ 147812 }, /* strex_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX\000\000\000event=0x6f\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 128878 }, /* remote_access\000\000memory\000Access to another socket in a multi-socket system\000\000\000event=0x31\000\000\000\000\000\000\000\000Access to another socket in a multi-socket system\000 */
{ 156587 }, /* unaligned_ld_spec\000\000memory\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000 */
{ 156967 }, /* unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 157149 }, /* unaligned_st_spec\000\000memory\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000 */
{ 133789 }, /* stall\000\000pipeline\000No operation sent for execution\000\000\000event=0x3c\000\000\000\000\000\000\000\000No operation sent for execution.  The counter counts every attributable cycle on which no attributable instruction or operation was sent for execution on this processing element\000 */
{ 134035 }, /* stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000No operation issued due to the backend\000 */
{ 140211 }, /* stall_backend_mem\000\000pipeline\000Memory stall cycles\000\000\000event=0x4005\000\000\000\000\000\000\000\000Memory stall cycles.  The counter counts each cycle counted by STALL_BACKEND where there is a cache miss in the last level of cache within the processing element clock domain\000 */
{ 143105 }, /* stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000No operation issued because of the frontend\000 */
{ 145656 }, /* stall_slot\000\000pipeline\000No operation sent for execution on a slot\000\000\000event=0x3f\000\000\000\000\000\000\000\000No operation sent for execution on a slot.  The counter counts on each attributable cycle the number of instruction or operation slots that were not occupied by an instruction or operation attributable to the processing element\000 */
{ 145967 }, /* stall_slot_backend\000\000pipeline\000No operation sent for execution on a slot due to the backend\000\000\000event=0x3d\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the backend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because the backend is unable to accept it\000 */
{ 146613 }, /* stall_slot_frontend\000\000pipeline\000No operation sent for execution on a slot due to the frontend\000\000\000event=0x3e\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the frontend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because there was no attributable instruction or operation available to issue from the processing element from the frontend for the slot\000 */
};

static const struct compact_pmu_event pme_arm_cortex_a77[] = {
{ 25798 }, /* br_immed_spec\000\000branch\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 34668 }, /* br_return_spec\000\000branch\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 45496 }, /* dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000Access to data TLB causes a translation table walk\000 */
{ 66317 }, /* itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000Access to instruction TLB that causes a translation table walk\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72009 }, /* l1d_cache_inval\000\000cache\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 73655 }, /* l1d_cache_refill_inner\000\000cache\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000 */
{ 73902 }, /* l1d_cache_refill_outer\000\000cache\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000 */
{ 75011 }, /* l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75248 }, /* l1d_cache_refill_wr\000\000cache\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 75865 }, /* l1d_cache_wb_clean\000\000cache\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000 */
{ 76162 }, /* l1d_cache_wb_victim\000\000cache\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 76972 }, /* l1d_tlb\000\000cache\000Attributable Level 1 data or unified TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access\000 */
{ 77503 }, /* l1d_tlb_rd\000\000cache\000L1D tlb access, read\000\000\000event=0x4e\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, read\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 78051 }, /* l1d_tlb_refill_rd\000\000cache\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000 */
{ 78276 }, /* l1d_tlb_refill_wr\000\000cache\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000 */
{ 78505 }, /* l1d_tlb_wr\000\000cache\000L1D tlb access, write\000\000\000event=0x4f\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, write\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83274 }, /* l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB access\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 88772 }, /* l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000Attributable Level 2 data cache allocation without refill\000 */
{ 89220 }, /* l2d_cache_inval\000\000cache\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 93050 }, /* l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93287 }, /* l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97102 }, /* l2d_cache_wb_clean\000\000cache\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000 */
{ 97399 }, /* l2d_cache_wb_victim\000\000cache\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 102443 }, /* l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access\000 */
{ 102985 }, /* l2d_tlb_rd\000\000cache\000L2D cache access, read\000\000\000event=0x5e\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, read\000 */
{ 103449 }, /* l2d_tlb_refill\000\000cache\000Attributable Level 2 data TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000Attributable Level 2 data TLB refill\000 */
{ 103565 }, /* l2d_tlb_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x5c\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, read\000 */
{ 103816 }, /* l2d_tlb_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x5d\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, write\000 */
{ 104071 }, /* l2d_tlb_wr\000\000cache\000L2D cache access, write\000\000\000event=0x5f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, write\000 */
{ 108575 }, /* l3d_cache\000\000cache\000Attributable Level 3 data cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000Attributable Level 3 data cache access\000 */
{ 109142 }, /* l3d_cache_allocate\000\000cache\000Attributable Level 3 data cache allocation without refill\000\000\000event=0x29\000\000\000\000\000\000\000\000Attributable Level 3 data cache allocation without refill\000 */
{ 109857 }, /* l3d_cache_rd\000\000cache\000Attributable Level 3 data or unified cache access, read\000\000\000event=0xa0\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache access, read\000 */
{ 110009 }, /* l3d_cache_refill\000\000cache\000Attributable Level 3 data cache refill\000\000\000event=0x2a\000\000\000\000\000\000\000\000Attributable Level 3 data cache refill\000 */
{ 116870 }, /* ll_cache_miss_rd\000\000cache\000Last level cache miss, read\000\000\000event=0x37\000\000\000\000\000\000\000\000Last level cache miss, read\000 */
{ 116970 }, /* ll_cache_rd\000\000cache\000Attributable Last level cache memory read\000\000\000event=0x36\000\000\000\000\000\000\000\000Attributable Last level cache memory read\000 */
{ 48296 }, /* exc_dabort\000\000exception\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48766 }, /* exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 49228 }, /* exc_pabort\000\000exception\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000 */
{ 49848 }, /* exc_smc\000\000exception\000Exception taken, Secure Monitor Call\000\000\000event=0x88\000\000\000\000\000\000\000\000Exception taken, Secure Monitor Call\000 */
{ 50069 }, /* exc_svc\000\000exception\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 50408 }, /* exc_trap_dabort\000\000exception\000Exception taken, Data Abort or SError not taken locally\000\000\000event=0x8c\000\000\000\000\000\000\000\000Exception taken, Data Abort or SError not taken locally\000 */
{ 50692 }, /* exc_trap_fiq\000\000exception\000Exception taken, FIQ not taken locally\000\000\000event=0x8f\000\000\000\000\000\000\000\000Exception taken, FIQ not taken locally\000 */
{ 51825 }, /* exc_trap_irq\000\000exception\000Exception taken, IRQ not taken locally\000\000\000event=0x8e\000\000\000\000\000\000\000\000Exception taken, IRQ not taken locally\000 */
{ 52090 }, /* exc_trap_other\000\000exception\000Exception taken, Other traps not taken locally\000\000\000event=0x8d\000\000\000\000\000\000\000\000Exception taken, Other traps not taken locally\000 */
{ 52386 }, /* exc_trap_pabort\000\000exception\000Exception taken, Instruction Abort not taken locally\000\000\000event=0x8b\000\000\000\000\000\000\000\000Exception taken, Instruction Abort not taken locally\000 */
{ 52653 }, /* exc_undef\000\000exception\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000 */
{ 120089 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 30824 }, /* br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000Instruction architecturally executed, mispredicted branch\000 */
{ 31554 }, /* br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000Instruction architecturally executed, branch\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 43623 }, /* dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 45327 }, /* dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116153 }, /* ldrex_spec\000\000instruction\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000 */
{ 116604 }, /* ldst_spec\000\000instruction\000Operation speculatively executed, load or store\000\000\000event=0x72\000\000\000\000\000\000\000\000Operation speculatively executed, load or store\000 */
{ 124643 }, /* pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000 */
{ 127257 }, /* rc_ld_spec\000\000instruction\000Release consistency operation speculatively executed, Load-Acquire\000\000\000event=0x90\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Load-Acquire\000 */
{ 127435 }, /* rc_st_spec\000\000instruction\000Release consistency operation speculatively executed, Store-Release\000\000\000event=0x91\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Store-Release\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 147124 }, /* strex_fail_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000 */
{ 147468 }, /* strex_pass_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX pass\000\000\000event=0x6d\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX pass\000 */
{ 147812 }, /* strex_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX\000\000\000event=0x6f\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 128878 }, /* remote_access\000\000memory\000Access to another socket in a multi-socket system\000\000\000event=0x31\000\000\000\000\000\000\000\000Access to another socket in a multi-socket system\000 */
{ 156587 }, /* unaligned_ld_spec\000\000memory\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000 */
{ 156967 }, /* unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 157149 }, /* unaligned_st_spec\000\000memory\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000 */
{ 134035 }, /* stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000No operation issued due to the backend\000 */
{ 143105 }, /* stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000No operation issued because of the frontend\000 */
};

static const struct compact_pmu_event pme_arm_neoverse_v1[] = {
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 39149 }, /* cnt_cycles\000\000bus\000Constant frequency cycles\000\000\000event=0x4004\000\000\000\000\000\000\000\000Constant frequency cycles.  The counter increments at a constant frequency equal to the rate of increment of the system counter, CNTPCT_EL0\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 45496 }, /* dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000Access to data TLB causes a translation table walk\000 */
{ 66317 }, /* itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000Access to instruction TLB that causes a translation table walk\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72009 }, /* l1d_cache_inval\000\000cache\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000 */
{ 72327 }, /* l1d_cache_lmiss_rd\000\000cache\000Level 1 data cache long-latency read miss\000\000\000event=0x39\000\000\000\000\000\000\000\000Level 1 data cache long-latency read miss.  The counter counts each memory read access counted by L1D_CACHE that incurs additional latency because it returns data from outside the Level 1 data or unified cache of this processing element\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 73655 }, /* l1d_cache_refill_inner\000\000cache\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000 */
{ 73902 }, /* l1d_cache_refill_outer\000\000cache\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000 */
{ 75011 }, /* l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75248 }, /* l1d_cache_refill_wr\000\000cache\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 75865 }, /* l1d_cache_wb_clean\000\000cache\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000 */
{ 76162 }, /* l1d_cache_wb_victim\000\000cache\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 76972 }, /* l1d_tlb\000\000cache\000Attributable Level 1 data or unified TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access\000 */
{ 77503 }, /* l1d_tlb_rd\000\000cache\000L1D tlb access, read\000\000\000event=0x4e\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, read\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 78051 }, /* l1d_tlb_refill_rd\000\000cache\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000 */
{ 78276 }, /* l1d_tlb_refill_wr\000\000cache\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000 */
{ 78505 }, /* l1d_tlb_wr\000\000cache\000L1D tlb access, write\000\000\000event=0x4f\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, write\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 81421 }, /* l1i_cache_lmiss\000\000cache\000Level 1 instruction cache long-latency read miss\000\000\000event=0x4006\000\000\000\000\000\000\000\000Level 1 instruction cache long-latency read miss.  If the L1I_CACHE_RD event is implemented, the counter counts each access counted by L1I_CACHE_RD that incurs additional latency because it returns instructions from outside of the Level 1 instruction cache of this PE.  If the L1I_CACHE_RD event is not implemented, the counter counts each access counted by L1I_CACHE that incurs additional latency because it returns instructions from outside the Level 1 instruction cache of this PE.  The event indicates to software that the access missed in the Level 1 instruction cache and might have a significant performance impact due to the additional latency, compared to the latency of an access that hits in the Level 1 instruction cache\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83274 }, /* l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB access\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 88772 }, /* l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000Attributable Level 2 data cache allocation without refill\000 */
{ 89220 }, /* l2d_cache_inval\000\000cache\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000 */
{ 89441 }, /* l2d_cache_lmiss_rd\000\000cache\000Level 2 data cache long-latency read miss\000\000\000event=0x4009\000\000\000\000\000\000\000\000Level 2 data cache long-latency read miss.  The counter counts each memory read access counted by L2D_CACHE that incurs additional latency because it returns data from outside the Level 2 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 2 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 2 data or unified cache\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 93050 }, /* l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93287 }, /* l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97102 }, /* l2d_cache_wb_clean\000\000cache\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000 */
{ 97399 }, /* l2d_cache_wb_victim\000\000cache\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 102443 }, /* l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access\000 */
{ 102985 }, /* l2d_tlb_rd\000\000cache\000L2D cache access, read\000\000\000event=0x5e\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, read\000 */
{ 103449 }, /* l2d_tlb_refill\000\000cache\000Attributable Level 2 data TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000Attributable Level 2 data TLB refill\000 */
{ 103565 }, /* l2d_tlb_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x5c\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, read\000 */
{ 103816 }, /* l2d_tlb_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x5d\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, write\000 */
{ 104071 }, /* l2d_tlb_wr\000\000cache\000L2D cache access, write\000\000\000event=0x5f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, write\000 */
{ 108575 }, /* l3d_cache\000\000cache\000Attributable Level 3 data cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000Attributable Level 3 data cache access\000 */
{ 109142 }, /* l3d_cache_allocate\000\000cache\000Attributable Level 3 data cache allocation without refill\000\000\000event=0x29\000\000\000\000\000\000\000\000Attributable Level 3 data cache allocation without refill\000 */
{ 109304 }, /* l3d_cache_lmiss_rd\000\000cache\000Level 3 data cache long-latency read miss\000\000\000event=0x400b\000\000\000\000\000\000\000\000Level 3 data cache long-latency read miss.  The counter counts each memory read access counted by L3D_CACHE that incurs additional latency because it returns data from outside the Level 3 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 3 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 3 data or unified cache\000 */
{ 109857 }, /* l3d_cache_rd\000\000cache\000Attributable Level 3 data or unified cache access, read\000\000\000event=0xa0\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache access, read\000 */
{ 110009 }, /* l3d_cache_refill\000\000cache\000Attributable Level 3 data cache refill\000\000\000event=0x2a\000\000\000\000\000\000\000\000Attributable Level 3 data cache refill\000 */
{ 116870 }, /* ll_cache_miss_rd\000\000cache\000Last level cache miss, read\000\000\000event=0x37\000\000\000\000\000\000\000\000Last level cache miss, read\000 */
{ 116970 }, /* ll_cache_rd\000\000cache\000Attributable Last level cache memory read\000\000\000event=0x36\000\000\000\000\000\000\000\000Attributable Last level cache memory read\000 */
{ 48296 }, /* exc_dabort\000\000exception\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48766 }, /* exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 49228 }, /* exc_pabort\000\000exception\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000 */
{ 49848 }, /* exc_smc\000\000exception\000Exception taken, Secure Monitor Call\000\000\000event=0x88\000\000\000\000\000\000\000\000Exception taken, Secure Monitor Call\000 */
{ 50069 }, /* exc_svc\000\000exception\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 50408 }, /* exc_trap_dabort\000\000exception\000Exception taken, Data Abort or SError not taken locally\000\000\000event=0x8c\000\000\000\000\000\000\000\000Exception taken, Data Abort or SError not taken locally\000 */
{ 50692 }, /* exc_trap_fiq\000\000exception\000Exception taken, FIQ not taken locally\000\000\000event=0x8f\000\000\000\000\000\000\000\000Exception taken, FIQ not taken locally\000 */
{ 51825 }, /* exc_trap_irq\000\000exception\000Exception taken, IRQ not taken locally\000\000\000event=0x8e\000\000\000\000\000\000\000\000Exception taken, IRQ not taken locally\000 */
{ 52090 }, /* exc_trap_other\000\000exception\000Exception taken, Other traps not taken locally\000\000\000event=0x8d\000\000\000\000\000\000\000\000Exception taken, Other traps not taken locally\000 */
{ 52386 }, /* exc_trap_pabort\000\000exception\000Exception taken, Instruction Abort not taken locally\000\000\000event=0x8b\000\000\000\000\000\000\000\000Exception taken, Instruction Abort not taken locally\000 */
{ 52653 }, /* exc_undef\000\000exception\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000 */
{ 120089 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000 */
{ 19434 }, /* ase_inst_spec\000\000instruction\000ASE operations speculatively executed\000\000\000event=0x8005\000\000\000\000\000\000\000\000ASE operations speculatively executed\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 25936 }, /* br_immed_spec\000\000instruction\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 30111 }, /* br_indirect_spec\000\000instruction\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30824 }, /* br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000Instruction architecturally executed, mispredicted branch\000 */
{ 31554 }, /* br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000Instruction architecturally executed, branch\000 */
{ 34807 }, /* br_return_spec\000\000instruction\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 43623 }, /* dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 45327 }, /* dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 55858 }, /* fp_fixed_ops_spec\000\000instruction\000Non-scalable floating-point element Operations speculatively executed\000\000\000event=0x80c1\000\000\000\000\000\000\000\000Non-scalable floating-point element Operations speculatively executed\000 */
{ 57590 }, /* fp_scale_ops_spec\000\000instruction\000Scalable floating-point element Operations speculatively executed\000\000\000event=0x80c0\000\000\000\000\000\000\000\000Scalable floating-point element Operations speculatively executed\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116153 }, /* ldrex_spec\000\000instruction\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000 */
{ 122928 }, /* op_retired\000\000instruction\000Micro-operation architecturally executed\000\000\000event=0x3a\000\000\000\000\000\000\000\000Micro-operation architecturally executed.  The counter counts each operation counted by OP_SPEC that would be executed in a simple sequential execution of the program\000 */
{ 123180 }, /* op_spec\000\000instruction\000Micro-operation speculatively executed\000\000\000event=0x3b\000\000\000\000\000\000\000\000Micro-operation speculatively executed.  The counter counts the number of operations executed by the processing element, including those that are executed speculatively and would not be executed in a simple sequential execution of the program\000 */
{ 124643 }, /* pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000 */
{ 127257 }, /* rc_ld_spec\000\000instruction\000Release consistency operation speculatively executed, Load-Acquire\000\000\000event=0x90\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Load-Acquire\000 */
{ 127435 }, /* rc_st_spec\000\000instruction\000Release consistency operation speculatively executed, Store-Release\000\000\000event=0x91\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Store-Release\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 147124 }, /* strex_fail_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000 */
{ 147468 }, /* strex_pass_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX pass\000\000\000event=0x6d\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX pass\000 */
{ 147812 }, /* strex_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX\000\000\000event=0x6f\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX\000 */
{ 148390 }, /* sve_inst_spec\000\000instruction\000SVE operations speculatively executed\000\000\000event=0x8006\000\000\000\000\000\000\000\000SVE operations speculatively executed\000 */
{ 148661 }, /* sve_ldff_fault_spec\000\000instruction\000SVE first-fault load operations speculatively executed which set FFR bit to 0\000\000\000event=0x80bd\000\000\000\000\000\000\000\000SVE first-fault load operations speculatively executed which set FFR bit to 0\000 */
{ 148872 }, /* sve_ldff_spec\000\000instruction\000SVE First-fault load Operations speculatively executed\000\000\000event=0x80bc\000\000\000\000\000\000\000\000SVE First-fault load Operations speculatively executed\000 */
{ 149966 }, /* sve_pred_empty_spec\000\000instruction\000SVE predicated operations with no active predicates speculatively executed\000\000\000event=0x8075\000\000\000\000\000\000\000\000SVE predicated operations with no active predicates speculatively executed\000 */
{ 150171 }, /* sve_pred_full_spec\000\000instruction\000SVE predicated operations speculatively executed with all active predicates\000\000\000event=0x8076\000\000\000\000\000\000\000\000SVE predicated operations speculatively executed with all active predicates\000 */
{ 150571 }, /* sve_pred_partial_spec\000\000instruction\000SVE predicated operations speculatively executed with partially active predicates\000\000\000event=0x8077\000\000\000\000\000\000\000\000SVE predicated operations speculatively executed with partially active predicates\000 */
{ 150792 }, /* sve_pred_spec\000\000instruction\000SVE predicated Operations speculatively executed\000\000\000event=0x8074\000\000\000\000\000\000\000\000SVE predicated Operations speculatively executed\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 128878 }, /* remote_access\000\000memory\000Access to another socket in a multi-socket system\000\000\000event=0x31\000\000\000\000\000\000\000\000Access to another socket in a multi-socket system\000 */
{ 156587 }, /* unaligned_ld_spec\000\000memory\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000 */
{ 156967 }, /* unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 157149 }, /* unaligned_st_spec\000\000memory\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000 */
{ 133789 }, /* stall\000\000pipeline\000No operation sent for execution\000\000\000event=0x3c\000\000\000\000\000\000\000\000No operation sent for execution.  The counter counts every attributable cycle on which no attributable instruction or operation was sent for execution on this processing element\000 */
{ 134035 }, /* stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000No operation issued due to the backend\000 */
{ 140211 }, /* stall_backend_mem\000\000pipeline\000Memory stall cycles\000\000\000event=0x4005\000\000\000\000\000\000\000\000Memory stall cycles.  The counter counts each cycle counted by STALL_BACKEND where there is a cache miss in the last level of cache within the processing element clock domain\000 */
{ 143105 }, /* stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000No operation issued because of the frontend\000 */
{ 145656 }, /* stall_slot\000\000pipeline\000No operation sent for execution on a slot\000\000\000event=0x3f\000\000\000\000\000\000\000\000No operation sent for execution on a slot.  The counter counts on each attributable cycle the number of instruction or operation slots that were not occupied by an instruction or operation attributable to the processing element\000 */
{ 145967 }, /* stall_slot_backend\000\000pipeline\000No operation sent for execution on a slot due to the backend\000\000\000event=0x3d\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the backend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because the backend is unable to accept it\000 */
{ 146613 }, /* stall_slot_frontend\000\000pipeline\000No operation sent for execution on a slot due to the frontend\000\000\000event=0x3e\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the frontend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because there was no attributable instruction or operation available to issue from the processing element from the frontend for the slot\000 */
};

static const struct compact_pmu_event pme_arm_cortex_a710[] = {
{ 25798 }, /* br_immed_spec\000\000branch\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 34668 }, /* br_return_spec\000\000branch\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 39149 }, /* cnt_cycles\000\000bus\000Constant frequency cycles\000\000\000event=0x4004\000\000\000\000\000\000\000\000Constant frequency cycles.  The counter increments at a constant frequency equal to the rate of increment of the system counter, CNTPCT_EL0\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 45496 }, /* dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000Access to data TLB causes a translation table walk\000 */
{ 66317 }, /* itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000Access to instruction TLB that causes a translation table walk\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72009 }, /* l1d_cache_inval\000\000cache\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000 */
{ 72327 }, /* l1d_cache_lmiss_rd\000\000cache\000Level 1 data cache long-latency read miss\000\000\000event=0x39\000\000\000\000\000\000\000\000Level 1 data cache long-latency read miss.  The counter counts each memory read access counted by L1D_CACHE that incurs additional latency because it returns data from outside the Level 1 data or unified cache of this processing element\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 73655 }, /* l1d_cache_refill_inner\000\000cache\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000 */
{ 73902 }, /* l1d_cache_refill_outer\000\000cache\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000 */
{ 75011 }, /* l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75248 }, /* l1d_cache_refill_wr\000\000cache\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 75865 }, /* l1d_cache_wb_clean\000\000cache\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000 */
{ 76162 }, /* l1d_cache_wb_victim\000\000cache\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 76972 }, /* l1d_tlb\000\000cache\000Attributable Level 1 data or unified TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access\000 */
{ 77503 }, /* l1d_tlb_rd\000\000cache\000L1D tlb access, read\000\000\000event=0x4e\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, read\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 78051 }, /* l1d_tlb_refill_rd\000\000cache\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000 */
{ 78276 }, /* l1d_tlb_refill_wr\000\000cache\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000 */
{ 78505 }, /* l1d_tlb_wr\000\000cache\000L1D tlb access, write\000\000\000event=0x4f\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, write\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 81421 }, /* l1i_cache_lmiss\000\000cache\000Level 1 instruction cache long-latency read miss\000\000\000event=0x4006\000\000\000\000\000\000\000\000Level 1 instruction cache long-latency read miss.  If the L1I_CACHE_RD event is implemented, the counter counts each access counted by L1I_CACHE_RD that incurs additional latency because it returns instructions from outside of the Level 1 instruction cache of this PE.  If the L1I_CACHE_RD event is not implemented, the counter counts each access counted by L1I_CACHE that incurs additional latency because it returns instructions from outside the Level 1 instruction cache of this PE.  The event indicates to software that the access missed in the Level 1 instruction cache and might have a significant performance impact due to the additional latency, compared to the latency of an access that hits in the Level 1 instruction cache\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83274 }, /* l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB access\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 88772 }, /* l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000Attributable Level 2 data cache allocation without refill\000 */
{ 89220 }, /* l2d_cache_inval\000\000cache\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000 */
{ 89441 }, /* l2d_cache_lmiss_rd\000\000cache\000Level 2 data cache long-latency read miss\000\000\000event=0x4009\000\000\000\000\000\000\000\000Level 2 data cache long-latency read miss.  The counter counts each memory read access counted by L2D_CACHE that incurs additional latency because it returns data from outside the Level 2 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 2 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 2 data or unified cache\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 93050 }, /* l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93287 }, /* l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97102 }, /* l2d_cache_wb_clean\000\000cache\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000 */
{ 97399 }, /* l2d_cache_wb_victim\000\000cache\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 102443 }, /* l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access\000 */
{ 102985 }, /* l2d_tlb_rd\000\000cache\000L2D cache access, read\000\000\000event=0x5e\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, read\000 */
{ 103449 }, /* l2d_tlb_refill\000\000cache\000Attributable Level 2 data TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000Attributable Level 2 data TLB refill\000 */
{ 103565 }, /* l2d_tlb_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x5c\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, read\000 */
{ 103816 }, /* l2d_tlb_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x5d\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, write\000 */
{ 104071 }, /* l2d_tlb_wr\000\000cache\000L2D cache access, write\000\000\000event=0x5f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, write\000 */
{ 108575 }, /* l3d_cache\000\000cache\000Attributable Level 3 data cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000Attributable Level 3 data cache access\000 */
{ 109142 }, /* l3d_cache_allocate\000\000cache\000Attributable Level 3 data cache allocation without refill\000\000\000event=0x29\000\000\000\000\000\000\000\000Attributable Level 3 data cache allocation without refill\000 */
{ 109304 }, /* l3d_cache_lmiss_rd\000\000cache\000Level 3 data cache long-latency read miss\000\000\000event=0x400b\000\000\000\000\000\000\000\000Level 3 data cache long-latency read miss.  The counter counts each memory read access counted by L3D_CACHE that incurs additional latency because it returns data from outside the Level 3 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 3 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 3 data or unified cache\000 */
{ 109857 }, /* l3d_cache_rd\000\000cache\000Attributable Level 3 data or unified cache access, read\000\000\000event=0xa0\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache access, read\000 */
{ 110009 }, /* l3d_cache_refill\000\000cache\000Attributable Level 3 data cache refill\000\000\000event=0x2a\000\000\000\000\000\000\000\000Attributable Level 3 data cache refill\000 */
{ 116870 }, /* ll_cache_miss_rd\000\000cache\000Last level cache miss, read\000\000\000event=0x37\000\000\000\000\000\000\000\000Last level cache miss, read\000 */
{ 116970 }, /* ll_cache_rd\000\000cache\000Attributable Last level cache memory read\000\000\000event=0x36\000\000\000\000\000\000\000\000Attributable Last level cache memory read\000 */
{ 48296 }, /* exc_dabort\000\000exception\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48766 }, /* exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 49228 }, /* exc_pabort\000\000exception\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000 */
{ 49848 }, /* exc_smc\000\000exception\000Exception taken, Secure Monitor Call\000\000\000event=0x88\000\000\000\000\000\000\000\000Exception taken, Secure Monitor Call\000 */
{ 50069 }, /* exc_svc\000\000exception\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 50408 }, /* exc_trap_dabort\000\000exception\000Exception taken, Data Abort or SError not taken locally\000\000\000event=0x8c\000\000\000\000\000\000\000\000Exception taken, Data Abort or SError not taken locally\000 */
{ 50692 }, /* exc_trap_fiq\000\000exception\000Exception taken, FIQ not taken locally\000\000\000event=0x8f\000\000\000\000\000\000\000\000Exception taken, FIQ not taken locally\000 */
{ 51825 }, /* exc_trap_irq\000\000exception\000Exception taken, IRQ not taken locally\000\000\000event=0x8e\000\000\000\000\000\000\000\000Exception taken, IRQ not taken locally\000 */
{ 52090 }, /* exc_trap_other\000\000exception\000Exception taken, Other traps not taken locally\000\000\000event=0x8d\000\000\000\000\000\000\000\000Exception taken, Other traps not taken locally\000 */
{ 52386 }, /* exc_trap_pabort\000\000exception\000Exception taken, Instruction Abort not taken locally\000\000\000event=0x8b\000\000\000\000\000\000\000\000Exception taken, Instruction Abort not taken locally\000 */
{ 52653 }, /* exc_undef\000\000exception\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000 */
{ 120089 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000 */
{ 19434 }, /* ase_inst_spec\000\000instruction\000ASE operations speculatively executed\000\000\000event=0x8005\000\000\000\000\000\000\000\000ASE operations speculatively executed\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 19721 }, /* ase_sve_int16_spec\000\000instruction\000Advanced SIMD and SVE 16-bit integer operations speculatively executed\000\000\000event=0x80e7\000\000\000\000\000\000\000\000Advanced SIMD and SVE 16-bit integer operations speculatively executed\000 */
{ 19917 }, /* ase_sve_int32_spec\000\000instruction\000Advanced SIMD and SVE 32-bit integer operations speculatively executed\000\000\000event=0x80eb\000\000\000\000\000\000\000\000Advanced SIMD and SVE 32-bit integer operations speculatively executed\000 */
{ 20113 }, /* ase_sve_int64_spec\000\000instruction\000Advanced SIMD and SVE 64-bit integer operations speculatively executed\000\000\000event=0x80ef\000\000\000\000\000\000\000\000Advanced SIMD and SVE 64-bit integer operations speculatively executed\000 */
{ 20309 }, /* ase_sve_int8_spec\000\000instruction\000Advanced SIMD and SVE 8-bit integer operations speculatively executed\000\000\000event=0x80e3\000\000\000\000\000\000\000\000Advanced SIMD and SVE 8-bit integer operations speculatively executed\000 */
{ 30824 }, /* br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000Instruction architecturally executed, mispredicted branch\000 */
{ 31554 }, /* br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000Instruction architecturally executed, branch\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 43623 }, /* dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 45327 }, /* dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 55680 }, /* fp_dp_spec\000\000instruction\000Floating-point double-precision operations speculatively executed\000\000\000event=0x801c\000\000\000\000\000\000\000\000Floating-point double-precision operations speculatively executed\000 */
{ 55858 }, /* fp_fixed_ops_spec\000\000instruction\000Non-scalable floating-point element Operations speculatively executed\000\000\000event=0x80c1\000\000\000\000\000\000\000\000Non-scalable floating-point element Operations speculatively executed\000 */
{ 56809 }, /* fp_hp_spec\000\000instruction\000Floating-point half-precision operations speculatively executed\000\000\000event=0x8014\000\000\000\000\000\000\000\000Floating-point half-precision operations speculatively executed\000 */
{ 57590 }, /* fp_scale_ops_spec\000\000instruction\000Scalable floating-point element Operations speculatively executed\000\000\000event=0x80c0\000\000\000\000\000\000\000\000Scalable floating-point element Operations speculatively executed\000 */
{ 58388 }, /* fp_sp_spec\000\000instruction\000Floating-point single-precision operations speculatively executed\000\000\000event=0x8018\000\000\000\000\000\000\000\000Floating-point single-precision operations speculatively executed\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116153 }, /* ldrex_spec\000\000instruction\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000 */
{ 122928 }, /* op_retired\000\000instruction\000Micro-operation architecturally executed\000\000\000event=0x3a\000\000\000\000\000\000\000\000Micro-operation architecturally executed.  The counter counts each operation counted by OP_SPEC that would be executed in a simple sequential execution of the program\000 */
{ 123180 }, /* op_spec\000\000instruction\000Micro-operation speculatively executed\000\000\000event=0x3b\000\000\000\000\000\000\000\000Micro-operation speculatively executed.  The counter counts the number of operations executed by the processing element, including those that are executed speculatively and would not be executed in a simple sequential execution of the program\000 */
{ 124643 }, /* pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000 */
{ 127257 }, /* rc_ld_spec\000\000instruction\000Release consistency operation speculatively executed, Load-Acquire\000\000\000event=0x90\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Load-Acquire\000 */
{ 127435 }, /* rc_st_spec\000\000instruction\000Release consistency operation speculatively executed, Store-Release\000\000\000event=0x91\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Store-Release\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 147124 }, /* strex_fail_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000 */
{ 147468 }, /* strex_pass_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX pass\000\000\000event=0x6d\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX pass\000 */
{ 147812 }, /* strex_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX\000\000\000event=0x6f\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX\000 */
{ 148390 }, /* sve_inst_spec\000\000instruction\000SVE operations speculatively executed\000\000\000event=0x8006\000\000\000\000\000\000\000\000SVE operations speculatively executed\000 */
{ 148661 }, /* sve_ldff_fault_spec\000\000instruction\000SVE first-fault load operations speculatively executed which set FFR bit to 0\000\000\000event=0x80bd\000\000\000\000\000\000\000\000SVE first-fault load operations speculatively executed which set FFR bit to 0\000 */
{ 148872 }, /* sve_ldff_spec\000\000instruction\000SVE First-fault load Operations speculatively executed\000\000\000event=0x80bc\000\000\000\000\000\000\000\000SVE First-fault load Operations speculatively executed\000 */
{ 149966 }, /* sve_pred_empty_spec\000\000instruction\000SVE predicated operations with no active predicates speculatively executed\000\000\000event=0x8075\000\000\000\000\000\000\000\000SVE predicated operations with no active predicates speculatively executed\000 */
{ 150171 }, /* sve_pred_full_spec\000\000instruction\000SVE predicated operations speculatively executed with all active predicates\000\000\000event=0x8076\000\000\000\000\000\000\000\000SVE predicated operations speculatively executed with all active predicates\000 */
{ 150377 }, /* sve_pred_not_full_spec\000\000instruction\000SVE predicated operations with empty or partially active predicates\000\000\000event=0x8079\000\000\000\000\000\000\000\000SVE predicated operations with empty or partially active predicates\000 */
{ 150571 }, /* sve_pred_partial_spec\000\000instruction\000SVE predicated operations speculatively executed with partially active predicates\000\000\000event=0x8077\000\000\000\000\000\000\000\000SVE predicated operations speculatively executed with partially active predicates\000 */
{ 150792 }, /* sve_pred_spec\000\000instruction\000SVE predicated Operations speculatively executed\000\000\000event=0x8074\000\000\000\000\000\000\000\000SVE predicated Operations speculatively executed\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 112722 }, /* ld_align_lat\000\000memory\000Load with additional latency from alignment\000\000\000event=0x4021\000\000\000\000\000\000\000\000Load with additional latency from alignment\000 */
{ 116467 }, /* ldst_align_lat\000\000memory\000Access with additional latency from alignment\000\000\000event=0x4020\000\000\000\000\000\000\000\000Access with additional latency from alignment\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118524 }, /* mem_access_checked\000\000memory\000Checked data memory access\000\000\000event=0x4024\000\000\000\000\000\000\000\000Checked data memory access\000 */
{ 118627 }, /* mem_access_checked_rd\000\000memory\000Checked data memory access, read\000\000\000event=0x4025\000\000\000\000\000\000\000\000Checked data memory access, read\000 */
{ 118745 }, /* mem_access_checked_wr\000\000memory\000Checked data memory access, write\000\000\000event=0x4026\000\000\000\000\000\000\000\000Checked data memory access, write\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 128878 }, /* remote_access\000\000memory\000Access to another socket in a multi-socket system\000\000\000event=0x31\000\000\000\000\000\000\000\000Access to another socket in a multi-socket system\000 */
{ 133247 }, /* st_align_lat\000\000memory\000Store with additional latency from alignment\000\000\000event=0x4022\000\000\000\000\000\000\000\000Store with additional latency from alignment\000 */
{ 156587 }, /* unaligned_ld_spec\000\000memory\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000 */
{ 156967 }, /* unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 157149 }, /* unaligned_st_spec\000\000memory\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000 */
{ 133789 }, /* stall\000\000pipeline\000No operation sent for execution\000\000\000event=0x3c\000\000\000\000\000\000\000\000No operation sent for execution.  The counter counts every attributable cycle on which no attributable instruction or operation was sent for execution on this processing element\000 */
{ 134035 }, /* stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000No operation issued due to the backend\000 */
{ 140211 }, /* stall_backend_mem\000\000pipeline\000Memory stall cycles\000\000\000event=0x4005\000\000\000\000\000\000\000\000Memory stall cycles.  The counter counts each cycle counted by STALL_BACKEND where there is a cache miss in the last level of cache within the processing element clock domain\000 */
{ 143105 }, /* stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000No operation issued because of the frontend\000 */
{ 145656 }, /* stall_slot\000\000pipeline\000No operation sent for execution on a slot\000\000\000event=0x3f\000\000\000\000\000\000\000\000No operation sent for execution on a slot.  The counter counts on each attributable cycle the number of instruction or operation slots that were not occupied by an instruction or operation attributable to the processing element\000 */
{ 145967 }, /* stall_slot_backend\000\000pipeline\000No operation sent for execution on a slot due to the backend\000\000\000event=0x3d\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the backend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because the backend is unable to accept it\000 */
{ 146613 }, /* stall_slot_frontend\000\000pipeline\000No operation sent for execution on a slot due to the frontend\000\000\000event=0x3e\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the frontend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because there was no attributable instruction or operation available to issue from the processing element from the frontend for the slot\000 */
{ 41211 }, /* cti_trigout4\000\000trace\000Cross-trigger Interface output trigger 4\000\000\000event=0x4018\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 4\000 */
{ 41335 }, /* cti_trigout5\000\000trace\000Cross-trigger Interface output trigger 5 \000\000\000event=0x4019\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 5 \000 */
{ 41461 }, /* cti_trigout6\000\000trace\000Cross-trigger Interface output trigger 6\000\000\000event=0x401a\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 6\000 */
{ 41585 }, /* cti_trigout7\000\000trace\000Cross-trigger Interface output trigger 7\000\000\000event=0x401b\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 7\000 */
{ 155265 }, /* trb_wrap\000\000trace\000Trace buffer current write pointer wrapped\000\000\000event=0x400c\000\000\000\000\000\000\000\000Trace buffer current write pointer wrapped\000 */
{ 155389 }, /* trcextout0\000\000trace\000PE Trace Unit external output 0\000\000\000event=0x4010\000\000\000\000\000\000\000\000PE Trace Unit external output 0\000 */
{ 155493 }, /* trcextout1\000\000trace\000PE Trace Unit external output 1\000\000\000event=0x4011\000\000\000\000\000\000\000\000PE Trace Unit external output 1\000 */
{ 155597 }, /* trcextout2\000\000trace\000PE Trace Unit external output 2\000\000\000event=0x4012\000\000\000\000\000\000\000\000PE Trace Unit external output 2\000 */
{ 155701 }, /* trcextout3\000\000trace\000PE Trace Unit external output 3\000\000\000event=0x4013\000\000\000\000\000\000\000\000PE Trace Unit external output 3\000 */
};

static const struct compact_pmu_event pme_arm_cortex_a35[] = {
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 120089 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 25639 }, /* br_immed_retired\000\000instruction\000Instruction architecturally executed, immediate branch\000\000\000event=0xd\000\000\000\000\000\000\000\000Instruction architecturally executed, immediate branch\000 */
{ 34454 }, /* br_return_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, procedure return\000\000\000event=0xe\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, procedure return\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 115851 }, /* ld_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, load\000\000\000event=0x6\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, load\000 */
{ 124412 }, /* pc_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, software change of the PC\000\000\000event=0xc\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, software change of the PC\000 */
{ 133483 }, /* st_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, store\000\000\000event=0x7\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, store\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 156679 }, /* unaligned_ldst_retired\000\000memory\000Instruction architecturally executed, condition code check pass, unaligned\000\000\000event=0xf\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, unaligned\000 */
};

static const struct compact_pmu_event pme_arm_neoverse_n2[] = {
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 39149 }, /* cnt_cycles\000\000bus\000Constant frequency cycles\000\000\000event=0x4004\000\000\000\000\000\000\000\000Constant frequency cycles.  The counter increments at a constant frequency equal to the rate of increment of the system counter, CNTPCT_EL0\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 45496 }, /* dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000Access to data TLB causes a translation table walk\000 */
{ 66317 }, /* itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000Access to instruction TLB that causes a translation table walk\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72009 }, /* l1d_cache_inval\000\000cache\000L1D cache invalidate\000\000\000event=0x48\000\000\000\000\000\000\000\000Attributable Level 1 data cache invalidate\000 */
{ 72327 }, /* l1d_cache_lmiss_rd\000\000cache\000Level 1 data cache long-latency read miss\000\000\000event=0x39\000\000\000\000\000\000\000\000Level 1 data cache long-latency read miss.  The counter counts each memory read access counted by L1D_CACHE that incurs additional latency because it returns data from outside the Level 1 data or unified cache of this processing element\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 73655 }, /* l1d_cache_refill_inner\000\000cache\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000 */
{ 73902 }, /* l1d_cache_refill_outer\000\000cache\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000 */
{ 75011 }, /* l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75248 }, /* l1d_cache_refill_wr\000\000cache\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 75865 }, /* l1d_cache_wb_clean\000\000cache\000L1D cache Write-Back, cleaning and coherency\000\000\000event=0x47\000\000\000\000\000\000\000\000Level 1 data cache Write-Back, cleaning and coherency\000 */
{ 76162 }, /* l1d_cache_wb_victim\000\000cache\000L1D cache Write-Back, victim\000\000\000event=0x46\000\000\000\000\000\000\000\000Attributable Level 1 data cache Write-Back, victim\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 76972 }, /* l1d_tlb\000\000cache\000Attributable Level 1 data or unified TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access\000 */
{ 77503 }, /* l1d_tlb_rd\000\000cache\000L1D tlb access, read\000\000\000event=0x4e\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, read\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 78051 }, /* l1d_tlb_refill_rd\000\000cache\000L1D tlb refill, read\000\000\000event=0x4c\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, read\000 */
{ 78276 }, /* l1d_tlb_refill_wr\000\000cache\000L1D tlb refill, write\000\000\000event=0x4d\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill, write\000 */
{ 78505 }, /* l1d_tlb_wr\000\000cache\000L1D tlb access, write\000\000\000event=0x4f\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access, write\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 81421 }, /* l1i_cache_lmiss\000\000cache\000Level 1 instruction cache long-latency read miss\000\000\000event=0x4006\000\000\000\000\000\000\000\000Level 1 instruction cache long-latency read miss.  If the L1I_CACHE_RD event is implemented, the counter counts each access counted by L1I_CACHE_RD that incurs additional latency because it returns instructions from outside of the Level 1 instruction cache of this PE.  If the L1I_CACHE_RD event is not implemented, the counter counts each access counted by L1I_CACHE that incurs additional latency because it returns instructions from outside the Level 1 instruction cache of this PE.  The event indicates to software that the access missed in the Level 1 instruction cache and might have a significant performance impact due to the additional latency, compared to the latency of an access that hits in the Level 1 instruction cache\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83274 }, /* l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB access\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 88772 }, /* l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000Attributable Level 2 data cache allocation without refill\000 */
{ 89220 }, /* l2d_cache_inval\000\000cache\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000 */
{ 89441 }, /* l2d_cache_lmiss_rd\000\000cache\000Level 2 data cache long-latency read miss\000\000\000event=0x4009\000\000\000\000\000\000\000\000Level 2 data cache long-latency read miss.  The counter counts each memory read access counted by L2D_CACHE that incurs additional latency because it returns data from outside the Level 2 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 2 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 2 data or unified cache\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 93050 }, /* l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93287 }, /* l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97102 }, /* l2d_cache_wb_clean\000\000cache\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000 */
{ 97399 }, /* l2d_cache_wb_victim\000\000cache\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 102443 }, /* l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access\000 */
{ 102985 }, /* l2d_tlb_rd\000\000cache\000L2D cache access, read\000\000\000event=0x5e\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, read\000 */
{ 103449 }, /* l2d_tlb_refill\000\000cache\000Attributable Level 2 data TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000Attributable Level 2 data TLB refill\000 */
{ 103565 }, /* l2d_tlb_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x5c\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, read\000 */
{ 103816 }, /* l2d_tlb_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x5d\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB refill, write\000 */
{ 104071 }, /* l2d_tlb_wr\000\000cache\000L2D cache access, write\000\000\000event=0x5f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access, write\000 */
{ 108575 }, /* l3d_cache\000\000cache\000Attributable Level 3 data cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000Attributable Level 3 data cache access\000 */
{ 109142 }, /* l3d_cache_allocate\000\000cache\000Attributable Level 3 data cache allocation without refill\000\000\000event=0x29\000\000\000\000\000\000\000\000Attributable Level 3 data cache allocation without refill\000 */
{ 109304 }, /* l3d_cache_lmiss_rd\000\000cache\000Level 3 data cache long-latency read miss\000\000\000event=0x400b\000\000\000\000\000\000\000\000Level 3 data cache long-latency read miss.  The counter counts each memory read access counted by L3D_CACHE that incurs additional latency because it returns data from outside the Level 3 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 3 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 3 data or unified cache\000 */
{ 109857 }, /* l3d_cache_rd\000\000cache\000Attributable Level 3 data or unified cache access, read\000\000\000event=0xa0\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache access, read\000 */
{ 110009 }, /* l3d_cache_refill\000\000cache\000Attributable Level 3 data cache refill\000\000\000event=0x2a\000\000\000\000\000\000\000\000Attributable Level 3 data cache refill\000 */
{ 116870 }, /* ll_cache_miss_rd\000\000cache\000Last level cache miss, read\000\000\000event=0x37\000\000\000\000\000\000\000\000Last level cache miss, read\000 */
{ 116970 }, /* ll_cache_rd\000\000cache\000Attributable Last level cache memory read\000\000\000event=0x36\000\000\000\000\000\000\000\000Attributable Last level cache memory read\000 */
{ 48296 }, /* exc_dabort\000\000exception\000Exception taken, Data Abort and SError\000\000\000event=0x84\000\000\000\000\000\000\000\000Exception taken, Data Abort and SError\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48766 }, /* exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 49228 }, /* exc_pabort\000\000exception\000Exception taken, Instruction Abort\000\000\000event=0x83\000\000\000\000\000\000\000\000Exception taken, Instruction Abort\000 */
{ 49848 }, /* exc_smc\000\000exception\000Exception taken, Secure Monitor Call\000\000\000event=0x88\000\000\000\000\000\000\000\000Exception taken, Secure Monitor Call\000 */
{ 50069 }, /* exc_svc\000\000exception\000Exception taken, Supervisor Call\000\000\000event=0x82\000\000\000\000\000\000\000\000Exception taken, Supervisor Call\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 50408 }, /* exc_trap_dabort\000\000exception\000Exception taken, Data Abort or SError not taken locally\000\000\000event=0x8c\000\000\000\000\000\000\000\000Exception taken, Data Abort or SError not taken locally\000 */
{ 50692 }, /* exc_trap_fiq\000\000exception\000Exception taken, FIQ not taken locally\000\000\000event=0x8f\000\000\000\000\000\000\000\000Exception taken, FIQ not taken locally\000 */
{ 51825 }, /* exc_trap_irq\000\000exception\000Exception taken, IRQ not taken locally\000\000\000event=0x8e\000\000\000\000\000\000\000\000Exception taken, IRQ not taken locally\000 */
{ 52090 }, /* exc_trap_other\000\000exception\000Exception taken, Other traps not taken locally\000\000\000event=0x8d\000\000\000\000\000\000\000\000Exception taken, Other traps not taken locally\000 */
{ 52386 }, /* exc_trap_pabort\000\000exception\000Exception taken, Instruction Abort not taken locally\000\000\000event=0x8b\000\000\000\000\000\000\000\000Exception taken, Instruction Abort not taken locally\000 */
{ 52653 }, /* exc_undef\000\000exception\000Exception taken, Other synchronous\000\000\000event=0x81\000\000\000\000\000\000\000\000Exception taken, Other synchronous\000 */
{ 120089 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000 */
{ 19434 }, /* ase_inst_spec\000\000instruction\000ASE operations speculatively executed\000\000\000event=0x8005\000\000\000\000\000\000\000\000ASE operations speculatively executed\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 19721 }, /* ase_sve_int16_spec\000\000instruction\000Advanced SIMD and SVE 16-bit integer operations speculatively executed\000\000\000event=0x80e7\000\000\000\000\000\000\000\000Advanced SIMD and SVE 16-bit integer operations speculatively executed\000 */
{ 19917 }, /* ase_sve_int32_spec\000\000instruction\000Advanced SIMD and SVE 32-bit integer operations speculatively executed\000\000\000event=0x80eb\000\000\000\000\000\000\000\000Advanced SIMD and SVE 32-bit integer operations speculatively executed\000 */
{ 20113 }, /* ase_sve_int64_spec\000\000instruction\000Advanced SIMD and SVE 64-bit integer operations speculatively executed\000\000\000event=0x80ef\000\000\000\000\000\000\000\000Advanced SIMD and SVE 64-bit integer operations speculatively executed\000 */
{ 20309 }, /* ase_sve_int8_spec\000\000instruction\000Advanced SIMD and SVE 8-bit integer operations speculatively executed\000\000\000event=0x80e3\000\000\000\000\000\000\000\000Advanced SIMD and SVE 8-bit integer operations speculatively executed\000 */
{ 25936 }, /* br_immed_spec\000\000instruction\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 30111 }, /* br_indirect_spec\000\000instruction\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30824 }, /* br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000Instruction architecturally executed, mispredicted branch\000 */
{ 31554 }, /* br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000Instruction architecturally executed, branch\000 */
{ 34807 }, /* br_return_spec\000\000instruction\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 43623 }, /* dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 45327 }, /* dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 55680 }, /* fp_dp_spec\000\000instruction\000Floating-point double-precision operations speculatively executed\000\000\000event=0x801c\000\000\000\000\000\000\000\000Floating-point double-precision operations speculatively executed\000 */
{ 55858 }, /* fp_fixed_ops_spec\000\000instruction\000Non-scalable floating-point element Operations speculatively executed\000\000\000event=0x80c1\000\000\000\000\000\000\000\000Non-scalable floating-point element Operations speculatively executed\000 */
{ 56809 }, /* fp_hp_spec\000\000instruction\000Floating-point half-precision operations speculatively executed\000\000\000event=0x8014\000\000\000\000\000\000\000\000Floating-point half-precision operations speculatively executed\000 */
{ 57590 }, /* fp_scale_ops_spec\000\000instruction\000Scalable floating-point element Operations speculatively executed\000\000\000event=0x80c0\000\000\000\000\000\000\000\000Scalable floating-point element Operations speculatively executed\000 */
{ 58388 }, /* fp_sp_spec\000\000instruction\000Floating-point single-precision operations speculatively executed\000\000\000event=0x8018\000\000\000\000\000\000\000\000Floating-point single-precision operations speculatively executed\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116153 }, /* ldrex_spec\000\000instruction\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000 */
{ 122928 }, /* op_retired\000\000instruction\000Micro-operation architecturally executed\000\000\000event=0x3a\000\000\000\000\000\000\000\000Micro-operation architecturally executed.  The counter counts each operation counted by OP_SPEC that would be executed in a simple sequential execution of the program\000 */
{ 123180 }, /* op_spec\000\000instruction\000Micro-operation speculatively executed\000\000\000event=0x3b\000\000\000\000\000\000\000\000Micro-operation speculatively executed.  The counter counts the number of operations executed by the processing element, including those that are executed speculatively and would not be executed in a simple sequential execution of the program\000 */
{ 124643 }, /* pc_write_spec\000\000instruction\000Operation speculatively executed, software change of the PC\000\000\000event=0x76\000\000\000\000\000\000\000\000Operation speculatively executed, software change of the PC\000 */
{ 127257 }, /* rc_ld_spec\000\000instruction\000Release consistency operation speculatively executed, Load-Acquire\000\000\000event=0x90\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Load-Acquire\000 */
{ 127435 }, /* rc_st_spec\000\000instruction\000Release consistency operation speculatively executed, Store-Release\000\000\000event=0x91\000\000\000\000\000\000\000\000Release consistency operation speculatively executed, Store-Release\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 147124 }, /* strex_fail_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000 */
{ 147468 }, /* strex_pass_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX pass\000\000\000event=0x6d\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX pass\000 */
{ 147812 }, /* strex_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX\000\000\000event=0x6f\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX\000 */
{ 148390 }, /* sve_inst_spec\000\000instruction\000SVE operations speculatively executed\000\000\000event=0x8006\000\000\000\000\000\000\000\000SVE operations speculatively executed\000 */
{ 148661 }, /* sve_ldff_fault_spec\000\000instruction\000SVE first-fault load operations speculatively executed which set FFR bit to 0\000\000\000event=0x80bd\000\000\000\000\000\000\000\000SVE first-fault load operations speculatively executed which set FFR bit to 0\000 */
{ 148872 }, /* sve_ldff_spec\000\000instruction\000SVE First-fault load Operations speculatively executed\000\000\000event=0x80bc\000\000\000\000\000\000\000\000SVE First-fault load Operations speculatively executed\000 */
{ 149966 }, /* sve_pred_empty_spec\000\000instruction\000SVE predicated operations with no active predicates speculatively executed\000\000\000event=0x8075\000\000\000\000\000\000\000\000SVE predicated operations with no active predicates speculatively executed\000 */
{ 150171 }, /* sve_pred_full_spec\000\000instruction\000SVE predicated operations speculatively executed with all active predicates\000\000\000event=0x8076\000\000\000\000\000\000\000\000SVE predicated operations speculatively executed with all active predicates\000 */
{ 150377 }, /* sve_pred_not_full_spec\000\000instruction\000SVE predicated operations with empty or partially active predicates\000\000\000event=0x8079\000\000\000\000\000\000\000\000SVE predicated operations with empty or partially active predicates\000 */
{ 150571 }, /* sve_pred_partial_spec\000\000instruction\000SVE predicated operations speculatively executed with partially active predicates\000\000\000event=0x8077\000\000\000\000\000\000\000\000SVE predicated operations speculatively executed with partially active predicates\000 */
{ 150792 }, /* sve_pred_spec\000\000instruction\000SVE predicated Operations speculatively executed\000\000\000event=0x8074\000\000\000\000\000\000\000\000SVE predicated Operations speculatively executed\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 112722 }, /* ld_align_lat\000\000memory\000Load with additional latency from alignment\000\000\000event=0x4021\000\000\000\000\000\000\000\000Load with additional latency from alignment\000 */
{ 116467 }, /* ldst_align_lat\000\000memory\000Access with additional latency from alignment\000\000\000event=0x4020\000\000\000\000\000\000\000\000Access with additional latency from alignment\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118524 }, /* mem_access_checked\000\000memory\000Checked data memory access\000\000\000event=0x4024\000\000\000\000\000\000\000\000Checked data memory access\000 */
{ 118627 }, /* mem_access_checked_rd\000\000memory\000Checked data memory access, read\000\000\000event=0x4025\000\000\000\000\000\000\000\000Checked data memory access, read\000 */
{ 118745 }, /* mem_access_checked_wr\000\000memory\000Checked data memory access, write\000\000\000event=0x4026\000\000\000\000\000\000\000\000Checked data memory access, write\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 128878 }, /* remote_access\000\000memory\000Access to another socket in a multi-socket system\000\000\000event=0x31\000\000\000\000\000\000\000\000Access to another socket in a multi-socket system\000 */
{ 133247 }, /* st_align_lat\000\000memory\000Store with additional latency from alignment\000\000\000event=0x4022\000\000\000\000\000\000\000\000Store with additional latency from alignment\000 */
{ 156587 }, /* unaligned_ld_spec\000\000memory\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000 */
{ 156967 }, /* unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 157149 }, /* unaligned_st_spec\000\000memory\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000 */
{ 133789 }, /* stall\000\000pipeline\000No operation sent for execution\000\000\000event=0x3c\000\000\000\000\000\000\000\000No operation sent for execution.  The counter counts every attributable cycle on which no attributable instruction or operation was sent for execution on this processing element\000 */
{ 134035 }, /* stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000No operation issued due to the backend\000 */
{ 140211 }, /* stall_backend_mem\000\000pipeline\000Memory stall cycles\000\000\000event=0x4005\000\000\000\000\000\000\000\000Memory stall cycles.  The counter counts each cycle counted by STALL_BACKEND where there is a cache miss in the last level of cache within the processing element clock domain\000 */
{ 143105 }, /* stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000No operation issued because of the frontend\000 */
{ 145656 }, /* stall_slot\000\000pipeline\000No operation sent for execution on a slot\000\000\000event=0x3f\000\000\000\000\000\000\000\000No operation sent for execution on a slot.  The counter counts on each attributable cycle the number of instruction or operation slots that were not occupied by an instruction or operation attributable to the processing element\000 */
{ 145967 }, /* stall_slot_backend\000\000pipeline\000No operation sent for execution on a slot due to the backend\000\000\000event=0x3d\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the backend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because the backend is unable to accept it\000 */
{ 146613 }, /* stall_slot_frontend\000\000pipeline\000No operation sent for execution on a slot due to the frontend\000\000\000event=0x3e\000\000\000\000\000\000\000\000No operation sent for execution on a slot due to the frontend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because there was no attributable instruction or operation available to issue from the processing element from the frontend for the slot\000 */
{ 131629 }, /* sample_collision\000\000spe\000Sample collided with previous sample\000\000\000event=0x4003\000\000\000\000\000\000\000\000Sample collided with previous sample\000 */
{ 131747 }, /* sample_feed\000\000spe\000Sample Taken\000\000\000event=0x4001\000\000\000\000\000\000\000\000Sample Taken\000 */
{ 131812 }, /* sample_filtrate\000\000spe\000Sample Taken and not removed by filtering\000\000\000event=0x4002\000\000\000\000\000\000\000\000Sample Taken and not removed by filtering\000 */
{ 131939 }, /* sample_pop\000\000spe\000Sample Population\000\000\000event=0x4000\000\000\000\000\000\000\000\000Sample Population\000 */
{ 41211 }, /* cti_trigout4\000\000trace\000Cross-trigger Interface output trigger 4\000\000\000event=0x4018\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 4\000 */
{ 41335 }, /* cti_trigout5\000\000trace\000Cross-trigger Interface output trigger 5 \000\000\000event=0x4019\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 5 \000 */
{ 41461 }, /* cti_trigout6\000\000trace\000Cross-trigger Interface output trigger 6\000\000\000event=0x401a\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 6\000 */
{ 41585 }, /* cti_trigout7\000\000trace\000Cross-trigger Interface output trigger 7\000\000\000event=0x401b\000\000\000\000\000\000\000\000Cross-trigger Interface output trigger 7\000 */
{ 155265 }, /* trb_wrap\000\000trace\000Trace buffer current write pointer wrapped\000\000\000event=0x400c\000\000\000\000\000\000\000\000Trace buffer current write pointer wrapped\000 */
{ 155389 }, /* trcextout0\000\000trace\000PE Trace Unit external output 0\000\000\000event=0x4010\000\000\000\000\000\000\000\000PE Trace Unit external output 0\000 */
{ 155493 }, /* trcextout1\000\000trace\000PE Trace Unit external output 1\000\000\000event=0x4011\000\000\000\000\000\000\000\000PE Trace Unit external output 1\000 */
{ 155597 }, /* trcextout2\000\000trace\000PE Trace Unit external output 2\000\000\000event=0x4012\000\000\000\000\000\000\000\000PE Trace Unit external output 2\000 */
{ 155701 }, /* trcextout3\000\000trace\000PE Trace Unit external output 3\000\000\000event=0x4013\000\000\000\000\000\000\000\000PE Trace Unit external output 3\000 */
};

static const struct compact_pmu_event pme_arm_cortex_a65_e1[] = {
{ 25798 }, /* br_immed_spec\000\000branch\000Branch speculatively executed, immediate branch\000\000\000event=0x78\000\000\000\000\000\000\000\000Branch speculatively executed, immediate branch\000 */
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 34668 }, /* br_return_spec\000\000branch\000Branch speculatively executed, procedure return\000\000\000event=0x79\000\000\000\000\000\000\000\000Branch speculatively executed, procedure return\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35774 }, /* bus_access_rd\000\000bus\000Bus access read\000\000\000event=0x60\000\000\000\000\000\000\000\000Bus access read\000 */
{ 36050 }, /* bus_access_wr\000\000bus\000Bus access write\000\000\000event=0x61\000\000\000\000\000\000\000\000Bus access write\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 45496 }, /* dtlb_walk\000\000cache\000Access to data TLB causes a translation table walk\000\000\000event=0x34\000\000\000\000\000\000\000\000Access to data TLB causes a translation table walk\000 */
{ 66317 }, /* itlb_walk\000\000cache\000Access to instruction TLB that causes a translation table walk\000\000\000event=0x35\000\000\000\000\000\000\000\000Access to instruction TLB that causes a translation table walk\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 73655 }, /* l1d_cache_refill_inner\000\000cache\000L1D cache refill, inner\000\000\000event=0x44\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, inner\000 */
{ 73902 }, /* l1d_cache_refill_outer\000\000cache\000L1D cache refill, outer\000\000\000event=0x45\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, outer\000 */
{ 75011 }, /* l1d_cache_refill_rd\000\000cache\000L1D cache refill, read\000\000\000event=0x42\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, read\000 */
{ 75248 }, /* l1d_cache_refill_wr\000\000cache\000L1D cache refill, write\000\000\000event=0x43\000\000\000\000\000\000\000\000Attributable Level 1 data cache refill, write\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 76650 }, /* l1d_pref_line_fill\000\000cache\000Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache\000\000\000event=0xc3\000\000\000\000\000\000\000\000Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache\000 */
{ 76972 }, /* l1d_tlb\000\000cache\000Attributable Level 1 data or unified TLB access\000\000\000event=0x25\000\000\000\000\000\000\000\000Attributable Level 1 data or unified TLB access\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 79107 }, /* l1d_ws_mode\000\000cache\000L1D is in write stream mode\000\000\000event=0xc7\000\000\000\000\000\000\000\000L1D is in write stream mode\000 */
{ 79563 }, /* l1d_ws_mode_enter\000\000cache\000L1D entering write stream mode\000\000\000event=0xc6\000\000\000\000\000\000\000\000L1D entering write stream mode\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83274 }, /* l1i_tlb\000\000cache\000Attributable Level 1 instruction TLB access\000\000\000event=0x26\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB access\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 84783 }, /* l2_l1d_cache_wb_unatt\000\000cache\000Unattributable Level 1 data cache write-back. This event occurs when a requestor outside the PE makes a coherency request that results in writeback\000\000\000event=0xf0\000\000\000\000\000\000\000\000Unattributable Level 1 data cache write-back. This event occurs when a requestor outside the PE makes a coherency request that results in writeback\000 */
{ 85128 }, /* l2_l2d_cache_rd_unatt\000\000cache\000Unattributable Level 2 data cache access, read. This event occurs when a requestor outside the PE makes a coherency request that results in level 2 data cache read access\000\000\000event=0xf2\000\000\000\000\000\000\000\000Unattributable Level 2 data cache access, read. This event occurs when a requestor outside the PE makes a coherency request that results in level 2 data cache read access\000 */
{ 85519 }, /* l2_l2d_cache_unatt\000\000cache\000Unattributable Level 2 data cache access. This event occurs when a requestor outside the PE makes a coherency request that results in level 2 data cache access\000\000\000event=0xf1\000\000\000\000\000\000\000\000Unattributable Level 2 data cache access. This event occurs when a requestor outside the PE makes a coherency request that results in level 2 data cache access\000 */
{ 85885 }, /* l2_l3d_cache_alloc_unatt\000\000cache\000Unattributable Level 3 data or unified cache allocation without refill. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 cache allocate without refill\000\000\000event=0xf5\000\000\000\000\000\000\000\000Unattributable Level 3 data or unified cache allocation without refill. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 cache allocate without refill\000 */
{ 86341 }, /* l2_l3d_cache_rd_unatt\000\000cache\000Unattributable Level 3 data cache access, read. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 data cache read access\000\000\000event=0xf4\000\000\000\000\000\000\000\000Unattributable Level 3 data cache access, read. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 data cache read access\000 */
{ 86732 }, /* l2_l3d_cache_refill_unatt\000\000cache\000Unattributable Level 3 data or unified cache refill. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 cache refill\000\000\000event=0xf6\000\000\000\000\000\000\000\000Unattributable Level 3 data or unified cache refill. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 cache refill\000 */
{ 87117 }, /* l2_l3d_cache_unatt\000\000cache\000Unattributable Level 3 data cache access. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 data cache read access\000\000\000event=0xf3\000\000\000\000\000\000\000\000Unattributable Level 3 data cache access. This event occurs when a requestor outside the PE makes a coherency request that results in level 3 data cache read access\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 88772 }, /* l2d_cache_allocate\000\000cache\000Attributable Level 2 data cache allocation without refill\000\000\000event=0x20\000\000\000\000\000\000\000\000Attributable Level 2 data cache allocation without refill\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 93050 }, /* l2d_cache_refill_rd\000\000cache\000L2D cache refill, read\000\000\000event=0x52\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, read\000 */
{ 93287 }, /* l2d_cache_refill_wr\000\000cache\000L2D cache refill, write\000\000\000event=0x53\000\000\000\000\000\000\000\000Attributable Level 2 data cache refill, write\000 */
{ 94037 }, /* l2d_cache_stash_dropped\000\000cache\000Level 2 cache stash dropped. This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request. L2 and L3 cache events (L2D_CACHE*, L3D_CACHE*) The behavior of these events depends on the configuration of the core. If the private L2 cache is present, the L2D_CACHE* events count the activity in the private L2 cache, and the L3D_CACHE* events count the activity in the DSU L3 cache (if present). If the private L2 cache is not present but the DSU L3 cache is present, the L2D_CACHE* events count activity in the DSU L3 cache and the L3D_CACHE* events do not count. The L2D_CACHE_WB, L2D_CACHE_WR and L2D_CACHE_REFILL_WR events do not count in this configuration. If neither the private L2 cache nor the DSU L3 cache are present, neither the L2D_CACHE* or L3D_CACHE* events will count\000\000\000event=0xf7\000\000\000\000\000\000\000\000Level 2 cache stash dropped. This event counts on each stash request received from the interconnect or ACP, that is targeting L2 and gets dropped due to lack of buffer space to hold the request. L2 and L3 cache events (L2D_CACHE*, L3D_CACHE*) The behavior of these events depends on the configuration of the core. If the private L2 cache is present, the L2D_CACHE* events count the activity in the private L2 cache, and the L3D_CACHE* events count the activity in the DSU L3 cache (if present). If the private L2 cache is not present but the DSU L3 cache is present, the L2D_CACHE* events count activity in the DSU L3 cache and the L3D_CACHE* events do not count. The L2D_CACHE_WB, L2D_CACHE_WR and L2D_CACHE_REFILL_WR events do not count in this configuration. If neither the private L2 cache nor the DSU L3 cache are present, neither the L2D_CACHE* or L3D_CACHE* events will count\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 99155 }, /* l2d_pref_line_fill\000\000cache\000Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3_PREF_LINE_FILL. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented\000\000\000event=0xc4\000\000\000\000\000\000\000\000Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 cache: This event counts the cluster cache event, as defined by L3_PREF_LINE_FILL. +//0 If there is neither a per-core cache nor a cluster cache configured, this event is not implemented\000 */
{ 102443 }, /* l2d_tlb\000\000cache\000Attributable Level 2 data or unified TLB access\000\000\000event=0x2f\000\000\000\000\000\000\000\000Attributable Level 2 data or unified TLB access\000 */
{ 103449 }, /* l2d_tlb_refill\000\000cache\000Attributable Level 2 data TLB refill\000\000\000event=0x2d\000\000\000\000\000\000\000\000Attributable Level 2 data TLB refill\000 */
{ 105393 }, /* l2d_ws_mode\000\000cache\000Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache\000\000\000event=0xc8\000\000\000\000\000\000\000\000Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L2 cache\000 */
{ 107520 }, /* l3_pref_line_fill\000\000cache\000Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to distinguish between both hardware and software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented\000\000\000event=0xc5\000\000\000\000\000\000\000\000Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which cause an allocation into the L3 cache. Note It might not be possible to distinguish between both hardware and software prefetches and also which prefetches cause an allocation. If so, only hardware prefetches should be counted, regardless of whether they allocate. If either the core is configured without a per-core L2 or the cluster is configured without an L3 cache, this event is not implemented\000 */
{ 108575 }, /* l3d_cache\000\000cache\000Attributable Level 3 data cache access\000\000\000event=0x2b\000\000\000\000\000\000\000\000Attributable Level 3 data cache access\000 */
{ 109142 }, /* l3d_cache_allocate\000\000cache\000Attributable Level 3 data cache allocation without refill\000\000\000event=0x29\000\000\000\000\000\000\000\000Attributable Level 3 data cache allocation without refill\000 */
{ 109857 }, /* l3d_cache_rd\000\000cache\000Attributable Level 3 data or unified cache access, read\000\000\000event=0xa0\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache access, read\000 */
{ 110009 }, /* l3d_cache_refill\000\000cache\000Attributable Level 3 data cache refill\000\000\000event=0x2a\000\000\000\000\000\000\000\000Attributable Level 3 data cache refill\000 */
{ 111522 }, /* l3d_cache_refill_rd\000\000cache\000Attributable Level 3 data or unified cache refill, read\000\000\000event=0xa2\000\000\000\000\000\000\000\000Attributable Level 3 data or unified cache refill, read\000 */
{ 112026 }, /* l3d_ws_mode\000\000cache\000Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache\000\000\000event=0xc9\000\000\000\000\000\000\000\000Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-streaming mode and not allocating writes into the L3 cache\000 */
{ 116870 }, /* ll_cache_miss_rd\000\000cache\000Last level cache miss, read\000\000\000event=0x37\000\000\000\000\000\000\000\000Last level cache miss, read\000 */
{ 116970 }, /* ll_cache_rd\000\000cache\000Attributable Last level cache memory read\000\000\000event=0x36\000\000\000\000\000\000\000\000Attributable Last level cache memory read\000 */
{ 147035 }, /* stb_stall\000\000cache\000Merge in the store buffer\000\000\000event=0xc0\000\000\000\000\000\000\000\000Merge in the store buffer\000 */
{ 152675 }, /* tlb_l2tlb_l2walk_access\000\000cache\000Level 2 TLB level-2 walk cache access. This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled\000\000\000event=0xcc\000\000\000\000\000\000\000\000Level 2 TLB level-2 walk cache access. This event counts accesses to the level-2 walk cache where the last-level walk cache has missed. The event only counts when the translation regime of the pagewalk uses level 2 descriptors. This event does not count if the MMU is disabled\000 */
{ 153280 }, /* tlb_l2tlb_l2walk_refill\000\000cache\000Level 2 TLB level-2 walk cache refill. This event does not count if the MMU is disabled\000\000\000event=0xcd\000\000\000\000\000\000\000\000Level 2 TLB level-2 walk cache refill. This event does not count if the MMU is disabled\000 */
{ 153507 }, /* tlb_l2tlb_llwalk_access\000\000cache\000Level 2 TLB last-level walk cache access. This event does not count if the MMU is disabled\000\000\000event=0xca\000\000\000\000\000\000\000\000Level 2 TLB last-level walk cache access. This event does not count if the MMU is disabled\000 */
{ 153740 }, /* tlb_l2tlb_llwalk_refill\000\000cache\000Level 2 TLB last-level walk cache refill. This event does not count if the MMU is disabled\000\000\000event=0xcb\000\000\000\000\000\000\000\000Level 2 TLB last-level walk cache refill. This event does not count if the MMU is disabled\000 */
{ 153973 }, /* tlb_l2tlb_s2_access\000\000cache\000Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count\000\000\000event=0xce\000\000\000\000\000\000\000\000Level 2 TLB IPA cache access. This event counts on each access to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 translation is disabled, this event does not count\000 */
{ 154516 }, /* tlb_l2tlb_s2_refill\000\000cache\000Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count\000\000\000event=0xcf\000\000\000\000\000\000\000\000Level 2 TLB IPA cache refill. This event counts on each refill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 translation is disabled, this event does not count\000 */
{ 44582 }, /* dpu_br_cond_mis\000\000dpu\000Instruction retired, conditional branch, mispredicted\000\000\000event=0xea\000\000\000\000\000\000\000\000Instruction retired, conditional branch, mispredicted\000 */
{ 44864 }, /* dpu_br_ind_mis\000\000dpu\000Instruction retired, indirect branch, mispredicted\000\000\000event=0xe9\000\000\000\000\000\000\000\000Instruction retired, indirect branch, mispredicted\000 */
{ 45006 }, /* dpu_mem_err_dcu\000\000dpu\000Memory error (any type) from DCU\000\000\000event=0xec\000\000\000\000\000\000\000\000Memory error (any type) from DCU\000 */
{ 45113 }, /* dpu_mem_err_ifu\000\000dpu\000Memory error (any type) from IFU\000\000\000event=0xeb\000\000\000\000\000\000\000\000Memory error (any type) from IFU\000 */
{ 45220 }, /* dpu_mem_err_tlb\000\000dpu\000Memory error (any type) from TLB\000\000\000event=0xed\000\000\000\000\000\000\000\000Memory error (any type) from TLB\000 */
{ 48500 }, /* exc_fiq\000\000exception\000Exception taken, FIQ\000\000\000event=0x87\000\000\000\000\000\000\000\000Exception taken, FIQ\000 */
{ 48955 }, /* exc_irq\000\000exception\000Exception taken, IRQ\000\000\000event=0x86\000\000\000\000\000\000\000\000Exception taken, IRQ\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 120089 }, /* memory_error\000\000exception\000Local memory error\000\000\000event=0x1a\000\000\000\000\000\000\000\000Local memory error\000 */
{ 60084 }, /* ifu_all_thrds_rdy\000\000ifu\000This thread and the other thread both ready for scheduling in if0\000\000\000event=0xdc\000\000\000\000\000\000\000\000This thread and the other thread both ready for scheduling in if0\000 */
{ 60259 }, /* ifu_flushed_excl_tlb_miss\000\000ifu\000Thread flushed due to reasons other than TLB miss\000\000\000event=0xdb\000\000\000\000\000\000\000\000Thread flushed due to reasons other than TLB miss\000 */
{ 60410 }, /* ifu_flushed_tlb_miss\000\000ifu\000Thread flushed due to TLB miss\000\000\000event=0xda\000\000\000\000\000\000\000\000Thread flushed due to TLB miss\000 */
{ 60518 }, /* ifu_goto_idle\000\000ifu\000The thread moved from an active state to an inactive state (long-term sleep state, causing deallocation of some resources)\000\000\000event=0xe0\000\000\000\000\000\000\000\000The thread moved from an active state to an inactive state (long-term sleep state, causing deallocation of some resources)\000 */
{ 60803 }, /* ifu_ic_lf_sp\000\000ifu\000I-Cache Speculative line fill\000\000\000event=0xe4\000\000\000\000\000\000\000\000I-Cache Speculative line fill\000 */
{ 60901 }, /* ifu_ic_lookup_under_miss\000\000ifu\000I-Cache lookup under miss from other thread\000\000\000event=0xe1\000\000\000\000\000\000\000\000I-Cache lookup under miss from other thread\000 */
{ 61039 }, /* ifu_ic_miss_under_miss\000\000ifu\000I-Cache miss under miss from other thread\000\000\000event=0xe2\000\000\000\000\000\000\000\000I-Cache miss under miss from other thread\000 */
{ 61171 }, /* ifu_ic_miss_wait\000\000ifu\000I-Cache miss on an access from the prefetch block\000\000\000event=0xd0\000\000\000\000\000\000\000\000I-Cache miss on an access from the prefetch block\000 */
{ 61313 }, /* ifu_instr_pushed\000\000ifu\000This thread pushed an instruction into the IQ\000\000\000event=0xe3\000\000\000\000\000\000\000\000This thread pushed an instruction into the IQ\000 */
{ 61447 }, /* ifu_iutlb_miss_wait\000\000ifu\000Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l ITLB miss\000\000\000event=0xd1\000\000\000\000\000\000\000\000Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l ITLB miss\000 */
{ 61666 }, /* ifu_micro_caddr_mispred\000\000ifu\000Micro-predictor address mispredict, with respect to if3/if4 predictor\000\000\000event=0xd3\000\000\000\000\000\000\000\000Micro-predictor address mispredict, with respect to if3/if4 predictor\000 */
{ 61855 }, /* ifu_micro_cond_mispred\000\000ifu\000Micro-predictor conditional/direction mispredict, with respect to. if3/if4 predictor\000\000\000event=0xd2\000\000\000\000\000\000\000\000Micro-predictor conditional/direction mispredict, with respect to. if3/if4 predictor\000 */
{ 62073 }, /* ifu_micro_correction\000\000ifu\000Micro-predictor correction\000\000\000event=0xd7\000\000\000\000\000\000\000\000Micro-predictor correction\000 */
{ 62173 }, /* ifu_micro_hit\000\000ifu\000Micro-predictor hit with immediate redirect\000\000\000event=0xd4\000\000\000\000\000\000\000\000Micro-predictor hit with immediate redirect\000 */
{ 62300 }, /* ifu_micro_neg_hit\000\000ifu\000Micro-predictor negative cache hit\000\000\000event=0xd6\000\000\000\000\000\000\000\000Micro-predictor negative cache hit\000 */
{ 62413 }, /* ifu_micro_no_instr1\000\000ifu\000A 2nd instruction could have been pushed but was not because it was nonsequential\000\000\000event=0xd8\000\000\000\000\000\000\000\000A 2nd instruction could have been pushed but was not because it was nonsequential\000 */
{ 62622 }, /* ifu_micro_no_pred\000\000ifu\000Micro-predictor miss\000\000\000event=0xd9\000\000\000\000\000\000\000\000Micro-predictor miss\000 */
{ 62707 }, /* ifu_not_rdy_for_arb\000\000ifu\000This thread was not arbitrated because it was not ready for scheduling. For example, due to a cache miss or TLB miss\000\000\000event=0xdf\000\000\000\000\000\000\000\000This thread was not arbitrated because it was not ready for scheduling. For example, due to a cache miss or TLB miss\000 */
{ 62986 }, /* ifu_win_arb_other_act\000\000ifu\000This thread was arbitrated when the other thread was also active, but not necessarily ready. For example, waiting for I-Cache or TLB\000\000\000event=0xde\000\000\000\000\000\000\000\000This thread was arbitrated when the other thread was also active, but not necessarily ready. For example, waiting for I-Cache or TLB\000 */
{ 63299 }, /* ifu_win_arb_other_rdy\000\000ifu\000This thread was arbitrated when the other thread was also ready for scheduling\000\000\000event=0xdd\000\000\000\000\000\000\000\000This thread was arbitrated when the other thread was also ready for scheduling\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 25639 }, /* br_immed_retired\000\000instruction\000Instruction architecturally executed, immediate branch\000\000\000event=0xd\000\000\000\000\000\000\000\000Instruction architecturally executed, immediate branch\000 */
{ 30824 }, /* br_mis_pred_retired\000\000instruction\000Instruction architecturally executed, mispredicted branch\000\000\000event=0x22\000\000\000\000\000\000\000\000Instruction architecturally executed, mispredicted branch\000 */
{ 31554 }, /* br_retired\000\000instruction\000Instruction architecturally executed, branch\000\000\000event=0x21\000\000\000\000\000\000\000\000Instruction architecturally executed, branch\000 */
{ 34454 }, /* br_return_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, procedure return\000\000\000event=0xe\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, procedure return\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 44731 }, /* dpu_br_cond_retired\000\000instruction\000Instruction retired, conditional branch\000\000\000event=0xe8\000\000\000\000\000\000\000\000Instruction retired, conditional branch\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 115851 }, /* ld_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, load\000\000\000event=0x6\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, load\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116604 }, /* ldst_spec\000\000instruction\000Operation speculatively executed, load or store\000\000\000event=0x72\000\000\000\000\000\000\000\000Operation speculatively executed, load or store\000 */
{ 124412 }, /* pc_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, software change of the PC\000\000\000event=0xc\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, software change of the PC\000 */
{ 133483 }, /* st_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, store\000\000\000event=0x7\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, store\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 22285 }, /* biu_ext_mem_req\000\000memory\000External memory request\000\000\000event=0xc1\000\000\000\000\000\000\000\000External memory request\000 */
{ 22377 }, /* biu_ext_mem_req_nc\000\000memory\000External memory request to non-cacheable memory\000\000\000event=0xc2\000\000\000\000\000\000\000\000External memory request to non-cacheable memory\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 129020 }, /* remote_access_rd\000\000memory\000Attributable memory read access to another socket in a multi-socket system\000\000\000event=0x38\000\000\000\000\000\000\000\000Attributable memory read access to another socket in a multi-socket system\000 */
{ 156587 }, /* unaligned_ld_spec\000\000memory\000Unaligned access, read\000\000\000event=0x68\000\000\000\000\000\000\000\000Unaligned access, read\000 */
{ 156967 }, /* unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 157149 }, /* unaligned_st_spec\000\000memory\000Unaligned access, write\000\000\000event=0x69\000\000\000\000\000\000\000\000Unaligned access, write\000 */
{ 134035 }, /* stall_backend\000\000pipeline\000No operation issued due to the backend\000\000\000event=0x24\000\000\000\000\000\000\000\000No operation issued due to the backend\000 */
{ 143105 }, /* stall_frontend\000\000pipeline\000No operation issued because of the frontend\000\000\000event=0x23\000\000\000\000\000\000\000\000No operation issued because of the frontend\000 */
};

static const struct compact_pmu_event pme_arm_cortex_a73[] = {
{ 29972 }, /* br_indirect_spec\000\000branch\000Branch speculatively executed, indirect branch\000\000\000event=0x7a\000\000\000\000\000\000\000\000Branch speculatively executed, indirect branch\000 */
{ 30375 }, /* br_mis_pred\000\000branch\000Mispredicted or not predicted branch speculatively executed\000\000\000event=0x10\000\000\000\000\000\000\000\000Mispredicted or not predicted branch speculatively executed\000 */
{ 31216 }, /* br_pred\000\000branch\000Predictable branch speculatively executed\000\000\000event=0x12\000\000\000\000\000\000\000\000Predictable branch speculatively executed\000 */
{ 35045 }, /* bus_access\000\000bus\000Attributable Bus access\000\000\000event=0x19\000\000\000\000\000\000\000\000Attributable Bus access\000 */
{ 35467 }, /* bus_access_normal\000\000bus\000Bus access, Normal\000\000\000event=0x64\000\000\000\000\000\000\000\000Bus access, Normal\000 */
{ 35548 }, /* bus_access_not_shared\000\000bus\000Bus access, not Normal, Cacheable, Shareable\000\000\000event=0x63\000\000\000\000\000\000\000\000Bus access, not Normal, Cacheable, Shareable\000 */
{ 35685 }, /* bus_access_periph\000\000bus\000Bus access, peripheral\000\000\000event=0x65\000\000\000\000\000\000\000\000Bus access, peripheral\000 */
{ 35925 }, /* bus_access_shared\000\000bus\000Bus access, Normal, Cacheable, Shareable\000\000\000event=0x62\000\000\000\000\000\000\000\000Bus access, Normal, Cacheable, Shareable\000 */
{ 36205 }, /* bus_cycles\000\000bus\000Bus cycle\000\000\000event=0x1d\000\000\000\000\000\000\000\000Bus cycle\000 */
{ 40772 }, /* cpu_cycles\000\000bus\000Cycle\000\000\000event=0x11\000\000\000\000\000\000\000\000Cycle\000 */
{ 39353 }, /* cp15_utlb_refill\000\000cache\000Level 1 CP15 TLB refill\000\000\000event=0xe8\000\000\000\000\000\000\000\000Level 1 CP15 TLB refill\000 */
{ 42057 }, /* dcache_self_hit_vipt\000\000cache\000Data cache hit in itself due to VIPT aliasing\000\000\000event=0xec\000\000\000\000\000\000\000\000Data cache hit in itself due to VIPT aliasing\000 */
{ 59203 }, /* i_btac_ram_rd\000\000cache\000Number of ways read in the instruction BTAC RAM\000\000\000event=0xc4\000\000\000\000\000\000\000\000Number of ways read in the instruction BTAC RAM\000 */
{ 59340 }, /* i_data_ram_rd\000\000cache\000Number of ways read in the instruction cache - Data RAM\000\000\000event=0xc3\000\000\000\000\000\000\000\000Number of ways read in the instruction cache - Data RAM\000 */
{ 59493 }, /* i_tag_ram_rd\000\000cache\000Number of ways read in the instruction cache - Tag RAM\000\000\000event=0xc2\000\000\000\000\000\000\000\000Number of ways read in the instruction cache - Tag RAM\000 */
{ 71394 }, /* l1d_cache\000\000cache\000Level 1 data cache access\000\000\000event=0x4\000\000\000\000\000\000\000\000Level 1 data cache access\000 */
{ 72754 }, /* l1d_cache_rd\000\000cache\000L1D cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, read\000 */
{ 72977 }, /* l1d_cache_refill\000\000cache\000Level 1 data cache refill\000\000\000event=0x3\000\000\000\000\000\000\000\000Level 1 data cache refill\000 */
{ 75489 }, /* l1d_cache_wb\000\000cache\000Attributable Level 1 data cache write-back\000\000\000event=0x15\000\000\000\000\000\000\000\000Attributable Level 1 data cache write-back\000 */
{ 76423 }, /* l1d_cache_wr\000\000cache\000L1D cache access, write\000\000\000event=0x41\000\000\000\000\000\000\000\000Attributable Level 1 data cache access, write\000 */
{ 77736 }, /* l1d_tlb_refill\000\000cache\000Attributable Level 1 data TLB refill\000\000\000event=0x5\000\000\000\000\000\000\000\000Attributable Level 1 data TLB refill\000 */
{ 80951 }, /* l1i_cache\000\000cache\000Attributable Level 1 instruction cache access\000\000\000event=0x14\000\000\000\000\000\000\000\000Attributable Level 1 instruction cache access\000 */
{ 82540 }, /* l1i_cache_refill\000\000cache\000Level 1 instruction cache refill\000\000\000event=0x1\000\000\000\000\000\000\000\000Level 1 instruction cache refill\000 */
{ 83757 }, /* l1i_tlb_refill\000\000cache\000Attributable Level 1 instruction TLB refill\000\000\000event=0x2\000\000\000\000\000\000\000\000Attributable Level 1 instruction TLB refill\000 */
{ 88426 }, /* l2d_cache\000\000cache\000Level 2 data cache access\000\000\000event=0x16\000\000\000\000\000\000\000\000Level 2 data cache access\000 */
{ 89220 }, /* l2d_cache_inval\000\000cache\000L2D cache invalidate\000\000\000event=0x58\000\000\000\000\000\000\000\000Attributable Level 2 data cache invalidate\000 */
{ 90391 }, /* l2d_cache_rd\000\000cache\000L2D cache access, read\000\000\000event=0x50\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, read\000 */
{ 90863 }, /* l2d_cache_refill\000\000cache\000Level 2 data refill\000\000\000event=0x17\000\000\000\000\000\000\000\000Level 2 data refill\000 */
{ 96586 }, /* l2d_cache_wb\000\000cache\000Attributable Level 2 data cache write-back\000\000\000event=0x18\000\000\000\000\000\000\000\000Attributable Level 2 data cache write-back\000 */
{ 97102 }, /* l2d_cache_wb_clean\000\000cache\000L2D cache Write-Back, cleaning and coherency\000\000\000event=0x57\000\000\000\000\000\000\000\000Level 2 data cache Write-Back, cleaning and coherency\000 */
{ 97399 }, /* l2d_cache_wb_victim\000\000cache\000L2D cache Write-Back, victim\000\000\000event=0x56\000\000\000\000\000\000\000\000Attributable Level 2 data cache Write-Back, victim\000 */
{ 97660 }, /* l2d_cache_wr\000\000cache\000L2D cache access, write\000\000\000event=0x51\000\000\000\000\000\000\000\000Attributable Level 2 data cache access, write\000 */
{ 124810 }, /* pld_utlb_refill\000\000cache\000Level 1 PLD TLB refill\000\000\000event=0xe7\000\000\000\000\000\000\000\000Level 1 PLD TLB refill\000 */
{ 152546 }, /* tlb_access\000\000cache\000Level 2 TLB access\000\000\000event=0xea\000\000\000\000\000\000\000\000Level 2 TLB access\000 */
{ 155103 }, /* tlb_miss\000\000cache\000Level 2 TLB miss\000\000\000event=0xeb\000\000\000\000\000\000\000\000Level 2 TLB miss\000 */
{ 158566 }, /* utlb_flush\000\000cache\000Level 1 TLB flush\000\000\000event=0xe9\000\000\000\000\000\000\000\000Level 1 TLB flush\000 */
{ 47150 }, /* etm_ext_out0\000\000etm\000ETM trace unit output 0\000\000\000event=0xde\000\000\000\000\000\000\000\000ETM trace unit output 0\000 */
{ 47236 }, /* etm_ext_out1\000\000etm\000ETM trace unit output 1\000\000\000event=0xdf\000\000\000\000\000\000\000\000ETM trace unit output 1\000 */
{ 48766 }, /* exc_hvc\000\000exception\000Exception taken, Hypervisor Call\000\000\000event=0x8a\000\000\000\000\000\000\000\000Exception taken, Hypervisor Call\000 */
{ 50174 }, /* exc_taken\000\000exception\000Exception taken\000\000\000event=0x9\000\000\000\000\000\000\000\000Exception taken\000 */
{ 50814 }, /* exc_trap_hyp\000\000exception\000Number of Traps to hypervisor\000\000\000event=0xdc\000\000\000\000\000\000\000\000Number of Traps to hypervisor\000 */
{ 19559 }, /* ase_spec\000\000instruction\000Operation speculatively executed, Advanced SIMD instruction\000\000\000event=0x74\000\000\000\000\000\000\000\000Operation speculatively executed, Advanced SIMD instruction\000 */
{ 25639 }, /* br_immed_retired\000\000instruction\000Instruction architecturally executed, immediate branch\000\000\000event=0xd\000\000\000\000\000\000\000\000Instruction architecturally executed, immediate branch\000 */
{ 34454 }, /* br_return_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, procedure return\000\000\000event=0xe\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, procedure return\000 */
{ 38524 }, /* cid_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000\000\000event=0xb\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, write to CONTEXTIDR\000 */
{ 41046 }, /* crypto_spec\000\000instruction\000Operation speculatively executed, Cryptographic instruction\000\000\000event=0x77\000\000\000\000\000\000\000\000Operation speculatively executed, Cryptographic instruction\000 */
{ 43623 }, /* dmb_spec\000\000instruction\000Barrier speculatively executed, DMB\000\000\000event=0x7e\000\000\000\000\000\000\000\000Barrier speculatively executed, DMB\000 */
{ 44425 }, /* dp_spec\000\000instruction\000Operation speculatively executed, integer data processing\000\000\000event=0x73\000\000\000\000\000\000\000\000Operation speculatively executed, integer data processing\000 */
{ 45327 }, /* dsb_spec\000\000instruction\000Barrier speculatively executed, DSB\000\000\000event=0x7d\000\000\000\000\000\000\000\000Barrier speculatively executed, DSB\000 */
{ 49535 }, /* exc_return\000\000instruction\000Instruction architecturally executed, condition check pass, exception return\000\000\000event=0xa\000\000\000\000\000\000\000\000Instruction architecturally executed, condition check pass, exception return\000 */
{ 65436 }, /* inst_retired\000\000instruction\000Instruction architecturally executed\000\000\000event=0x8\000\000\000\000\000\000\000\000Instruction architecturally executed\000 */
{ 65729 }, /* inst_spec\000\000instruction\000Operation speculatively executed\000\000\000event=0x1b\000\000\000\000\000\000\000\000Operation speculatively executed\000 */
{ 66148 }, /* isb_spec\000\000instruction\000Barrier speculatively executed, ISB\000\000\000event=0x7c\000\000\000\000\000\000\000\000Barrier speculatively executed, ISB\000 */
{ 116034 }, /* ld_spec\000\000instruction\000Operation speculatively executed, load\000\000\000event=0x70\000\000\000\000\000\000\000\000Operation speculatively executed, load\000 */
{ 116153 }, /* ldrex_spec\000\000instruction\000Exclusive operation speculatively executed, LDREX or LDX\000\000\000event=0x6c\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, LDREX or LDX\000 */
{ 116604 }, /* ldst_spec\000\000instruction\000Operation speculatively executed, load or store\000\000\000event=0x72\000\000\000\000\000\000\000\000Operation speculatively executed, load or store\000 */
{ 124412 }, /* pc_write_retired\000\000instruction\000Instruction architecturally executed, condition code check pass, software change of the PC\000\000\000event=0xc\000\000\000\000\000\000\000\000Instruction architecturally executed, condition code check pass, software change of the PC\000 */
{ 133668 }, /* st_spec\000\000instruction\000Operation speculatively executed, store\000\000\000event=0x71\000\000\000\000\000\000\000\000Operation speculatively executed, store\000 */
{ 147124 }, /* strex_fail_spec\000\000instruction\000Exclusive operation speculatively executed, STREX or STX fail\000\000\000event=0x6e\000\000\000\000\000\000\000\000Exclusive operation speculatively executed, STREX or STX fail\000 */
{ 151910 }, /* sw_incr\000\000instruction\000Instruction architecturally executed, Condition code check pass, software increment\000\000\000event=0\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, software increment\000 */
{ 155805 }, /* ttbr_write_retired\000\000instruction\000Instruction architecturally executed, Condition code check pass, write to TTBR\000\000\000event=0x1c\000\000\000\000\000\000\000\000Instruction architecturally executed, Condition code check pass, write to TTBR\000 */
{ 158640 }, /* vfp_spec\000\000instruction\000Operation speculatively executed, floating-point instruction\000\000\000event=0x75\000\000\000\000\000\000\000\000Operation speculatively executed, floating-point instruction\000 */
{ 118259 }, /* mem_access\000\000memory\000Data memory access\000\000\000event=0x13\000\000\000\000\000\000\000\000Data memory access\000 */
{ 118963 }, /* mem_access_rd\000\000memory\000Data memory access, read\000\000\000event=0x66\000\000\000\000\000\000\000\000Data memory access, read\000 */
{ 119155 }, /* mem_access_wr\000\000memory\000Data memory access, write\000\000\000event=0x67\000\000\000\000\000\000\000\000Data memory access, write\000 */
{ 156967 }, /* unaligned_ldst_spec\000\000memory\000Unaligned access\000\000\000event=0x6a\000\000\000\000\000\000\000\000Unaligned access\000 */
{ 120508 }, /* mmu_ptw\000\000mmu\000Duration of a translation table walk handled by the MMU\000\000\000event=0xe0\000\000\000\000\000\000\000\000Duration of a translation table walk handled by the MMU\000 */
{ 120653 }, /* mmu_ptw_cp15\000\000mmu\000Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA to PA operations)\000\000\000event=0xe6\000\000\000\000\000\000\000\000Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA to PA operations)\000 */
{ 121119 }, /* mmu_ptw_iside\000\000mmu\000Duration of a translation table walk requested by the Instruction Side\000\000\000event=0xe4\000\000\000\000\000\000\000\000Duration of a translation table walk requested by the Instruction Side\000 */
{ 121481 }, /* mmu_ptw_lsu\000\000mmu\000Duration of a translation table walk requested by the LSU\000\000\000event=0xe3\000\000\000\000\000\000\000\000Duration of a translation table walk requested by the LSU\000 */
{ 121634 }, /* mmu_ptw_pld\000\000mmu\000Duration of a translation table walk requested by a Preload instruction or Prefetch request\000\000\000event=0xe5\000\000\000\000\000\000\000\000Duration of a translation table walk requested by a Preload instruction or Prefetch request\000 */
{ 122172 }, /* mmu_ptw_st1\000\000mmu\000Duration of a Stage 1 translation table walk handled by the MMU\000\000\000event=0xe1\000\000\000\000\000\000\000\000Duration of a Stage 1 translation table walk handled by the MMU\000 */
{ 122654 }, /* mmu_ptw_st2\000\000mmu\000Duration of a Stage 2 translation table walk handled by the MMU\000\000\000event=0xe2\000\000\000\000\000\000\000\000Duration of a Stage 2 translation table walk handled by the MMU\000 */
{ 41889 }, /* d_lsu_slot_full\000\000pipeline\000Duration for which all slots in the Load-Store Unit are busy\000\000\000event=0xd3\000\000\000\000\000\000\000\000Duration for which all slots in the Load-Store Unit are busy\000 */
{ 42441 }, /* de_iq_full\000\000pipeline\000Duration for which all slots in the Data Engine issue queue are busy\000\000\000event=0xda\000\000\000\000\000\000\000\000Duration for which all slots in the Data Engine issue queue are busy\000 */
{ 44238 }, /* dp_iq_full\000\000pipeline\000Duration for which all slots in the data processing issue queue are busy\000\000\000event=0xd9\000\000\000\000\000\000\000\000Duration for which all slots in the data processing issue queue are busy\000 */
{ 116743 }, /* lf_stall\000\000pipeline\000A linefill caused an instruction side stall\000\000\000event=0xc0\000\000\000\000\000\000\000\000A linefill caused an instruction side stall\000 */
{ 117934 }, /* ls_iq_full\000\000pipeline\000Duration for which all slots in the load-store issue queue are busy\000\000\000event=0xd8\000\000\000\000\000\000\000\000Duration for which all slots in the load-store issue queue are busy\000 */
{ 127101 }, /* ptw_stall\000\000pipeline\000A translation table walk caused an instruction side stall\000\000\000event=0xc1\000\000\000\000\000\000\000\000A translation table walk caused an instruction side stall\000 */
};

static const struct compact_pmu_event pme_test_soc_cpu[] = {
{ 5151 }, /* \000\000metrics\000\000CPI\000\000\000\000\000\000\000\000\0001 / IPC\000\000 */
{ 5183 }, /* \000\000metrics\000\000DCache_L2_All\000\000\000\000\000\000\000\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000 */
{ 5257 }, /* \000\000metrics\000\000DCache_L2_All_Hits\000\000\000\000\000\000\000\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000 */
{ 5361 }, /* \000\000metrics\000\000DCache_L2_All_Miss\000\000\000\000\000\000\000\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000 */
{ 5505 }, /* \000\000metrics\000\000DCache_L2_Hits\000\000\000\000\000\000\000\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000 */
{ 5583 }, /* \000\000metrics\000\000DCache_L2_Misses\000\000\000\000\000\000\000\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000 */
{ 5663 }, /* \000\000metrics\000\000Frontend_Bound_SMT\000\000\000\000\000\000\000\000\000idq_uops_not_delivered.core / (4 * (( ( cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk ) )))\000\000 */
{ 5849 }, /* \000\000metrics\000\000IPC\000group1\000\000\000\000\000\000\000\000inst_retired.any / cpu_clk_unhalted.thread\000\000 */
{ 5922 }, /* \000\000metrics\000\000L1D_Cache_Fill_BW\000\000\000\000\000\000\000\000\00064 * l1d.replacement / 1000000000 / duration_time\000\000 */
{ 6010 }, /* \000\000metrics\000\000M1\000\000\000\000\000\000\000\000\000ipc + M2\000\000 */
{ 6042 }, /* \000\000metrics\000\000M2\000\000\000\000\000\000\000\000\000ipc + M1\000\000 */
{ 6074 }, /* \000\000metrics\000\000M3\000\000\000\000\000\000\000\000\0001/M3\000\000 */
{ 6102 }, /* \000\000metrics\000\000cache_miss_cycles\000group1\000\000\000\000\000\000\000\000(dcache_miss_cpi + icache_miss_cycles)\000\000 */
{ 6185 }, /* \000\000metrics\000\000dcache_miss_cpi\000\000\000\000\000\000\000\000\000l1d\\-loads\\-misses / inst_retired.any\000\000 */
{ 6259 }, /* \000\000metrics\000\000icache_miss_cycles\000\000\000\000\000\000\000\000\000l1i\\-loads\\-misses / inst_retired.any\000\000 */
{ 22520 }, /* bp_l1_btb_correct\000\000branch\000L1 BTB Correction\000\000\000event=0x8a\000\000\000\000\000\000\000\000\000 */
{ 22585 }, /* bp_l2_btb_correct\000\000branch\000L2 BTB Correction\000\000\000event=0x8b\000\000\000\000\000\000\000\000\000 */
{ 107419 }, /* l3_cache_rd\000\000cache\000L3 cache access, read\000\000\000event=0x40\000\000\000\000\000\000\000\000Attributable Level 3 cache access, read\000 */
{ 43396 }, /* dispatch_blocked.any\000\000other\000Memory cluster signals to block micro-op dispatch for any reason\000\000\000event=0x9,period=200000,umask=0x20\000\000\000\000\000\000\000\000\000 */
{ 47019 }, /* eist_trans\000\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000\000\000event=0x3a,period=200000,umask=0x0\000\000\000\000\000\000\000\000\000 */
{ 132256 }, /* segment_reg_loads.any\000\000other\000Number of segment register loads\000\000\000event=0x6,period=200000,umask=0x80\000\000\000\000\000\000\000\000\000 */
{ 47675 }, /* event-hyphen\000uncore_cbox\000uncore\000UNC_CBO_HYPHEN. Unit: uncore_cbox \000\000\000event=0xe0,umask=0x00\000\000\000\000\000\000\000\000UNC_CBO_HYPHEN\000 */
{ 47788 }, /* event-two-hyph\000uncore_cbox\000uncore\000UNC_CBO_TWO_HYPH. Unit: uncore_cbox \000\000\000event=0xc0,umask=0x00\000\000\000\000\000\000\000\000UNC_CBO_TWO_HYPH\000 */
{ 157243 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore_cbox\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core. Unit: uncore_cbox \000\000\000event=0x22,umask=0x81\000\000\000\000\000\000\000\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000 */
{ 157511 }, /* uncore_hisi_ddrc.flux_wcmd\000hisi_sccl,ddrc\000uncore\000DDRC write commands. Unit: hisi_sccl,ddrc \000\000\000event=0x2\000\000\000\000\000\000\000\000DDRC write commands\000 */
{ 157642 }, /* uncore_hisi_l3c.rd_hit_cpipe\000hisi_sccl,l3c\000uncore\000Total read hits. Unit: hisi_sccl,l3c \000\000\000event=0x7\000\000\000\000\000\000\000\000Total read hits\000 */
{ 157765 }, /* uncore_imc.cache_hits\000uncore_imc\000uncore\000Total cache hits. Unit: uncore_imc \000\000\000event=0x34\000\000\000\000\000\000\000\000Total cache hits\000 */
{ 157878 }, /* uncore_imc_free_running.cache_miss\000uncore_imc_free_running\000uncore\000Total cache misses. Unit: uncore_imc_free_running \000\000\000event=0x12\000\000\000\000\000\000\000\000Total cache misses\000 */
};

static const struct compact_pmu_event pme_test_soc_sys[] = {
{ 152297 }, /* sys_ccn_pmu.read_cycles\000uncore_sys_ccn_pmu\000uncore\000ccn read-cycles event. Unit: uncore_sys_ccn_pmu \000\000\000config=0x2c\000\0000x01\000\000\000\000\000\000\000 */
{ 152422 }, /* sys_ddr_pmu.write_cycles\000uncore_sys_ddr_pmu\000uncore\000ddr write-cycles event. Unit: uncore_sys_ddr_pmu \000\000\000event=0x2b\000\000v8\000\000\000\000\000\000\000 */
};


/* Struct used to make the PMU event table implementation opaque to callers. */
struct pmu_events_table {
        const struct compact_pmu_event *entries;
        size_t length;
};

/*
 * Map a CPU to its table of PMU events. The CPU is identified by the
 * cpuid field, which is an arch-specific identifier for the CPU.
 * The identifier specified in tools/perf/pmu-events/arch/xxx/mapfile
 * must match the get_cpuid_str() in tools/perf/arch/xxx/util/header.c)
 *
 * The  cpuid can contain any character other than the comma.
 */
struct pmu_events_map {
        const char *arch;
        const char *cpuid;
        struct pmu_events_table table;
};

/*
 * Global table mapping each known CPU for the architecture to its
 * table of PMU events.
 */
const struct pmu_events_map pmu_events_map[] = {
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd020",
	.table = {
		.entries = pme_arm_cortex_a34,
		.length = ARRAY_SIZE(pme_arm_cortex_a34)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd030",
	.table = {
		.entries = pme_arm_cortex_a53,
		.length = ARRAY_SIZE(pme_arm_cortex_a53)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000420f1000",
	.table = {
		.entries = pme_arm_cortex_a53,
		.length = ARRAY_SIZE(pme_arm_cortex_a53)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd040",
	.table = {
		.entries = pme_arm_cortex_a35,
		.length = ARRAY_SIZE(pme_arm_cortex_a35)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd050",
	.table = {
		.entries = pme_arm_cortex_a55,
		.length = ARRAY_SIZE(pme_arm_cortex_a55)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd060",
	.table = {
		.entries = pme_arm_cortex_a65_e1,
		.length = ARRAY_SIZE(pme_arm_cortex_a65_e1)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd4a0",
	.table = {
		.entries = pme_arm_cortex_a65_e1,
		.length = ARRAY_SIZE(pme_arm_cortex_a65_e1)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd070",
	.table = {
		.entries = pme_arm_cortex_a57_a72,
		.length = ARRAY_SIZE(pme_arm_cortex_a57_a72)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd080",
	.table = {
		.entries = pme_arm_cortex_a57_a72,
		.length = ARRAY_SIZE(pme_arm_cortex_a57_a72)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd090",
	.table = {
		.entries = pme_arm_cortex_a73,
		.length = ARRAY_SIZE(pme_arm_cortex_a73)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd0a0",
	.table = {
		.entries = pme_arm_cortex_a75,
		.length = ARRAY_SIZE(pme_arm_cortex_a75)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd0b0",
	.table = {
		.entries = pme_arm_cortex_a76_n1,
		.length = ARRAY_SIZE(pme_arm_cortex_a76_n1)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd0c0",
	.table = {
		.entries = pme_arm_cortex_a76_n1,
		.length = ARRAY_SIZE(pme_arm_cortex_a76_n1)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd0d0",
	.table = {
		.entries = pme_arm_cortex_a77,
		.length = ARRAY_SIZE(pme_arm_cortex_a77)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd400",
	.table = {
		.entries = pme_arm_neoverse_v1,
		.length = ARRAY_SIZE(pme_arm_neoverse_v1)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd410",
	.table = {
		.entries = pme_arm_cortex_a78,
		.length = ARRAY_SIZE(pme_arm_cortex_a78)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd4b0",
	.table = {
		.entries = pme_arm_cortex_a78,
		.length = ARRAY_SIZE(pme_arm_cortex_a78)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd440",
	.table = {
		.entries = pme_arm_cortex_x1,
		.length = ARRAY_SIZE(pme_arm_cortex_x1)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd4c0",
	.table = {
		.entries = pme_arm_cortex_x1,
		.length = ARRAY_SIZE(pme_arm_cortex_x1)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd460",
	.table = {
		.entries = pme_arm_cortex_a510,
		.length = ARRAY_SIZE(pme_arm_cortex_a510)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd470",
	.table = {
		.entries = pme_arm_cortex_a710,
		.length = ARRAY_SIZE(pme_arm_cortex_a710)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd480",
	.table = {
		.entries = pme_arm_cortex_x2,
		.length = ARRAY_SIZE(pme_arm_cortex_x2)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000410fd490",
	.table = {
		.entries = pme_arm_neoverse_n2,
		.length = ARRAY_SIZE(pme_arm_neoverse_n2)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000420f5160",
	.table = {
		.entries = pme_cavium_thunderx2,
		.length = ARRAY_SIZE(pme_cavium_thunderx2)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000430f0af0",
	.table = {
		.entries = pme_cavium_thunderx2,
		.length = ARRAY_SIZE(pme_cavium_thunderx2)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000460f0010",
	.table = {
		.entries = pme_fujitsu_a64fx,
		.length = ARRAY_SIZE(pme_fujitsu_a64fx)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000480fd010",
	.table = {
		.entries = pme_hisilicon_hip08,
		.length = ARRAY_SIZE(pme_hisilicon_hip08)
	}
},
{
	.arch = "arm64",
	.cpuid = "0x00000000500f0000",
	.table = {
		.entries = pme_ampere_emag,
		.length = ARRAY_SIZE(pme_ampere_emag)
	}
},
{
	.arch = "testarch",
	.cpuid = "testcpu",
	.table = {
	.entries = pme_test_soc_cpu,
	.length = ARRAY_SIZE(pme_test_soc_cpu),
	}
},
{
	.arch = 0,
	.cpuid = 0,
	.table = { 0, 0 },
}
};

struct pmu_sys_events {
	const char *name;
	struct pmu_events_table table;
};

static const struct pmu_sys_events pmu_sys_event_tables[] = {
	{
		.table = {
			.entries = pme_hisilicon_hip09_sys,
			.length = ARRAY_SIZE(pme_hisilicon_hip09_sys)
		},
		.name = "pme_hisilicon_hip09_sys",
	},
	{
		.table = {
			.entries = pme_freescale_imx8mq_sys,
			.length = ARRAY_SIZE(pme_freescale_imx8mq_sys)
		},
		.name = "pme_freescale_imx8mq_sys",
	},
	{
		.table = {
			.entries = pme_freescale_imx8mp_sys,
			.length = ARRAY_SIZE(pme_freescale_imx8mp_sys)
		},
		.name = "pme_freescale_imx8mp_sys",
	},
	{
		.table = {
			.entries = pme_freescale_imx8mn_sys,
			.length = ARRAY_SIZE(pme_freescale_imx8mn_sys)
		},
		.name = "pme_freescale_imx8mn_sys",
	},
	{
		.table = {
			.entries = pme_freescale_imx8mm_sys,
			.length = ARRAY_SIZE(pme_freescale_imx8mm_sys)
		},
		.name = "pme_freescale_imx8mm_sys",
	},
	{
		.table = {
			.entries = pme_test_soc_sys,
			.length = ARRAY_SIZE(pme_test_soc_sys)
		},
		.name = "pme_test_soc_sys",
	},
	{
		.table = { 0, 0 }
	},
};

static void decompress(int offset, struct pmu_event *pe)
{
	const char *p = &big_c_string[offset];

	pe->name = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->pmu = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->topic = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->desc = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->metric_name = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->metric_group = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->event = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->aggr_mode = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->compat = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->deprecated = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->perpkg = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->unit = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->metric_constraint = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->metric_expr = (*p == '\0' ? NULL : p);
	while (*p++);
	pe->long_desc = (*p == '\0' ? NULL : p);
}

int pmu_events_table_for_each_event(const struct pmu_events_table *table,
                                    pmu_event_iter_fn fn,
                                    void *data)
{
        for (size_t i = 0; i < table->length; i++) {
                struct pmu_event pe;
                int ret;

                decompress(table->entries[i].offset, &pe);
                ret = fn(&pe, table, data);
                if (ret)
                        return ret;
        }
        return 0;
}

const struct pmu_events_table *perf_pmu__find_table(struct perf_pmu *pmu)
{
        const struct pmu_events_table *table = NULL;
        char *cpuid = perf_pmu__getcpuid(pmu);
        int i;

        /* on some platforms which uses cpus map, cpuid can be NULL for
         * PMUs other than CORE PMUs.
         */
        if (!cpuid)
                return NULL;

        i = 0;
        for (;;) {
                const struct pmu_events_map *map = &pmu_events_map[i++];
                if (!map->arch)
                        break;

                if (!strcmp_cpuid_str(map->cpuid, cpuid)) {
                        table = &map->table;
                        break;
                }
        }
        free(cpuid);
        return table;
}

const struct pmu_events_table *find_core_events_table(const char *arch, const char *cpuid)
{
        for (const struct pmu_events_map *tables = &pmu_events_map[0];
             tables->arch;
             tables++) {
                if (!strcmp(tables->arch, arch) && !strcmp_cpuid_str(tables->cpuid, cpuid))
                        return &tables->table;
        }
        return NULL;
}

int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data)
{
        for (const struct pmu_events_map *tables = &pmu_events_map[0];
             tables->arch;
             tables++) {
                int ret = pmu_events_table_for_each_event(&tables->table, fn, data);

                if (ret)
                        return ret;
        }
        return 0;
}

const struct pmu_events_table *find_sys_events_table(const char *name)
{
        for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0];
             tables->name;
             tables++) {
                if (!strcmp(tables->name, name))
                        return &tables->table;
        }
        return NULL;
}

int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data)
{
        for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0];
             tables->name;
             tables++) {
                int ret = pmu_events_table_for_each_event(&tables->table, fn, data);

                if (ret)
                        return ret;
        }
        return 0;
}
