/* Generated automatically by the program `genemit'
from the machine description file `md'.  */

#define IN_TARGET_CODE 1
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "backend.h"
#include "predict.h"
#include "tree.h"
#include "rtl.h"
#include "alias.h"
#include "varasm.h"
#include "stor-layout.h"
#include "calls.h"
#include "memmodel.h"
#include "tm_p.h"
#include "flags.h"
#include "insn-config.h"
#include "expmed.h"
#include "dojump.h"
#include "explow.h"
#include "emit-rtl.h"
#include "stmt.h"
#include "expr.h"
#include "insn-codes.h"
#include "optabs.h"
#include "dfp.h"
#include "output.h"
#include "recog.h"
#include "df.h"
#include "resource.h"
#include "reload.h"
#include "diagnostic-core.h"
#include "regs.h"
#include "tm-constrs.h"
#include "ggc.h"
#include "target.h"

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:370 */
rtx
gen_indirect_jump (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (pc_rtx,
	operand0);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:377 */
rtx
gen_jump (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (pc_rtx,
	gen_rtx_LABEL_REF (VOIDmode,
	operand0));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:422 */
rtx
gen_ccmpsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand1,
	gen_rtx_IF_THEN_ELSE (CCmode,
	gen_rtx_fmt_ee (GET_CODE (operand4), VOIDmode,
		operand0,
		const0_rtx),
	gen_rtx_COMPARE (CCmode,
	operand2,
	operand3),
	gen_rtx_UNSPEC (CCmode,
	gen_rtvec (1,
		operand5),
	82)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:422 */
rtx
gen_ccmpdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand1,
	gen_rtx_IF_THEN_ELSE (CCmode,
	gen_rtx_fmt_ee (GET_CODE (operand4), VOIDmode,
		operand0,
		const0_rtx),
	gen_rtx_COMPARE (CCmode,
	operand2,
	operand3),
	gen_rtx_UNSPEC (CCmode,
	gen_rtvec (1,
		operand5),
	82)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:440 */
rtx
gen_fccmpsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand1,
	gen_rtx_IF_THEN_ELSE (CCFPmode,
	gen_rtx_fmt_ee (GET_CODE (operand4), VOIDmode,
		operand0,
		const0_rtx),
	gen_rtx_COMPARE (CCFPmode,
	operand2,
	operand3),
	gen_rtx_UNSPEC (CCFPmode,
	gen_rtvec (1,
		operand5),
	82)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:440 */
rtx
gen_fccmpdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand1,
	gen_rtx_IF_THEN_ELSE (CCFPmode,
	gen_rtx_fmt_ee (GET_CODE (operand4), VOIDmode,
		operand0,
		const0_rtx),
	gen_rtx_COMPARE (CCFPmode,
	operand2,
	operand3),
	gen_rtx_UNSPEC (CCFPmode,
	gen_rtvec (1,
		operand5),
	82)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:455 */
rtx
gen_fccmpesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand1,
	gen_rtx_IF_THEN_ELSE (CCFPEmode,
	gen_rtx_fmt_ee (GET_CODE (operand4), VOIDmode,
		operand0,
		const0_rtx),
	gen_rtx_COMPARE (CCFPEmode,
	operand2,
	operand3),
	gen_rtx_UNSPEC (CCFPEmode,
	gen_rtvec (1,
		operand5),
	82)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:455 */
rtx
gen_fccmpedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand1,
	gen_rtx_IF_THEN_ELSE (CCFPEmode,
	gen_rtx_fmt_ee (GET_CODE (operand4), VOIDmode,
		operand0,
		const0_rtx),
	gen_rtx_COMPARE (CCFPEmode,
	operand2,
	operand3),
	gen_rtx_UNSPEC (CCFPEmode,
	gen_rtvec (1,
		operand5),
	82)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:526 */
rtx
gen_condjump (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand2),
	pc_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:664 */
rtx
gen_nop (void)
{
  return gen_rtx_UNSPEC (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	43);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:671 */
rtx
gen_prefetch (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PREFETCH (VOIDmode,
	operand0,
	operand1,
	operand2);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:702 */
rtx
gen_trap (void)
{
  return gen_rtx_TRAP_IF (VOIDmode,
	const1_rtx,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:755 */
rtx
gen_simple_return (void)
{
  return simple_return_rtx;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1153 */
rtx
gen_insv_immsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_ZERO_EXTRACT (SImode,
	operand0,
	const_int_rtx[MAX_SAVED_CONST_INT + (16)],
	operand1),
	operand2);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1153 */
rtx
gen_insv_immdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_ZERO_EXTRACT (DImode,
	operand0,
	const_int_rtx[MAX_SAVED_CONST_INT + (16)],
	operand1),
	operand2);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1384 */
rtx
gen_load_pair_sw_sisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1384 */
rtx
gen_load_pair_sw_sfsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1384 */
rtx
gen_load_pair_sw_sisf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1384 */
rtx
gen_load_pair_sw_sfsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1401 */
rtx
gen_load_pair_dw_didi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1401 */
rtx
gen_load_pair_dw_didf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1401 */
rtx
gen_load_pair_dw_dfdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1401 */
rtx
gen_load_pair_dw_dfdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1417 */
rtx
gen_load_pair_dw_tftf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1434 */
rtx
gen_store_pair_sw_sisi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1434 */
rtx
gen_store_pair_sw_sfsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1434 */
rtx
gen_store_pair_sw_sisf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1434 */
rtx
gen_store_pair_sw_sfsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1451 */
rtx
gen_store_pair_dw_didi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1451 */
rtx
gen_store_pair_dw_didf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1451 */
rtx
gen_store_pair_dw_dfdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1451 */
rtx
gen_store_pair_dw_dfdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1467 */
rtx
gen_store_pair_dw_tftf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1484 */
rtx
gen_loadwb_pairsi_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (SImode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (SImode,
	gen_rtx_PLUS (SImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1484 */
rtx
gen_loadwb_pairsi_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (SImode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (SImode,
	gen_rtx_PLUS (DImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1484 */
rtx
gen_loadwb_pairdi_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (DImode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (DImode,
	gen_rtx_PLUS (SImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1484 */
rtx
gen_loadwb_pairdi_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (DImode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (DImode,
	gen_rtx_PLUS (DImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1499 */
rtx
gen_loadwb_pairsf_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (SFmode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (SFmode,
	gen_rtx_PLUS (SImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1499 */
rtx
gen_loadwb_pairsf_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (SFmode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (SFmode,
	gen_rtx_PLUS (DImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1499 */
rtx
gen_loadwb_pairdf_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (DFmode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (DFmode,
	gen_rtx_PLUS (SImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1499 */
rtx
gen_loadwb_pairdf_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (DFmode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (DFmode,
	gen_rtx_PLUS (DImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1514 */
rtx
gen_loadwb_pairti_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (TImode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (TImode,
	gen_rtx_PLUS (SImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1514 */
rtx
gen_loadwb_pairti_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (TImode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (TImode,
	gen_rtx_PLUS (DImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1514 */
rtx
gen_loadwb_pairtf_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (TFmode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (TFmode,
	gen_rtx_PLUS (SImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1514 */
rtx
gen_loadwb_pairtf_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (TFmode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (TFmode,
	gen_rtx_PLUS (DImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1531 */
rtx
gen_storewb_pairsi_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (SImode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (SImode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1531 */
rtx
gen_storewb_pairsi_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (SImode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (SImode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1531 */
rtx
gen_storewb_pairdi_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (DImode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (DImode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1531 */
rtx
gen_storewb_pairdi_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (DImode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (DImode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1547 */
rtx
gen_storewb_pairsf_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (SFmode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (SFmode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1547 */
rtx
gen_storewb_pairsf_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (SFmode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (SFmode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1547 */
rtx
gen_storewb_pairdf_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (DFmode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (DFmode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1547 */
rtx
gen_storewb_pairdf_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (DFmode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (DFmode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1563 */
rtx
gen_storewb_pairti_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (TImode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (TImode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1563 */
rtx
gen_storewb_pairti_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (TImode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (TImode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1563 */
rtx
gen_storewb_pairtf_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (TFmode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (TFmode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1563 */
rtx
gen_storewb_pairtf_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (TFmode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (TFmode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2000 */
rtx
gen_addsi3_compare0 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_PLUS (SImode,
	operand1,
	operand2),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2000 */
rtx
gen_adddi3_compare0 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_PLUS (DImode,
	operand1,
	operand2),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2048 */
rtx
gen_addsi3_compareC (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Cmode,
	66),
	gen_rtx_COMPARE (CC_Cmode,
	gen_rtx_PLUS (SImode,
	operand1,
	operand2),
	copy_rtx (operand1))),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2048 */
rtx
gen_adddi3_compareC (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Cmode,
	66),
	gen_rtx_COMPARE (CC_Cmode,
	gen_rtx_PLUS (DImode,
	operand1,
	operand2),
	copy_rtx (operand1))),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2094 */
rtx
gen_addsi3_compareV_imm (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_PLUS (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	operand2),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	copy_rtx (operand2))))),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2094 */
rtx
gen_adddi3_compareV_imm (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_PLUS (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	operand1),
	operand2),
	gen_rtx_SIGN_EXTEND (TImode,
	gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	copy_rtx (operand2))))),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2112 */
rtx
gen_addsi3_compareV (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_PLUS (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	copy_rtx (operand2))))),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2112 */
rtx
gen_adddi3_compareV (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_PLUS (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	operand1),
	gen_rtx_SIGN_EXTEND (TImode,
	operand2)),
	gen_rtx_SIGN_EXTEND (TImode,
	gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	copy_rtx (operand2))))),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2308 */
rtx
gen_aarch64_subsi_compare0 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_MINUS (SImode,
	operand0,
	operand1),
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2308 */
rtx
gen_aarch64_subdi_compare0 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_MINUS (DImode,
	operand0,
	operand1),
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2689 */
rtx
gen_subsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2709 */
rtx
gen_subdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2737 */
rtx
gen_subvsi_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2)),
	gen_rtx_MINUS (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	copy_rtx (operand1)),
	gen_rtx_SIGN_EXTEND (DImode,
	copy_rtx (operand2))))),
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2737 */
rtx
gen_subvdi_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_SIGN_EXTEND (TImode,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2)),
	gen_rtx_MINUS (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	copy_rtx (operand1)),
	gen_rtx_SIGN_EXTEND (TImode,
	copy_rtx (operand2))))),
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2753 */
rtx
gen_subvsi_imm (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2)),
	gen_rtx_MINUS (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	copy_rtx (operand1)),
	copy_rtx (operand2)))),
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2753 */
rtx
gen_subvdi_imm (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_SIGN_EXTEND (TImode,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2)),
	gen_rtx_MINUS (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	copy_rtx (operand1)),
	copy_rtx (operand2)))),
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2784 */
rtx
gen_negvsi_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_NEG (SImode,
	operand1)),
	gen_rtx_NEG (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	copy_rtx (operand1))))),
		gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	copy_rtx (operand1)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2784 */
rtx
gen_negvdi_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_SIGN_EXTEND (TImode,
	gen_rtx_NEG (DImode,
	operand1)),
	gen_rtx_NEG (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	copy_rtx (operand1))))),
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	copy_rtx (operand1)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2797 */
rtx
gen_negvsi_cmp_only (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_NEG (SImode,
	operand0)),
	gen_rtx_NEG (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand0))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2797 */
rtx
gen_negvdi_cmp_only (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_SIGN_EXTEND (TImode,
	gen_rtx_NEG (DImode,
	operand0)),
	gen_rtx_NEG (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	operand0))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2911 */
rtx
gen_negdi_carryout (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	const0_rtx,
	operand1)),
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	copy_rtx (operand1)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2922 */
rtx
gen_negvdi_carryinV (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_NEG (TImode,
	gen_rtx_PLUS (TImode,
	gen_rtx_LTU (TImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx),
	gen_rtx_SIGN_EXTEND (TImode,
	operand1))),
	gen_rtx_SIGN_EXTEND (TImode,
	gen_rtx_NEG (DImode,
	gen_rtx_PLUS (DImode,
	gen_rtx_LTU (DImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx),
	copy_rtx (operand1)))))),
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_PLUS (DImode,
	gen_rtx_LTU (DImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx),
	copy_rtx (operand1))))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2964 */
rtx
gen_subsi3_compare1_imm (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	operand1,
	operand2)),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2964 */
rtx
gen_subdi3_compare1_imm (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	operand1,
	operand2)),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2980 */
rtx
gen_subsi3_compare1 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	operand1,
	operand2)),
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2980 */
rtx
gen_subdi3_compare1 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	operand1,
	operand2)),
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3489 */
rtx
gen_negsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3489 */
rtx
gen_negdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3530 */
rtx
gen_negsi2_compare0 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_NEG (SImode,
	operand1),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	copy_rtx (operand1)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3530 */
rtx
gen_negdi2_compare0 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_NEG (DImode,
	operand1),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	copy_rtx (operand1)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3611 */
rtx
gen_mulsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3611 */
rtx
gen_muldi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3631 */
rtx
gen_maddsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_MULT (SImode,
	operand1,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3631 */
rtx
gen_madddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_MULT (DImode,
	operand1,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3699 */
rtx
gen_mulsidi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3699 */
rtx
gen_umulsidi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (DImode,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1),
	gen_rtx_ZERO_EXTEND (DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3708 */
rtx
gen_maddsidi4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3708 */
rtx
gen_umaddsidi4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1),
	gen_rtx_ZERO_EXTEND (DImode,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3719 */
rtx
gen_msubsidi4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	operand3,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3719 */
rtx
gen_umsubsidi4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	operand3,
	gen_rtx_MULT (DImode,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1),
	gen_rtx_ZERO_EXTEND (DImode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3783 */
rtx
gen_smuldi3_highpart (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (DImode,
	gen_rtx_LSHIFTRT (TImode,
	gen_rtx_MULT (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	operand1),
	gen_rtx_SIGN_EXTEND (TImode,
	operand2)),
	const_int_rtx[MAX_SAVED_CONST_INT + (64)])));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3783 */
rtx
gen_umuldi3_highpart (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (DImode,
	gen_rtx_LSHIFTRT (TImode,
	gen_rtx_MULT (TImode,
	gen_rtx_ZERO_EXTEND (TImode,
	operand1),
	gen_rtx_ZERO_EXTEND (TImode,
	operand2)),
	const_int_rtx[MAX_SAVED_CONST_INT + (64)])));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3796 */
rtx
gen_divsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_DIV (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3796 */
rtx
gen_udivsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UDIV (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3796 */
rtx
gen_divdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_DIV (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3796 */
rtx
gen_udivdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UDIV (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3820 */
rtx
gen_cmpsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	operand0,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3820 */
rtx
gen_cmpdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	operand0,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3832 */
rtx
gen_fcmpsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCFPmode,
	66),
	gen_rtx_COMPARE (CCFPmode,
	operand0,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3832 */
rtx
gen_fcmpdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCFPmode,
	66),
	gen_rtx_COMPARE (CCFPmode,
	operand0,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3843 */
rtx
gen_fcmpesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCFPEmode,
	66),
	gen_rtx_COMPARE (CCFPEmode,
	operand0,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3843 */
rtx
gen_fcmpedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCFPEmode,
	66),
	gen_rtx_COMPARE (CCFPEmode,
	operand0,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3929 */
rtx
gen_aarch64_cstoreqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), QImode,
		operand2,
		const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3929 */
rtx
gen_aarch64_cstorehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), HImode,
		operand2,
		const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3929 */
rtx
gen_aarch64_cstoresi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3929 */
rtx
gen_aarch64_cstoredi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), DImode,
		operand2,
		const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3984 */
rtx
gen_cstoreqi_neg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (QImode,
	gen_rtx_fmt_ee (GET_CODE (operand1), QImode,
		operand2,
		const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3984 */
rtx
gen_cstorehi_neg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_fmt_ee (GET_CODE (operand1), HImode,
		operand2,
		const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3984 */
rtx
gen_cstoresi_neg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3984 */
rtx
gen_cstoredi_neg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_fmt_ee (GET_CODE (operand1), DImode,
		operand2,
		const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4181 */
rtx
gen_aarch64_crc32b (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4181 */
rtx
gen_aarch64_crc32h (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	8));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4181 */
rtx
gen_aarch64_crc32w (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4181 */
rtx
gen_aarch64_crc32x (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4181 */
rtx
gen_aarch64_crc32cb (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	4));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4181 */
rtx
gen_aarch64_crc32ch (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	5));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4181 */
rtx
gen_aarch64_crc32cw (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	6));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4181 */
rtx
gen_aarch64_crc32cx (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	7));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4205 */
rtx
gen_csinc3si_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	gen_rtx_PLUS (SImode,
	operand2,
	const1_rtx),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4205 */
rtx
gen_csinc3di_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	gen_rtx_PLUS (DImode,
	operand2,
	const1_rtx),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4228 */
rtx
gen_csneg3_uxtw_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	gen_rtx_NEG (SImode,
	operand2),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4240 */
rtx
gen_csneg3si_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	gen_rtx_NEG (SImode,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4240 */
rtx
gen_csneg3di_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	gen_rtx_NEG (DImode,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4296 */
rtx
gen_aarch64_uqdecsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	gen_rtx_UMAX (SImode,
	operand1,
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4296 */
rtx
gen_aarch64_uqdecdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	gen_rtx_UMAX (DImode,
	operand1,
	operand2),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4332 */
rtx
gen_andsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4332 */
rtx
gen_iorsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4332 */
rtx
gen_xorsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4332 */
rtx
gen_anddi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4332 */
rtx
gen_iordi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4332 */
rtx
gen_xordi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4468 */
rtx
gen_one_cmplsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4468 */
rtx
gen_one_cmpldi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_and_one_cmpl_ashlsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_ior_one_cmpl_ashlsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_xor_one_cmpl_ashlsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_and_one_cmpl_ashrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ASHIFTRT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_ior_one_cmpl_ashrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ASHIFTRT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_xor_one_cmpl_ashrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ASHIFTRT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_and_one_cmpl_lshrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_ior_one_cmpl_lshrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_xor_one_cmpl_lshrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_and_one_cmpl_rotrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ROTATERT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_ior_one_cmpl_rotrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ROTATERT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_xor_one_cmpl_rotrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ROTATERT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_and_one_cmpl_ashldi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_ior_one_cmpl_ashldi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_xor_one_cmpl_ashldi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_and_one_cmpl_ashrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ASHIFTRT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_ior_one_cmpl_ashrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ASHIFTRT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_xor_one_cmpl_ashrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ASHIFTRT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_and_one_cmpl_lshrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_ior_one_cmpl_lshrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_xor_one_cmpl_lshrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_and_one_cmpl_rotrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ROTATERT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_ior_one_cmpl_rotrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ROTATERT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4583 */
rtx
gen_xor_one_cmpl_rotrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ROTATERT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4672 */
rtx
gen_clzsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4672 */
rtx
gen_clzdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4728 */
rtx
gen_clrsbsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4728 */
rtx
gen_clrsbdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4736 */
rtx
gen_rbitsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	48));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4736 */
rtx
gen_rbitdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	48));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4749 */
rtx
gen_ctzsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CTZ (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4749 */
rtx
gen_ctzdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CTZ (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5668 */
rtx
gen_bswapsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5668 */
rtx
gen_bswapdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5676 */
rtx
gen_bswaphi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5740 */
rtx
gen_rev16si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	gen_rtx_AND (SImode,
	gen_rtx_ASHIFT (SImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand3),
	gen_rtx_AND (SImode,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5740 */
rtx
gen_rev16di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	gen_rtx_AND (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand3),
	gen_rtx_AND (DImode,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5754 */
rtx
gen_rev16si2_alt (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	gen_rtx_AND (SImode,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand2),
	gen_rtx_AND (SImode,
	gen_rtx_ASHIFT (SImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5754 */
rtx
gen_rev16di2_alt (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	gen_rtx_AND (DImode,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand2),
	gen_rtx_AND (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_btrunchf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	23));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_ceilhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_floorhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_frintnhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_nearbyinthf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_rinthf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	22));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_roundhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_btruncsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	23));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_ceilsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_floorsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_frintnsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_nearbyintsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_rintsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	22));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_roundsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_btruncdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	23));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_ceildf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_floordf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_frintndf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_nearbyintdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_rintdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	22));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5784 */
rtx
gen_rounddf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lbtrunchfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lceilhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfloorhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lroundhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfrintnhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lbtruncuhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lceiluhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lflooruhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lrounduhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfrintnuhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lbtrunchfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lceilhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfloorhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lroundhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfrintnhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lbtruncuhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lceiluhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lflooruhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lrounduhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfrintnuhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lbtruncsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lceilsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfloorsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lroundsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfrintnsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lbtruncusfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lceilusfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfloorusfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lroundusfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfrintnusfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lbtruncsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lceilsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfloorsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lroundsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfrintnsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lbtruncusfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lceilusfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfloorusfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lroundusfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfrintnusfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lbtruncdfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lceildfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfloordfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lrounddfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfrintndfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lbtruncudfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lceiludfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfloorudfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lroundudfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfrintnudfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lbtruncdfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lceildfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfloordfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lrounddfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfrintndfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lbtruncudfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lceiludfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfloorudfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lroundudfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5795 */
rtx
gen_lfrintnudfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5919 */
rtx
gen_extendsfdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5927 */
rtx
gen_extendhfsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5935 */
rtx
gen_extendhfdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5943 */
rtx
gen_truncdfsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_TRUNCATE (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5951 */
rtx
gen_truncsfhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_TRUNCATE (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5959 */
rtx
gen_truncdfhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_TRUNCATE (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5970 */
rtx
gen_fix_truncsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5970 */
rtx
gen_fixuns_truncsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5970 */
rtx
gen_fix_truncdfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5970 */
rtx
gen_fixuns_truncdfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5982 */
rtx
gen_fix_trunchfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5982 */
rtx
gen_fixuns_trunchfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5982 */
rtx
gen_fix_trunchfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5982 */
rtx
gen_fixuns_trunchfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5993 */
rtx
gen_fix_truncdfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5993 */
rtx
gen_fixuns_truncdfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5993 */
rtx
gen_fix_truncsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5993 */
rtx
gen_fixuns_truncsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6011 */
rtx
gen_floatsisf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6011 */
rtx
gen_floatunssisf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6011 */
rtx
gen_floatdidf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6011 */
rtx
gen_floatunsdidf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6022 */
rtx
gen_floatdisf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6022 */
rtx
gen_floatunsdisf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6022 */
rtx
gen_floatsidf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6022 */
rtx
gen_floatunssidf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6037 */
rtx
gen_aarch64_fp16_floatsihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6037 */
rtx
gen_aarch64_fp16_floatunssihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6037 */
rtx
gen_aarch64_fp16_floatdihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6037 */
rtx
gen_aarch64_fp16_floatunsdihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6094 */
rtx
gen_fcvtzssf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	11));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6094 */
rtx
gen_fcvtzusf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6094 */
rtx
gen_fcvtzsdf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	11));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6094 */
rtx
gen_fcvtzudf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6107 */
rtx
gen_scvtfsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6107 */
rtx
gen_ucvtfsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6107 */
rtx
gen_scvtfdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6107 */
rtx
gen_ucvtfdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6120 */
rtx
gen_fcvtzshfsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	11));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6120 */
rtx
gen_fcvtzuhfsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6120 */
rtx
gen_fcvtzshfdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	11));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6120 */
rtx
gen_fcvtzuhfdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6130 */
rtx
gen_scvtfsihf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6130 */
rtx
gen_ucvtfsihf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6130 */
rtx
gen_scvtfdihf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6130 */
rtx
gen_ucvtfdihf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6140 */
rtx
gen_fcvtzshf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	11));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6140 */
rtx
gen_fcvtzuhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6150 */
rtx
gen_scvtfhi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6150 */
rtx
gen_ucvtfhi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6164 */
rtx
gen_addhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6164 */
rtx
gen_addsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6164 */
rtx
gen_adddf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6174 */
rtx
gen_subhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6174 */
rtx
gen_subsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6174 */
rtx
gen_subdf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6184 */
rtx
gen_mulhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6184 */
rtx
gen_mulsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6184 */
rtx
gen_muldf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6235 */
rtx
gen_neghf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6235 */
rtx
gen_negsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6235 */
rtx
gen_negdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6260 */
rtx
gen_abshf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6260 */
rtx
gen_abssf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6260 */
rtx
gen_absdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6272 */
rtx
gen_smaxsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6272 */
rtx
gen_smaxdf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6281 */
rtx
gen_sminsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6281 */
rtx
gen_smindf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6293 */
rtx
gen_smax_nanhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	109));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6293 */
rtx
gen_smin_nanhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6293 */
rtx
gen_fmaxhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	207));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6293 */
rtx
gen_fminhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	208));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6293 */
rtx
gen_smax_nansf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	109));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6293 */
rtx
gen_smin_nansf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6293 */
rtx
gen_fmaxsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	207));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6293 */
rtx
gen_fminsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	208));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6293 */
rtx
gen_smax_nandf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	109));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6293 */
rtx
gen_smin_nandf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6293 */
rtx
gen_fmaxdf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	207));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6293 */
rtx
gen_fmindf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	208));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6347 */
rtx
gen_copysignsf3_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	105));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6347 */
rtx
gen_copysigndf3_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	105));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6449 */
rtx
gen_aarch64_movdi_tilow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (64)],
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6449 */
rtx
gen_aarch64_movdi_tflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (64)],
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6459 */
rtx
gen_aarch64_movdi_tihigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (64)],
	const_int_rtx[MAX_SAVED_CONST_INT + (64)]));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6459 */
rtx
gen_aarch64_movdi_tfhigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (64)],
	const_int_rtx[MAX_SAVED_CONST_INT + (64)]));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6469 */
rtx
gen_aarch64_movtihigh_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_ZERO_EXTRACT (TImode,
	operand0,
	const_int_rtx[MAX_SAVED_CONST_INT + (64)],
	const_int_rtx[MAX_SAVED_CONST_INT + (64)]),
	gen_rtx_ZERO_EXTEND (TImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6469 */
rtx
gen_aarch64_movtfhigh_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_ZERO_EXTRACT (TFmode,
	operand0,
	const_int_rtx[MAX_SAVED_CONST_INT + (64)],
	const_int_rtx[MAX_SAVED_CONST_INT + (64)]),
	gen_rtx_ZERO_EXTEND (TFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6479 */
rtx
gen_aarch64_movtilow_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (TImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6479 */
rtx
gen_aarch64_movtflow_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (TFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6488 */
rtx
gen_aarch64_movtilow_tilow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (TImode,
	gen_rtx_TRUNCATE (DImode,
	operand1)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6519 */
rtx
gen_add_losym_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LO_SUM (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6519 */
rtx
gen_add_losym_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LO_SUM (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6528 */
rtx
gen_ldr_got_small_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		gen_rtx_MEM (SImode,
	gen_rtx_LO_SUM (SImode,
	operand1,
	operand2))),
	24));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6528 */
rtx
gen_ldr_got_small_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		gen_rtx_MEM (DImode,
	gen_rtx_LO_SUM (DImode,
	operand1,
	operand2))),
	24));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6539 */
rtx
gen_ldr_got_small_sidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		gen_rtx_MEM (SImode,
	gen_rtx_LO_SUM (DImode,
	operand1,
	operand2))),
	24)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6551 */
rtx
gen_ldr_got_small_28k_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		gen_rtx_MEM (SImode,
	gen_rtx_LO_SUM (SImode,
	operand1,
	operand2))),
	25));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6551 */
rtx
gen_ldr_got_small_28k_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		gen_rtx_MEM (DImode,
	gen_rtx_LO_SUM (DImode,
	operand1,
	operand2))),
	25));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6562 */
rtx
gen_ldr_got_small_28k_sidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		gen_rtx_MEM (SImode,
	gen_rtx_LO_SUM (DImode,
	operand1,
	operand2))),
	25)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6574 */
rtx
gen_ldr_got_tiny (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6583 */
rtx
gen_aarch64_load_tp_hard (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	64));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6615 */
rtx
gen_tlsie_small_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	26));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6615 */
rtx
gen_tlsie_small_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	26));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6625 */
rtx
gen_tlsie_small_sidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	26)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6636 */
rtx
gen_tlsie_tiny_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	28));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6636 */
rtx
gen_tlsie_tiny_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	28));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6647 */
rtx
gen_tlsie_tiny_sidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	28)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6660 */
rtx
gen_tlsle12_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	66));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6660 */
rtx
gen_tlsle12_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	66));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6671 */
rtx
gen_tlsle24_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	67));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6671 */
rtx
gen_tlsle24_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	67));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6682 */
rtx
gen_tlsle32_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	68));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6682 */
rtx
gen_tlsle32_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	68));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6692 */
rtx
gen_tlsle48_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	69));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6692 */
rtx
gen_tlsle48_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	69));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6716 */
rtx
gen_tlsdesc_small_advsimd_si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (gen_rtx_REG (SImode,
	0),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand0),
	65)),
		gen_hard_reg_clobber (DImode, 30),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6716 */
rtx
gen_tlsdesc_small_advsimd_di (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (gen_rtx_REG (DImode,
	0),
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand0),
	65)),
		gen_hard_reg_clobber (DImode, 30),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6731 */
rtx
gen_tlsdesc_small_sve_si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (52,
		gen_rtx_SET (gen_rtx_REG (SImode,
	0),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand0),
	65)),
		gen_hard_reg_clobber (DImode, 30),
		gen_hard_reg_clobber (CCmode, 66),
		gen_hard_reg_clobber_high (TImode, 32),
		gen_hard_reg_clobber_high (TImode, 33),
		gen_hard_reg_clobber_high (TImode, 34),
		gen_hard_reg_clobber_high (TImode, 35),
		gen_hard_reg_clobber_high (TImode, 36),
		gen_hard_reg_clobber_high (TImode, 37),
		gen_hard_reg_clobber_high (TImode, 38),
		gen_hard_reg_clobber_high (TImode, 39),
		gen_hard_reg_clobber_high (TImode, 40),
		gen_hard_reg_clobber_high (TImode, 41),
		gen_hard_reg_clobber_high (TImode, 42),
		gen_hard_reg_clobber_high (TImode, 43),
		gen_hard_reg_clobber_high (TImode, 44),
		gen_hard_reg_clobber_high (TImode, 45),
		gen_hard_reg_clobber_high (TImode, 46),
		gen_hard_reg_clobber_high (TImode, 47),
		gen_hard_reg_clobber_high (TImode, 48),
		gen_hard_reg_clobber_high (TImode, 49),
		gen_hard_reg_clobber_high (TImode, 50),
		gen_hard_reg_clobber_high (TImode, 51),
		gen_hard_reg_clobber_high (TImode, 52),
		gen_hard_reg_clobber_high (TImode, 53),
		gen_hard_reg_clobber_high (TImode, 54),
		gen_hard_reg_clobber_high (TImode, 55),
		gen_hard_reg_clobber_high (TImode, 56),
		gen_hard_reg_clobber_high (TImode, 57),
		gen_hard_reg_clobber_high (TImode, 58),
		gen_hard_reg_clobber_high (TImode, 59),
		gen_hard_reg_clobber_high (TImode, 60),
		gen_hard_reg_clobber_high (TImode, 61),
		gen_hard_reg_clobber_high (TImode, 62),
		gen_hard_reg_clobber_high (TImode, 63),
		gen_hard_reg_clobber (VNx2BImode, 68),
		gen_hard_reg_clobber (VNx2BImode, 69),
		gen_hard_reg_clobber (VNx2BImode, 70),
		gen_hard_reg_clobber (VNx2BImode, 71),
		gen_hard_reg_clobber (VNx2BImode, 72),
		gen_hard_reg_clobber (VNx2BImode, 73),
		gen_hard_reg_clobber (VNx2BImode, 74),
		gen_hard_reg_clobber (VNx2BImode, 75),
		gen_hard_reg_clobber (VNx2BImode, 76),
		gen_hard_reg_clobber (VNx2BImode, 77),
		gen_hard_reg_clobber (VNx2BImode, 78),
		gen_hard_reg_clobber (VNx2BImode, 79),
		gen_hard_reg_clobber (VNx2BImode, 80),
		gen_hard_reg_clobber (VNx2BImode, 81),
		gen_hard_reg_clobber (VNx2BImode, 82),
		gen_hard_reg_clobber (VNx2BImode, 83),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6731 */
rtx
gen_tlsdesc_small_sve_di (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (52,
		gen_rtx_SET (gen_rtx_REG (DImode,
	0),
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand0),
	65)),
		gen_hard_reg_clobber (DImode, 30),
		gen_hard_reg_clobber (CCmode, 66),
		gen_hard_reg_clobber_high (TImode, 32),
		gen_hard_reg_clobber_high (TImode, 33),
		gen_hard_reg_clobber_high (TImode, 34),
		gen_hard_reg_clobber_high (TImode, 35),
		gen_hard_reg_clobber_high (TImode, 36),
		gen_hard_reg_clobber_high (TImode, 37),
		gen_hard_reg_clobber_high (TImode, 38),
		gen_hard_reg_clobber_high (TImode, 39),
		gen_hard_reg_clobber_high (TImode, 40),
		gen_hard_reg_clobber_high (TImode, 41),
		gen_hard_reg_clobber_high (TImode, 42),
		gen_hard_reg_clobber_high (TImode, 43),
		gen_hard_reg_clobber_high (TImode, 44),
		gen_hard_reg_clobber_high (TImode, 45),
		gen_hard_reg_clobber_high (TImode, 46),
		gen_hard_reg_clobber_high (TImode, 47),
		gen_hard_reg_clobber_high (TImode, 48),
		gen_hard_reg_clobber_high (TImode, 49),
		gen_hard_reg_clobber_high (TImode, 50),
		gen_hard_reg_clobber_high (TImode, 51),
		gen_hard_reg_clobber_high (TImode, 52),
		gen_hard_reg_clobber_high (TImode, 53),
		gen_hard_reg_clobber_high (TImode, 54),
		gen_hard_reg_clobber_high (TImode, 55),
		gen_hard_reg_clobber_high (TImode, 56),
		gen_hard_reg_clobber_high (TImode, 57),
		gen_hard_reg_clobber_high (TImode, 58),
		gen_hard_reg_clobber_high (TImode, 59),
		gen_hard_reg_clobber_high (TImode, 60),
		gen_hard_reg_clobber_high (TImode, 61),
		gen_hard_reg_clobber_high (TImode, 62),
		gen_hard_reg_clobber_high (TImode, 63),
		gen_hard_reg_clobber (VNx2BImode, 68),
		gen_hard_reg_clobber (VNx2BImode, 69),
		gen_hard_reg_clobber (VNx2BImode, 70),
		gen_hard_reg_clobber (VNx2BImode, 71),
		gen_hard_reg_clobber (VNx2BImode, 72),
		gen_hard_reg_clobber (VNx2BImode, 73),
		gen_hard_reg_clobber (VNx2BImode, 74),
		gen_hard_reg_clobber (VNx2BImode, 75),
		gen_hard_reg_clobber (VNx2BImode, 76),
		gen_hard_reg_clobber (VNx2BImode, 77),
		gen_hard_reg_clobber (VNx2BImode, 78),
		gen_hard_reg_clobber (VNx2BImode, 79),
		gen_hard_reg_clobber (VNx2BImode, 80),
		gen_hard_reg_clobber (VNx2BImode, 81),
		gen_hard_reg_clobber (VNx2BImode, 82),
		gen_hard_reg_clobber (VNx2BImode, 83),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6791 */
rtx
gen_stack_tie (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand0,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6810 */
rtx
gen_pacisp (void)
{
  return gen_rtx_SET (gen_rtx_REG (DImode,
	30),
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		gen_rtx_REG (DImode,
	30),
		gen_rtx_REG (DImode,
	31)),
	45));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6810 */
rtx
gen_autisp (void)
{
  return gen_rtx_SET (gen_rtx_REG (DImode,
	30),
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		gen_rtx_REG (DImode,
	30),
		gen_rtx_REG (DImode,
	31)),
	1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6819 */
rtx
gen_paci1716 (void)
{
  return gen_rtx_SET (gen_rtx_REG (DImode,
	17),
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		gen_rtx_REG (DImode,
	17),
		gen_rtx_REG (DImode,
	16)),
	44));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6819 */
rtx
gen_auti1716 (void)
{
  return gen_rtx_SET (gen_rtx_REG (DImode,
	17),
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		gen_rtx_REG (DImode,
	17),
		gen_rtx_REG (DImode,
	16)),
	0));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6828 */
rtx
gen_xpaclri (void)
{
  return gen_rtx_SET (gen_rtx_REG (DImode,
	30),
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		gen_rtx_REG (DImode,
	30)),
	83));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6837 */
rtx
gen_blockage (void)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	5);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6845 */
rtx
gen_probe_stack_range (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	6));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6861 */
rtx
gen_probe_sve_stack_clash_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	6));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6861 */
rtx
gen_probe_sve_stack_clash_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	6));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6920 */
rtx
gen_reg_stack_protect_address_si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		const0_rtx),
	76));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6920 */
rtx
gen_reg_stack_protect_address_di (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	76));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6934 */
rtx
gen_stack_protect_set_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	77)),
		gen_rtx_SET (gen_rtx_SCRATCH (SImode),
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6934 */
rtx
gen_stack_protect_set_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	77)),
		gen_rtx_SET (gen_rtx_SCRATCH (DImode),
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6992 */
rtx
gen_stack_protect_test_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	78)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6992 */
rtx
gen_stack_protect_test_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	78)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7004 */
rtx
gen_set_fpcr (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		operand0),
	2);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7011 */
rtx
gen_get_fpcr (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		const0_rtx),
	1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7019 */
rtx
gen_set_fpsr (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		operand0),
	4);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7026 */
rtx
gen_get_fpsr (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		const0_rtx),
	3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7073 */
rtx
gen_speculation_tracker (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (DImode,
	15),
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		gen_rtx_REG (DImode,
	15),
		operand0),
	104));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7087 */
rtx
gen_bti_noarg (void)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	8);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7094 */
rtx
gen_bti_c (void)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	9);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7101 */
rtx
gen_bti_j (void)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	10);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7108 */
rtx
gen_bti_jc (void)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	11);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7122 */
rtx
gen_speculation_barrier (void)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	7);
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7202 */
rtx
gen_despeculate_simpleqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_USE (VOIDmode,
	operand2)),
	7));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7202 */
rtx
gen_despeculate_simplehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_USE (VOIDmode,
	operand2)),
	7));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7202 */
rtx
gen_despeculate_simplesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_USE (VOIDmode,
	operand2)),
	7));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7202 */
rtx
gen_despeculate_simpledi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_USE (VOIDmode,
	operand2)),
	7));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7215 */
rtx
gen_despeculate_simpleti (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (TImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_USE (VOIDmode,
	operand2)),
	7));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:54 */
rtx
gen_aarch64_simd_dupv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:54 */
rtx
gen_aarch64_simd_dupv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:54 */
rtx
gen_aarch64_simd_dupv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:54 */
rtx
gen_aarch64_simd_dupv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:54 */
rtx
gen_aarch64_simd_dupv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:54 */
rtx
gen_aarch64_simd_dupv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:54 */
rtx
gen_aarch64_simd_dupv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:65 */
rtx
gen_aarch64_simd_dupv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:65 */
rtx
gen_aarch64_simd_dupv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:65 */
rtx
gen_aarch64_simd_dupv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:65 */
rtx
gen_aarch64_simd_dupv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:65 */
rtx
gen_aarch64_simd_dupv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:74 */
rtx
gen_aarch64_dup_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:74 */
rtx
gen_aarch64_dup_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:74 */
rtx
gen_aarch64_dup_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:74 */
rtx
gen_aarch64_dup_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:74 */
rtx
gen_aarch64_dup_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:74 */
rtx
gen_aarch64_dup_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:74 */
rtx
gen_aarch64_dup_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:74 */
rtx
gen_aarch64_dup_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:74 */
rtx
gen_aarch64_dup_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:74 */
rtx
gen_aarch64_dup_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:74 */
rtx
gen_aarch64_dup_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:74 */
rtx
gen_aarch64_dup_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:89 */
rtx
gen_aarch64_dup_lane_to_128v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:89 */
rtx
gen_aarch64_dup_lane_to_64v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:89 */
rtx
gen_aarch64_dup_lane_to_128v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:89 */
rtx
gen_aarch64_dup_lane_to_64v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:89 */
rtx
gen_aarch64_dup_lane_to_128v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:89 */
rtx
gen_aarch64_dup_lane_to_64v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:89 */
rtx
gen_aarch64_dup_lane_to_128v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:89 */
rtx
gen_aarch64_dup_lane_to_64v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:89 */
rtx
gen_aarch64_dup_lane_to_128v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:89 */
rtx
gen_aarch64_dup_lane_to_64v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_aarch64_store_lane0v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_aarch64_store_lane0v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_aarch64_store_lane0v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_aarch64_store_lane0v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_aarch64_store_lane0v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_aarch64_store_lane0v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_aarch64_store_lane0v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_aarch64_store_lane0v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_aarch64_store_lane0v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_aarch64_store_lane0v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_aarch64_store_lane0v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_aarch64_store_lane0v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv8qiv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv4hiv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv4hfv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv2siv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv2sfv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairdfv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv8qiv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv4hiv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv4hfv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv2siv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv2sfv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairdfv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv8qiv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv4hiv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv4hfv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv2siv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv2sfv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairdfv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv8qiv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv4hiv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv4hfv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv2siv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv2sfv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairdfv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv8qiv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv4hiv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv4hfv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv2siv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv2sfv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairdfv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv8qidf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv4hidf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv4hfdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv2sidf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairv2sfdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:180 */
rtx
gen_load_pairdfdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv8qiv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv4hiv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv4hfv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv2siv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv2sfv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairdfv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv8qiv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv4hiv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv4hfv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv2siv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv2sfv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairdfv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv8qiv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv4hiv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv4hfv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv2siv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv2sfv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairdfv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv8qiv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv4hiv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv4hfv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv2siv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv2sfv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairdfv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv8qiv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv4hiv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv4hfv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv2siv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv2sfv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairdfv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv8qidf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv4hidf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv4hfdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv2sidf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairv2sfdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:194 */
rtx
gen_vec_store_pairdfdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv16qiv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hiv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4siv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2div16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hfv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4sfv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2dfv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv16qiv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hiv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4siv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2div8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hfv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4sfv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2dfv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv16qiv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hiv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4siv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2div4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hfv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4sfv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2dfv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv16qiv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hiv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4siv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2div2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hfv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4sfv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2dfv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv16qiv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hiv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4siv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2div8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hfv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4sfv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2dfv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv16qiv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hiv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4siv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2div4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hfv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4sfv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2dfv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv16qiv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hiv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4siv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2div2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv8hfv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv4sfv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_load_pairv2dfv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv16qiv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hiv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4siv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2div16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hfv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4sfv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2dfv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv16qiv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hiv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4siv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2div8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hfv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4sfv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2dfv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv16qiv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hiv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4siv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2div4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hfv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4sfv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2dfv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv16qiv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hiv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4siv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2div2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hfv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4sfv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2dfv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv16qiv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hiv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4siv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2div8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hfv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4sfv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2dfv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv16qiv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hiv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4siv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2div4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hfv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4sfv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2dfv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv16qiv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hiv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4siv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2div2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv8hfv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv4sfv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:222 */
rtx
gen_vec_store_pairv2dfv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:295 */
rtx
gen_aarch64_simd_mov_from_v16qilow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:295 */
rtx
gen_aarch64_simd_mov_from_v8hilow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:295 */
rtx
gen_aarch64_simd_mov_from_v4silow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:295 */
rtx
gen_aarch64_simd_mov_from_v2dilow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:295 */
rtx
gen_aarch64_simd_mov_from_v8hflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:295 */
rtx
gen_aarch64_simd_mov_from_v4sflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:295 */
rtx
gen_aarch64_simd_mov_from_v2dflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:306 */
rtx
gen_aarch64_simd_mov_from_v16qihigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:306 */
rtx
gen_aarch64_simd_mov_from_v8hihigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:306 */
rtx
gen_aarch64_simd_mov_from_v4sihigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:306 */
rtx
gen_aarch64_simd_mov_from_v2dihigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:306 */
rtx
gen_aarch64_simd_mov_from_v8hfhigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:306 */
rtx
gen_aarch64_simd_mov_from_v4sfhigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:306 */
rtx
gen_aarch64_simd_mov_from_v2dfhigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:317 */
rtx
gen_ornv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V8QImode,
	gen_rtx_NOT (V8QImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:317 */
rtx
gen_ornv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V16QImode,
	gen_rtx_NOT (V16QImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:317 */
rtx
gen_ornv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V4HImode,
	gen_rtx_NOT (V4HImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:317 */
rtx
gen_ornv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V8HImode,
	gen_rtx_NOT (V8HImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:317 */
rtx
gen_ornv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V2SImode,
	gen_rtx_NOT (V2SImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:317 */
rtx
gen_ornv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V4SImode,
	gen_rtx_NOT (V4SImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:317 */
rtx
gen_ornv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V2DImode,
	gen_rtx_NOT (V2DImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:326 */
rtx
gen_bicv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V8QImode,
	gen_rtx_NOT (V8QImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:326 */
rtx
gen_bicv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V16QImode,
	gen_rtx_NOT (V16QImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:326 */
rtx
gen_bicv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V4HImode,
	gen_rtx_NOT (V4HImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:326 */
rtx
gen_bicv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V8HImode,
	gen_rtx_NOT (V8HImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:326 */
rtx
gen_bicv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V2SImode,
	gen_rtx_NOT (V2SImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:326 */
rtx
gen_bicv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V4SImode,
	gen_rtx_NOT (V4SImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:326 */
rtx
gen_bicv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V2DImode,
	gen_rtx_NOT (V2DImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:335 */
rtx
gen_addv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:335 */
rtx
gen_addv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:335 */
rtx
gen_addv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:335 */
rtx
gen_addv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:335 */
rtx
gen_addv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:335 */
rtx
gen_addv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:335 */
rtx
gen_addv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:344 */
rtx
gen_subv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:344 */
rtx
gen_subv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:344 */
rtx
gen_subv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:344 */
rtx
gen_subv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:344 */
rtx
gen_subv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:344 */
rtx
gen_subv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:344 */
rtx
gen_subv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:353 */
rtx
gen_mulv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:353 */
rtx
gen_mulv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:353 */
rtx
gen_mulv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:353 */
rtx
gen_mulv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:353 */
rtx
gen_mulv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:353 */
rtx
gen_mulv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:362 */
rtx
gen_bswapv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:362 */
rtx
gen_bswapv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:362 */
rtx
gen_bswapv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:362 */
rtx
gen_bswapv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:362 */
rtx
gen_bswapv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:370 */
rtx
gen_aarch64_rbitv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	48));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:370 */
rtx
gen_aarch64_rbitv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	48));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:428 */
rtx
gen_aarch64_fcadd90v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	254));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:428 */
rtx
gen_aarch64_fcadd270v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	255));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:428 */
rtx
gen_aarch64_fcadd90v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	254));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:428 */
rtx
gen_aarch64_fcadd270v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	255));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:428 */
rtx
gen_aarch64_fcadd90v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	254));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:428 */
rtx
gen_aarch64_fcadd270v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	255));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:428 */
rtx
gen_aarch64_fcadd90v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	254));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:428 */
rtx
gen_aarch64_fcadd270v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	255));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:428 */
rtx
gen_aarch64_fcadd90v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	254));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:428 */
rtx
gen_aarch64_fcadd270v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	255));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla0v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	256)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla90v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	257)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla180v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	258)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla270v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	259)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla0v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	256)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla90v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	257)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla180v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	258)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla270v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	259)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla0v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SFmode,
	operand1,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	256)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla90v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SFmode,
	operand1,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	257)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla180v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SFmode,
	operand1,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	258)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla270v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SFmode,
	operand1,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	259)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla0v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	256)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla90v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	257)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla180v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	258)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla270v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	259)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla0v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DFmode,
	operand1,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	256)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla90v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DFmode,
	operand1,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	257)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla180v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DFmode,
	operand1,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	258)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:438 */
rtx
gen_aarch64_fcmla270v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DFmode,
	operand1,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	259)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane0v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	256)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane90v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	257)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane180v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	258)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane270v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	259)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane0v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	256)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane90v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	257)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane180v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	258)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane270v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	259)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane0v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SFmode,
	operand1,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	256)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane90v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SFmode,
	operand1,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	257)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane180v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SFmode,
	operand1,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	258)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane270v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SFmode,
	operand1,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	259)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane0v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	256)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane90v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	257)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane180v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	258)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane270v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	259)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane0v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DFmode,
	operand1,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	256)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane90v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DFmode,
	operand1,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	257)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane180v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DFmode,
	operand1,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	258)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:450 */
rtx
gen_aarch64_fcmla_lane270v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DFmode,
	operand1,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	259)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:465 */
rtx
gen_aarch64_fcmla_laneq0v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	256)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:465 */
rtx
gen_aarch64_fcmla_laneq90v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	257)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:465 */
rtx
gen_aarch64_fcmla_laneq180v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	258)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:465 */
rtx
gen_aarch64_fcmla_laneq270v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	259)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:480 */
rtx
gen_aarch64_fcmlaq_lane0v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	256)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:480 */
rtx
gen_aarch64_fcmlaq_lane90v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	257)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:480 */
rtx
gen_aarch64_fcmlaq_lane180v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	258)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:480 */
rtx
gen_aarch64_fcmlaq_lane270v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	259)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:480 */
rtx
gen_aarch64_fcmlaq_lane0v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	256)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:480 */
rtx
gen_aarch64_fcmlaq_lane90v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	257)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:480 */
rtx
gen_aarch64_fcmlaq_lane180v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	258)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:480 */
rtx
gen_aarch64_fcmlaq_lane270v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	259)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:498 */
rtx
gen_aarch64_sdotv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	operand1,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	209)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:498 */
rtx
gen_aarch64_udotv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	operand1,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	210)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:498 */
rtx
gen_aarch64_sdotv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	209)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:498 */
rtx
gen_aarch64_udotv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	210)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:546 */
rtx
gen_aarch64_sdot_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	operand1,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	209)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:546 */
rtx
gen_aarch64_udot_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	operand1,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	210)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:546 */
rtx
gen_aarch64_sdot_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	209)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:546 */
rtx
gen_aarch64_udot_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	210)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:561 */
rtx
gen_aarch64_sdot_laneqv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	operand1,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	209)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:561 */
rtx
gen_aarch64_udot_laneqv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	operand1,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	210)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:561 */
rtx
gen_aarch64_sdot_laneqv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	209)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:561 */
rtx
gen_aarch64_udot_laneqv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	210)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:637 */
rtx
gen_aarch64_rsqrtev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:637 */
rtx
gen_aarch64_rsqrtev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:637 */
rtx
gen_aarch64_rsqrtev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:637 */
rtx
gen_aarch64_rsqrtev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:637 */
rtx
gen_aarch64_rsqrtev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:637 */
rtx
gen_aarch64_rsqrtehf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:637 */
rtx
gen_aarch64_rsqrtesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:637 */
rtx
gen_aarch64_rsqrtedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:645 */
rtx
gen_aarch64_rsqrtsv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:645 */
rtx
gen_aarch64_rsqrtsv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:645 */
rtx
gen_aarch64_rsqrtsv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:645 */
rtx
gen_aarch64_rsqrtsv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:645 */
rtx
gen_aarch64_rsqrtsv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:645 */
rtx
gen_aarch64_rsqrtshf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:645 */
rtx
gen_aarch64_rsqrtssf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:645 */
rtx
gen_aarch64_rsqrtsdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:679 */
rtx
gen_negv8qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:679 */
rtx
gen_negv16qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:679 */
rtx
gen_negv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:679 */
rtx
gen_negv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:679 */
rtx
gen_negv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:679 */
rtx
gen_negv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:679 */
rtx
gen_negv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:687 */
rtx
gen_absv8qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:687 */
rtx
gen_absv16qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:687 */
rtx
gen_absv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:687 */
rtx
gen_absv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:687 */
rtx
gen_absv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:687 */
rtx
gen_absv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:687 */
rtx
gen_absv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:698 */
rtx
gen_aarch64_absv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	108));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:698 */
rtx
gen_aarch64_absv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	108));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:698 */
rtx
gen_aarch64_absv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	108));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:698 */
rtx
gen_aarch64_absv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	108));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:698 */
rtx
gen_aarch64_absv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	108));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:698 */
rtx
gen_aarch64_absv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	108));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:698 */
rtx
gen_aarch64_absv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	108));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:698 */
rtx
gen_aarch64_absdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	108));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:727 */
rtx
gen_aarch64_sabdl2v8qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:727 */
rtx
gen_aarch64_uabdl2v8qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	71));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:727 */
rtx
gen_aarch64_sabdl2v16qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:727 */
rtx
gen_aarch64_uabdl2v16qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	71));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:727 */
rtx
gen_aarch64_sabdl2v4hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:727 */
rtx
gen_aarch64_uabdl2v4hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	71));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:727 */
rtx
gen_aarch64_sabdl2v8hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:727 */
rtx
gen_aarch64_uabdl2v8hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	71));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:727 */
rtx
gen_aarch64_sabdl2v4si_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:727 */
rtx
gen_aarch64_uabdl2v4si_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	71));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:737 */
rtx
gen_aarch64_sabalv8qi_4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	49));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:737 */
rtx
gen_aarch64_uabalv8qi_4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	70));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:737 */
rtx
gen_aarch64_sabalv16qi_4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	49));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:737 */
rtx
gen_aarch64_uabalv16qi_4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	70));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:737 */
rtx
gen_aarch64_sabalv4hi_4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	49));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:737 */
rtx
gen_aarch64_uabalv4hi_4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	70));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:737 */
rtx
gen_aarch64_sabalv8hi_4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	49));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:737 */
rtx
gen_aarch64_uabalv8hi_4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	70));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:737 */
rtx
gen_aarch64_sabalv4si_4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	49));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:737 */
rtx
gen_aarch64_uabalv4si_4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	70));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:748 */
rtx
gen_aarch64_sadalpv8qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:748 */
rtx
gen_aarch64_uadalpv8qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	72));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:748 */
rtx
gen_aarch64_sadalpv16qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:748 */
rtx
gen_aarch64_uadalpv16qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	72));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:748 */
rtx
gen_aarch64_sadalpv4hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:748 */
rtx
gen_aarch64_uadalpv4hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	72));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:748 */
rtx
gen_aarch64_sadalpv8hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:748 */
rtx
gen_aarch64_uadalpv8hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	72));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:748 */
rtx
gen_aarch64_sadalpv4si_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:748 */
rtx
gen_aarch64_uadalpv4si_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	72));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:788 */
rtx
gen_abav8qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8QImode,
	gen_rtx_ABS (V8QImode,
	gen_rtx_MINUS (V8QImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:788 */
rtx
gen_abav16qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V16QImode,
	gen_rtx_ABS (V16QImode,
	gen_rtx_MINUS (V16QImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:788 */
rtx
gen_abav4hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HImode,
	gen_rtx_ABS (V4HImode,
	gen_rtx_MINUS (V4HImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:788 */
rtx
gen_abav8hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ABS (V8HImode,
	gen_rtx_MINUS (V8HImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:788 */
rtx
gen_abav2si_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	gen_rtx_ABS (V2SImode,
	gen_rtx_MINUS (V2SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:788 */
rtx
gen_abav4si_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ABS (V4SImode,
	gen_rtx_MINUS (V4SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:799 */
rtx
gen_fabdv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4HFmode,
	gen_rtx_MINUS (V4HFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:799 */
rtx
gen_fabdv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V8HFmode,
	gen_rtx_MINUS (V8HFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:799 */
rtx
gen_fabdv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V2SFmode,
	gen_rtx_MINUS (V2SFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:799 */
rtx
gen_fabdv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4SFmode,
	gen_rtx_MINUS (V4SFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:799 */
rtx
gen_fabdv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V2DFmode,
	gen_rtx_MINUS (V2DFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:799 */
rtx
gen_fabdhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (HFmode,
	gen_rtx_MINUS (HFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:799 */
rtx
gen_fabdsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (SFmode,
	gen_rtx_MINUS (SFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:799 */
rtx
gen_fabddf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (DFmode,
	gen_rtx_MINUS (DFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:811 */
rtx
gen_andv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:811 */
rtx
gen_andv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:811 */
rtx
gen_andv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:811 */
rtx
gen_andv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:811 */
rtx
gen_andv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:811 */
rtx
gen_andv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:811 */
rtx
gen_andv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:832 */
rtx
gen_iorv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:832 */
rtx
gen_iorv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:832 */
rtx
gen_iorv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:832 */
rtx
gen_iorv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:832 */
rtx
gen_iorv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:832 */
rtx
gen_iorv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:832 */
rtx
gen_iorv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:852 */
rtx
gen_xorv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:852 */
rtx
gen_xorv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:852 */
rtx
gen_xorv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:852 */
rtx
gen_xorv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:852 */
rtx
gen_xorv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:852 */
rtx
gen_xorv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:852 */
rtx
gen_xorv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:861 */
rtx
gen_one_cmplv8qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:861 */
rtx
gen_one_cmplv16qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:861 */
rtx
gen_one_cmplv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:861 */
rtx
gen_one_cmplv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:861 */
rtx
gen_one_cmplv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:861 */
rtx
gen_one_cmplv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:861 */
rtx
gen_one_cmplv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:869 */
rtx
gen_aarch64_simd_vec_setv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V8QImode,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:869 */
rtx
gen_aarch64_simd_vec_setv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V16QImode,
	gen_rtx_VEC_DUPLICATE (V16QImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:869 */
rtx
gen_aarch64_simd_vec_setv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V4HImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:869 */
rtx
gen_aarch64_simd_vec_setv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V8HImode,
	gen_rtx_VEC_DUPLICATE (V8HImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:869 */
rtx
gen_aarch64_simd_vec_setv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V2SImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:869 */
rtx
gen_aarch64_simd_vec_setv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4SImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:869 */
rtx
gen_aarch64_simd_vec_setv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2DImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:869 */
rtx
gen_aarch64_simd_vec_setv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V4HFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:869 */
rtx
gen_aarch64_simd_vec_setv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V8HFmode,
	gen_rtx_VEC_DUPLICATE (V8HFmode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:869 */
rtx
gen_aarch64_simd_vec_setv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V2SFmode,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:869 */
rtx
gen_aarch64_simd_vec_setv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V4SFmode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:869 */
rtx
gen_aarch64_simd_vec_setv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V2DFmode,
	gen_rtx_VEC_DUPLICATE (V2DFmode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:938 */
rtx
gen_aarch64_simd_lshrv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:938 */
rtx
gen_aarch64_simd_lshrv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:938 */
rtx
gen_aarch64_simd_lshrv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:938 */
rtx
gen_aarch64_simd_lshrv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:938 */
rtx
gen_aarch64_simd_lshrv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:938 */
rtx
gen_aarch64_simd_lshrv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:938 */
rtx
gen_aarch64_simd_lshrv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:947 */
rtx
gen_aarch64_simd_ashrv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:947 */
rtx
gen_aarch64_simd_ashrv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:947 */
rtx
gen_aarch64_simd_ashrv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:947 */
rtx
gen_aarch64_simd_ashrv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:947 */
rtx
gen_aarch64_simd_ashrv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:947 */
rtx
gen_aarch64_simd_ashrv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:947 */
rtx
gen_aarch64_simd_ashrv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:956 */
rtx
gen_aarch64_simd_imm_shlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:956 */
rtx
gen_aarch64_simd_imm_shlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:956 */
rtx
gen_aarch64_simd_imm_shlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:956 */
rtx
gen_aarch64_simd_imm_shlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:956 */
rtx
gen_aarch64_simd_imm_shlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:956 */
rtx
gen_aarch64_simd_imm_shlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:956 */
rtx
gen_aarch64_simd_imm_shlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:965 */
rtx
gen_aarch64_simd_reg_sshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:965 */
rtx
gen_aarch64_simd_reg_sshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:965 */
rtx
gen_aarch64_simd_reg_sshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:965 */
rtx
gen_aarch64_simd_reg_sshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:965 */
rtx
gen_aarch64_simd_reg_sshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:965 */
rtx
gen_aarch64_simd_reg_sshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:965 */
rtx
gen_aarch64_simd_reg_sshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:974 */
rtx
gen_aarch64_simd_reg_shlv8qi_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	107));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:974 */
rtx
gen_aarch64_simd_reg_shlv16qi_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	107));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:974 */
rtx
gen_aarch64_simd_reg_shlv4hi_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	107));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:974 */
rtx
gen_aarch64_simd_reg_shlv8hi_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	107));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:974 */
rtx
gen_aarch64_simd_reg_shlv2si_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	107));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:974 */
rtx
gen_aarch64_simd_reg_shlv4si_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	107));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:974 */
rtx
gen_aarch64_simd_reg_shlv2di_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	107));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:984 */
rtx
gen_aarch64_simd_reg_shlv8qi_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	106));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:984 */
rtx
gen_aarch64_simd_reg_shlv16qi_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	106));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:984 */
rtx
gen_aarch64_simd_reg_shlv4hi_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	106));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:984 */
rtx
gen_aarch64_simd_reg_shlv8hi_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	106));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:984 */
rtx
gen_aarch64_simd_reg_shlv2si_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	106));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:984 */
rtx
gen_aarch64_simd_reg_shlv4si_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	106));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:984 */
rtx
gen_aarch64_simd_reg_shlv2di_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	106));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1207 */
rtx
gen_vec_shr_v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	204));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1207 */
rtx
gen_vec_shr_v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	204));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1207 */
rtx
gen_vec_shr_v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	204));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1207 */
rtx
gen_vec_shr_v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	204));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1207 */
rtx
gen_vec_shr_v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	204));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1236 */
rtx
gen_aarch64_mlav8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8QImode,
	gen_rtx_MULT (V8QImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1236 */
rtx
gen_aarch64_mlav16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V16QImode,
	gen_rtx_MULT (V16QImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1236 */
rtx
gen_aarch64_mlav4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HImode,
	gen_rtx_MULT (V4HImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1236 */
rtx
gen_aarch64_mlav8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_MULT (V8HImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1236 */
rtx
gen_aarch64_mlav2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	gen_rtx_MULT (V2SImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1236 */
rtx
gen_aarch64_mlav4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_MULT (V4SImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1295 */
rtx
gen_aarch64_mlsv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8QImode,
	operand1,
	gen_rtx_MULT (V8QImode,
	operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1295 */
rtx
gen_aarch64_mlsv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V16QImode,
	operand1,
	gen_rtx_MULT (V16QImode,
	operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1295 */
rtx
gen_aarch64_mlsv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4HImode,
	operand1,
	gen_rtx_MULT (V4HImode,
	operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1295 */
rtx
gen_aarch64_mlsv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_MULT (V8HImode,
	operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1295 */
rtx
gen_aarch64_mlsv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2SImode,
	operand1,
	gen_rtx_MULT (V2SImode,
	operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1295 */
rtx
gen_aarch64_mlsv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_MULT (V4SImode,
	operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_smaxv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_sminv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_umaxv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_uminv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_smaxv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_sminv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_umaxv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_uminv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_smaxv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_sminv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_umaxv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_uminv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_smaxv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_sminv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_umaxv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_uminv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_smaxv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_sminv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_umaxv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_uminv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_smaxv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_sminv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_umaxv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1354 */
rtx
gen_uminv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_umaxpv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	119));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_uminpv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	120));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_smaxpv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	117));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_sminpv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	118));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_umaxpv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	119));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_uminpv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	120));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_smaxpv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	117));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_sminpv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	118));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_umaxpv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	119));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_uminpv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	120));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_smaxpv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	117));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_sminpv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	118));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_umaxpv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	119));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_uminpv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	120));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_smaxpv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	117));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_sminpv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	118));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_umaxpv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	119));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_uminpv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	120));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_smaxpv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	117));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_sminpv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	118));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_umaxpv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	119));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_uminpv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	120));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_smaxpv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	117));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1397 */
rtx
gen_aarch64_sminpv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	118));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smax_nanpv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	111));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smin_nanpv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smaxpv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	110));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_sminpv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	113));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smax_nanpv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	111));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smin_nanpv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smaxpv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	110));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_sminpv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	113));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smax_nanpv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	111));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smin_nanpv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smaxpv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	110));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_sminpv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	113));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smax_nanpv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	111));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smin_nanpv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smaxpv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	110));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_sminpv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	113));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smax_nanpv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	111));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smin_nanpv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_smaxpv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	110));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1408 */
rtx
gen_aarch64_sminpv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	113));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1428 */
rtx
gen_move_lo_quad_internal_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V16QImode,
	operand1,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1428 */
rtx
gen_move_lo_quad_internal_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HImode,
	operand1,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1428 */
rtx
gen_move_lo_quad_internal_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SImode,
	operand1,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1428 */
rtx
gen_move_lo_quad_internal_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	operand1,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1428 */
rtx
gen_move_lo_quad_internal_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	operand1,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1443 */
rtx
gen_move_lo_quad_internal_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DImode,
	operand1,
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1443 */
rtx
gen_move_lo_quad_internal_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DFmode,
	operand1,
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1458 */
rtx
gen_move_lo_quad_internal_be_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1458 */
rtx
gen_move_lo_quad_internal_be_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1458 */
rtx
gen_move_lo_quad_internal_be_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1458 */
rtx
gen_move_lo_quad_internal_be_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1458 */
rtx
gen_move_lo_quad_internal_be_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1473 */
rtx
gen_move_lo_quad_internal_be_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DImode,
	const0_rtx,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1473 */
rtx
gen_move_lo_quad_internal_be_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DFmode,
	const0_rtx,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1506 */
rtx
gen_aarch64_simd_move_hi_quad_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1506 */
rtx
gen_aarch64_simd_move_hi_quad_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1506 */
rtx
gen_aarch64_simd_move_hi_quad_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1506 */
rtx
gen_aarch64_simd_move_hi_quad_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1506 */
rtx
gen_aarch64_simd_move_hi_quad_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1506 */
rtx
gen_aarch64_simd_move_hi_quad_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_VEC_SELECT (V2SFmode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1506 */
rtx
gen_aarch64_simd_move_hi_quad_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1520 */
rtx
gen_aarch64_simd_move_hi_quad_be_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V16QImode,
	operand1,
	gen_rtx_VEC_SELECT (V8QImode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1520 */
rtx
gen_aarch64_simd_move_hi_quad_be_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HImode,
	operand1,
	gen_rtx_VEC_SELECT (V4HImode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1520 */
rtx
gen_aarch64_simd_move_hi_quad_be_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SImode,
	operand1,
	gen_rtx_VEC_SELECT (V2SImode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1520 */
rtx
gen_aarch64_simd_move_hi_quad_be_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DImode,
	operand1,
	gen_rtx_VEC_SELECT (DImode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1520 */
rtx
gen_aarch64_simd_move_hi_quad_be_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	operand1,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1520 */
rtx
gen_aarch64_simd_move_hi_quad_be_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	operand1,
	gen_rtx_VEC_SELECT (V2SFmode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1520 */
rtx
gen_aarch64_simd_move_hi_quad_be_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DFmode,
	operand1,
	gen_rtx_VEC_SELECT (DFmode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1552 */
rtx
gen_aarch64_simd_vec_pack_trunc_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1552 */
rtx
gen_aarch64_simd_vec_pack_trunc_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1552 */
rtx
gen_aarch64_simd_vec_pack_trunc_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1578 */
rtx
gen_vec_pack_trunc_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_TRUNCATE (V8QImode,
	operand1),
	gen_rtx_TRUNCATE (V8QImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1578 */
rtx
gen_vec_pack_trunc_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_TRUNCATE (V4HImode,
	operand1),
	gen_rtx_TRUNCATE (V4HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1578 */
rtx
gen_vec_pack_trunc_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_TRUNCATE (V2SImode,
	operand1),
	gen_rtx_TRUNCATE (V2SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1596 */
rtx
gen_aarch64_simd_vec_unpacks_lo_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1596 */
rtx
gen_aarch64_simd_vec_unpacku_lo_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1596 */
rtx
gen_aarch64_simd_vec_unpacks_lo_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1596 */
rtx
gen_aarch64_simd_vec_unpacku_lo_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1596 */
rtx
gen_aarch64_simd_vec_unpacks_lo_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1596 */
rtx
gen_aarch64_simd_vec_unpacku_lo_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1607 */
rtx
gen_aarch64_simd_vec_unpacks_hi_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1607 */
rtx
gen_aarch64_simd_vec_unpacku_hi_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1607 */
rtx
gen_aarch64_simd_vec_unpacks_hi_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1607 */
rtx
gen_aarch64_simd_vec_unpacku_hi_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1607 */
rtx
gen_aarch64_simd_vec_unpacks_hi_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1607 */
rtx
gen_aarch64_simd_vec_unpacku_hi_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1736 */
rtx
gen_aarch64_simd_vec_smult_lo_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1736 */
rtx
gen_aarch64_simd_vec_umult_lo_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1736 */
rtx
gen_aarch64_simd_vec_smult_lo_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1736 */
rtx
gen_aarch64_simd_vec_umult_lo_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1736 */
rtx
gen_aarch64_simd_vec_smult_lo_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1736 */
rtx
gen_aarch64_simd_vec_umult_lo_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1763 */
rtx
gen_aarch64_simd_vec_smult_hi_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1763 */
rtx
gen_aarch64_simd_vec_umult_hi_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1763 */
rtx
gen_aarch64_simd_vec_smult_hi_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1763 */
rtx
gen_aarch64_simd_vec_umult_hi_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1763 */
rtx
gen_aarch64_simd_vec_smult_hi_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1763 */
rtx
gen_aarch64_simd_vec_umult_hi_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1816 */
rtx
gen_addv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1816 */
rtx
gen_addv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1816 */
rtx
gen_addv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1816 */
rtx
gen_addv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1816 */
rtx
gen_addv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1825 */
rtx
gen_subv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1825 */
rtx
gen_subv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1825 */
rtx
gen_subv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1825 */
rtx
gen_subv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1825 */
rtx
gen_subv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1834 */
rtx
gen_mulv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1834 */
rtx
gen_mulv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1834 */
rtx
gen_mulv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1834 */
rtx
gen_mulv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1834 */
rtx
gen_mulv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1864 */
rtx
gen_negv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1864 */
rtx
gen_negv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1864 */
rtx
gen_negv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1864 */
rtx
gen_negv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1864 */
rtx
gen_negv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1872 */
rtx
gen_absv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1872 */
rtx
gen_absv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V8HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1872 */
rtx
gen_absv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V2SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1872 */
rtx
gen_absv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1872 */
rtx
gen_absv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V2DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1880 */
rtx
gen_fmav4hf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4HFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1880 */
rtx
gen_fmav8hf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V8HFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1880 */
rtx
gen_fmav2sf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1880 */
rtx
gen_fmav4sf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1880 */
rtx
gen_fmav2df4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2DFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1952 */
rtx
gen_fnmav4hf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4HFmode,
	gen_rtx_NEG (V4HFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1952 */
rtx
gen_fnmav8hf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V8HFmode,
	gen_rtx_NEG (V8HFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1952 */
rtx
gen_fnmav2sf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	gen_rtx_NEG (V2SFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1952 */
rtx
gen_fnmav4sf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	gen_rtx_NEG (V4SFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1952 */
rtx
gen_fnmav2df4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2DFmode,
	gen_rtx_NEG (V2DFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_btruncv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	23));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_ceilv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_floorv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_frintnv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_nearbyintv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_rintv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	22));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_roundv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_btruncv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	23));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_ceilv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_floorv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_frintnv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_nearbyintv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_rintv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	22));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_roundv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_btruncv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	23));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_ceilv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_floorv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_frintnv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_nearbyintv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_rintv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	22));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_roundv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_btruncv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	23));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_ceilv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_floorv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_frintnv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_nearbyintv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_rintv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	22));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_roundv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_btruncv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	23));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_ceilv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_floorv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_frintnv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_nearbyintv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_rintv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	22));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2031 */
rtx
gen_roundv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lbtruncv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lceilv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfloorv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lroundv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfrintnv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lbtruncuv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lceiluv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lflooruv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lrounduv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfrintnuv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lbtruncv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lceilv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfloorv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lroundv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfrintnv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lbtruncuv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lceiluv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lflooruv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lrounduv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfrintnuv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lbtruncv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lceilv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfloorv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lroundv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfrintnv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lbtruncuv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lceiluv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lflooruv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lrounduv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfrintnuv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lbtruncv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lceilv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfloorv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lroundv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfrintnv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lbtruncuv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lceiluv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lflooruv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lrounduv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfrintnuv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lbtruncv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lceilv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfloorv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lroundv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfrintnv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lbtruncuv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lceiluv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lflooruv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lrounduv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2042 */
rtx
gen_lfrintnuv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2053 */
rtx
gen_lbtrunchfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2053 */
rtx
gen_lceilhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2053 */
rtx
gen_lfloorhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2053 */
rtx
gen_lroundhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2053 */
rtx
gen_lfrintnhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2053 */
rtx
gen_lbtruncuhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	23)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2053 */
rtx
gen_lceiluhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2053 */
rtx
gen_lflooruhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2053 */
rtx
gen_lrounduhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2053 */
rtx
gen_lfrintnuhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	20)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2062 */
rtx
gen_fix_trunchfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2062 */
rtx
gen_fixuns_trunchfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2070 */
rtx
gen_floathihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2070 */
rtx
gen_floatunshihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_floatv4hiv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (V4HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_floatunsv4hiv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (V4HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_floatv8hiv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (V8HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_floatunsv8hiv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (V8HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_floatv2siv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (V2SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_floatunsv2siv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (V2SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_floatv4siv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (V4SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_floatunsv4siv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (V4SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_floatv2div2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (V2DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_floatunsv2div2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (V2DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2136 */
rtx
gen_aarch64_simd_vec_unpacks_lo_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2136 */
rtx
gen_aarch64_simd_vec_unpacks_lo_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (V2DFmode,
	gen_rtx_VEC_SELECT (V2SFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_fcvtzsv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	11));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_fcvtzuv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_fcvtzsv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	11));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_fcvtzuv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_fcvtzsv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	11));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_fcvtzuv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_fcvtzsv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	11));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_fcvtzuv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_fcvtzsv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	11));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_fcvtzuv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2160 */
rtx
gen_scvtfv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2160 */
rtx
gen_ucvtfv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2160 */
rtx
gen_scvtfv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2160 */
rtx
gen_ucvtfv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2160 */
rtx
gen_scvtfv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2160 */
rtx
gen_ucvtfv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2160 */
rtx
gen_scvtfv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2160 */
rtx
gen_ucvtfv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2160 */
rtx
gen_scvtfv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2160 */
rtx
gen_ucvtfv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2192 */
rtx
gen_aarch64_simd_vec_unpacks_hi_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2192 */
rtx
gen_aarch64_simd_vec_unpacks_hi_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (V2DFmode,
	gen_rtx_VEC_SELECT (V2SFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2214 */
rtx
gen_aarch64_float_extend_lo_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (V2DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2214 */
rtx
gen_aarch64_float_extend_lo_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2225 */
rtx
gen_aarch64_float_truncate_lo_v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_TRUNCATE (V2SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2225 */
rtx
gen_aarch64_float_truncate_lo_v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_TRUNCATE (V4HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2234 */
rtx
gen_aarch64_float_truncate_hi_v4sf_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	operand1,
	gen_rtx_FLOAT_TRUNCATE (V2SFmode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2234 */
rtx
gen_aarch64_float_truncate_hi_v8hf_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	operand1,
	gen_rtx_FLOAT_TRUNCATE (V4HFmode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2245 */
rtx
gen_aarch64_float_truncate_hi_v4sf_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_FLOAT_TRUNCATE (V2SFmode,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2245 */
rtx
gen_aarch64_float_truncate_hi_v8hf_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_FLOAT_TRUNCATE (V4HFmode,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2327 */
rtx
gen_smaxv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2327 */
rtx
gen_sminv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2327 */
rtx
gen_smaxv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V8HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2327 */
rtx
gen_sminv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V8HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2327 */
rtx
gen_smaxv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2327 */
rtx
gen_sminv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2327 */
rtx
gen_smaxv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V4SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2327 */
rtx
gen_sminv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V4SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2327 */
rtx
gen_smaxv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V2DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2327 */
rtx
gen_sminv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V2DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_smax_nanv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	109));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_smin_nanv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_fmaxv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	207));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_fminv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	208));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_smax_nanv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	109));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_smin_nanv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_fmaxv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	207));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_fminv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	208));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_smax_nanv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	109));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_smin_nanv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_fmaxv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	207));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_fminv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	208));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_smax_nanv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	109));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_smin_nanv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_fmaxv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	207));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_fminv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	208));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_smax_nanv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	109));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_smin_nanv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_fmaxv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	207));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2339 */
rtx
gen_fminv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	208));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2365 */
rtx
gen_aarch64_faddpv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2365 */
rtx
gen_aarch64_faddpv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2365 */
rtx
gen_aarch64_faddpv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2365 */
rtx
gen_aarch64_faddpv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2365 */
rtx
gen_aarch64_faddpv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2375 */
rtx
gen_aarch64_reduc_plus_internalv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	116));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2375 */
rtx
gen_aarch64_reduc_plus_internalv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	116));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2375 */
rtx
gen_aarch64_reduc_plus_internalv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	116));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2375 */
rtx
gen_aarch64_reduc_plus_internalv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	116));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2375 */
rtx
gen_aarch64_reduc_plus_internalv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	116));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2375 */
rtx
gen_aarch64_reduc_plus_internalv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	116));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2384 */
rtx
gen_aarch64_reduc_plus_internalv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	116));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2393 */
rtx
gen_reduc_plus_scal_v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	115));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2393 */
rtx
gen_reduc_plus_scal_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	115));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2416 */
rtx
gen_clrsbv8qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2416 */
rtx
gen_clrsbv16qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2416 */
rtx
gen_clrsbv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2416 */
rtx
gen_clrsbv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2416 */
rtx
gen_clrsbv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2416 */
rtx
gen_clrsbv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2424 */
rtx
gen_clzv8qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2424 */
rtx
gen_clzv16qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2424 */
rtx
gen_clzv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2424 */
rtx
gen_clzv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2424 */
rtx
gen_clzv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2424 */
rtx
gen_clzv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2432 */
rtx
gen_popcountv8qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2432 */
rtx
gen_popcountv16qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_umax_internalv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	119));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_umin_internalv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	120));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_smax_internalv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	117));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_smin_internalv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	118));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_umax_internalv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	119));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_umin_internalv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	120));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_smax_internalv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	117));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_smin_internalv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	118));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_umax_internalv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	119));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_umin_internalv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	120));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_smax_internalv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	117));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_smin_internalv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	118));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_umax_internalv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	119));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_umin_internalv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	120));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_smax_internalv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	117));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_smin_internalv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	118));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_umax_internalv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	119));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_umin_internalv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	120));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_smax_internalv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	117));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2475 */
rtx
gen_aarch64_reduc_smin_internalv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	118));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2484 */
rtx
gen_aarch64_reduc_umax_internalv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	119));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2484 */
rtx
gen_aarch64_reduc_umin_internalv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	120));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2484 */
rtx
gen_aarch64_reduc_smax_internalv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	117));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2484 */
rtx
gen_aarch64_reduc_smin_internalv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	118));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smax_nan_internalv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	111));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smin_nan_internalv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smax_internalv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	110));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smin_internalv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	113));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smax_nan_internalv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	111));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smin_nan_internalv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smax_internalv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	110));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smin_internalv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	113));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smax_nan_internalv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	111));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smin_nan_internalv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smax_internalv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	110));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smin_internalv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	113));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smax_nan_internalv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	111));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smin_nan_internalv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smax_internalv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	110));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smin_internalv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	113));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smax_nan_internalv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	111));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smin_nan_internalv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	114));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smax_internalv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	110));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2493 */
rtx
gen_aarch64_reduc_smin_internalv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	113));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2522 */
rtx
gen_aarch64_simd_bslv8qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V8QImode,
	gen_rtx_AND (V8QImode,
	gen_rtx_XOR (V8QImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2522 */
rtx
gen_aarch64_simd_bslv16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V16QImode,
	gen_rtx_AND (V16QImode,
	gen_rtx_XOR (V16QImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2522 */
rtx
gen_aarch64_simd_bslv4hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V4HImode,
	gen_rtx_AND (V4HImode,
	gen_rtx_XOR (V4HImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2522 */
rtx
gen_aarch64_simd_bslv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V8HImode,
	gen_rtx_AND (V8HImode,
	gen_rtx_XOR (V8HImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2522 */
rtx
gen_aarch64_simd_bslv2si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V2SImode,
	gen_rtx_AND (V2SImode,
	gen_rtx_XOR (V2SImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2522 */
rtx
gen_aarch64_simd_bslv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V4SImode,
	gen_rtx_AND (V4SImode,
	gen_rtx_XOR (V4SImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2522 */
rtx
gen_aarch64_simd_bslv2di_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V2DImode,
	gen_rtx_AND (V2DImode,
	gen_rtx_XOR (V2DImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2573 */
rtx
gen_aarch64_simd_bsldi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	gen_rtx_AND (DImode,
	gen_rtx_XOR (DImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2615 */
rtx
gen_aarch64_simd_bsldi_alt (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	gen_rtx_AND (DImode,
	gen_rtx_XOR (DImode,
	operand3,
	operand2),
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3134 */
rtx
gen_aarch64_get_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3134 */
rtx
gen_aarch64_get_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3134 */
rtx
gen_aarch64_get_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3134 */
rtx
gen_aarch64_get_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3134 */
rtx
gen_aarch64_get_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3134 */
rtx
gen_aarch64_get_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3134 */
rtx
gen_aarch64_get_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3134 */
rtx
gen_aarch64_get_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3134 */
rtx
gen_aarch64_get_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3134 */
rtx
gen_aarch64_get_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3134 */
rtx
gen_aarch64_get_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3134 */
rtx
gen_aarch64_get_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_load_pair_lanesv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_load_pair_lanesv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_load_pair_lanesv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_load_pair_lanesv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_load_pair_lanesv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_load_pair_lanesdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_load_pair_lanesdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3171 */
rtx
gen_store_pair_lanesv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3171 */
rtx
gen_store_pair_lanesv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3171 */
rtx
gen_store_pair_lanesv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3171 */
rtx
gen_store_pair_lanesv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3171 */
rtx
gen_store_pair_lanesv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3171 */
rtx
gen_store_pair_lanesdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3171 */
rtx
gen_store_pair_lanesdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_saddlv16qi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_ssublv16qi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_uaddlv16qi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_usublv16qi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_saddlv8hi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_ssublv8hi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_uaddlv8hi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_usublv8hi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_saddlv4si_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_ssublv4si_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_uaddlv4si_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_usublv4si_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3254 */
rtx
gen_aarch64_saddlv16qi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3254 */
rtx
gen_aarch64_ssublv16qi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3254 */
rtx
gen_aarch64_uaddlv16qi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3254 */
rtx
gen_aarch64_usublv16qi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3254 */
rtx
gen_aarch64_saddlv8hi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3254 */
rtx
gen_aarch64_ssublv8hi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3254 */
rtx
gen_aarch64_uaddlv8hi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3254 */
rtx
gen_aarch64_usublv8hi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3254 */
rtx
gen_aarch64_saddlv4si_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3254 */
rtx
gen_aarch64_ssublv4si_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3254 */
rtx
gen_aarch64_uaddlv4si_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3254 */
rtx
gen_aarch64_usublv4si_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3316 */
rtx
gen_aarch64_saddlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3316 */
rtx
gen_aarch64_ssublv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3316 */
rtx
gen_aarch64_uaddlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand1),
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3316 */
rtx
gen_aarch64_usublv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand1),
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3316 */
rtx
gen_aarch64_saddlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3316 */
rtx
gen_aarch64_ssublv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3316 */
rtx
gen_aarch64_uaddlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand1),
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3316 */
rtx
gen_aarch64_usublv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand1),
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3316 */
rtx
gen_aarch64_saddlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3316 */
rtx
gen_aarch64_ssublv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3316 */
rtx
gen_aarch64_uaddlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand1),
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3316 */
rtx
gen_aarch64_usublv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand1),
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3385 */
rtx
gen_aarch64_ssubwv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3385 */
rtx
gen_aarch64_usubwv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3385 */
rtx
gen_aarch64_ssubwv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3385 */
rtx
gen_aarch64_usubwv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3385 */
rtx
gen_aarch64_ssubwv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3385 */
rtx
gen_aarch64_usubwv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3395 */
rtx
gen_aarch64_ssubwv16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3395 */
rtx
gen_aarch64_usubwv16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3395 */
rtx
gen_aarch64_ssubwv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3395 */
rtx
gen_aarch64_usubwv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3395 */
rtx
gen_aarch64_ssubwv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3395 */
rtx
gen_aarch64_usubwv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3407 */
rtx
gen_aarch64_ssubw2v16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3407 */
rtx
gen_aarch64_usubw2v16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3407 */
rtx
gen_aarch64_ssubw2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3407 */
rtx
gen_aarch64_usubw2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3407 */
rtx
gen_aarch64_ssubw2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3407 */
rtx
gen_aarch64_usubw2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3419 */
rtx
gen_aarch64_saddwv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3419 */
rtx
gen_aarch64_uaddwv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3419 */
rtx
gen_aarch64_saddwv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3419 */
rtx
gen_aarch64_uaddwv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3419 */
rtx
gen_aarch64_saddwv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3419 */
rtx
gen_aarch64_uaddwv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3429 */
rtx
gen_aarch64_saddwv16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3429 */
rtx
gen_aarch64_uaddwv16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3429 */
rtx
gen_aarch64_saddwv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3429 */
rtx
gen_aarch64_uaddwv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3429 */
rtx
gen_aarch64_saddwv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3429 */
rtx
gen_aarch64_uaddwv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3442 */
rtx
gen_aarch64_saddw2v16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3442 */
rtx
gen_aarch64_uaddw2v16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3442 */
rtx
gen_aarch64_saddw2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3442 */
rtx
gen_aarch64_uaddw2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3442 */
rtx
gen_aarch64_saddw2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3442 */
rtx
gen_aarch64_uaddw2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_shaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_uhaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_srhaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_urhaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_shsubv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_uhsubv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_srhsubv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_urhsubv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_shaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_uhaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_srhaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_urhaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_shsubv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_uhsubv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_srhsubv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_urhsubv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_shaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_uhaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_srhaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_urhaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_shsubv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_uhsubv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_srhsubv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_urhsubv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_shaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_uhaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_srhaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_urhaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_shsubv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_uhsubv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_srhsubv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_urhsubv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_shaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_uhaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_srhaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_urhaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_shsubv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_uhsubv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_srhsubv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_urhsubv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_shaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_uhaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_srhaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_urhaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_shsubv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_uhsubv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_srhsubv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3522 */
rtx
gen_aarch64_urhsubv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3534 */
rtx
gen_aarch64_addhnv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	129));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3534 */
rtx
gen_aarch64_raddhnv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	130));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3534 */
rtx
gen_aarch64_subhnv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	131));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3534 */
rtx
gen_aarch64_rsubhnv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	132));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3534 */
rtx
gen_aarch64_addhnv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	129));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3534 */
rtx
gen_aarch64_raddhnv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	130));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3534 */
rtx
gen_aarch64_subhnv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	131));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3534 */
rtx
gen_aarch64_rsubhnv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	132));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3534 */
rtx
gen_aarch64_addhnv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	129));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3534 */
rtx
gen_aarch64_raddhnv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	130));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3534 */
rtx
gen_aarch64_subhnv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	131));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3534 */
rtx
gen_aarch64_rsubhnv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	132));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_addhn2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	133));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_raddhn2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	134));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_subhn2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	135));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_rsubhn2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	136));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_addhn2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	133));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_raddhn2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	134));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_subhn2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	135));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_rsubhn2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	136));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_addhn2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	133));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_raddhn2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	134));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_subhn2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	135));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_rsubhn2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	136));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3557 */
rtx
gen_aarch64_pmulv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3557 */
rtx
gen_aarch64_pmulv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3569 */
rtx
gen_aarch64_fmulxv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3569 */
rtx
gen_aarch64_fmulxv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3569 */
rtx
gen_aarch64_fmulxv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3569 */
rtx
gen_aarch64_fmulxv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3569 */
rtx
gen_aarch64_fmulxv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3569 */
rtx
gen_aarch64_fmulxhf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3569 */
rtx
gen_aarch64_fmulxsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3569 */
rtx
gen_aarch64_fmulxdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqsubv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqsubv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqsubv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqsubv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqsubv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqsubv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqsubv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqsubv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqsubv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqsubv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqsubv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqsubv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqaddv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqaddv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqsubv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqsubv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqaddqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqaddqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqsubqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqsubqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqaddhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqaddhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqsubhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqsubhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqaddsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqaddsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqsubsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqsubsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqadddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqadddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_sqsubdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3653 */
rtx
gen_aarch64_uqsubdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_suqaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_usqaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_suqaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_usqaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_suqaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_usqaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_suqaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_usqaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_suqaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_usqaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_suqaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_usqaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_suqaddv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_usqaddv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_suqaddqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_usqaddqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_suqaddhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_usqaddhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_suqaddsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_usqaddsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_suqadddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3664 */
rtx
gen_aarch64_usqadddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3676 */
rtx
gen_aarch64_sqmovunv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	143));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3676 */
rtx
gen_aarch64_sqmovunv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	143));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3676 */
rtx
gen_aarch64_sqmovunv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	143));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3676 */
rtx
gen_aarch64_sqmovunhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand1),
	143));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3676 */
rtx
gen_aarch64_sqmovunsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (1,
		operand1),
	143));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3676 */
rtx
gen_aarch64_sqmovundi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	143));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3687 */
rtx
gen_aarch64_sqmovnv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	144));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3687 */
rtx
gen_aarch64_uqmovnv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	145));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3687 */
rtx
gen_aarch64_sqmovnv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	144));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3687 */
rtx
gen_aarch64_uqmovnv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	145));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3687 */
rtx
gen_aarch64_sqmovnv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	144));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3687 */
rtx
gen_aarch64_uqmovnv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	145));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3687 */
rtx
gen_aarch64_sqmovnhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand1),
	144));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3687 */
rtx
gen_aarch64_uqmovnhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand1),
	145));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3687 */
rtx
gen_aarch64_sqmovnsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (1,
		operand1),
	144));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3687 */
rtx
gen_aarch64_uqmovnsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (1,
		operand1),
	145));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3687 */
rtx
gen_aarch64_sqmovndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	144));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3687 */
rtx
gen_aarch64_uqmovndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	145));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqnegv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqabsv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqnegv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqabsv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqnegv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqabsv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqnegv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqabsv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqnegv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqabsv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqnegv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqabsv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqnegv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqabsv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqnegqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqabsqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqneghi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqabshi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqnegsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqabssi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqnegdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3698 */
rtx
gen_aarch64_sqabsdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3709 */
rtx
gen_aarch64_sqdmulhv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3709 */
rtx
gen_aarch64_sqrdmulhv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3709 */
rtx
gen_aarch64_sqdmulhv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3709 */
rtx
gen_aarch64_sqrdmulhv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3709 */
rtx
gen_aarch64_sqdmulhv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3709 */
rtx
gen_aarch64_sqrdmulhv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3709 */
rtx
gen_aarch64_sqdmulhv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3709 */
rtx
gen_aarch64_sqrdmulhv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3709 */
rtx
gen_aarch64_sqdmulhhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3709 */
rtx
gen_aarch64_sqrdmulhhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3709 */
rtx
gen_aarch64_sqdmulhsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3709 */
rtx
gen_aarch64_sqrdmulhsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3722 */
rtx
gen_aarch64_sqdmulh_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3722 */
rtx
gen_aarch64_sqrdmulh_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3722 */
rtx
gen_aarch64_sqdmulh_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3722 */
rtx
gen_aarch64_sqrdmulh_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3722 */
rtx
gen_aarch64_sqdmulh_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3722 */
rtx
gen_aarch64_sqrdmulh_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3722 */
rtx
gen_aarch64_sqdmulh_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3722 */
rtx
gen_aarch64_sqrdmulh_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3737 */
rtx
gen_aarch64_sqdmulh_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3737 */
rtx
gen_aarch64_sqrdmulh_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3737 */
rtx
gen_aarch64_sqdmulh_laneqv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3737 */
rtx
gen_aarch64_sqrdmulh_laneqv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3737 */
rtx
gen_aarch64_sqdmulh_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3737 */
rtx
gen_aarch64_sqrdmulh_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3737 */
rtx
gen_aarch64_sqdmulh_laneqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3737 */
rtx
gen_aarch64_sqrdmulh_laneqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3752 */
rtx
gen_aarch64_sqdmulh_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3752 */
rtx
gen_aarch64_sqrdmulh_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3752 */
rtx
gen_aarch64_sqdmulh_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3752 */
rtx
gen_aarch64_sqrdmulh_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3767 */
rtx
gen_aarch64_sqdmulh_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3767 */
rtx
gen_aarch64_sqrdmulh_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3767 */
rtx
gen_aarch64_sqdmulh_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	137));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3767 */
rtx
gen_aarch64_sqrdmulh_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	138));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3784 */
rtx
gen_aarch64_sqrdmlahv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3784 */
rtx
gen_aarch64_sqrdmlshv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3784 */
rtx
gen_aarch64_sqrdmlahv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3784 */
rtx
gen_aarch64_sqrdmlshv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3784 */
rtx
gen_aarch64_sqrdmlahv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3784 */
rtx
gen_aarch64_sqrdmlshv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3784 */
rtx
gen_aarch64_sqrdmlahv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3784 */
rtx
gen_aarch64_sqrdmlshv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3784 */
rtx
gen_aarch64_sqrdmlahhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3784 */
rtx
gen_aarch64_sqrdmlshhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3784 */
rtx
gen_aarch64_sqrdmlahsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3784 */
rtx
gen_aarch64_sqrdmlshsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3798 */
rtx
gen_aarch64_sqrdmlah_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3798 */
rtx
gen_aarch64_sqrdmlsh_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3798 */
rtx
gen_aarch64_sqrdmlah_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3798 */
rtx
gen_aarch64_sqrdmlsh_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3798 */
rtx
gen_aarch64_sqrdmlah_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3798 */
rtx
gen_aarch64_sqrdmlsh_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3798 */
rtx
gen_aarch64_sqrdmlah_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3798 */
rtx
gen_aarch64_sqrdmlsh_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3816 */
rtx
gen_aarch64_sqrdmlah_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3816 */
rtx
gen_aarch64_sqrdmlsh_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3816 */
rtx
gen_aarch64_sqrdmlah_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3816 */
rtx
gen_aarch64_sqrdmlsh_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3836 */
rtx
gen_aarch64_sqrdmlah_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3836 */
rtx
gen_aarch64_sqrdmlsh_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3836 */
rtx
gen_aarch64_sqrdmlah_laneqv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3836 */
rtx
gen_aarch64_sqrdmlsh_laneqv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3836 */
rtx
gen_aarch64_sqrdmlah_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3836 */
rtx
gen_aarch64_sqrdmlsh_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3836 */
rtx
gen_aarch64_sqrdmlah_laneqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3836 */
rtx
gen_aarch64_sqrdmlsh_laneqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3854 */
rtx
gen_aarch64_sqrdmlah_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3854 */
rtx
gen_aarch64_sqrdmlsh_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3854 */
rtx
gen_aarch64_sqrdmlah_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	205));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3854 */
rtx
gen_aarch64_sqrdmlsh_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	206));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3874 */
rtx
gen_aarch64_sqdmlalv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3874 */
rtx
gen_aarch64_sqdmlslv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3874 */
rtx
gen_aarch64_sqdmlalv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3874 */
rtx
gen_aarch64_sqdmlslv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3874 */
rtx
gen_aarch64_sqdmlalhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (SImode,
	operand1,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (SImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3874 */
rtx
gen_aarch64_sqdmlslhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (SImode,
	operand1,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (SImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3874 */
rtx
gen_aarch64_sqdmlalsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (DImode,
	operand1,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (DImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3874 */
rtx
gen_aarch64_sqdmlslsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (DImode,
	operand1,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (DImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3892 */
rtx
gen_aarch64_sqdmlal_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3892 */
rtx
gen_aarch64_sqdmlsl_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3892 */
rtx
gen_aarch64_sqdmlal_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3892 */
rtx
gen_aarch64_sqdmlsl_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3916 */
rtx
gen_aarch64_sqdmlal_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3916 */
rtx
gen_aarch64_sqdmlsl_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3916 */
rtx
gen_aarch64_sqdmlal_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3916 */
rtx
gen_aarch64_sqdmlsl_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3940 */
rtx
gen_aarch64_sqdmlal_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (SImode,
	operand1,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (SImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3940 */
rtx
gen_aarch64_sqdmlsl_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (SImode,
	operand1,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (SImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3940 */
rtx
gen_aarch64_sqdmlal_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (DImode,
	operand1,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3940 */
rtx
gen_aarch64_sqdmlsl_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (DImode,
	operand1,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3963 */
rtx
gen_aarch64_sqdmlal_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (SImode,
	operand1,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (SImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3963 */
rtx
gen_aarch64_sqdmlsl_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (SImode,
	operand1,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (SImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3963 */
rtx
gen_aarch64_sqdmlal_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (DImode,
	operand1,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3963 */
rtx
gen_aarch64_sqdmlsl_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (DImode,
	operand1,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3988 */
rtx
gen_aarch64_sqdmlal_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3988 */
rtx
gen_aarch64_sqdmlsl_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3988 */
rtx
gen_aarch64_sqdmlal_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3988 */
rtx
gen_aarch64_sqdmlsl_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4007 */
rtx
gen_aarch64_sqdmlal2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand3,
	operand4))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4007 */
rtx
gen_aarch64_sqdmlsl2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand3,
	operand4))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4007 */
rtx
gen_aarch64_sqdmlal2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand3,
	operand4))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4007 */
rtx
gen_aarch64_sqdmlsl2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand3,
	operand4))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4055 */
rtx
gen_aarch64_sqdmlal2_lanev8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4055 */
rtx
gen_aarch64_sqdmlsl2_lanev8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4055 */
rtx
gen_aarch64_sqdmlal2_lanev4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4055 */
rtx
gen_aarch64_sqdmlsl2_lanev4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4081 */
rtx
gen_aarch64_sqdmlal2_laneqv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4081 */
rtx
gen_aarch64_sqdmlsl2_laneqv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4081 */
rtx
gen_aarch64_sqdmlal2_laneqv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4081 */
rtx
gen_aarch64_sqdmlsl2_laneqv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4167 */
rtx
gen_aarch64_sqdmlal2_nv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4167 */
rtx
gen_aarch64_sqdmlsl2_nv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4167 */
rtx
gen_aarch64_sqdmlal2_nv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4167 */
rtx
gen_aarch64_sqdmlsl2_nv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4216 */
rtx
gen_aarch64_sqdmullv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2)),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4216 */
rtx
gen_aarch64_sqdmullv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2)),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4216 */
rtx
gen_aarch64_sqdmullhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (SImode,
	operand2)),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4216 */
rtx
gen_aarch64_sqdmullsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4232 */
rtx
gen_aarch64_sqdmull_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4232 */
rtx
gen_aarch64_sqdmull_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4253 */
rtx
gen_aarch64_sqdmull_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4253 */
rtx
gen_aarch64_sqdmull_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4274 */
rtx
gen_aarch64_sqdmull_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (SImode,
	gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4274 */
rtx
gen_aarch64_sqdmull_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4294 */
rtx
gen_aarch64_sqdmull_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (SImode,
	gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4294 */
rtx
gen_aarch64_sqdmull_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4316 */
rtx
gen_aarch64_sqdmull_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand2))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4316 */
rtx
gen_aarch64_sqdmull_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand2))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4336 */
rtx
gen_aarch64_sqdmull2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4336 */
rtx
gen_aarch64_sqdmull2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4369 */
rtx
gen_aarch64_sqdmull2_lanev8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand4)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4369 */
rtx
gen_aarch64_sqdmull2_lanev4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand4)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4392 */
rtx
gen_aarch64_sqdmull2_laneqv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand4)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4392 */
rtx
gen_aarch64_sqdmull2_laneqv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand4)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4445 */
rtx
gen_aarch64_sqdmull2_nv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand2))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4445 */
rtx
gen_aarch64_sqdmull2_nv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand2))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_sshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	161));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_ushlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	162));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_srshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	163));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_urshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	164));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_sshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	161));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_ushlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	162));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_srshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	163));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_urshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	164));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_sshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	161));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_ushlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	162));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_srshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	163));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_urshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	164));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_sshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	161));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_ushlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	162));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_srshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	163));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_urshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	164));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_sshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	161));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_ushlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	162));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_srshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	163));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_urshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	164));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_sshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	161));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_ushlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	162));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_srshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	163));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_urshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	164));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_sshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	161));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_ushlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	162));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_srshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	163));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_urshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	164));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_sshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	161));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_ushldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	162));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_srshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	163));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4477 */
rtx
gen_aarch64_urshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	164));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqrshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqrshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqrshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqrshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqrshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqrshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqrshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqrshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqrshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqrshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqrshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqrshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqrshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqrshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqshlqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqshlqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqrshlqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqrshlqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqshlhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqshlhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqrshlhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqrshlhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqshlsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqshlsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqrshlsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqrshlsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_sqrshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4491 */
rtx
gen_aarch64_uqrshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4504 */
rtx
gen_aarch64_sshll_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	171));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4504 */
rtx
gen_aarch64_ushll_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	172));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4504 */
rtx
gen_aarch64_sshll_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	171));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4504 */
rtx
gen_aarch64_ushll_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	172));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4504 */
rtx
gen_aarch64_sshll_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	171));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4504 */
rtx
gen_aarch64_ushll_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	172));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4522 */
rtx
gen_aarch64_sshll2_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	171));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4522 */
rtx
gen_aarch64_ushll2_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	172));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4522 */
rtx
gen_aarch64_sshll2_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	171));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4522 */
rtx
gen_aarch64_ushll2_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	172));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4522 */
rtx
gen_aarch64_sshll2_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	171));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4522 */
rtx
gen_aarch64_ushll2_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	172));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_srshr_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	150));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_urshr_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	151));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_srshr_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	150));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_urshr_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	151));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_srshr_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	150));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_urshr_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	151));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_srshr_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	150));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_urshr_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	151));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_srshr_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	150));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_urshr_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	151));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_srshr_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	150));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_urshr_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	151));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_srshr_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	150));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_urshr_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	151));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_srshr_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	150));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4539 */
rtx
gen_aarch64_urshr_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	151));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ssra_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	146));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_usra_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	147));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_srsra_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	148));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ursra_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	149));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ssra_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	146));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_usra_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	147));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_srsra_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	148));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ursra_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	149));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ssra_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	146));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_usra_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	147));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_srsra_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	148));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ursra_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	149));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ssra_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	146));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_usra_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	147));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_srsra_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	148));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ursra_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	149));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ssra_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	146));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_usra_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	147));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_srsra_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	148));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ursra_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	149));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ssra_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	146));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_usra_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	147));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_srsra_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	148));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ursra_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	149));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ssra_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	146));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_usra_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	147));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_srsra_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	148));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ursra_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	149));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ssra_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	146));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_usra_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	147));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_srsra_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	148));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4552 */
rtx
gen_aarch64_ursra_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	149));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssli_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usli_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssri_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	169));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usri_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	170));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssli_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usli_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssri_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	169));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usri_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	170));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssli_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usli_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssri_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	169));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usri_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	170));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssli_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usli_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssri_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	169));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usri_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	170));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssli_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usli_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssri_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	169));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usri_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	170));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssli_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usli_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssri_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	169));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usri_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	170));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssli_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usli_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssri_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	169));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usri_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	170));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssli_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usli_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_ssri_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	169));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4566 */
rtx
gen_aarch64_usri_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	170));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshlu_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	152));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshl_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_uqshl_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshlu_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	152));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshl_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_uqshl_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshlu_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	152));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshl_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_uqshl_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshlu_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	152));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshl_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_uqshl_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshlu_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	152));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshl_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_uqshl_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshlu_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	152));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshl_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_uqshl_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshlu_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	152));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshl_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_uqshl_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshlu_nqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	152));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshl_nqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_uqshl_nqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshlu_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	152));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshl_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_uqshl_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshlu_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	152));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshl_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_uqshl_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshlu_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	152));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_sqshl_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	153));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4580 */
rtx
gen_aarch64_uqshl_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	154));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqshrun_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	155));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqrshrun_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	156));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqshrn_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	157));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_uqshrn_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	158));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqrshrn_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	159));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_uqrshrn_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	160));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqshrun_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	155));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqrshrun_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	156));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqshrn_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	157));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_uqshrn_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	158));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqrshrn_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	159));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_uqrshrn_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	160));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqshrun_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	155));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqrshrun_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	156));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqshrn_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	157));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_uqshrn_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	158));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqrshrn_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	159));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_uqrshrn_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	160));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqshrun_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	155));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqrshrun_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	156));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqshrn_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	157));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_uqshrn_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	158));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqrshrn_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	159));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_uqrshrn_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	160));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqshrun_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	155));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqrshrun_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	156));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqshrn_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	157));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_uqshrn_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	158));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqrshrn_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	159));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_uqrshrn_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	160));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqshrun_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	155));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqrshrun_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	156));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqshrn_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	157));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_uqshrn_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	158));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_sqrshrn_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	159));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4594 */
rtx
gen_aarch64_uqrshrn_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	160));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmltv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_LT (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmlev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_LE (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmeqv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_EQ (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_GE (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgtv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_GT (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmltv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_LT (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmlev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_LE (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmeqv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_EQ (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_GE (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgtv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_GT (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmltv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmlev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LE (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmeqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_EQ (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GE (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgtv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmltv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LT (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmlev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LE (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmeqv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_EQ (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GE (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgtv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GT (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmltv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmlev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LE (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmeqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_EQ (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GE (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgtv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmltv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LT (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmlev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LE (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmeqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_EQ (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GE (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgtv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GT (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmltv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LT (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmlev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LE (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmeqv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_EQ (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GE (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4610 */
rtx
gen_aarch64_cmgtv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GT (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4624 */
rtx
gen_aarch64_cmltdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LT (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4624 */
rtx
gen_aarch64_cmledi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LE (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4624 */
rtx
gen_aarch64_cmeqdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_EQ (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4624 */
rtx
gen_aarch64_cmgedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GE (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4624 */
rtx
gen_aarch64_cmgtdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GT (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmltuv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_LTU (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmleuv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_LEU (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgeuv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_GEU (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgtuv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_GTU (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmltuv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_LTU (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmleuv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_LEU (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgeuv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_GEU (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgtuv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_GTU (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmltuv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LTU (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmleuv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LEU (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgeuv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GEU (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgtuv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GTU (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmltuv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LTU (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmleuv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LEU (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgeuv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GEU (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgtuv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GTU (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmltuv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LTU (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmleuv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LEU (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgeuv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GEU (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgtuv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GTU (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmltuv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LTU (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmleuv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LEU (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgeuv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GEU (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgtuv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GTU (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmltuv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LTU (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmleuv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LEU (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgeuv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GEU (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4675 */
rtx
gen_aarch64_cmgtuv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GTU (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4687 */
rtx
gen_aarch64_cmltudi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LTU (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4687 */
rtx
gen_aarch64_cmleudi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LEU (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4687 */
rtx
gen_aarch64_cmgeudi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GEU (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4687 */
rtx
gen_aarch64_cmgtudi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GTU (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4742 */
rtx
gen_aarch64_cmtstv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8QImode,
	gen_rtx_EQ (V8QImode,
	gen_rtx_AND (V8QImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4742 */
rtx
gen_aarch64_cmtstv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V16QImode,
	gen_rtx_EQ (V16QImode,
	gen_rtx_AND (V16QImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4742 */
rtx
gen_aarch64_cmtstv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HImode,
	gen_rtx_EQ (V4HImode,
	gen_rtx_AND (V4HImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4742 */
rtx
gen_aarch64_cmtstv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_EQ (V8HImode,
	gen_rtx_AND (V8HImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4742 */
rtx
gen_aarch64_cmtstv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	gen_rtx_EQ (V2SImode,
	gen_rtx_AND (V2SImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4742 */
rtx
gen_aarch64_cmtstv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_EQ (V4SImode,
	gen_rtx_AND (V4SImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4742 */
rtx
gen_aarch64_cmtstv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_EQ (V2DImode,
	gen_rtx_AND (V2DImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4757 */
rtx
gen_aarch64_cmtstdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_NE (DImode,
	gen_rtx_AND (DImode,
	operand1,
	operand2),
	const0_rtx))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmltv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmlev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LE (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmeqv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_EQ (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GE (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgtv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmltv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LT (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmlev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LE (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmeqv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_EQ (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GE (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgtv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GT (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmltv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmlev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LE (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmeqv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_EQ (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GE (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgtv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmltv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LT (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmlev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LE (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmeqv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_EQ (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GE (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgtv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GT (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmltv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LT (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmlev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LE (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmeqv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_EQ (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GE (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgtv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GT (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmlthf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_LT (HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmlehf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_LE (HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmeqhf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_EQ (HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgehf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_GE (HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgthf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_GT (HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmltsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_LT (SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmlesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_LE (SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmeqsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_EQ (SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_GE (SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgtsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_GT (SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmltdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LT (DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmledf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LE (DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmeqdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_EQ (DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GE (DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4810 */
rtx
gen_aarch64_cmgtdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GT (DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facltv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LT (V4HImode,
	gen_rtx_ABS (V4HFmode,
	operand1),
	gen_rtx_ABS (V4HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_faclev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LE (V4HImode,
	gen_rtx_ABS (V4HFmode,
	operand1),
	gen_rtx_ABS (V4HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GE (V4HImode,
	gen_rtx_ABS (V4HFmode,
	operand1),
	gen_rtx_ABS (V4HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgtv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GT (V4HImode,
	gen_rtx_ABS (V4HFmode,
	operand1),
	gen_rtx_ABS (V4HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facltv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LT (V8HImode,
	gen_rtx_ABS (V8HFmode,
	operand1),
	gen_rtx_ABS (V8HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_faclev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LE (V8HImode,
	gen_rtx_ABS (V8HFmode,
	operand1),
	gen_rtx_ABS (V8HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GE (V8HImode,
	gen_rtx_ABS (V8HFmode,
	operand1),
	gen_rtx_ABS (V8HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgtv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GT (V8HImode,
	gen_rtx_ABS (V8HFmode,
	operand1),
	gen_rtx_ABS (V8HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facltv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LT (V2SImode,
	gen_rtx_ABS (V2SFmode,
	operand1),
	gen_rtx_ABS (V2SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_faclev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LE (V2SImode,
	gen_rtx_ABS (V2SFmode,
	operand1),
	gen_rtx_ABS (V2SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GE (V2SImode,
	gen_rtx_ABS (V2SFmode,
	operand1),
	gen_rtx_ABS (V2SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgtv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GT (V2SImode,
	gen_rtx_ABS (V2SFmode,
	operand1),
	gen_rtx_ABS (V2SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facltv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LT (V4SImode,
	gen_rtx_ABS (V4SFmode,
	operand1),
	gen_rtx_ABS (V4SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_faclev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LE (V4SImode,
	gen_rtx_ABS (V4SFmode,
	operand1),
	gen_rtx_ABS (V4SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GE (V4SImode,
	gen_rtx_ABS (V4SFmode,
	operand1),
	gen_rtx_ABS (V4SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgtv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GT (V4SImode,
	gen_rtx_ABS (V4SFmode,
	operand1),
	gen_rtx_ABS (V4SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facltv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LT (V2DImode,
	gen_rtx_ABS (V2DFmode,
	operand1),
	gen_rtx_ABS (V2DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_faclev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LE (V2DImode,
	gen_rtx_ABS (V2DFmode,
	operand1),
	gen_rtx_ABS (V2DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GE (V2DImode,
	gen_rtx_ABS (V2DFmode,
	operand1),
	gen_rtx_ABS (V2DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgtv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GT (V2DImode,
	gen_rtx_ABS (V2DFmode,
	operand1),
	gen_rtx_ABS (V2DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_faclthf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_LT (HImode,
	gen_rtx_ABS (HFmode,
	operand1),
	gen_rtx_ABS (HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_faclehf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_LE (HImode,
	gen_rtx_ABS (HFmode,
	operand1),
	gen_rtx_ABS (HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgehf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_GE (HImode,
	gen_rtx_ABS (HFmode,
	operand1),
	gen_rtx_ABS (HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgthf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_GT (HImode,
	gen_rtx_ABS (HFmode,
	operand1),
	gen_rtx_ABS (HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facltsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_LT (SImode,
	gen_rtx_ABS (SFmode,
	operand1),
	gen_rtx_ABS (SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_faclesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_LE (SImode,
	gen_rtx_ABS (SFmode,
	operand1),
	gen_rtx_ABS (SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_GE (SImode,
	gen_rtx_ABS (SFmode,
	operand1),
	gen_rtx_ABS (SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgtsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_GT (SImode,
	gen_rtx_ABS (SFmode,
	operand1),
	gen_rtx_ABS (SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facltdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LT (DImode,
	gen_rtx_ABS (DFmode,
	operand1),
	gen_rtx_ABS (DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facledf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LE (DImode,
	gen_rtx_ABS (DFmode,
	operand1),
	gen_rtx_ABS (DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GE (DImode,
	gen_rtx_ABS (DFmode,
	operand1),
	gen_rtx_ABS (DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4828 */
rtx
gen_aarch64_facgtdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GT (DImode,
	gen_rtx_ABS (DFmode,
	operand1),
	gen_rtx_ABS (DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4844 */
rtx
gen_aarch64_addpv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	173));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4844 */
rtx
gen_aarch64_addpv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	173));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4844 */
rtx
gen_aarch64_addpv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	173));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_addpdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	173));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4886 */
rtx
gen_aarch64_simd_ld2v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4886 */
rtx
gen_aarch64_simd_ld2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4886 */
rtx
gen_aarch64_simd_ld2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4886 */
rtx
gen_aarch64_simd_ld2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4886 */
rtx
gen_aarch64_simd_ld2v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4886 */
rtx
gen_aarch64_simd_ld2v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4886 */
rtx
gen_aarch64_simd_ld2v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4896 */
rtx
gen_aarch64_simd_ld2rdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	32));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_vec_load_lanesoi_lanedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	39));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4940 */
rtx
gen_aarch64_simd_st2v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4940 */
rtx
gen_aarch64_simd_st2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4940 */
rtx
gen_aarch64_simd_st2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4940 */
rtx
gen_aarch64_simd_st2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4940 */
rtx
gen_aarch64_simd_st2v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4940 */
rtx
gen_aarch64_simd_st2v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4940 */
rtx
gen_aarch64_simd_st2v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4951 */
rtx
gen_aarch64_vec_store_lanesoi_lanedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	61));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4984 */
rtx
gen_aarch64_simd_ld3v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4984 */
rtx
gen_aarch64_simd_ld3v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4984 */
rtx
gen_aarch64_simd_ld3v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4984 */
rtx
gen_aarch64_simd_ld3v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4984 */
rtx
gen_aarch64_simd_ld3v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4984 */
rtx
gen_aarch64_simd_ld3v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4984 */
rtx
gen_aarch64_simd_ld3v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4994 */
rtx
gen_aarch64_simd_ld3rdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	35));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5004 */
rtx
gen_aarch64_vec_load_lanesci_lanedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	40));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5038 */
rtx
gen_aarch64_simd_st3v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5038 */
rtx
gen_aarch64_simd_st3v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5038 */
rtx
gen_aarch64_simd_st3v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5038 */
rtx
gen_aarch64_simd_st3v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5038 */
rtx
gen_aarch64_simd_st3v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5038 */
rtx
gen_aarch64_simd_st3v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5038 */
rtx
gen_aarch64_simd_st3v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5049 */
rtx
gen_aarch64_vec_store_lanesci_lanedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	62));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5082 */
rtx
gen_aarch64_simd_ld4v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5082 */
rtx
gen_aarch64_simd_ld4v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5082 */
rtx
gen_aarch64_simd_ld4v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5082 */
rtx
gen_aarch64_simd_ld4v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5082 */
rtx
gen_aarch64_simd_ld4v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5082 */
rtx
gen_aarch64_simd_ld4v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5082 */
rtx
gen_aarch64_simd_ld4v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5092 */
rtx
gen_aarch64_simd_ld4rdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	38));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5102 */
rtx
gen_aarch64_vec_load_lanesxi_lanedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	41));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5136 */
rtx
gen_aarch64_simd_st4v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5136 */
rtx
gen_aarch64_simd_st4v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5136 */
rtx
gen_aarch64_simd_st4v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5136 */
rtx
gen_aarch64_simd_st4v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5136 */
rtx
gen_aarch64_simd_st4v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5136 */
rtx
gen_aarch64_simd_st4v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5136 */
rtx
gen_aarch64_simd_st4v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5147 */
rtx
gen_aarch64_vec_store_lanesxi_lanedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75),
		operand2),
	63));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5180 */
rtx
gen_aarch64_rev_reglistoi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		operand2),
	203));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5180 */
rtx
gen_aarch64_rev_reglistci (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		operand2),
	203));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5180 */
rtx
gen_aarch64_rev_reglistxi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		operand2),
	203));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5231 */
rtx
gen_aarch64_ld1_x3_df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5252 */
rtx
gen_aarch64_st1_x2_df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (2)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5273 */
rtx
gen_aarch64_st1_x3_df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)]),
	75)),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5298 */
rtx
gen_aarch64_be_ld1v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5298 */
rtx
gen_aarch64_be_ld1v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5298 */
rtx
gen_aarch64_be_ld1v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5298 */
rtx
gen_aarch64_be_ld1v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5298 */
rtx
gen_aarch64_be_ld1v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5298 */
rtx
gen_aarch64_be_ld1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5298 */
rtx
gen_aarch64_be_ld1v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5298 */
rtx
gen_aarch64_be_ld1v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5298 */
rtx
gen_aarch64_be_ld1v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5298 */
rtx
gen_aarch64_be_ld1v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5298 */
rtx
gen_aarch64_be_ld1v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5298 */
rtx
gen_aarch64_be_ld1v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5298 */
rtx
gen_aarch64_be_ld1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5308 */
rtx
gen_aarch64_be_st1v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5308 */
rtx
gen_aarch64_be_st1v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5308 */
rtx
gen_aarch64_be_st1v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5308 */
rtx
gen_aarch64_be_st1v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5308 */
rtx
gen_aarch64_be_st1v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5308 */
rtx
gen_aarch64_be_st1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5308 */
rtx
gen_aarch64_be_st1v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5308 */
rtx
gen_aarch64_be_st1v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5308 */
rtx
gen_aarch64_be_st1v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5308 */
rtx
gen_aarch64_be_st1v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5308 */
rtx
gen_aarch64_be_st1v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5308 */
rtx
gen_aarch64_be_st1v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5308 */
rtx
gen_aarch64_be_st1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5430 */
rtx
gen_aarch64_ld2v8qi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	31));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5430 */
rtx
gen_aarch64_ld2v4hi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	31));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5430 */
rtx
gen_aarch64_ld2v4hf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	31));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5430 */
rtx
gen_aarch64_ld2v2si_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	31));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5430 */
rtx
gen_aarch64_ld2v2sf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	31));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5440 */
rtx
gen_aarch64_ld2di_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	31));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5440 */
rtx
gen_aarch64_ld2df_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	31));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5450 */
rtx
gen_aarch64_ld3v8qi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	34));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5450 */
rtx
gen_aarch64_ld3v4hi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	34));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5450 */
rtx
gen_aarch64_ld3v4hf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	34));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5450 */
rtx
gen_aarch64_ld3v2si_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	34));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5450 */
rtx
gen_aarch64_ld3v2sf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	34));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5460 */
rtx
gen_aarch64_ld3di_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	34));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5460 */
rtx
gen_aarch64_ld3df_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	34));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5470 */
rtx
gen_aarch64_ld4v8qi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	37));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5470 */
rtx
gen_aarch64_ld4v4hi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	37));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5470 */
rtx
gen_aarch64_ld4v4hf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	37));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5470 */
rtx
gen_aarch64_ld4v2si_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	37));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5470 */
rtx
gen_aarch64_ld4v2sf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	37));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_ld4di_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	37));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_ld4df_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	37));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5630 */
rtx
gen_aarch64_tbl1v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	174));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5630 */
rtx
gen_aarch64_tbl1v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	174));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5642 */
rtx
gen_aarch64_tbl2v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	174));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5652 */
rtx
gen_aarch64_tbl3v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	174));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5652 */
rtx
gen_aarch64_tbl3v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	174));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5662 */
rtx
gen_aarch64_tbx4v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	175));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5662 */
rtx
gen_aarch64_tbx4v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	175));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5675 */
rtx
gen_aarch64_qtbl3v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	174));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5675 */
rtx
gen_aarch64_qtbl3v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	174));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5685 */
rtx
gen_aarch64_qtbx3v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	175));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5685 */
rtx
gen_aarch64_qtbx3v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	175));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5698 */
rtx
gen_aarch64_qtbl4v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	174));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5698 */
rtx
gen_aarch64_qtbl4v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	174));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5708 */
rtx
gen_aarch64_qtbx4v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	175));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5708 */
rtx
gen_aarch64_qtbx4v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	175));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5719 */
rtx
gen_aarch64_combinev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		operand2),
	176));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip1v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip2v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn1v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn2v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp1v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp2v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip1v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip2v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn1v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn2v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp1v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp2v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip1v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip2v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn1v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn2v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp1v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp2v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip1v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn1v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp1v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip1v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip2v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn1v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn2v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp1v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp2v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip1v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn1v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp1v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip1v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip2v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn1v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn2v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp1v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp2v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip1v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip2v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn1v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn2v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp1v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp2v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip1v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip2v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn1v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn2v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp1v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp2v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip1v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip2v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn1v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn2v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp1v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp2v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip1v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_zip2v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn1v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_trn2v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp1v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5738 */
rtx
gen_aarch64_uzp2v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5752 */
rtx
gen_aarch64_extv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	183));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5752 */
rtx
gen_aarch64_extv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	183));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5752 */
rtx
gen_aarch64_extv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	183));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5752 */
rtx
gen_aarch64_extv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	183));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5752 */
rtx
gen_aarch64_extv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	183));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5752 */
rtx
gen_aarch64_extv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	183));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5752 */
rtx
gen_aarch64_extv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	183));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5752 */
rtx
gen_aarch64_extv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	183));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5752 */
rtx
gen_aarch64_extv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	183));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5752 */
rtx
gen_aarch64_extv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	183));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5752 */
rtx
gen_aarch64_extv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	183));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5752 */
rtx
gen_aarch64_extv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	183));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev64v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	184));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev32v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	185));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev16v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	186));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev64v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	184));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev32v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	185));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev16v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	186));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev64v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	184));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev32v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	185));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev16v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	186));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev64v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	184));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev32v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	185));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev16v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	186));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev64v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	184));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev32v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	185));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev16v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	186));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev64v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	184));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev32v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	185));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev16v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	186));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev64v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	184));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev32v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	185));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev16v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	186));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev64v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	184));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev32v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	185));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev16v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	186));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev64v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	184));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev32v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	185));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev16v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	186));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev64v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	184));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev32v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	185));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev16v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	186));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev64v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	184));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev32v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	185));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev16v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	186));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev64v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	184));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev32v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	185));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5770 */
rtx
gen_aarch64_rev16v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	186));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5779 */
rtx
gen_aarch64_st2v8qi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5779 */
rtx
gen_aarch64_st2v4hi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5779 */
rtx
gen_aarch64_st2v4hf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5779 */
rtx
gen_aarch64_st2v2si_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5779 */
rtx
gen_aarch64_st2v2sf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5789 */
rtx
gen_aarch64_st2di_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5789 */
rtx
gen_aarch64_st2df_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5799 */
rtx
gen_aarch64_st3v8qi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5799 */
rtx
gen_aarch64_st3v4hi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5799 */
rtx
gen_aarch64_st3v4hf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5799 */
rtx
gen_aarch64_st3v2si_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5799 */
rtx
gen_aarch64_st3v2sf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5809 */
rtx
gen_aarch64_st3di_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5809 */
rtx
gen_aarch64_st3df_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5819 */
rtx
gen_aarch64_st4v8qi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5819 */
rtx
gen_aarch64_st4v4hi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5819 */
rtx
gen_aarch64_st4v4hf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5819 */
rtx
gen_aarch64_st4v2si_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5819 */
rtx
gen_aarch64_st4v2sf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5829 */
rtx
gen_aarch64_st4di_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5829 */
rtx
gen_aarch64_st4df_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5938 */
rtx
gen_aarch64_simd_ld1v16qi_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5938 */
rtx
gen_aarch64_simd_ld1v8hi_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5938 */
rtx
gen_aarch64_simd_ld1v4si_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5938 */
rtx
gen_aarch64_simd_ld1v2di_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5938 */
rtx
gen_aarch64_simd_ld1v8hf_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5938 */
rtx
gen_aarch64_simd_ld1v4sf_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5938 */
rtx
gen_aarch64_simd_ld1v2df_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5948 */
rtx
gen_aarch64_simd_ld1v8qi_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5948 */
rtx
gen_aarch64_simd_ld1v4hi_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5948 */
rtx
gen_aarch64_simd_ld1v4hf_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5948 */
rtx
gen_aarch64_simd_ld1v2si_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5948 */
rtx
gen_aarch64_simd_ld1v2sf_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5948 */
rtx
gen_aarch64_simd_ld1di_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5948 */
rtx
gen_aarch64_simd_ld1df_x2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	29));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5959 */
rtx
gen_aarch64_frecpev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	14));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5959 */
rtx
gen_aarch64_frecpev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	14));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5959 */
rtx
gen_aarch64_frecpev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	14));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5959 */
rtx
gen_aarch64_frecpev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	14));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5959 */
rtx
gen_aarch64_frecpev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	14));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5959 */
rtx
gen_aarch64_frecpehf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	14));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5959 */
rtx
gen_aarch64_frecpesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	14));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5959 */
rtx
gen_aarch64_frecpedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	14));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5969 */
rtx
gen_aarch64_frecpxhf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	16));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5969 */
rtx
gen_aarch64_frecpxsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	16));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5969 */
rtx
gen_aarch64_frecpxdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	16));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5978 */
rtx
gen_aarch64_frecpsv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	15));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5978 */
rtx
gen_aarch64_frecpsv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	15));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5978 */
rtx
gen_aarch64_frecpsv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	15));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5978 */
rtx
gen_aarch64_frecpsv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	15));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5978 */
rtx
gen_aarch64_frecpsv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	15));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5978 */
rtx
gen_aarch64_frecpshf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	15));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5978 */
rtx
gen_aarch64_frecpssf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	15));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5978 */
rtx
gen_aarch64_frecpsdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	15));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5989 */
rtx
gen_aarch64_urecpev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	13));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5989 */
rtx
gen_aarch64_urecpev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	13));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6012 */
rtx
gen_aarch64_crypto_aesev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	187));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6012 */
rtx
gen_aarch64_crypto_aesdv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	188));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6051 */
rtx
gen_aarch64_crypto_aesmcv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	189));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6051 */
rtx
gen_aarch64_crypto_aesimcv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	190));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6106 */
rtx
gen_aarch64_crypto_sha1hsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	194));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6116 */
rtx
gen_aarch64_crypto_sha1hv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const0_rtx)))),
	194));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6126 */
rtx
gen_aarch64_be_crypto_sha1hv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		const_int_rtx[MAX_SAVED_CONST_INT + (3)])))),
	194));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6136 */
rtx
gen_aarch64_crypto_sha1su1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	196));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6146 */
rtx
gen_aarch64_crypto_sha1cv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	191));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6146 */
rtx
gen_aarch64_crypto_sha1mv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	192));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6146 */
rtx
gen_aarch64_crypto_sha1pv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	193));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6157 */
rtx
gen_aarch64_crypto_sha1su0v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	195));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6170 */
rtx
gen_aarch64_crypto_sha256hv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	197));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6170 */
rtx
gen_aarch64_crypto_sha256h2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	198));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6181 */
rtx
gen_aarch64_crypto_sha256su0v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	199));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6191 */
rtx
gen_aarch64_crypto_sha256su1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	200));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6204 */
rtx
gen_aarch64_crypto_sha512hqv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	220));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6204 */
rtx
gen_aarch64_crypto_sha512h2qv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	221));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6215 */
rtx
gen_aarch64_crypto_sha512su0qv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	222));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6225 */
rtx
gen_aarch64_crypto_sha512su1qv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	223));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6238 */
rtx
gen_eor3qv16qi4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V16QImode,
	gen_rtx_XOR (V16QImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6238 */
rtx
gen_eor3qv8hi4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V8HImode,
	gen_rtx_XOR (V8HImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6238 */
rtx
gen_eor3qv4si4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V4SImode,
	gen_rtx_XOR (V4SImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6238 */
rtx
gen_eor3qv2di4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V2DImode,
	gen_rtx_XOR (V2DImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6250 */
rtx
gen_aarch64_rax1qv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V2DImode,
	gen_rtx_ROTATE (V2DImode,
	operand2,
	const1_rtx),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6262 */
rtx
gen_aarch64_xarqv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ROTATERT (V2DImode,
	gen_rtx_XOR (V2DImode,
	operand1,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6274 */
rtx
gen_bcaxqv16qi4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V16QImode,
	gen_rtx_AND (V16QImode,
	gen_rtx_NOT (V16QImode,
	operand3),
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6274 */
rtx
gen_bcaxqv8hi4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V8HImode,
	gen_rtx_AND (V8HImode,
	gen_rtx_NOT (V8HImode,
	operand3),
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6274 */
rtx
gen_bcaxqv4si4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V4SImode,
	gen_rtx_AND (V4SImode,
	gen_rtx_NOT (V4SImode,
	operand3),
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6274 */
rtx
gen_bcaxqv2di4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V2DImode,
	gen_rtx_AND (V2DImode,
	gen_rtx_NOT (V2DImode,
	operand3),
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6288 */
rtx
gen_aarch64_sm3ss1qv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	211));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6300 */
rtx
gen_aarch64_sm3tt1aqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	212));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6300 */
rtx
gen_aarch64_sm3tt1bqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	213));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6300 */
rtx
gen_aarch64_sm3tt2aqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	214));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6300 */
rtx
gen_aarch64_sm3tt2bqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	215));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6312 */
rtx
gen_aarch64_sm3partw1qv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	216));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6312 */
rtx
gen_aarch64_sm3partw2qv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	217));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6325 */
rtx
gen_aarch64_sm4eqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	218));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6335 */
rtx
gen_aarch64_sm4ekeyqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	219));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6390 */
rtx
gen_aarch64_simd_fmlal_lowv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand2,
	operand4)),
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand3,
	operand5)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6390 */
rtx
gen_aarch64_simd_fmlalq_lowv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand2,
	operand4)),
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand3,
	operand5)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6407 */
rtx
gen_aarch64_simd_fmlsl_lowv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_NEG (V2HFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand2,
	operand4))),
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand3,
	operand5)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6407 */
rtx
gen_aarch64_simd_fmlslq_lowv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_NEG (V4HFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand2,
	operand4))),
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand3,
	operand5)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6425 */
rtx
gen_aarch64_simd_fmlal_highv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand2,
	operand4)),
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand3,
	operand5)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6425 */
rtx
gen_aarch64_simd_fmlalq_highv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand2,
	operand4)),
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand3,
	operand5)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6442 */
rtx
gen_aarch64_simd_fmlsl_highv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_NEG (V2HFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand2,
	operand4))),
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand3,
	operand5)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6442 */
rtx
gen_aarch64_simd_fmlslq_highv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_NEG (V4HFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand2,
	operand4))),
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand3,
	operand5)),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6501 */
rtx
gen_aarch64_simd_fmlal_lane_lowv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand2,
	operand4)),
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_DUPLICATE (V2HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6519 */
rtx
gen_aarch64_simd_fmlsl_lane_lowv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_NEG (V2HFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand2,
	operand4))),
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_DUPLICATE (V2HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6538 */
rtx
gen_aarch64_simd_fmlal_lane_highv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand2,
	operand4)),
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_DUPLICATE (V2HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6556 */
rtx
gen_aarch64_simd_fmlsl_lane_highv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_NEG (V2HFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand2,
	operand4))),
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_DUPLICATE (V2HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6615 */
rtx
gen_aarch64_simd_fmlalq_laneq_lowv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand2,
	operand4)),
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6633 */
rtx
gen_aarch64_simd_fmlslq_laneq_lowv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_NEG (V4HFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand2,
	operand4))),
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6652 */
rtx
gen_aarch64_simd_fmlalq_laneq_highv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand2,
	operand4)),
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6670 */
rtx
gen_aarch64_simd_fmlslq_laneq_highv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_NEG (V4HFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand2,
	operand4))),
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6731 */
rtx
gen_aarch64_simd_fmlal_laneq_lowv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand2,
	operand4)),
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_DUPLICATE (V2HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6749 */
rtx
gen_aarch64_simd_fmlsl_laneq_lowv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_NEG (V2HFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand2,
	operand4))),
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_DUPLICATE (V2HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6768 */
rtx
gen_aarch64_simd_fmlal_laneq_highv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand2,
	operand4)),
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_DUPLICATE (V2HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6786 */
rtx
gen_aarch64_simd_fmlsl_laneq_highv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_NEG (V2HFmode,
	gen_rtx_VEC_SELECT (V2HFmode,
	operand2,
	operand4))),
	gen_rtx_FLOAT_EXTEND (V2SFmode,
	gen_rtx_VEC_DUPLICATE (V2HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6845 */
rtx
gen_aarch64_simd_fmlalq_lane_lowv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand2,
	operand4)),
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6863 */
rtx
gen_aarch64_simd_fmlslq_lane_lowv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_NEG (V4HFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand2,
	operand4))),
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6882 */
rtx
gen_aarch64_simd_fmlalq_lane_highv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand2,
	operand4)),
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6900 */
rtx
gen_aarch64_simd_fmlslq_lane_highv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_NEG (V4HFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand2,
	operand4))),
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand5))))),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6921 */
rtx
gen_aarch64_crypto_pmulldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (TImode,
	gen_rtvec (2,
		operand1,
		operand2),
	201));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6931 */
rtx
gen_aarch64_crypto_pmullv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (TImode,
	gen_rtvec (2,
		operand1,
		operand2),
	202));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:42 */
rtx
gen_aarch64_compare_and_swapqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_UNSPEC_VOLATILE (CCmode,
	gen_rtvec (1,
		const0_rtx),
	16)),
		gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (5,
		operand2,
		operand3,
		operand4,
		operand5,
		operand6),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:42 */
rtx
gen_aarch64_compare_and_swaphi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_UNSPEC_VOLATILE (CCmode,
	gen_rtvec (1,
		const0_rtx),
	16)),
		gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (5,
		operand2,
		operand3,
		operand4,
		operand5,
		operand6),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:67 */
rtx
gen_aarch64_compare_and_swapsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_UNSPEC_VOLATILE (CCmode,
	gen_rtvec (1,
		const0_rtx),
	16)),
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (5,
		operand2,
		operand3,
		operand4,
		operand5,
		operand6),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:67 */
rtx
gen_aarch64_compare_and_swapdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_UNSPEC_VOLATILE (CCmode,
	gen_rtvec (1,
		const0_rtx),
	16)),
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (5,
		operand2,
		operand3,
		operand4,
		operand5,
		operand6),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:91 */
rtx
gen_aarch64_compare_and_swapqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand2,
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:91 */
rtx
gen_aarch64_compare_and_swaphi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand2,
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:114 */
rtx
gen_aarch64_compare_and_swapsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand2,
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:114 */
rtx
gen_aarch64_compare_and_swapdi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand2,
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:157 */
rtx
gen_aarch64_atomic_exchangeqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	17)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:157 */
rtx
gen_aarch64_atomic_exchangehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand2,
		operand3),
	17)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:157 */
rtx
gen_aarch64_atomic_exchangesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	17)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:157 */
rtx
gen_aarch64_atomic_exchangedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand2,
		operand3),
	17)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:178 */
rtx
gen_aarch64_atomic_exchangeqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	17))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:178 */
rtx
gen_aarch64_atomic_exchangehi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand2,
		operand3),
	17))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:178 */
rtx
gen_aarch64_atomic_exchangesi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	17))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:178 */
rtx
gen_aarch64_atomic_exchangedi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand2,
		operand3),
	17))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_addqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_subqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_orqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_IOR (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_xorqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_XOR (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_andqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_AND (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_addhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_subhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_orhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_IOR (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_xorhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_XOR (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_andhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_AND (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_addsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_subsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_orsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_IOR (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_xorsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_XOR (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_andsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_AND (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_adddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_subdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_ordi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_IOR (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_xordi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_XOR (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
rtx
gen_aarch64_atomic_anddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_AND (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_iorqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	21)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_bicqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	22)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_xorqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	23)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_addqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	24)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_iorhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	21)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_bichi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	22)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_xorhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	23)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_addhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	24)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_iorsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	21)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_bicsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	22)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_xorsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	23)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_addsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	24)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_iordi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	21)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_bicdi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	22)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_xordi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	23)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:278 */
rtx
gen_aarch64_atomic_adddi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand1,
		operand2),
	24)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:300 */
rtx
gen_atomic_nandqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_NOT (QImode,
	gen_rtx_AND (QImode,
	copy_rtx (operand0),
	operand1)),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:300 */
rtx
gen_atomic_nandhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_NOT (HImode,
	gen_rtx_AND (HImode,
	copy_rtx (operand0),
	operand1)),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:300 */
rtx
gen_atomic_nandsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_NOT (SImode,
	gen_rtx_AND (SImode,
	copy_rtx (operand0),
	operand1)),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:300 */
rtx
gen_atomic_nanddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_NOT (DImode,
	gen_rtx_AND (DImode,
	copy_rtx (operand0),
	operand1)),
		operand2),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_addqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_subqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_orqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_IOR (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_xorqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_XOR (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_andqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_AND (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_addhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_subhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_orhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_IOR (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_xorhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_XOR (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_andhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_AND (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_addsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_subsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_orsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_IOR (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_xorsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_XOR (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_andsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_AND (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_adddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_subdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_ordi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_IOR (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_xordi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_XOR (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
rtx
gen_aarch64_atomic_fetch_anddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_AND (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_iorqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	21))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_bicqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	22))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_xorqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	23))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_addqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	24))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_iorhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	21))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_bichi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	22))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_xorhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	23))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_addhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	24))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_iorsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	21))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_bicsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	22))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_xorsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	23))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_addsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	24))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_iordi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	21))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_bicdi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	22))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_xordi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	23))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:392 */
rtx
gen_aarch64_atomic_fetch_adddi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	24))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:415 */
rtx
gen_atomic_fetch_nandqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_NOT (QImode,
	gen_rtx_AND (QImode,
	copy_rtx (operand1),
	operand2)),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:415 */
rtx
gen_atomic_fetch_nandhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_NOT (HImode,
	gen_rtx_AND (HImode,
	copy_rtx (operand1),
	operand2)),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:415 */
rtx
gen_atomic_fetch_nandsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_NOT (SImode,
	gen_rtx_AND (SImode,
	copy_rtx (operand1),
	operand2)),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:415 */
rtx
gen_atomic_fetch_nanddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_NOT (DImode,
	gen_rtx_AND (DImode,
	copy_rtx (operand1),
	operand2)),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_add_fetchqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_sub_fetchqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_or_fetchqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_IOR (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_xor_fetchqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_XOR (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_and_fetchqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_AND (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_add_fetchhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_sub_fetchhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_or_fetchhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_IOR (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_xor_fetchhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_XOR (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_and_fetchhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_AND (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_add_fetchsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_sub_fetchsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_or_fetchsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_xor_fetchsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_and_fetchsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_add_fetchdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_sub_fetchdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_or_fetchdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_xor_fetchdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
rtx
gen_aarch64_atomic_and_fetchdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:492 */
rtx
gen_atomic_nand_fetchqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_NOT (QImode,
	gen_rtx_AND (QImode,
	operand1,
	operand2))),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:492 */
rtx
gen_atomic_nand_fetchhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_NOT (HImode,
	gen_rtx_AND (HImode,
	operand1,
	operand2))),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:492 */
rtx
gen_atomic_nand_fetchsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_NOT (SImode,
	gen_rtx_AND (SImode,
	operand1,
	operand2))),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:492 */
rtx
gen_atomic_nand_fetchdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_NOT (DImode,
	gen_rtx_AND (DImode,
	operand1,
	operand2))),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	20)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:516 */
rtx
gen_atomic_loadqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	14));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:516 */
rtx
gen_atomic_loadhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	14));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:516 */
rtx
gen_atomic_loadsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	14));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:516 */
rtx
gen_atomic_loaddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	14));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:532 */
rtx
gen_atomic_storeqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	15));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:532 */
rtx
gen_atomic_storehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	15));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:532 */
rtx
gen_atomic_storesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	15));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:532 */
rtx
gen_atomic_storedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	15));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:551 */
rtx
gen_aarch64_load_exclusiveqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:551 */
rtx
gen_aarch64_load_exclusivehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:568 */
rtx
gen_aarch64_load_exclusivesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:568 */
rtx
gen_aarch64_load_exclusivedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	12));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:584 */
rtx
gen_aarch64_store_exclusiveqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		const0_rtx),
	13)),
		gen_rtx_SET (operand1,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	13))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:584 */
rtx
gen_aarch64_store_exclusivehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		const0_rtx),
	13)),
		gen_rtx_SET (operand1,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand2,
		operand3),
	13))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:584 */
rtx
gen_aarch64_store_exclusivesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		const0_rtx),
	13)),
		gen_rtx_SET (operand1,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	13))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:584 */
rtx
gen_aarch64_store_exclusivedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		const0_rtx),
	13)),
		gen_rtx_SET (operand1,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand2,
		operand3),
	13))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
rtx
gen_aarch64_pred_movvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
rtx
gen_aarch64_pred_movvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
rtx
gen_aarch64_pred_movvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
rtx
gen_aarch64_pred_movvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
rtx
gen_aarch64_pred_movvnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
rtx
gen_aarch64_pred_movvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
rtx
gen_aarch64_pred_movvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:202 */
rtx
gen_maskloadvnx16qivnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	84));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:202 */
rtx
gen_maskloadvnx8hivnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	84));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:202 */
rtx
gen_maskloadvnx4sivnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	84));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:202 */
rtx
gen_maskloadvnx2divnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	84));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:202 */
rtx
gen_maskloadvnx8hfvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	84));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:202 */
rtx
gen_maskloadvnx4sfvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	84));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:202 */
rtx
gen_maskloadvnx2dfvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	84));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:212 */
rtx
gen_maskstorevnx16qivnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	85));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:212 */
rtx
gen_maskstorevnx8hivnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	85));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:212 */
rtx
gen_maskstorevnx4sivnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	85));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:212 */
rtx
gen_maskstorevnx2divnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	85));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:212 */
rtx
gen_maskstorevnx8hfvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	85));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:212 */
rtx
gen_maskstorevnx4sfvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	85));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:212 */
rtx
gen_maskstorevnx2dfvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	85));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:241 */
rtx
gen_mask_gather_loadvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (6,
		operand5,
		operand1,
		operand2,
		operand3,
		operand4,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode))),
	87));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:241 */
rtx
gen_mask_gather_loadvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (6,
		operand5,
		operand1,
		operand2,
		operand3,
		operand4,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode))),
	87));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:262 */
rtx
gen_mask_gather_loadvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (6,
		operand5,
		operand1,
		operand2,
		operand3,
		operand4,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode))),
	87));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:262 */
rtx
gen_mask_gather_loadvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (6,
		operand5,
		operand1,
		operand2,
		operand3,
		operand4,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode))),
	87));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:298 */
rtx
gen_mask_scatter_storevnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (6,
		operand5,
		operand0,
		operand1,
		operand2,
		operand3,
		operand4),
	88));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:298 */
rtx
gen_mask_scatter_storevnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (6,
		operand5,
		operand0,
		operand1,
		operand2,
		operand3,
		operand4),
	88));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:319 */
rtx
gen_mask_scatter_storevnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (6,
		operand5,
		operand0,
		operand1,
		operand2,
		operand3,
		operand4),
	88));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:319 */
rtx
gen_mask_scatter_storevnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (6,
		operand5,
		operand0,
		operand1,
		operand2,
		operand3,
		operand4),
	88));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx32qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx16hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx8si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx4di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx16hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx8sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx4df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx48qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx48QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx24hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx24HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx12si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx12SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx6di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx6DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx24hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx24HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx12sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx12SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx6df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx6DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx64qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx32hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx16si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx8di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx32hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx16sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
rtx
gen_aarch64_pred_movvnx8df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:610 */
rtx
gen_extract_last_vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	253));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:610 */
rtx
gen_extract_last_vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	253));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:610 */
rtx
gen_extract_last_vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	253));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:610 */
rtx
gen_extract_last_vnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	253));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:610 */
rtx
gen_extract_last_vnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	253));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:610 */
rtx
gen_extract_last_vnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	253));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:610 */
rtx
gen_extract_last_vnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	253));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:670 */
rtx
gen_sve_ld1rvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand2),
		operand3),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:670 */
rtx
gen_sve_ld1rvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand2),
		operand3),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:670 */
rtx
gen_sve_ld1rvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand2),
		operand3),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:670 */
rtx
gen_sve_ld1rvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand2),
		operand3),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:670 */
rtx
gen_sve_ld1rvnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_VEC_DUPLICATE (VNx8HFmode,
	operand2),
		operand3),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:670 */
rtx
gen_sve_ld1rvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand2),
		operand3),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:670 */
rtx
gen_sve_ld1rvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand2),
		operand3),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:711 */
rtx
gen_vec_seriesvnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SERIES (VNx16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:711 */
rtx
gen_vec_seriesvnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SERIES (VNx8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:711 */
rtx
gen_vec_seriesvnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SERIES (VNx4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:711 */
rtx
gen_vec_seriesvnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SERIES (VNx2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx32qivnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx16hivnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx8sivnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx4divnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx16hfvnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx8sfvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx4dfvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx48qivnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx48QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx24hivnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx24HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx12sivnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx12SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx6divnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx6DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx24hfvnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx24HFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx12sfvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx12SFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx6dfvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx6DFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx64qivnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx32hivnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx16sivnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx8divnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx32hfvnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx16sfvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:752 */
rtx
gen_vec_mask_load_lanesvnx8dfvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx32qivnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx16hivnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx8sivnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx4divnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx16hfvnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx8sfvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx4dfvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx48qivnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx48QImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx24hivnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx24HImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx12sivnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx12SImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx6divnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx6DImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx24hfvnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx24HFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx12sfvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx12SFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx6dfvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx6DFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx64qivnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx32hivnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx16sivnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx8divnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx32hfvnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx16sfvnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:781 */
rtx
gen_vec_mask_store_lanesvnx8dfvnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		operand0),
	99));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip1vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip2vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn1vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn2vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp1vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp2vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip1vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip2vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn1vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn2vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp1vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp2vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip1vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip2vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn1vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn2vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp1vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp2vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip1vnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip2vnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn1vnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn2vnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp1vnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp2vnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip1vnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip2vnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn1vnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn2vnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp1vnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp2vnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip1vnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip2vnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn1vnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn2vnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp1vnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp2vnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip1vnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	177));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_zip2vnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	178));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn1vnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	181));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_trn2vnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	182));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp1vnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	179));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:824 */
rtx
gen_aarch64_sve_uzp2vnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	180));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:900 */
rtx
gen_addvnx16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (VNx16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:900 */
rtx
gen_addvnx8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (VNx8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:900 */
rtx
gen_addvnx4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (VNx4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:900 */
rtx
gen_addvnx2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (VNx2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:913 */
rtx
gen_subvnx16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (VNx16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:913 */
rtx
gen_subvnx8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (VNx8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:913 */
rtx
gen_subvnx4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (VNx4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:913 */
rtx
gen_subvnx2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (VNx2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1100 */
rtx
gen_andvnx16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1100 */
rtx
gen_iorvnx16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (VNx16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1100 */
rtx
gen_xorvnx16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (VNx16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1100 */
rtx
gen_andvnx8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1100 */
rtx
gen_iorvnx8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (VNx8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1100 */
rtx
gen_xorvnx8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (VNx8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1100 */
rtx
gen_andvnx4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1100 */
rtx
gen_iorvnx4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (VNx4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1100 */
rtx
gen_xorvnx4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (VNx4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1100 */
rtx
gen_andvnx2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1100 */
rtx
gen_iorvnx2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (VNx2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1100 */
rtx
gen_xorvnx2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (VNx2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1125 */
rtx
gen_bicvnx16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16QImode,
	gen_rtx_NOT (VNx16QImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1125 */
rtx
gen_bicvnx8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8HImode,
	gen_rtx_NOT (VNx8HImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1125 */
rtx
gen_bicvnx4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4SImode,
	gen_rtx_NOT (VNx4SImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1125 */
rtx
gen_bicvnx2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2DImode,
	gen_rtx_NOT (VNx2DImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1135 */
rtx
gen_andvnx16bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1135 */
rtx
gen_andvnx8bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1135 */
rtx
gen_andvnx4bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1135 */
rtx
gen_andvnx2bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1158 */
rtx
gen_pred_andvnx16bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_AND (VNx16BImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1158 */
rtx
gen_pred_iorvnx16bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_IOR (VNx16BImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1158 */
rtx
gen_pred_xorvnx16bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_XOR (VNx16BImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1158 */
rtx
gen_pred_andvnx8bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_AND (VNx8BImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1158 */
rtx
gen_pred_iorvnx8bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_IOR (VNx8BImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1158 */
rtx
gen_pred_xorvnx8bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_XOR (VNx8BImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1158 */
rtx
gen_pred_andvnx4bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_AND (VNx4BImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1158 */
rtx
gen_pred_iorvnx4bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_IOR (VNx4BImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1158 */
rtx
gen_pred_xorvnx4bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_XOR (VNx4BImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1158 */
rtx
gen_pred_andvnx2bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_AND (VNx2BImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1158 */
rtx
gen_pred_iorvnx2bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_IOR (VNx2BImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1158 */
rtx
gen_pred_xorvnx2bi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_XOR (VNx2BImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1322 */
rtx
gen_ptest_ptruevnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand0,
		operand1),
	90),
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1322 */
rtx
gen_ptest_ptruevnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand0,
		operand1),
	90),
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1322 */
rtx
gen_ptest_ptruevnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand0,
		operand1),
	90),
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1322 */
rtx
gen_ptest_ptruevnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand0,
		operand1),
	90),
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1335 */
rtx
gen_while_ultsivnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		operand1,
		operand2),
	97)),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1335 */
rtx
gen_while_ultdivnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		operand1,
		operand2),
	97)),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1335 */
rtx
gen_while_ultsivnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		operand1,
		operand2),
	97)),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1335 */
rtx
gen_while_ultdivnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		operand1,
		operand2),
	97)),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1335 */
rtx
gen_while_ultsivnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		operand1,
		operand2),
	97)),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1335 */
rtx
gen_while_ultdivnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		operand1,
		operand2),
	97)),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1335 */
rtx
gen_while_ultsivnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		operand1,
		operand2),
	97)),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1335 */
rtx
gen_while_ultdivnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		operand1,
		operand2),
	97)),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
rtx
gen_while_ultsivnx16bi_cc (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		operand2,
		operand3),
	97)),
	90),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		copy_rtx (operand2),
		copy_rtx (operand3)),
	97))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
rtx
gen_while_ultdivnx16bi_cc (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		operand2,
		operand3),
	97)),
	90),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		copy_rtx (operand2),
		copy_rtx (operand3)),
	97))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
rtx
gen_while_ultsivnx8bi_cc (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		operand2,
		operand3),
	97)),
	90),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		copy_rtx (operand2),
		copy_rtx (operand3)),
	97))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
rtx
gen_while_ultdivnx8bi_cc (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		operand2,
		operand3),
	97)),
	90),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		copy_rtx (operand2),
		copy_rtx (operand3)),
	97))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
rtx
gen_while_ultsivnx4bi_cc (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		operand2,
		operand3),
	97)),
	90),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		copy_rtx (operand2),
		copy_rtx (operand3)),
	97))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
rtx
gen_while_ultdivnx4bi_cc (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		operand2,
		operand3),
	97)),
	90),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		copy_rtx (operand2),
		copy_rtx (operand3)),
	97))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
rtx
gen_while_ultsivnx2bi_cc (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		operand2,
		operand3),
	97)),
	90),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		copy_rtx (operand2),
		copy_rtx (operand3)),
	97))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
rtx
gen_while_ultdivnx2bi_cc (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		operand2,
		operand3),
	97)),
	90),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (2,
		copy_rtx (operand2),
		copy_rtx (operand3)),
	97))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1607 */
rtx
gen_vcond_mask_vnx16qivnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand3,
		operand1,
		operand2),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1607 */
rtx
gen_vcond_mask_vnx8hivnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand3,
		operand1,
		operand2),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1607 */
rtx
gen_vcond_mask_vnx4sivnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand3,
		operand1,
		operand2),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1607 */
rtx
gen_vcond_mask_vnx2divnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand3,
		operand1,
		operand2),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1607 */
rtx
gen_vcond_mask_vnx8hfvnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand3,
		operand1,
		operand2),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1607 */
rtx
gen_vcond_mask_vnx4sfvnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand3,
		operand1,
		operand2),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1607 */
rtx
gen_vcond_mask_vnx2dfvnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand3,
		operand1,
		operand2),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1619 */
rtx
gen_aarch64_sve_dupvnx16qi_const (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1619 */
rtx
gen_aarch64_sve_dupvnx8hi_const (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1619 */
rtx
gen_aarch64_sve_dupvnx4si_const (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1619 */
rtx
gen_aarch64_sve_dupvnx2di_const (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2059 */
rtx
gen_fold_extract_last_vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	101));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2059 */
rtx
gen_fold_extract_last_vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	101));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2059 */
rtx
gen_fold_extract_last_vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	101));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2059 */
rtx
gen_fold_extract_last_vnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	101));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2059 */
rtx
gen_fold_extract_last_vnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	101));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2059 */
rtx
gen_fold_extract_last_vnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	101));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2059 */
rtx
gen_fold_extract_last_vnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	101));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2649 */
rtx
gen_aarch64_sve_floatvnx4sivnx2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_FLOAT (VNx2DFmode,
	operand2)),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2649 */
rtx
gen_aarch64_sve_floatunsvnx4sivnx2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSIGNED_FLOAT (VNx2DFmode,
	operand2)),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2649 */
rtx
gen_aarch64_sve_floatvnx2divnx2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_FLOAT (VNx2DFmode,
	operand2)),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2649 */
rtx
gen_aarch64_sve_floatunsvnx2divnx2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSIGNED_FLOAT (VNx2DFmode,
	operand2)),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2676 */
rtx
gen_aarch64_sve_extendvnx8hfvnx4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand2),
	96)),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2676 */
rtx
gen_aarch64_sve_extendvnx4sfvnx2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (1,
		operand2),
	96)),
	89));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2706 */
rtx
gen_aarch64_sve_punpklo_vnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (1,
		operand1),
	94));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2706 */
rtx
gen_aarch64_sve_punpkhi_vnx16bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (1,
		operand1),
	92));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2706 */
rtx
gen_aarch64_sve_punpklo_vnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (1,
		operand1),
	94));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2706 */
rtx
gen_aarch64_sve_punpkhi_vnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (1,
		operand1),
	92));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2706 */
rtx
gen_aarch64_sve_punpklo_vnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (1,
		operand1),
	94));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2706 */
rtx
gen_aarch64_sve_punpkhi_vnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (1,
		operand1),
	92));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2731 */
rtx
gen_aarch64_sve_sunpkhi_vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (1,
		operand1),
	91));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2731 */
rtx
gen_aarch64_sve_uunpkhi_vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (1,
		operand1),
	92));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2731 */
rtx
gen_aarch64_sve_sunpklo_vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (1,
		operand1),
	93));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2731 */
rtx
gen_aarch64_sve_uunpklo_vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (1,
		operand1),
	94));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2731 */
rtx
gen_aarch64_sve_sunpkhi_vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand1),
	91));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2731 */
rtx
gen_aarch64_sve_uunpkhi_vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand1),
	92));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2731 */
rtx
gen_aarch64_sve_sunpklo_vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand1),
	93));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2731 */
rtx
gen_aarch64_sve_uunpklo_vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand1),
	94));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2731 */
rtx
gen_aarch64_sve_sunpkhi_vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand1),
	91));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2731 */
rtx
gen_aarch64_sve_uunpkhi_vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand1),
	92));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2731 */
rtx
gen_aarch64_sve_sunpklo_vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand1),
	93));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2731 */
rtx
gen_aarch64_sve_uunpklo_vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand1),
	94));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2792 */
rtx
gen_vec_pack_trunc_vnx8bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16BImode,
	gen_rtvec (2,
		operand1,
		operand2),
	95));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2792 */
rtx
gen_vec_pack_trunc_vnx4bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (2,
		operand1,
		operand2),
	95));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2792 */
rtx
gen_vec_pack_trunc_vnx2bi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (2,
		operand1,
		operand2),
	95));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2804 */
rtx
gen_vec_pack_trunc_vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	95));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2804 */
rtx
gen_vec_pack_trunc_vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	95));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2804 */
rtx
gen_vec_pack_trunc_vnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	95));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3070 */
rtx
gen_vec_shl_insert_vnx16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	100));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3070 */
rtx
gen_vec_shl_insert_vnx8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	100));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3070 */
rtx
gen_vec_shl_insert_vnx4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	100));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3070 */
rtx
gen_vec_shl_insert_vnx2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	100));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3070 */
rtx
gen_vec_shl_insert_vnx8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	100));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3070 */
rtx
gen_vec_shl_insert_vnx4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	100));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3070 */
rtx
gen_vec_shl_insert_vnx2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	100));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:384 */
rtx
gen_cbranchsi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 391 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
					 operands[2]);
  operands[2] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:384 */
rtx
gen_cbranchdi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 391 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
					 operands[2]);
  operands[2] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:398 */
rtx
gen_cbranchsf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 405 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
					 operands[2]);
  operands[2] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:398 */
rtx
gen_cbranchdf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 405 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
					 operands[2]);
  operands[2] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:412 */
rtx
gen_cbranchcc4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:477 */
rtx
gen_modsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 482 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT val = INTVAL (operands[2]);

    if (val <= 0
       || exact_log2 (val) <= 0
       || !aarch64_bitmask_imm (val - 1, SImode))
      FAIL;

    rtx mask = GEN_INT (val - 1);

    /* In the special case of x0 % 2 we can do the even shorter:
	cmp    x0, xzr
	and    x0, x0, 1
	cneg   x0, x0, lt.  */
    if (val == 2)
      {
	rtx masked = gen_reg_rtx (SImode);
	rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
	emit_insn (gen_andsi3 (masked, operands[1], mask));
	rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
	emit_insn (gen_csneg3si_insn (operands[0], x, masked, masked));
	DONE;
      }

    rtx neg_op = gen_reg_rtx (SImode);
    rtx_insn *insn = emit_insn (gen_negsi2_compare0 (neg_op, operands[1]));

    /* Extract the condition register and mode.  */
    rtx cmp = XVECEXP (PATTERN (insn), 0, 0);
    rtx cc_reg = SET_DEST (cmp);
    rtx cond = gen_rtx_GE (VOIDmode, cc_reg, const0_rtx);

    rtx masked_pos = gen_reg_rtx (SImode);
    emit_insn (gen_andsi3 (masked_pos, operands[1], mask));

    rtx masked_neg = gen_reg_rtx (SImode);
    emit_insn (gen_andsi3 (masked_neg, neg_op, mask));

    emit_insn (gen_csneg3si_insn (operands[0], cond,
				       masked_neg, masked_pos));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:477 */
rtx
gen_moddi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 482 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT val = INTVAL (operands[2]);

    if (val <= 0
       || exact_log2 (val) <= 0
       || !aarch64_bitmask_imm (val - 1, DImode))
      FAIL;

    rtx mask = GEN_INT (val - 1);

    /* In the special case of x0 % 2 we can do the even shorter:
	cmp    x0, xzr
	and    x0, x0, 1
	cneg   x0, x0, lt.  */
    if (val == 2)
      {
	rtx masked = gen_reg_rtx (DImode);
	rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
	emit_insn (gen_anddi3 (masked, operands[1], mask));
	rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
	emit_insn (gen_csneg3di_insn (operands[0], x, masked, masked));
	DONE;
      }

    rtx neg_op = gen_reg_rtx (DImode);
    rtx_insn *insn = emit_insn (gen_negdi2_compare0 (neg_op, operands[1]));

    /* Extract the condition register and mode.  */
    rtx cmp = XVECEXP (PATTERN (insn), 0, 0);
    rtx cc_reg = SET_DEST (cmp);
    rtx cond = gen_rtx_GE (VOIDmode, cc_reg, const0_rtx);

    rtx masked_pos = gen_reg_rtx (DImode);
    emit_insn (gen_anddi3 (masked_pos, operands[1], mask));

    rtx masked_neg = gen_reg_rtx (DImode);
    emit_insn (gen_anddi3 (masked_neg, neg_op, mask));

    emit_insn (gen_csneg3di_insn (operands[0], cond,
				       masked_neg, masked_pos));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:561 */
extern rtx_insn *gen_split_1 (rtx_insn *, rtx *);
rtx_insn *
gen_split_1 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_1\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 573 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (SImode);
    emit_insn (gen_addsi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_addsi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (EQ, SImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:561 */
extern rtx_insn *gen_split_2 (rtx_insn *, rtx *);
rtx_insn *
gen_split_2 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_2\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 573 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (SImode);
    emit_insn (gen_addsi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_addsi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (NE, SImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:561 */
extern rtx_insn *gen_split_3 (rtx_insn *, rtx *);
rtx_insn *
gen_split_3 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_3\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 573 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (SImode);
    emit_insn (gen_addsi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_addsi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (EQ, SImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:561 */
extern rtx_insn *gen_split_4 (rtx_insn *, rtx *);
rtx_insn *
gen_split_4 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_4\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 573 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (SImode);
    emit_insn (gen_addsi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_addsi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (NE, SImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:561 */
extern rtx_insn *gen_split_5 (rtx_insn *, rtx *);
rtx_insn *
gen_split_5 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_5\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 573 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (DImode);
    emit_insn (gen_adddi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_adddi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (EQ, DImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:561 */
extern rtx_insn *gen_split_6 (rtx_insn *, rtx *);
rtx_insn *
gen_split_6 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_6\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 573 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (DImode);
    emit_insn (gen_adddi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_adddi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (NE, DImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:561 */
extern rtx_insn *gen_split_7 (rtx_insn *, rtx *);
rtx_insn *
gen_split_7 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_7\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 573 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (DImode);
    emit_insn (gen_adddi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_adddi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (EQ, DImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:561 */
extern rtx_insn *gen_split_8 (rtx_insn *, rtx *);
rtx_insn *
gen_split_8 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_8\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 573 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (DImode);
    emit_insn (gen_adddi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_adddi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (NE, DImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:586 */
rtx
gen_casesi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 593 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (operands[1] != const0_rtx)
      {
	rtx reg = gen_reg_rtx (SImode);

	/* Canonical RTL says that if you have:

	   (minus (X) (CONST))

           then this should be emitted as:

           (plus (X) (-CONST))

	   The use of trunc_int_for_mode ensures that the resulting
	   constant can be represented in SImode, this is important
	   for the corner case where operand[1] is INT_MIN.  */

	operands[1] = GEN_INT (trunc_int_for_mode (-INTVAL (operands[1]), SImode));

	if (!(*insn_data[CODE_FOR_addsi3].operand[2].predicate)
	      (operands[1], SImode))
	  operands[1] = force_reg (SImode, operands[1]);
	emit_insn (gen_addsi3 (reg, operands[0], operands[1]));
	operands[0] = reg;
      }

    if (!aarch64_plus_operand (operands[2], SImode))
      operands[2] = force_reg (SImode, operands[2]);
    emit_jump_insn (gen_cbranchsi4 (gen_rtx_GTU (SImode, const0_rtx,
						 const0_rtx),
				    operands[0], operands[2], operands[4]));

    operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[3]));
    operands[2]
      = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[2], operands[0]),
			UNSPEC_CASESI);
    operands[2] = gen_rtx_MEM (DImode, operands[2]);
    MEM_READONLY_P (operands[2]) = 1;
    MEM_NOTRAP_P (operands[2]) = 1;
    emit_jump_insn (gen_casesi_dispatch (operands[2], operands[3]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:637 */
rtx
gen_casesi_dispatch (rtx operand0,
	rtx operand1)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (pc_rtx,
	operand0),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_USE (VOIDmode,
	gen_rtx_LABEL_REF (DImode,
	operand1))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:708 */
rtx
gen_prologue (void)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 711 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  aarch64_expand_prologue ();
  DONE;
  
#undef DONE
#undef FAIL
  }
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	const0_rtx));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:717 */
rtx
gen_epilogue (void)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 720 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  aarch64_expand_epilogue (false);
  DONE;
  
#undef DONE
#undef FAIL
  }
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	const0_rtx));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:726 */
rtx
gen_sibcall_epilogue (void)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 729 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  aarch64_expand_epilogue (true);
  DONE;
  
#undef DONE
#undef FAIL
  }
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	const0_rtx));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:749 */
rtx
gen_return (void)
{
  return simple_return_rtx;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:870 */
rtx
gen_call (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 876 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  {
    aarch64_expand_call (NULL_RTX, operands[0], false);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_CALL (VOIDmode,
	operand0,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2),
		gen_hard_reg_clobber (DImode, 30))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:894 */
rtx
gen_call_value (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 901 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  {
    aarch64_expand_call (operands[0], operands[1], false);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_CALL (VOIDmode,
	operand1,
	operand2)),
		gen_rtx_USE (VOIDmode,
	operand3),
		gen_hard_reg_clobber (DImode, 30))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:920 */
rtx
gen_sibcall (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 926 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    aarch64_expand_call (NULL_RTX, operands[0], true);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_CALL (VOIDmode,
	operand0,
	operand1),
		ret_rtx,
		gen_rtx_USE (VOIDmode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:932 */
rtx
gen_sibcall_value (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 939 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    aarch64_expand_call (operands[0], operands[1], true);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_CALL (VOIDmode,
	operand1,
	operand2)),
		ret_rtx,
		gen_rtx_USE (VOIDmode,
	operand3))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:971 */
rtx
gen_untyped_call (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 977 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  int i;

  emit_call_insn (gen_call (operands[0], const0_rtx, NULL));

  for (i = 0; i < XVECLEN (operands[2], 0); i++)
    {
      rtx set = XVECEXP (operands[2], 0, i);
      emit_move_insn (SET_DEST (set), SET_SRC (set));
    }

  /* The optimizer does not know that the call sets the function value
     registers we stored in the result block.  We avoid problems by
     claiming that all hard registers are used and clobbered at this
     point.  */
  emit_insn (gen_blockage ());
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_CALL (VOIDmode,
	operand0,
	const0_rtx),
		operand1,
		operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1000 */
rtx
gen_movqi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

    if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
      operands[1] = force_reg (QImode, operands[1]);

    if (GET_CODE (operands[1]) == CONST_POLY_INT)
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1000 */
rtx
gen_movhi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

    if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
      operands[1] = force_reg (HImode, operands[1]);

    if (GET_CODE (operands[1]) == CONST_POLY_INT)
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1057 */
rtx
gen_movsi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1061 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

    if (MEM_P (operands[0]) && CONST_INT_P (operands[1])
	&& SImode == DImode
	&& aarch64_split_dimode_const_store (operands[0], operands[1]))
      DONE;

    if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
      operands[1] = force_reg (SImode, operands[1]);

    /* FIXME: RR we still need to fix up what we are doing with
       symbol_refs and other types of constants.  */
    if (CONSTANT_P (operands[1])
        && !CONST_INT_P (operands[1]))
     {
       aarch64_expand_mov_immediate (operands[0], operands[1]);
       DONE;
     }
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1057 */
rtx
gen_movdi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1061 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

    if (MEM_P (operands[0]) && CONST_INT_P (operands[1])
	&& DImode == DImode
	&& aarch64_split_dimode_const_store (operands[0], operands[1]))
      DONE;

    if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
      operands[1] = force_reg (DImode, operands[1]);

    /* FIXME: RR we still need to fix up what we are doing with
       symbol_refs and other types of constants.  */
    if (CONSTANT_P (operands[1])
        && !CONST_INT_P (operands[1]))
     {
       aarch64_expand_mov_immediate (operands[0], operands[1]);
       DONE;
     }
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1081 */
extern rtx_insn *gen_split_9 (rtx_insn *, rtx *);
rtx_insn *
gen_split_9 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_9\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1106 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
       aarch64_expand_mov_immediate (operands[0], operands[1]);
       DONE;
    }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1116 */
extern rtx_insn *gen_split_10 (rtx_insn *, rtx *);
rtx_insn *
gen_split_10 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_10\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1142 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
       aarch64_expand_mov_immediate (operands[0], operands[1]);
       DONE;
    }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1164 */
rtx
gen_movti (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1168 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

    if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
      operands[1] = force_reg (TImode, operands[1]);

    if (GET_CODE (operands[1]) == CONST_POLY_INT)
      {
	emit_move_insn (gen_lowpart (DImode, operands[0]),
			gen_lowpart (DImode, operands[1]));
	emit_move_insn (gen_highpart (DImode, operands[0]), const0_rtx);
	DONE;
      }
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1209 */
extern rtx_insn *gen_split_11 (rtx_insn *, rtx *);
rtx_insn *
gen_split_11 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_11\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1214 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  aarch64_split_128bit_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1219 */
rtx
gen_movhf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1223 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (!TARGET_FLOAT)
      {
	aarch64_err_no_fpadvsimd (HFmode);
	FAIL;
      }

    if (GET_CODE (operands[0]) == MEM
        && ! (GET_CODE (operands[1]) == CONST_DOUBLE
	      && aarch64_float_const_zero_rtx_p (operands[1])))
      operands[1] = force_reg (HFmode, operands[1]);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1219 */
rtx
gen_movsf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1223 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (!TARGET_FLOAT)
      {
	aarch64_err_no_fpadvsimd (SFmode);
	FAIL;
      }

    if (GET_CODE (operands[0]) == MEM
        && ! (GET_CODE (operands[1]) == CONST_DOUBLE
	      && aarch64_float_const_zero_rtx_p (operands[1])))
      operands[1] = force_reg (SFmode, operands[1]);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1219 */
rtx
gen_movdf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1223 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (!TARGET_FLOAT)
      {
	aarch64_err_no_fpadvsimd (DFmode);
	FAIL;
      }

    if (GET_CODE (operands[0]) == MEM
        && ! (GET_CODE (operands[1]) == CONST_DOUBLE
	      && aarch64_float_const_zero_rtx_p (operands[1])))
      operands[1] = force_reg (DFmode, operands[1]);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1219 */
rtx
gen_movtf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1223 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (!TARGET_FLOAT)
      {
	aarch64_err_no_fpadvsimd (TFmode);
	FAIL;
      }

    if (GET_CODE (operands[0]) == MEM
        && ! (GET_CODE (operands[1]) == CONST_DOUBLE
	      && aarch64_float_const_zero_rtx_p (operands[1])))
      operands[1] = force_reg (TFmode, operands[1]);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1308 */
extern rtx_insn *gen_split_12 (rtx_insn *, rtx *);
rtx_insn *
gen_split_12 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_12\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1316 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    unsigned HOST_WIDE_INT ival;
    if (!aarch64_reinterpret_float_as_int (operands[1], &ival))
      FAIL;

    rtx tmp = gen_reg_rtx (HImode);
    emit_move_insn (tmp, gen_int_mode (ival, HImode));
    emit_move_insn (operands[0], gen_lowpart (HFmode, tmp));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1308 */
extern rtx_insn *gen_split_13 (rtx_insn *, rtx *);
rtx_insn *
gen_split_13 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_13\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1316 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    unsigned HOST_WIDE_INT ival;
    if (!aarch64_reinterpret_float_as_int (operands[1], &ival))
      FAIL;

    rtx tmp = gen_reg_rtx (SImode);
    emit_move_insn (tmp, gen_int_mode (ival, SImode));
    emit_move_insn (operands[0], gen_lowpart (SFmode, tmp));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1308 */
extern rtx_insn *gen_split_14 (rtx_insn *, rtx *);
rtx_insn *
gen_split_14 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_14\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1316 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    unsigned HOST_WIDE_INT ival;
    if (!aarch64_reinterpret_float_as_int (operands[1], &ival))
      FAIL;

    rtx tmp = gen_reg_rtx (DImode);
    emit_move_insn (tmp, gen_int_mode (ival, DImode));
    emit_move_insn (operands[0], gen_lowpart (DFmode, tmp));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1353 */
extern rtx_insn *gen_split_15 (rtx_insn *, rtx *);
rtx_insn *
gen_split_15 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_15\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1358 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    aarch64_split_128bit_move (operands[0], operands[1]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1369 */
rtx
gen_movmemdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1375 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_expand_movmem (operands))
    DONE;
  FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1585 */
rtx
gen_extendsidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1585 */
rtx
gen_zero_extendsidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1645 */
rtx
gen_extendqisi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1645 */
rtx
gen_zero_extendqisi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1645 */
rtx
gen_extendqidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1645 */
rtx
gen_zero_extendqidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1645 */
rtx
gen_extendhisi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1645 */
rtx
gen_zero_extendhisi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1645 */
rtx
gen_extendhidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1645 */
rtx
gen_zero_extendhidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1673 */
rtx
gen_extendqihi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1673 */
rtx
gen_zero_extendqihi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1703 */
rtx
gen_addsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1709 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  /* If operands[1] is a subreg extract the inner RTX.  */
  rtx op1 = REG_P (operands[1]) ? operands[1] : SUBREG_REG (operands[1]);

  /* If the constant is too large for a single instruction and isn't frame
     based, split off the immediate so it is available for CSE.  */
  if (!aarch64_plus_immediate (operands[2], SImode)
      && can_create_pseudo_p ()
      && (!REG_P (op1)
	 || !REGNO_PTR_FRAME_P (REGNO (op1))))
    operands[2] = force_reg (SImode, operands[2]);
  /* Expand polynomial additions now if the destination is the stack
     pointer, since we don't want to use that as a temporary.  */
  else if (operands[0] == stack_pointer_rtx
	   && aarch64_split_add_offset_immediate (operands[2], SImode))
    {
      aarch64_split_add_offset (SImode, operands[0], operands[1],
				operands[2], NULL_RTX, NULL_RTX);
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1703 */
rtx
gen_adddi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1709 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  /* If operands[1] is a subreg extract the inner RTX.  */
  rtx op1 = REG_P (operands[1]) ? operands[1] : SUBREG_REG (operands[1]);

  /* If the constant is too large for a single instruction and isn't frame
     based, split off the immediate so it is available for CSE.  */
  if (!aarch64_plus_immediate (operands[2], DImode)
      && can_create_pseudo_p ()
      && (!REG_P (op1)
	 || !REGNO_PTR_FRAME_P (REGNO (op1))))
    operands[2] = force_reg (DImode, operands[2]);
  /* Expand polynomial additions now if the destination is the stack
     pointer, since we don't want to use that as a temporary.  */
  else if (operands[0] == stack_pointer_rtx
	   && aarch64_split_add_offset_immediate (operands[2], DImode))
    {
      aarch64_split_add_offset (DImode, operands[0], operands[1],
				operands[2], NULL_RTX, NULL_RTX);
      DONE;
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1768 */
extern rtx_insn *gen_peephole2_1 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_1 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[3] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_1\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	copy_rtx (operand3))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1768 */
extern rtx_insn *gen_peephole2_2 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_2 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[3] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_2\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	copy_rtx (operand3))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1779 */
extern rtx_insn *gen_peephole2_3 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_3 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[3] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_3\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_PLUS (SImode,
	operand1,
	copy_rtx (operand3)))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1793 */
extern rtx_insn *gen_split_16 (rtx_insn *, rtx *);
rtx_insn *
gen_split_16 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_16\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1801 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT i = INTVAL (operands[2]);
    HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff));
    operands[3] = GEN_INT (i - s);
    operands[4] = GEN_INT (s);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_PLUS (SImode,
	copy_rtx (operand0),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1793 */
extern rtx_insn *gen_split_17 (rtx_insn *, rtx *);
rtx_insn *
gen_split_17 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_17\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1801 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT i = INTVAL (operands[2]);
    HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff));
    operands[3] = GEN_INT (i - s);
    operands[4] = GEN_INT (s);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_PLUS (DImode,
	copy_rtx (operand0),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1824 */
extern rtx_insn *gen_split_18 (rtx_insn *, rtx *);
rtx_insn *
gen_split_18 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_18\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1842 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    aarch64_split_add_offset (SImode, operands[0], operands[1],
			      operands[2], operands[0], NULL_RTX);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1824 */
extern rtx_insn *gen_split_19 (rtx_insn *, rtx *);
rtx_insn *
gen_split_19 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_19\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1842 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    aarch64_split_add_offset (DImode, operands[0], operands[1],
			      operands[2], operands[0], NULL_RTX);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1851 */
extern rtx_insn *gen_split_20 (rtx_insn *, rtx *);
rtx_insn *
gen_split_20 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_20\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1860 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT i = INTVAL (operands[2]);
    HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff));
    operands[3] = GEN_INT (i - s);
    operands[4] = GEN_INT (s);
    operands[5] = gen_lowpart (SImode, operands[0]);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand5,
	gen_rtx_PLUS (SImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_PLUS (SImode,
	copy_rtx (operand5),
	operand4))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1869 */
rtx
gen_addvsi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1875 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (CONST_INT_P (operands[2]))
    emit_insn (gen_addsi3_compareV_imm (operands[0], operands[1],
					    operands[2]));
  else
    emit_insn (gen_addsi3_compareV (operands[0], operands[1], operands[2]));
  aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1869 */
rtx
gen_addvdi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1875 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (CONST_INT_P (operands[2]))
    emit_insn (gen_adddi3_compareV_imm (operands[0], operands[1],
					    operands[2]));
  else
    emit_insn (gen_adddi3_compareV (operands[0], operands[1], operands[2]));
  aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1886 */
rtx
gen_uaddvsi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1892 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  emit_insn (gen_addsi3_compareC (operands[0], operands[1], operands[2]));
  aarch64_gen_unlikely_cbranch (LTU, CC_Cmode, operands[3]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1886 */
rtx
gen_uaddvdi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1892 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  emit_insn (gen_adddi3_compareC (operands[0], operands[1], operands[2]));
  aarch64_gen_unlikely_cbranch (LTU, CC_Cmode, operands[3]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1899 */
rtx
gen_addti3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1904 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high;

  aarch64_addti_scratch_regs (operands[1], operands[2],
			      &low_dest, &op1_low, &op2_low,
			      &high_dest, &op1_high, &op2_high);

  if (op2_low == const0_rtx)
    {
      low_dest = op1_low;
      if (!aarch64_pluslong_operand (op2_high, DImode))
	op2_high = force_reg (DImode, op2_high);
      emit_insn (gen_adddi3 (high_dest, op1_high, op2_high));
    }
  else
    {
      emit_insn (gen_adddi3_compareC (low_dest, op1_low,
				      force_reg (DImode, op2_low)));
      emit_insn (gen_adddi3_carryin (high_dest, op1_high,
				     force_reg (DImode, op2_high)));
    }

  emit_move_insn (gen_lowpart (DImode, operands[0]), low_dest);
  emit_move_insn (gen_highpart (DImode, operands[0]), high_dest);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (TImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1932 */
rtx
gen_addvti4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1938 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high;

  aarch64_addti_scratch_regs (operands[1], operands[2],
			      &low_dest, &op1_low, &op2_low,
			      &high_dest, &op1_high, &op2_high);

  if (op2_low == const0_rtx)
    {
      low_dest = op1_low;
      emit_insn (gen_adddi3_compareV (high_dest, op1_high,
				      force_reg (DImode, op2_high)));
    }
  else
    {
      emit_insn (gen_adddi3_compareC (low_dest, op1_low,
				      force_reg (DImode, op2_low)));
      emit_insn (gen_adddi3_carryinV (high_dest, op1_high,
				      force_reg (DImode, op2_high)));
    }

  emit_move_insn (gen_lowpart (DImode, operands[0]), low_dest);
  emit_move_insn (gen_highpart (DImode, operands[0]), high_dest);

  aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:1966 */
rtx
gen_uaddvti4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1972 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high;

  aarch64_addti_scratch_regs (operands[1], operands[2],
			      &low_dest, &op1_low, &op2_low,
			      &high_dest, &op1_high, &op2_high);

  if (op2_low == const0_rtx)
    {
      low_dest = op1_low;
      emit_insn (gen_adddi3_compareC (high_dest, op1_high,
				      force_reg (DImode, op2_high)));
    }
  else
    {
      emit_insn (gen_adddi3_compareC (low_dest, op1_low,
				      force_reg (DImode, op2_low)));
      emit_insn (gen_adddi3_carryinC (high_dest, op1_high,
				      force_reg (DImode, op2_high)));
    }

  emit_move_insn (gen_lowpart (DImode, operands[0]), low_dest);
  emit_move_insn (gen_highpart (DImode, operands[0]), high_dest);

  aarch64_gen_unlikely_cbranch (GEU, CC_ADCmode, operands[3]);
  DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2456 */
rtx
gen_addsi3_carryin (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_PLUS (SImode,
	gen_rtx_LTU (SImode,
	gen_rtx_REG (CC_Cmode,
	66),
	const0_rtx),
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2456 */
rtx
gen_adddi3_carryin (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_PLUS (DImode,
	gen_rtx_LTU (DImode,
	gen_rtx_REG (CC_Cmode,
	66),
	const0_rtx),
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2496 */
rtx
gen_addsi3_carryinC (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[7];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2513 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  operands[3] = gen_rtx_REG (CC_ADCmode, CC_REGNUM);
  rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
  operands[4] = gen_rtx_LTU (DImode, ccin, const0_rtx);
  operands[5] = gen_rtx_LTU (SImode, ccin, const0_rtx);
  operands[6] = immed_wide_int_const (wi::shwi (1, DImode)
				      << GET_MODE_BITSIZE (SImode),
				      TImode);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand3,
	gen_rtx_COMPARE (CC_ADCmode,
	gen_rtx_PLUS (DImode,
	gen_rtx_PLUS (DImode,
	operand4,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1)),
	gen_rtx_ZERO_EXTEND (DImode,
	operand2)),
	operand6)),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_PLUS (SImode,
	operand5,
	copy_rtx (operand1)),
	copy_rtx (operand2))))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2496 */
rtx
gen_adddi3_carryinC (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx operand6;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[7];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2513 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  operands[3] = gen_rtx_REG (CC_ADCmode, CC_REGNUM);
  rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
  operands[4] = gen_rtx_LTU (TImode, ccin, const0_rtx);
  operands[5] = gen_rtx_LTU (DImode, ccin, const0_rtx);
  operands[6] = immed_wide_int_const (wi::shwi (1, TImode)
				      << GET_MODE_BITSIZE (DImode),
				      TImode);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand3,
	gen_rtx_COMPARE (CC_ADCmode,
	gen_rtx_PLUS (TImode,
	gen_rtx_PLUS (TImode,
	operand4,
	gen_rtx_ZERO_EXTEND (TImode,
	operand1)),
	gen_rtx_ZERO_EXTEND (TImode,
	operand2)),
	operand6)),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_PLUS (DImode,
	operand5,
	copy_rtx (operand1)),
	copy_rtx (operand2))))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2559 */
rtx
gen_addsi3_carryinV (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2579 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx cc = gen_rtx_REG (CC_Cmode, CC_REGNUM);
  operands[3] = gen_rtx_LTU (DImode, cc, const0_rtx);
  operands[4] = gen_rtx_LTU (SImode, cc, const0_rtx);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_PLUS (DImode,
	gen_rtx_PLUS (DImode,
	operand3,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1)),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_PLUS (SImode,
	gen_rtx_PLUS (SImode,
	operand4,
	copy_rtx (operand1)),
	copy_rtx (operand2))))),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_PLUS (SImode,
	copy_rtx (operand4),
	copy_rtx (operand1)),
	copy_rtx (operand2))))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2559 */
rtx
gen_adddi3_carryinV (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2579 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx cc = gen_rtx_REG (CC_Cmode, CC_REGNUM);
  operands[3] = gen_rtx_LTU (TImode, cc, const0_rtx);
  operands[4] = gen_rtx_LTU (DImode, cc, const0_rtx);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_PLUS (TImode,
	gen_rtx_PLUS (TImode,
	operand3,
	gen_rtx_SIGN_EXTEND (TImode,
	operand1)),
	gen_rtx_SIGN_EXTEND (TImode,
	operand2)),
	gen_rtx_SIGN_EXTEND (TImode,
	gen_rtx_PLUS (DImode,
	gen_rtx_PLUS (DImode,
	operand4,
	copy_rtx (operand1)),
	copy_rtx (operand2))))),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_PLUS (DImode,
	copy_rtx (operand4),
	copy_rtx (operand1)),
	copy_rtx (operand2))))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2721 */
rtx
gen_subvsi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2727 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (CONST_INT_P (operands[2]))
    emit_insn (gen_subvsi_imm (operands[0], operands[1], operands[2]));
  else
    emit_insn (gen_subvsi_insn (operands[0], operands[1], operands[2]));
  aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2721 */
rtx
gen_subvdi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2727 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (CONST_INT_P (operands[2]))
    emit_insn (gen_subvdi_imm (operands[0], operands[1], operands[2]));
  else
    emit_insn (gen_subvdi_insn (operands[0], operands[1], operands[2]));
  aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2771 */
rtx
gen_negvsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2776 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    emit_insn (gen_negvsi_insn (operands[0], operands[1]));
    aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2771 */
rtx
gen_negvdi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2776 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    emit_insn (gen_negvdi_insn (operands[0], operands[1]));
    aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2824 */
rtx
gen_usubvsi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2830 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  emit_insn (gen_subsi3_compare1 (operands[0], operands[1], operands[2]));
  aarch64_gen_unlikely_cbranch (LTU, CCmode, operands[3]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2824 */
rtx
gen_usubvdi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2830 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  emit_insn (gen_subdi3_compare1 (operands[0], operands[1], operands[2]));
  aarch64_gen_unlikely_cbranch (LTU, CCmode, operands[3]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2837 */
rtx
gen_subti3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2842 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high;

  aarch64_subvti_scratch_regs (operands[1], operands[2],
			       &low_dest, &op1_low, &op2_low,
			       &high_dest, &op1_high, &op2_high);

  emit_insn (gen_subdi3_compare1 (low_dest, op1_low, op2_low));
  emit_insn (gen_subdi3_carryin (high_dest, op1_high, op2_high));

  emit_move_insn (gen_lowpart (DImode, operands[0]), low_dest);
  emit_move_insn (gen_highpart (DImode, operands[0]), high_dest);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MINUS (TImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2857 */
rtx
gen_subvti4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2863 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high;

  aarch64_subvti_scratch_regs (operands[1], operands[2],
			       &low_dest, &op1_low, &op2_low,
			       &high_dest, &op1_high, &op2_high);
  aarch64_expand_subvti (operands[0], low_dest, op1_low, op2_low,
			 high_dest, op1_high, op2_high, false);

  aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2876 */
rtx
gen_usubvti4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2882 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx low_dest, op1_low, op2_low, high_dest, op1_high, op2_high;

  aarch64_subvti_scratch_regs (operands[1], operands[2],
				    &low_dest, &op1_low, &op2_low,
			       &high_dest, &op1_high, &op2_high);
  aarch64_expand_subvti (operands[0], low_dest, op1_low, op2_low,
			 high_dest, op1_high, op2_high, true);

  aarch64_gen_unlikely_cbranch (LTU, CCmode, operands[3]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2895 */
rtx
gen_negvti3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2900 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    emit_insn (gen_negdi_carryout (gen_lowpart (DImode, operands[0]),
				   gen_lowpart (DImode, operands[1])));
    emit_insn (gen_negvdi_carryinV (gen_highpart (DImode, operands[0]),
				    gen_highpart (DImode, operands[1])));
    aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[2]);

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_LABEL_REF (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2992 */
extern rtx_insn *gen_peephole2_4 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_4 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_4\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3003 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    emit_insn (gen_subsi3_compare1 (operands[0], operands[1],
					 operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:2992 */
extern rtx_insn *gen_peephole2_5 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_5 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_5\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3003 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    emit_insn (gen_subdi3_compare1 (operands[0], operands[1],
					 operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3013 */
extern rtx_insn *gen_peephole2_6 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_6 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_6\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3023 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    emit_insn (gen_subsi3_compare1 (operands[0], operands[1],
					 operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3013 */
extern rtx_insn *gen_peephole2_7 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_7 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_7\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3023 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    emit_insn (gen_subdi3_compare1 (operands[0], operands[1],
					 operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3030 */
extern rtx_insn *gen_peephole2_8 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_8 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_8\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3041 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    emit_insn (gen_subsi3_compare1_imm (operands[0], operands[1],
					 operands[3], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3030 */
extern rtx_insn *gen_peephole2_9 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_9 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_9\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3041 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    emit_insn (gen_subdi3_compare1_imm (operands[0], operands[1],
					 operands[3], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3051 */
extern rtx_insn *gen_peephole2_10 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_10 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_10\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3061 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    emit_insn (gen_subsi3_compare1_imm (operands[0], operands[1],
					 operands[3], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3051 */
extern rtx_insn *gen_peephole2_11 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_11 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_11\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3061 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    emit_insn (gen_subdi3_compare1_imm (operands[0], operands[1],
					 operands[3], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3218 */
rtx
gen_subsi3_carryin (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2),
	gen_rtx_LTU (SImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3218 */
rtx
gen_subdi3_carryin (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2),
	gen_rtx_LTU (DImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3283 */
rtx
gen_usubsi3_carryinC (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1),
	gen_rtx_PLUS (DImode,
	gen_rtx_ZERO_EXTEND (DImode,
	operand2),
	gen_rtx_LTU (DImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx)))),
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2),
	gen_rtx_LTU (SImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3283 */
rtx
gen_usubdi3_carryinC (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	gen_rtx_ZERO_EXTEND (TImode,
	operand1),
	gen_rtx_PLUS (TImode,
	gen_rtx_ZERO_EXTEND (TImode,
	operand2),
	gen_rtx_LTU (TImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx)))),
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2),
	gen_rtx_LTU (DImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3350 */
rtx
gen_subsi3_carryinV (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_MINUS (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_PLUS (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2),
	gen_rtx_LTU (DImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx))),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_MINUS (SImode,
	operand1,
	gen_rtx_PLUS (SImode,
	gen_rtx_LTU (SImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx),
	operand2))))),
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2),
	gen_rtx_LTU (SImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3350 */
rtx
gen_subdi3_carryinV (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Vmode,
	66),
	gen_rtx_COMPARE (CC_Vmode,
	gen_rtx_MINUS (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	operand1),
	gen_rtx_PLUS (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	operand2),
	gen_rtx_LTU (TImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx))),
	gen_rtx_SIGN_EXTEND (TImode,
	gen_rtx_MINUS (DImode,
	operand1,
	gen_rtx_PLUS (DImode,
	gen_rtx_LTU (DImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx),
	operand2))))),
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2),
	gen_rtx_LTU (DImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx)))));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3477 */
rtx
gen_abssi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3481 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
    rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
    emit_insn (gen_csneg3si_insn (operands[0], x, operands[1], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3477 */
rtx
gen_absdi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3481 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
    rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
    emit_insn (gen_csneg3di_insn (operands[0], x, operands[1], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3741 */
rtx
gen_mulditi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx low = gen_reg_rtx (DImode);
  emit_insn (gen_muldi3 (low, operands[1], operands[2]));

  rtx high = gen_reg_rtx (DImode);
  emit_insn (gen_smuldi3_highpart (high, operands[1], operands[2]));

  emit_move_insn (gen_lowpart (DImode, operands[0]), low);
  emit_move_insn (gen_highpart (DImode, operands[0]), high);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	operand1),
	gen_rtx_SIGN_EXTEND (TImode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3741 */
rtx
gen_umulditi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx low = gen_reg_rtx (DImode);
  emit_insn (gen_muldi3 (low, operands[1], operands[2]));

  rtx high = gen_reg_rtx (DImode);
  emit_insn (gen_umuldi3_highpart (high, operands[1], operands[2]));

  emit_move_insn (gen_lowpart (DImode, operands[0]), low);
  emit_move_insn (gen_highpart (DImode, operands[0]), high);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (TImode,
	gen_rtx_ZERO_EXTEND (TImode,
	operand1),
	gen_rtx_ZERO_EXTEND (TImode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3760 */
rtx
gen_multi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3765 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx l0 = gen_reg_rtx (DImode);
  rtx l1 = gen_lowpart (DImode, operands[1]);
  rtx l2 = gen_lowpart (DImode, operands[2]);
  rtx h0 = gen_reg_rtx (DImode);
  rtx h1 = gen_highpart (DImode, operands[1]);
  rtx h2 = gen_highpart (DImode, operands[2]);

  emit_insn (gen_muldi3 (l0, l1, l2));
  emit_insn (gen_umuldi3_highpart (h0, l1, l2));
  emit_insn (gen_madddi (h0, h1, l2, h0));
  emit_insn (gen_madddi (h0, l1, h2, h0));

  emit_move_insn (gen_lowpart (DImode, operands[0]), l0);
  emit_move_insn (gen_highpart (DImode, operands[0]), h0);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (TImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3891 */
rtx
gen_cstoresi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3897 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3891 */
rtx
gen_cstoredi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3897 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3904 */
rtx
gen_cstorecc4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3910 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  emit_insn (gen_rtx_SET (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3916 */
rtx
gen_cstoresf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3922 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3916 */
rtx
gen_cstoredf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3922 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3948 */
extern rtx_insn *gen_split_21 (rtx_insn *, rtx *);
rtx_insn *
gen_split_21 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_21\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3959 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[2]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[2]) & 0xfff000;
    rtx tmp = gen_reg_rtx (SImode);
    emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (-hi_imm)));
    emit_insn (gen_addsi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (EQ, SImode, cc_reg, const0_rtx);
    emit_insn (gen_aarch64_cstoresi (operands[0], cmp_rtx, cc_reg));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3948 */
extern rtx_insn *gen_split_22 (rtx_insn *, rtx *);
rtx_insn *
gen_split_22 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_22\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3959 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[2]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[2]) & 0xfff000;
    rtx tmp = gen_reg_rtx (SImode);
    emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (-hi_imm)));
    emit_insn (gen_addsi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (NE, SImode, cc_reg, const0_rtx);
    emit_insn (gen_aarch64_cstoresi (operands[0], cmp_rtx, cc_reg));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3948 */
extern rtx_insn *gen_split_23 (rtx_insn *, rtx *);
rtx_insn *
gen_split_23 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_23\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3959 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[2]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[2]) & 0xfff000;
    rtx tmp = gen_reg_rtx (DImode);
    emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (-hi_imm)));
    emit_insn (gen_adddi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (EQ, DImode, cc_reg, const0_rtx);
    emit_insn (gen_aarch64_cstoredi (operands[0], cmp_rtx, cc_reg));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:3948 */
extern rtx_insn *gen_split_24 (rtx_insn *, rtx *);
rtx_insn *
gen_split_24 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_24\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3959 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[2]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[2]) & 0xfff000;
    rtx tmp = gen_reg_rtx (DImode);
    emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (-hi_imm)));
    emit_insn (gen_adddi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (NE, DImode, cc_reg, const0_rtx);
    emit_insn (gen_aarch64_cstoredi (operands[0], cmp_rtx, cc_reg));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4004 */
rtx
gen_cmovsi6 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4013 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3),
	operand4,
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4004 */
rtx
gen_cmovdi6 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4013 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3),
	operand4,
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4020 */
rtx
gen_cmovsf6 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4029 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3),
	operand4,
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4020 */
rtx
gen_cmovdf6 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4029 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3),
	operand4,
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4104 */
rtx
gen_movqicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4110 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				     XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (QImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4104 */
rtx
gen_movhicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4110 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				     XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (HImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4104 */
rtx
gen_movsicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4110 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				     XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4104 */
rtx
gen_movdicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4110 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				     XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4123 */
rtx
gen_movsfsicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4129 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				  XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4123 */
rtx
gen_movsfdicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4129 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				  XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4123 */
rtx
gen_movdfsicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4129 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				  XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4123 */
rtx
gen_movdfdicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4129 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				  XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4142 */
rtx
gen_movsfcc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4148 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				  XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SFmode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4142 */
rtx
gen_movdfcc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4148 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				  XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DFmode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4161 */
rtx
gen_negsicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4167 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				      XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	gen_rtx_NEG (SImode,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4161 */
rtx
gen_notsicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4167 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				      XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	gen_rtx_NOT (SImode,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4161 */
rtx
gen_negdicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4167 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				      XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	gen_rtx_NEG (DImode,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4161 */
rtx
gen_notdicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4167 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				      XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	gen_rtx_NOT (DImode,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4277 */
rtx
gen_umaxsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4282 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (aarch64_sve_cnt_immediate (operands[1], SImode))
      std::swap (operands[1], operands[2]);
    else if (!aarch64_sve_cnt_immediate (operands[2], SImode))
      FAIL;
    rtx temp = gen_reg_rtx (SImode);
    operands[1] = force_reg (SImode, operands[1]);
    emit_insn (gen_aarch64_uqdecsi (temp, operands[1], operands[2]));
    emit_insn (gen_addsi3 (operands[0], temp, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UMAX (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4277 */
rtx
gen_umaxdi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4282 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (aarch64_sve_cnt_immediate (operands[1], DImode))
      std::swap (operands[1], operands[2]);
    else if (!aarch64_sve_cnt_immediate (operands[2], DImode))
      FAIL;
    rtx temp = gen_reg_rtx (DImode);
    operands[1] = force_reg (DImode, operands[1]);
    emit_insn (gen_aarch64_uqdecdi (temp, operands[1], operands[2]));
    emit_insn (gen_adddi3 (operands[0], temp, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UMAX (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4313 */
extern rtx_insn *gen_split_25 (rtx_insn *, rtx *);
rtx_insn *
gen_split_25 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_25\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4321 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
     HOST_WIDE_INT val = INTVAL (operands[2]);
     rtx imm1 = GEN_INT (aarch64_and_split_imm1 (val));
     rtx imm2 = GEN_INT (aarch64_and_split_imm2 (val));

     emit_insn (gen_andsi3 (operands[0], operands[1], imm1));
     emit_insn (gen_andsi3 (operands[0], operands[0], imm2));
     DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4313 */
extern rtx_insn *gen_split_26 (rtx_insn *, rtx *);
rtx_insn *
gen_split_26 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_26\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4321 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
     HOST_WIDE_INT val = INTVAL (operands[2]);
     rtx imm1 = GEN_INT (aarch64_and_split_imm1 (val));
     rtx imm2 = GEN_INT (aarch64_and_split_imm2 (val));

     emit_insn (gen_anddi3 (operands[0], operands[1], imm1));
     emit_insn (gen_anddi3 (operands[0], operands[0], imm2));
     DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4524 */
extern rtx_insn *gen_split_27 (rtx_insn *, rtx *);
rtx_insn *
gen_split_27 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_27\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4537 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_NOT (SImode,
	copy_rtx (operand0))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4524 */
extern rtx_insn *gen_split_28 (rtx_insn *, rtx *);
rtx_insn *
gen_split_28 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_28\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4537 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_NOT (DImode,
	copy_rtx (operand0))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4680 */
rtx
gen_ffssi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"ffssi2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4684 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg = aarch64_gen_compare_reg (EQ, operands[1], const0_rtx);
    rtx x = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);

    emit_insn (gen_rbitsi2 (operands[0], operands[1]));
    emit_insn (gen_clzsi2 (operands[0], operands[0]));
    emit_insn (gen_csinc3si_insn (operands[0], x, operands[0], const0_rtx));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4680 */
rtx
gen_ffsdi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"ffsdi2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4684 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg = aarch64_gen_compare_reg (EQ, operands[1], const0_rtx);
    rtx x = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);

    emit_insn (gen_rbitdi2 (operands[0], operands[1]));
    emit_insn (gen_clzdi2 (operands[0], operands[0]));
    emit_insn (gen_csinc3di_insn (operands[0], x, operands[0], const0_rtx));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4702 */
rtx
gen_popcountsi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"popcountsi2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4706 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx v = gen_reg_rtx (V8QImode);
  rtx v1 = gen_reg_rtx (V8QImode);
  rtx r = gen_reg_rtx (QImode);
  rtx in = operands[1];
  rtx out = operands[0];
  if(SImode == SImode)
    {
      rtx tmp;
      tmp = gen_reg_rtx (DImode);
      /* If we have SImode, zero extend to DImode, pop count does
         not change if we have extra zeros. */
      emit_insn (gen_zero_extendsidi2 (tmp, in));
      in = tmp;
    }
  emit_move_insn (v, gen_lowpart (V8QImode, in));
  emit_insn (gen_popcountv8qi2 (v1, v));
  emit_insn (gen_reduc_plus_scal_v8qi (r, v1));
  emit_insn (gen_zero_extendqisi2 (out, r));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4702 */
rtx
gen_popcountdi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"popcountdi2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4706 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx v = gen_reg_rtx (V8QImode);
  rtx v1 = gen_reg_rtx (V8QImode);
  rtx r = gen_reg_rtx (QImode);
  rtx in = operands[1];
  rtx out = operands[0];
  if(DImode == SImode)
    {
      rtx tmp;
      tmp = gen_reg_rtx (DImode);
      /* If we have SImode, zero extend to DImode, pop count does
         not change if we have extra zeros. */
      emit_insn (gen_zero_extendsidi2 (tmp, in));
      in = tmp;
    }
  emit_move_insn (v, gen_lowpart (V8QImode, in));
  emit_insn (gen_popcountv8qi2 (v1, v));
  emit_insn (gen_reduc_plus_scal_v8qi (r, v1));
  emit_insn (gen_zero_extendqidi2 (out, r));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4749 */
extern rtx_insn *gen_split_29 (rtx_insn *, rtx *);
rtx_insn *
gen_split_29 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_29\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4756 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  emit_insn (gen_rbitsi2 (operands[0], operands[1]));
  emit_insn (gen_clzsi2 (operands[0], operands[0]));
  DONE;

#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4749 */
extern rtx_insn *gen_split_30 (rtx_insn *, rtx *);
rtx_insn *
gen_split_30 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_30\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4756 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  emit_insn (gen_rbitdi2 (operands[0], operands[1]));
  emit_insn (gen_clzdi2 (operands[0], operands[0]));
  DONE;

#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4797 */
extern rtx_insn *gen_split_31 (rtx_insn *, rtx *);
rtx_insn *
gen_split_31 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_31\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand2,
	operand1));
  emit_insn (gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_AND (SImode,
	operand0,
	copy_rtx (operand2)),
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4797 */
extern rtx_insn *gen_split_32 (rtx_insn *, rtx *);
rtx_insn *
gen_split_32 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_32\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand2,
	operand1));
  emit_insn (gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_AND (DImode,
	operand0,
	copy_rtx (operand2)),
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4848 */
extern rtx_insn *gen_split_33 (rtx_insn *, rtx *);
rtx_insn *
gen_split_33 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_33\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_AND (SImode,
	gen_rtx_ASHIFT (SImode,
	operand0,
	operand1),
	copy_rtx (operand3)),
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4848 */
extern rtx_insn *gen_split_34 (rtx_insn *, rtx *);
rtx_insn *
gen_split_34 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_34\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_AND (SImode,
	gen_rtx_ASHIFTRT (SImode,
	operand0,
	operand1),
	copy_rtx (operand3)),
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4848 */
extern rtx_insn *gen_split_35 (rtx_insn *, rtx *);
rtx_insn *
gen_split_35 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_35\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_AND (SImode,
	gen_rtx_LSHIFTRT (SImode,
	operand0,
	operand1),
	copy_rtx (operand3)),
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4848 */
extern rtx_insn *gen_split_36 (rtx_insn *, rtx *);
rtx_insn *
gen_split_36 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_36\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_AND (SImode,
	gen_rtx_ROTATERT (SImode,
	operand0,
	operand1),
	copy_rtx (operand3)),
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4848 */
extern rtx_insn *gen_split_37 (rtx_insn *, rtx *);
rtx_insn *
gen_split_37 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_37\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_AND (DImode,
	gen_rtx_ASHIFT (DImode,
	operand0,
	operand1),
	copy_rtx (operand3)),
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4848 */
extern rtx_insn *gen_split_38 (rtx_insn *, rtx *);
rtx_insn *
gen_split_38 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_38\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_AND (DImode,
	gen_rtx_ASHIFTRT (DImode,
	operand0,
	operand1),
	copy_rtx (operand3)),
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4848 */
extern rtx_insn *gen_split_39 (rtx_insn *, rtx *);
rtx_insn *
gen_split_39 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_39\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_AND (DImode,
	gen_rtx_LSHIFTRT (DImode,
	operand0,
	operand1),
	copy_rtx (operand3)),
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4848 */
extern rtx_insn *gen_split_40 (rtx_insn *, rtx *);
rtx_insn *
gen_split_40 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_40\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_AND (DImode,
	gen_rtx_ROTATERT (DImode,
	operand0,
	operand1),
	copy_rtx (operand3)),
	const0_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4872 */
rtx
gen_ashlsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (SImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movsi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4872 */
rtx
gen_ashrsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (SImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movsi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4872 */
rtx
gen_lshrsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (SImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movsi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4872 */
rtx
gen_ashldi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (DImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movdi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4872 */
rtx
gen_ashrdi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (DImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movdi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4872 */
rtx
gen_lshrdi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4877 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (DImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movdi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4892 */
rtx
gen_ashlqi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4897 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    operands[2] = GEN_INT (INTVAL (operands[2]) & GET_MODE_MASK (QImode));

    if (operands[2] == const0_rtx)
      {
	emit_insn (gen_movqi (operands[0], operands[1]));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (QImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4892 */
rtx
gen_ashlhi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4897 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    operands[2] = GEN_INT (INTVAL (operands[2]) & GET_MODE_MASK (HImode));

    if (operands[2] == const0_rtx)
      {
	emit_insn (gen_movhi (operands[0], operands[1]));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (HImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4908 */
rtx
gen_rotrsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4913 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (SImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movsi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ROTATERT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4908 */
rtx
gen_rotrdi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4913 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (DImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movdi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ROTATERT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4928 */
rtx
gen_rotlsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4933 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    /* (SZ - cnt) % SZ == -cnt % SZ */
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT ((-INTVAL (operands[2]))
			       & (GET_MODE_BITSIZE (SImode) - 1));
        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movsi (operands[0], operands[1]));
	    DONE;
          }
      }
    else
      operands[2] = expand_simple_unop (QImode, NEG, operands[2],
					NULL_RTX, 1);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ROTATERT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4928 */
rtx
gen_rotldi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4933 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    /* (SZ - cnt) % SZ == -cnt % SZ */
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT ((-INTVAL (operands[2]))
			       & (GET_MODE_BITSIZE (DImode) - 1));
        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movdi (operands[0], operands[1]));
	    DONE;
          }
      }
    else
      operands[2] = expand_simple_unop (QImode, NEG, operands[2],
					NULL_RTX, 1);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ROTATERT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4971 */
extern rtx_insn *gen_split_41 (rtx_insn *, rtx *);
rtx_insn *
gen_split_41 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_41\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4982 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : lowpart_subreg (SImode, operands[0], SImode));
    emit_insn (gen_negsi2 (tmp, operands[2]));

    rtx and_op = gen_rtx_AND (SImode, tmp, operands[3]);
    rtx subreg_tmp = gen_rtx_SUBREG (GET_MODE (operands[4]), and_op,
				     SUBREG_BYTE (operands[4]));
    emit_insn (gen_ashlsi3 (operands[0], operands[1], subreg_tmp));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4971 */
extern rtx_insn *gen_split_42 (rtx_insn *, rtx *);
rtx_insn *
gen_split_42 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_42\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4982 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : lowpart_subreg (SImode, operands[0], SImode));
    emit_insn (gen_negsi2 (tmp, operands[2]));

    rtx and_op = gen_rtx_AND (SImode, tmp, operands[3]);
    rtx subreg_tmp = gen_rtx_SUBREG (GET_MODE (operands[4]), and_op,
				     SUBREG_BYTE (operands[4]));
    emit_insn (gen_ashrsi3 (operands[0], operands[1], subreg_tmp));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4971 */
extern rtx_insn *gen_split_43 (rtx_insn *, rtx *);
rtx_insn *
gen_split_43 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_43\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4982 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : lowpart_subreg (SImode, operands[0], SImode));
    emit_insn (gen_negsi2 (tmp, operands[2]));

    rtx and_op = gen_rtx_AND (SImode, tmp, operands[3]);
    rtx subreg_tmp = gen_rtx_SUBREG (GET_MODE (operands[4]), and_op,
				     SUBREG_BYTE (operands[4]));
    emit_insn (gen_lshrsi3 (operands[0], operands[1], subreg_tmp));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4971 */
extern rtx_insn *gen_split_44 (rtx_insn *, rtx *);
rtx_insn *
gen_split_44 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_44\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4982 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : lowpart_subreg (SImode, operands[0], SImode));
    emit_insn (gen_negsi2 (tmp, operands[2]));

    rtx and_op = gen_rtx_AND (SImode, tmp, operands[3]);
    rtx subreg_tmp = gen_rtx_SUBREG (GET_MODE (operands[4]), and_op,
				     SUBREG_BYTE (operands[4]));
    emit_insn (gen_rotrsi3 (operands[0], operands[1], subreg_tmp));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4971 */
extern rtx_insn *gen_split_45 (rtx_insn *, rtx *);
rtx_insn *
gen_split_45 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_45\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4982 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : lowpart_subreg (SImode, operands[0], DImode));
    emit_insn (gen_negsi2 (tmp, operands[2]));

    rtx and_op = gen_rtx_AND (SImode, tmp, operands[3]);
    rtx subreg_tmp = gen_rtx_SUBREG (GET_MODE (operands[4]), and_op,
				     SUBREG_BYTE (operands[4]));
    emit_insn (gen_ashldi3 (operands[0], operands[1], subreg_tmp));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4971 */
extern rtx_insn *gen_split_46 (rtx_insn *, rtx *);
rtx_insn *
gen_split_46 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_46\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4982 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : lowpart_subreg (SImode, operands[0], DImode));
    emit_insn (gen_negsi2 (tmp, operands[2]));

    rtx and_op = gen_rtx_AND (SImode, tmp, operands[3]);
    rtx subreg_tmp = gen_rtx_SUBREG (GET_MODE (operands[4]), and_op,
				     SUBREG_BYTE (operands[4]));
    emit_insn (gen_ashrdi3 (operands[0], operands[1], subreg_tmp));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4971 */
extern rtx_insn *gen_split_47 (rtx_insn *, rtx *);
rtx_insn *
gen_split_47 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_47\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4982 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : lowpart_subreg (SImode, operands[0], DImode));
    emit_insn (gen_negsi2 (tmp, operands[2]));

    rtx and_op = gen_rtx_AND (SImode, tmp, operands[3]);
    rtx subreg_tmp = gen_rtx_SUBREG (GET_MODE (operands[4]), and_op,
				     SUBREG_BYTE (operands[4]));
    emit_insn (gen_lshrdi3 (operands[0], operands[1], subreg_tmp));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4971 */
extern rtx_insn *gen_split_48 (rtx_insn *, rtx *);
rtx_insn *
gen_split_48 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_48\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4982 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : lowpart_subreg (SImode, operands[0], DImode));
    emit_insn (gen_negsi2 (tmp, operands[2]));

    rtx and_op = gen_rtx_AND (SImode, tmp, operands[3]);
    rtx subreg_tmp = gen_rtx_SUBREG (GET_MODE (operands[4]), and_op,
				     SUBREG_BYTE (operands[4]));
    emit_insn (gen_rotrdi3 (operands[0], operands[1], subreg_tmp));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4995 */
extern rtx_insn *gen_split_49 (rtx_insn *, rtx *);
rtx_insn *
gen_split_49 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_49\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5008 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : operands[0]);

    emit_insn (gen_negsi2 (tmp, operands[3]));

    rtx and_op = gen_rtx_AND (SImode, tmp, operands[4]);
    rtx subreg_tmp = gen_rtx_SUBREG (GET_MODE (operands[5]), and_op,
				     SUBREG_BYTE (operands[5]));

    emit_insn (gen_ashlsi3 (operands[0], operands[1], subreg_tmp));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:4995 */
extern rtx_insn *gen_split_50 (rtx_insn *, rtx *);
rtx_insn *
gen_split_50 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_50\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5008 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : operands[0]);

    emit_insn (gen_negsi2 (tmp, operands[3]));

    rtx and_op = gen_rtx_AND (SImode, tmp, operands[4]);
    rtx subreg_tmp = gen_rtx_SUBREG (GET_MODE (operands[5]), and_op,
				     SUBREG_BYTE (operands[5]));

    emit_insn (gen_ashldi3 (operands[0], operands[1], subreg_tmp));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5042 */
extern rtx_insn *gen_split_51 (rtx_insn *, rtx *);
rtx_insn *
gen_split_51 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_51\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5052 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx subreg_tmp = gen_lowpart (SImode, operands[3]);

    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : gen_lowpart (SImode, operands[0]));

    emit_insn (gen_negsi2 (tmp, subreg_tmp));

    rtx and_op = gen_rtx_AND (SImode, tmp,
			      GEN_INT (GET_MODE_BITSIZE (SImode) - 1));

    rtx subreg_tmp2 = gen_lowpart_SUBREG (QImode, and_op);

    emit_insn (gen_ashlsi3 (operands[0], operands[1], subreg_tmp2));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5042 */
extern rtx_insn *gen_split_52 (rtx_insn *, rtx *);
rtx_insn *
gen_split_52 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_52\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5052 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx subreg_tmp = gen_lowpart (SImode, operands[3]);

    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : gen_lowpart (SImode, operands[0]));

    emit_insn (gen_negsi2 (tmp, subreg_tmp));

    rtx and_op = gen_rtx_AND (SImode, tmp,
			      GEN_INT (GET_MODE_BITSIZE (SImode) - 1));

    rtx subreg_tmp2 = gen_lowpart_SUBREG (QImode, and_op);

    emit_insn (gen_ashrsi3 (operands[0], operands[1], subreg_tmp2));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5042 */
extern rtx_insn *gen_split_53 (rtx_insn *, rtx *);
rtx_insn *
gen_split_53 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_53\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5052 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx subreg_tmp = gen_lowpart (SImode, operands[3]);

    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : gen_lowpart (SImode, operands[0]));

    emit_insn (gen_negsi2 (tmp, subreg_tmp));

    rtx and_op = gen_rtx_AND (SImode, tmp,
			      GEN_INT (GET_MODE_BITSIZE (SImode) - 1));

    rtx subreg_tmp2 = gen_lowpart_SUBREG (QImode, and_op);

    emit_insn (gen_lshrsi3 (operands[0], operands[1], subreg_tmp2));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5042 */
extern rtx_insn *gen_split_54 (rtx_insn *, rtx *);
rtx_insn *
gen_split_54 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_54\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5052 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx subreg_tmp = gen_lowpart (SImode, operands[3]);

    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : gen_lowpart (SImode, operands[0]));

    emit_insn (gen_negsi2 (tmp, subreg_tmp));

    rtx and_op = gen_rtx_AND (SImode, tmp,
			      GEN_INT (GET_MODE_BITSIZE (DImode) - 1));

    rtx subreg_tmp2 = gen_lowpart_SUBREG (QImode, and_op);

    emit_insn (gen_ashldi3 (operands[0], operands[1], subreg_tmp2));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5042 */
extern rtx_insn *gen_split_55 (rtx_insn *, rtx *);
rtx_insn *
gen_split_55 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_55\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5052 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx subreg_tmp = gen_lowpart (SImode, operands[3]);

    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : gen_lowpart (SImode, operands[0]));

    emit_insn (gen_negsi2 (tmp, subreg_tmp));

    rtx and_op = gen_rtx_AND (SImode, tmp,
			      GEN_INT (GET_MODE_BITSIZE (DImode) - 1));

    rtx subreg_tmp2 = gen_lowpart_SUBREG (QImode, and_op);

    emit_insn (gen_ashrdi3 (operands[0], operands[1], subreg_tmp2));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5042 */
extern rtx_insn *gen_split_56 (rtx_insn *, rtx *);
rtx_insn *
gen_split_56 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_56\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5052 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx subreg_tmp = gen_lowpart (SImode, operands[3]);

    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
	       : gen_lowpart (SImode, operands[0]));

    emit_insn (gen_negsi2 (tmp, subreg_tmp));

    rtx and_op = gen_rtx_AND (SImode, tmp,
			      GEN_INT (GET_MODE_BITSIZE (DImode) - 1));

    rtx subreg_tmp2 = gen_lowpart_SUBREG (QImode, and_op);

    emit_insn (gen_lshrdi3 (operands[0], operands[1], subreg_tmp2));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5105 */
extern rtx_insn *gen_split_57 (rtx_insn *, rtx *);
rtx_insn *
gen_split_57 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_57\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5115 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    operands[3] = gen_lowpart (QImode, operands[0]);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand2),
	53)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		copy_rtx (operand3)),
	55)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5120 */
extern rtx_insn *gen_split_58 (rtx_insn *, rtx *);
rtx_insn *
gen_split_58 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_58\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5130 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    operands[3] = gen_lowpart (QImode, operands[0]);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand2),
	53)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		copy_rtx (operand3)),
	74)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5153 */
extern rtx_insn *gen_split_59 (rtx_insn *, rtx *);
rtx_insn *
gen_split_59 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_59\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5163 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  operands[3] = gen_lowpart (QImode, operands[0]);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand2),
	53)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		copy_rtx (operand3)),
	54)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5168 */
extern rtx_insn *gen_split_60 (rtx_insn *, rtx *);
rtx_insn *
gen_split_60 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_60\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5178 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  operands[3] = gen_lowpart (QImode, operands[0]);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand2),
	53)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		copy_rtx (operand3)),
	56)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5393 */
rtx
gen_extv (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5400 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (!IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]),
		   1, GET_MODE_BITSIZE (DImode) - 1))
     FAIL;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTRACT (DImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5393 */
rtx
gen_extzv (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5400 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (!IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]),
		   1, GET_MODE_BITSIZE (DImode) - 1))
     FAIL;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5423 */
extern rtx_insn *gen_split_61 (rtx_insn *, rtx *);
rtx_insn *
gen_split_61 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_61\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5436 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    operands[4] = gen_lowpart (SImode, operands[1]);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_LSHIFTRT (SImode,
	operand4,
	operand3))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5442 */
rtx
gen_insvsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  unsigned HOST_WIDE_INT width = UINTVAL (operands[1]);
  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
  rtx value = operands[3];

  if (width == 0 || (pos + width) > GET_MODE_BITSIZE (SImode))
    FAIL;

  if (CONST_INT_P (value))
    {
      unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;

      /* Prefer AND/OR for inserting all zeros or all ones.  */
      if ((UINTVAL (value) & mask) == 0
	   || (UINTVAL (value) & mask) == mask)
	FAIL;

      /* 16-bit aligned 16-bit wide insert is handled by insv_imm.  */
      if (width == 16 && (pos % 16) == 0)
	DONE;
    }
  operands[3] = force_reg (SImode, value);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (gen_rtx_ZERO_EXTRACT (SImode,
	operand0,
	operand1,
	operand2),
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5442 */
rtx
gen_insvdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  unsigned HOST_WIDE_INT width = UINTVAL (operands[1]);
  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
  rtx value = operands[3];

  if (width == 0 || (pos + width) > GET_MODE_BITSIZE (DImode))
    FAIL;

  if (CONST_INT_P (value))
    {
      unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;

      /* Prefer AND/OR for inserting all zeros or all ones.  */
      if ((UINTVAL (value) & mask) == 0
	   || (UINTVAL (value) & mask) == mask)
	FAIL;

      /* 16-bit aligned 16-bit wide insert is handled by insv_imm.  */
      if (width == 16 && (pos % 16) == 0)
	DONE;
    }
  operands[3] = force_reg (DImode, value);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (gen_rtx_ZERO_EXTRACT (DImode,
	operand0,
	operand1,
	operand2),
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5653 */
extern rtx_insn *gen_split_62 (rtx_insn *, rtx *);
rtx_insn *
gen_split_62 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_62\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    operands[4] = gen_lowpart (SImode, operands[1]);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_ASHIFT (SImode,
	operand4,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5829 */
rtx
gen_fmahf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (HFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5829 */
rtx
gen_fmasf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (SFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5829 */
rtx
gen_fmadf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (DFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5847 */
rtx
gen_fnmahf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (HFmode,
	gen_rtx_NEG (HFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5847 */
rtx
gen_fnmasf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (SFmode,
	gen_rtx_NEG (SFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5847 */
rtx
gen_fnmadf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (DFmode,
	gen_rtx_NEG (DFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5868 */
rtx
gen_fmssf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (SFmode,
	operand1,
	operand2,
	gen_rtx_NEG (SFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5868 */
rtx
gen_fmsdf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (DFmode,
	operand1,
	operand2,
	gen_rtx_NEG (DFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5886 */
rtx
gen_fnmssf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (SFmode,
	gen_rtx_NEG (SFmode,
	operand1),
	operand2,
	gen_rtx_NEG (SFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:5886 */
rtx
gen_fnmsdf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (DFmode,
	gen_rtx_NEG (DFmode,
	operand1),
	operand2,
	gen_rtx_NEG (DFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6045 */
rtx
gen_floatsihf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6049 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (TARGET_FP_F16INST)
    emit_insn (gen_aarch64_fp16_floatsihf2 (operands[0], operands[1]));
  else
    {
      rtx convert_target = gen_reg_rtx (DFmode);
      emit_insn (gen_floatsidf2 (convert_target, operands[1]));
      emit_insn (gen_truncdfhf2 (operands[0], convert_target));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FLOAT (HFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6045 */
rtx
gen_floatunssihf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6049 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (TARGET_FP_F16INST)
    emit_insn (gen_aarch64_fp16_floatunssihf2 (operands[0], operands[1]));
  else
    {
      rtx convert_target = gen_reg_rtx (DFmode);
      emit_insn (gen_floatunssidf2 (convert_target, operands[1]));
      emit_insn (gen_truncdfhf2 (operands[0], convert_target));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (HFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6074 */
rtx
gen_floatdihf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6078 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (TARGET_FP_F16INST)
    emit_insn (gen_aarch64_fp16_floatdihf2 (operands[0], operands[1]));
  else
    {
      rtx sat_target = gen_reg_rtx (SImode);
      emit_insn (gen_aarch64_sqmovndi (sat_target, operands[1]));
      emit_insn (gen_floatsihf2 (operands[0], sat_target));
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FLOAT (HFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6074 */
rtx
gen_floatunsdihf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6078 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (TARGET_FP_F16INST)
    emit_insn (gen_aarch64_fp16_floatunsdihf2 (operands[0], operands[1]));
  else
    {
      rtx sat_target = gen_reg_rtx (SImode);
      emit_insn (gen_aarch64_uqmovndi (sat_target, operands[1]));
      emit_insn (gen_floatunssihf2 (operands[0], sat_target));
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (HFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6214 */
rtx
gen_divhf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6219 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (HFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (HFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6214 */
rtx
gen_divsf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6219 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (SFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (SFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6214 */
rtx
gen_divdf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6219 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (DFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (DFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6243 */
rtx
gen_sqrthf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrthf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6247 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (HFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6243 */
rtx
gen_sqrtsf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtsf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6247 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (SFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6243 */
rtx
gen_sqrtdf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtdf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6247 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (DFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6303 */
rtx
gen_lrintsfsi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6309 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx cvt = gen_reg_rtx (SFmode);
  emit_insn (gen_rintsf2 (cvt, operands[1]));
  emit_insn (gen_lbtruncsfsi2 (operands[0], cvt));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6303 */
rtx
gen_lrintsfdi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6309 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx cvt = gen_reg_rtx (SFmode);
  emit_insn (gen_rintsf2 (cvt, operands[1]));
  emit_insn (gen_lbtruncsfdi2 (operands[0], cvt));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6303 */
rtx
gen_lrintdfsi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6309 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx cvt = gen_reg_rtx (DFmode);
  emit_insn (gen_rintdf2 (cvt, operands[1]));
  emit_insn (gen_lbtruncdfsi2 (operands[0], cvt));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6303 */
rtx
gen_lrintdfdi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6309 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx cvt = gen_reg_rtx (DFmode);
  emit_insn (gen_rintdf2 (cvt, operands[1]));
  emit_insn (gen_lbtruncdfdi2 (operands[0], cvt));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6332 */
rtx
gen_copysignsf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"copysignsf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6337 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx bitmask = gen_reg_rtx (SImode);
  emit_move_insn (bitmask, GEN_INT (HOST_WIDE_INT_M1U
				    << (GET_MODE_BITSIZE (SFmode) - 1)));
  emit_insn (gen_copysignsf3_insn (operands[0], operands[1], operands[2],
				       bitmask));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6332 */
rtx
gen_copysigndf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"copysigndf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6337 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx bitmask = gen_reg_rtx (DImode);
  emit_move_insn (bitmask, GEN_INT (HOST_WIDE_INT_M1U
				    << (GET_MODE_BITSIZE (DFmode) - 1)));
  emit_insn (gen_copysigndf3_insn (operands[0], operands[1], operands[2],
				       bitmask));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6370 */
rtx
gen_xorsignsf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"xorsignsf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6375 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{

  machine_mode imode = SImode;
  rtx mask = gen_reg_rtx (imode);
  rtx op1x = gen_reg_rtx (imode);
  rtx op2x = gen_reg_rtx (imode);

  int bits = GET_MODE_BITSIZE (SFmode) - 1;
  emit_move_insn (mask, GEN_INT (trunc_int_for_mode (HOST_WIDE_INT_M1U << bits,
						     imode)));

  emit_insn (gen_andsi3 (op2x, mask,
				    lowpart_subreg (imode, operands[2],
						    SFmode)));
  emit_insn (gen_xorsi3 (op1x,
				    lowpart_subreg (imode, operands[1],
						    SFmode),
				    op2x));
  emit_move_insn (operands[0],
		  lowpart_subreg (SFmode, op1x, imode));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6370 */
rtx
gen_xorsigndf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"xorsigndf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6375 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{

  machine_mode imode = DImode;
  rtx mask = gen_reg_rtx (imode);
  rtx op1x = gen_reg_rtx (imode);
  rtx op2x = gen_reg_rtx (imode);

  int bits = GET_MODE_BITSIZE (DFmode) - 1;
  emit_move_insn (mask, GEN_INT (trunc_int_for_mode (HOST_WIDE_INT_M1U << bits,
						     imode)));

  emit_insn (gen_anddi3 (op2x, mask,
				    lowpart_subreg (imode, operands[2],
						    DFmode)));
  emit_insn (gen_xordi3 (op1x,
				    lowpart_subreg (imode, operands[1],
						    DFmode),
				    op2x));
  emit_move_insn (operands[0],
		  lowpart_subreg (DFmode, op1x, imode));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6404 */
rtx
gen_aarch64_reload_movcpsfsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6409 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (SFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (SFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6404 */
rtx
gen_aarch64_reload_movcpsfdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6409 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (SFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (SFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6404 */
rtx
gen_aarch64_reload_movcpdfsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6409 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (DFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (DFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6404 */
rtx
gen_aarch64_reload_movcpdfdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6409 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (DFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (DFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6404 */
rtx
gen_aarch64_reload_movcptfsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6409 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (TFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (TFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6404 */
rtx
gen_aarch64_reload_movcptfdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6409 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (TFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (TFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv8qisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V8QImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V8QImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv16qisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V16QImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V16QImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv4hisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V4HImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V4HImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv8hisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V8HImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V8HImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv2sisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2SImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2SImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv4sisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V4SImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V4SImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv2disi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2DImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2DImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv2sfsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2SFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2SFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv4sfsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V4SFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V4SFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv2dfsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2DFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2DFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv8qidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V8QImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V8QImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv16qidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V16QImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V16QImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv4hidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V4HImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V4HImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv8hidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V8HImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V8HImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv2sidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2SImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2SImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv4sidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V4SImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V4SImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv2didi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2DImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2DImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv2sfdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2SFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2SFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv4sfdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V4SFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V4SFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6417 */
rtx
gen_aarch64_reload_movcpv2dfdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6422 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2DFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2DFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6429 */
rtx
gen_aarch64_reload_movti (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6435 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx op0 = simplify_gen_subreg (TImode, operands[0], TImode, 0);
    rtx op1 = simplify_gen_subreg (TImode, operands[1], TImode, 0);
    gen_aarch64_movtilow_tilow (op0, op1);
    gen_aarch64_movdi_tihigh (operands[2], op1);
    gen_aarch64_movtihigh_di (op0, operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6429 */
rtx
gen_aarch64_reload_movtf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6435 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    rtx op0 = simplify_gen_subreg (TImode, operands[0], TFmode, 0);
    rtx op1 = simplify_gen_subreg (TImode, operands[1], TFmode, 0);
    gen_aarch64_movtilow_tilow (op0, op1);
    gen_aarch64_movdi_tihigh (operands[2], op1);
    gen_aarch64_movtihigh_di (op0, operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6503 */
rtx
gen_add_losym (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6508 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  machine_mode mode = GET_MODE (operands[0]);

  emit_insn ((mode == DImode
	      ? gen_add_losym_di
	      : gen_add_losym_si) (operands[0],
				   operands[1],
				   operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LO_SUM (VOIDmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6594 */
rtx
gen_tlsgd_small_si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6600 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  operands[2] = aarch64_tls_get_addr ();
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_CALL (VOIDmode,
	gen_rtx_MEM (DImode,
	operand2),
	const1_rtx)),
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	26),
		gen_hard_reg_clobber (DImode, 30))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6594 */
rtx
gen_tlsgd_small_di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6600 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  operands[2] = aarch64_tls_get_addr ();
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_CALL (VOIDmode,
	gen_rtx_MEM (DImode,
	operand2),
	const1_rtx)),
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	26),
		gen_hard_reg_clobber (DImode, 30))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6702 */
rtx
gen_tlsdesc_small_si (rtx operand0)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[1];
    operands[0] = operand0;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6705 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (TARGET_SVE)
      emit_insn (gen_tlsdesc_small_sve_si (operands[0]));
    else
      emit_insn (gen_tlsdesc_small_advsimd_si (operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
  }
  emit_insn (gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand0),
	65));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6702 */
rtx
gen_tlsdesc_small_di (rtx operand0)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[1];
    operands[0] = operand0;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6705 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
    if (TARGET_SVE)
      emit_insn (gen_tlsdesc_small_sve_di (operands[0]));
    else
      emit_insn (gen_tlsdesc_small_advsimd_di (operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
  }
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand0),
	65));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6877 */
rtx
gen_get_thread_pointerdi (rtx operand0)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[1];
    operands[0] = operand0;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6880 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx tmp = aarch64_load_tp (operands[0]);
  if (tmp != operands[0])
    emit_move_insn (operands[0], tmp);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
  }
  emit (operand0, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6888 */
rtx
gen_stack_protect_set (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6892 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  machine_mode mode = GET_MODE (operands[0]);
  if (aarch64_stack_protector_guard != SSP_GLOBAL)
  {
    /* Generate access through the system register.  */
    rtx tmp_reg = gen_reg_rtx (mode);
    if (mode == DImode)
    {
        emit_insn (gen_reg_stack_protect_address_di (tmp_reg));
        emit_insn (gen_adddi3 (tmp_reg, tmp_reg,
			       GEN_INT (aarch64_stack_protector_guard_offset)));
    }
    else
    {
	emit_insn (gen_reg_stack_protect_address_si (tmp_reg));
	emit_insn (gen_addsi3 (tmp_reg, tmp_reg,
			       GEN_INT (aarch64_stack_protector_guard_offset)));

    }
    operands[1] = gen_rtx_MEM (mode, tmp_reg);
  }
  
  emit_insn ((mode == DImode
	      ? gen_stack_protect_set_di
	      : gen_stack_protect_set_si) (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:6944 */
rtx
gen_stack_protect_test (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6949 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx result;
  machine_mode mode = GET_MODE (operands[0]);

  result = gen_reg_rtx(mode);
  if (aarch64_stack_protector_guard != SSP_GLOBAL)
  {
    /* Generate access through the system register. The
       sequence we want here is the access
       of the stack offset to come with
       mrs scratch_reg, <system_register>
       add scratch_reg, scratch_reg, :lo12:offset. */
    rtx tmp_reg = gen_reg_rtx (mode);
    if (mode == DImode)
    {
       emit_insn (gen_reg_stack_protect_address_di (tmp_reg));
       emit_insn (gen_adddi3 (tmp_reg, tmp_reg,
       		              GEN_INT (aarch64_stack_protector_guard_offset)));
    }
    else
    {
	emit_insn (gen_reg_stack_protect_address_si (tmp_reg));
	emit_insn (gen_addsi3 (tmp_reg, tmp_reg,
			       GEN_INT (aarch64_stack_protector_guard_offset)));

    }
    operands[1] = gen_rtx_MEM (mode, tmp_reg);
  }
  emit_insn ((mode == DImode
		  ? gen_stack_protect_test_di
		  : gen_stack_protect_test_si) (result,
					        operands[0],
					        operands[1]));

  if (mode == DImode)
    emit_jump_insn (gen_cbranchdi4 (gen_rtx_EQ (VOIDmode, result, const0_rtx),
				    result, const0_rtx, operands[2]));
  else
    emit_jump_insn (gen_cbranchsi4 (gen_rtx_EQ (VOIDmode, result, const0_rtx),
				    result, const0_rtx, operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7036 */
rtx
gen_doloop_end (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 7040 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"
{
  rtx s0;
  rtx bcomp;
  rtx loc_ref;
  rtx cc_reg;
  rtx insn;
  rtx cmp;

  /* Currently SMS relies on the do-loop pattern to recognize loops
     where (1) the control part consists of all insns defining and/or
     using a certain 'count' register and (2) the loop count can be
     adjusted by modifying this register prior to the loop.
     ??? The possible introduction of a new block to initialize the
     new IV can potentially affect branch optimizations.  */

  if (GET_MODE (operands[0]) != DImode)
    FAIL;

  s0 = operands [0];
  insn = emit_insn (gen_adddi3_compare0 (s0, s0, GEN_INT (-1)));

  cmp = XVECEXP (PATTERN (insn), 0, 0);
  cc_reg = SET_DEST (cmp);
  bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
  loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [1]);
  emit_jump_insn (gen_rtx_SET (pc_rtx,
			       gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
						     loc_ref, pc_rtx)));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_USE (VOIDmode,
	operand0));
  emit_insn (gen_rtx_USE (VOIDmode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7116 */
rtx
gen_set_clobber_cc (rtx operand0,
	rtx operand1)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7134 */
rtx
gen_despeculate_copyqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 7142 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  {
    if (operands[2] == const0_rtx)
      {
	rtx tracker;
	if (QImode == TImode)
	  tracker = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM);
	else
	  tracker = gen_rtx_REG (QImode, SPECULATION_TRACKER_REGNUM);

	emit_insn (gen_despeculate_simpleqi (operands[0], operands[1],
						 tracker));
	DONE;
      }
  }
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (4,
		operand1,
		operand2,
		gen_rtx_USE (VOIDmode,
	gen_rtx_REG (DImode,
	15)),
		gen_hard_reg_clobber (CCmode, 66)),
	7)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7134 */
rtx
gen_despeculate_copyhi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 7142 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  {
    if (operands[2] == const0_rtx)
      {
	rtx tracker;
	if (HImode == TImode)
	  tracker = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM);
	else
	  tracker = gen_rtx_REG (HImode, SPECULATION_TRACKER_REGNUM);

	emit_insn (gen_despeculate_simplehi (operands[0], operands[1],
						 tracker));
	DONE;
      }
  }
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (4,
		operand1,
		operand2,
		gen_rtx_USE (VOIDmode,
	gen_rtx_REG (DImode,
	15)),
		gen_hard_reg_clobber (CCmode, 66)),
	7)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7134 */
rtx
gen_despeculate_copysi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 7142 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  {
    if (operands[2] == const0_rtx)
      {
	rtx tracker;
	if (SImode == TImode)
	  tracker = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM);
	else
	  tracker = gen_rtx_REG (SImode, SPECULATION_TRACKER_REGNUM);

	emit_insn (gen_despeculate_simplesi (operands[0], operands[1],
						 tracker));
	DONE;
      }
  }
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (4,
		operand1,
		operand2,
		gen_rtx_USE (VOIDmode,
	gen_rtx_REG (DImode,
	15)),
		gen_hard_reg_clobber (CCmode, 66)),
	7)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7134 */
rtx
gen_despeculate_copydi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 7142 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  {
    if (operands[2] == const0_rtx)
      {
	rtx tracker;
	if (DImode == TImode)
	  tracker = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM);
	else
	  tracker = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM);

	emit_insn (gen_despeculate_simpledi (operands[0], operands[1],
						 tracker));
	DONE;
      }
  }
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (4,
		operand1,
		operand2,
		gen_rtx_USE (VOIDmode,
	gen_rtx_REG (DImode,
	15)),
		gen_hard_reg_clobber (CCmode, 66)),
	7)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md:7134 */
rtx
gen_despeculate_copyti (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 7142 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64.md"

  {
    if (operands[2] == const0_rtx)
      {
	rtx tracker;
	if (TImode == TImode)
	  tracker = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM);
	else
	  tracker = gen_rtx_REG (TImode, SPECULATION_TRACKER_REGNUM);

	emit_insn (gen_despeculate_simpleti (operands[0], operands[1],
						 tracker));
	DONE;
      }
  }
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (TImode,
	gen_rtvec (4,
		operand1,
		operand2,
		gen_rtx_USE (VOIDmode,
	gen_rtx_REG (DImode,
	15)),
		gen_hard_reg_clobber (CCmode, 66)),
	7)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"

  /* Force the operand into a register if it is not an
     immediate whose use can be replaced with xzr.
     If the mode is 16 bytes wide, then we will be doing
     a stp in DI mode, so we check the validity of that.
     If the mode is 8 bytes wide, then we will do doing a
     normal str, so the check need not apply.  */
  if (GET_CODE (operands[0]) == MEM
      && !(aarch64_simd_imm_zero (operands[1], V8QImode)
	   && ((known_eq (GET_MODE_SIZE (V8QImode), 16)
		&& aarch64_mem_pair_operand (operands[0], DImode))
	       || known_eq (GET_MODE_SIZE (V8QImode), 8))))
      operands[1] = force_reg (V8QImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"

  /* Force the operand into a register if it is not an
     immediate whose use can be replaced with xzr.
     If the mode is 16 bytes wide, then we will be doing
     a stp in DI mode, so we check the validity of that.
     If the mode is 8 bytes wide, then we will do doing a
     normal str, so the check need not apply.  */
  if (GET_CODE (operands[0]) == MEM
      && !(aarch64_simd_imm_zero (operands[1], V16QImode)
	   && ((known_eq (GET_MODE_SIZE (V16QImode), 16)
		&& aarch64_mem_pair_operand (operands[0], DImode))
	       || known_eq (GET_MODE_SIZE (V16QImode), 8))))
      operands[1] = force_reg (V16QImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"

  /* Force the operand into a register if it is not an
     immediate whose use can be replaced with xzr.
     If the mode is 16 bytes wide, then we will be doing
     a stp in DI mode, so we check the validity of that.
     If the mode is 8 bytes wide, then we will do doing a
     normal str, so the check need not apply.  */
  if (GET_CODE (operands[0]) == MEM
      && !(aarch64_simd_imm_zero (operands[1], V4HImode)
	   && ((known_eq (GET_MODE_SIZE (V4HImode), 16)
		&& aarch64_mem_pair_operand (operands[0], DImode))
	       || known_eq (GET_MODE_SIZE (V4HImode), 8))))
      operands[1] = force_reg (V4HImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"

  /* Force the operand into a register if it is not an
     immediate whose use can be replaced with xzr.
     If the mode is 16 bytes wide, then we will be doing
     a stp in DI mode, so we check the validity of that.
     If the mode is 8 bytes wide, then we will do doing a
     normal str, so the check need not apply.  */
  if (GET_CODE (operands[0]) == MEM
      && !(aarch64_simd_imm_zero (operands[1], V8HImode)
	   && ((known_eq (GET_MODE_SIZE (V8HImode), 16)
		&& aarch64_mem_pair_operand (operands[0], DImode))
	       || known_eq (GET_MODE_SIZE (V8HImode), 8))))
      operands[1] = force_reg (V8HImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"

  /* Force the operand into a register if it is not an
     immediate whose use can be replaced with xzr.
     If the mode is 16 bytes wide, then we will be doing
     a stp in DI mode, so we check the validity of that.
     If the mode is 8 bytes wide, then we will do doing a
     normal str, so the check need not apply.  */
  if (GET_CODE (operands[0]) == MEM
      && !(aarch64_simd_imm_zero (operands[1], V2SImode)
	   && ((known_eq (GET_MODE_SIZE (V2SImode), 16)
		&& aarch64_mem_pair_operand (operands[0], DImode))
	       || known_eq (GET_MODE_SIZE (V2SImode), 8))))
      operands[1] = force_reg (V2SImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"

  /* Force the operand into a register if it is not an
     immediate whose use can be replaced with xzr.
     If the mode is 16 bytes wide, then we will be doing
     a stp in DI mode, so we check the validity of that.
     If the mode is 8 bytes wide, then we will do doing a
     normal str, so the check need not apply.  */
  if (GET_CODE (operands[0]) == MEM
      && !(aarch64_simd_imm_zero (operands[1], V4SImode)
	   && ((known_eq (GET_MODE_SIZE (V4SImode), 16)
		&& aarch64_mem_pair_operand (operands[0], DImode))
	       || known_eq (GET_MODE_SIZE (V4SImode), 8))))
      operands[1] = force_reg (V4SImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"

  /* Force the operand into a register if it is not an
     immediate whose use can be replaced with xzr.
     If the mode is 16 bytes wide, then we will be doing
     a stp in DI mode, so we check the validity of that.
     If the mode is 8 bytes wide, then we will do doing a
     normal str, so the check need not apply.  */
  if (GET_CODE (operands[0]) == MEM
      && !(aarch64_simd_imm_zero (operands[1], V2DImode)
	   && ((known_eq (GET_MODE_SIZE (V2DImode), 16)
		&& aarch64_mem_pair_operand (operands[0], DImode))
	       || known_eq (GET_MODE_SIZE (V2DImode), 8))))
      operands[1] = force_reg (V2DImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"

  /* Force the operand into a register if it is not an
     immediate whose use can be replaced with xzr.
     If the mode is 16 bytes wide, then we will be doing
     a stp in DI mode, so we check the validity of that.
     If the mode is 8 bytes wide, then we will do doing a
     normal str, so the check need not apply.  */
  if (GET_CODE (operands[0]) == MEM
      && !(aarch64_simd_imm_zero (operands[1], V4HFmode)
	   && ((known_eq (GET_MODE_SIZE (V4HFmode), 16)
		&& aarch64_mem_pair_operand (operands[0], DImode))
	       || known_eq (GET_MODE_SIZE (V4HFmode), 8))))
      operands[1] = force_reg (V4HFmode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"

  /* Force the operand into a register if it is not an
     immediate whose use can be replaced with xzr.
     If the mode is 16 bytes wide, then we will be doing
     a stp in DI mode, so we check the validity of that.
     If the mode is 8 bytes wide, then we will do doing a
     normal str, so the check need not apply.  */
  if (GET_CODE (operands[0]) == MEM
      && !(aarch64_simd_imm_zero (operands[1], V8HFmode)
	   && ((known_eq (GET_MODE_SIZE (V8HFmode), 16)
		&& aarch64_mem_pair_operand (operands[0], DImode))
	       || known_eq (GET_MODE_SIZE (V8HFmode), 8))))
      operands[1] = force_reg (V8HFmode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"

  /* Force the operand into a register if it is not an
     immediate whose use can be replaced with xzr.
     If the mode is 16 bytes wide, then we will be doing
     a stp in DI mode, so we check the validity of that.
     If the mode is 8 bytes wide, then we will do doing a
     normal str, so the check need not apply.  */
  if (GET_CODE (operands[0]) == MEM
      && !(aarch64_simd_imm_zero (operands[1], V2SFmode)
	   && ((known_eq (GET_MODE_SIZE (V2SFmode), 16)
		&& aarch64_mem_pair_operand (operands[0], DImode))
	       || known_eq (GET_MODE_SIZE (V2SFmode), 8))))
      operands[1] = force_reg (V2SFmode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"

  /* Force the operand into a register if it is not an
     immediate whose use can be replaced with xzr.
     If the mode is 16 bytes wide, then we will be doing
     a stp in DI mode, so we check the validity of that.
     If the mode is 8 bytes wide, then we will do doing a
     normal str, so the check need not apply.  */
  if (GET_CODE (operands[0]) == MEM
      && !(aarch64_simd_imm_zero (operands[1], V4SFmode)
	   && ((known_eq (GET_MODE_SIZE (V4SFmode), 16)
		&& aarch64_mem_pair_operand (operands[0], DImode))
	       || known_eq (GET_MODE_SIZE (V4SFmode), 8))))
      operands[1] = force_reg (V4SFmode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"

  /* Force the operand into a register if it is not an
     immediate whose use can be replaced with xzr.
     If the mode is 16 bytes wide, then we will be doing
     a stp in DI mode, so we check the validity of that.
     If the mode is 8 bytes wide, then we will do doing a
     normal str, so the check need not apply.  */
  if (GET_CODE (operands[0]) == MEM
      && !(aarch64_simd_imm_zero (operands[1], V2DFmode)
	   && ((known_eq (GET_MODE_SIZE (V2DFmode), 16)
		&& aarch64_mem_pair_operand (operands[0], DImode))
	       || known_eq (GET_MODE_SIZE (V2DFmode), 8))))
      operands[1] = force_reg (V2DFmode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:41 */
rtx
gen_movmisalignv8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 45 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V8QImode)
      && !register_operand (operands[1], V8QImode))
    operands[1] = force_reg (V8QImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:41 */
rtx
gen_movmisalignv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 45 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V16QImode)
      && !register_operand (operands[1], V16QImode))
    operands[1] = force_reg (V16QImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:41 */
rtx
gen_movmisalignv4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 45 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V4HImode)
      && !register_operand (operands[1], V4HImode))
    operands[1] = force_reg (V4HImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:41 */
rtx
gen_movmisalignv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 45 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V8HImode)
      && !register_operand (operands[1], V8HImode))
    operands[1] = force_reg (V8HImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:41 */
rtx
gen_movmisalignv2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 45 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V2SImode)
      && !register_operand (operands[1], V2SImode))
    operands[1] = force_reg (V2SImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:41 */
rtx
gen_movmisalignv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 45 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V4SImode)
      && !register_operand (operands[1], V4SImode))
    operands[1] = force_reg (V4SImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:41 */
rtx
gen_movmisalignv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 45 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V2DImode)
      && !register_operand (operands[1], V2DImode))
    operands[1] = force_reg (V2DImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:41 */
rtx
gen_movmisalignv2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 45 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V2SFmode)
      && !register_operand (operands[1], V2SFmode))
    operands[1] = force_reg (V2SFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:41 */
rtx
gen_movmisalignv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 45 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V4SFmode)
      && !register_operand (operands[1], V4SFmode))
    operands[1] = force_reg (V4SFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:41 */
rtx
gen_movmisalignv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 45 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V2DFmode)
      && !register_operand (operands[1], V2DFmode))
    operands[1] = force_reg (V2DFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:236 */
extern rtx_insn *gen_split_63 (rtx_insn *, rtx *);
rtx_insn *
gen_split_63 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_63\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 243 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:236 */
extern rtx_insn *gen_split_64 (rtx_insn *, rtx *);
rtx_insn *
gen_split_64 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_64\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 243 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:236 */
extern rtx_insn *gen_split_65 (rtx_insn *, rtx *);
rtx_insn *
gen_split_65 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_65\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 243 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:236 */
extern rtx_insn *gen_split_66 (rtx_insn *, rtx *);
rtx_insn *
gen_split_66 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_66\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 243 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:236 */
extern rtx_insn *gen_split_67 (rtx_insn *, rtx *);
rtx_insn *
gen_split_67 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_67\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 243 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:236 */
extern rtx_insn *gen_split_68 (rtx_insn *, rtx *);
rtx_insn *
gen_split_68 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_68\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 243 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:236 */
extern rtx_insn *gen_split_69 (rtx_insn *, rtx *);
rtx_insn *
gen_split_69 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_69\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 243 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:248 */
extern rtx_insn *gen_split_70 (rtx_insn *, rtx *);
rtx_insn *
gen_split_70 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_70\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 255 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:248 */
extern rtx_insn *gen_split_71 (rtx_insn *, rtx *);
rtx_insn *
gen_split_71 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_71\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 255 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:248 */
extern rtx_insn *gen_split_72 (rtx_insn *, rtx *);
rtx_insn *
gen_split_72 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_72\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 255 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:248 */
extern rtx_insn *gen_split_73 (rtx_insn *, rtx *);
rtx_insn *
gen_split_73 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_73\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 255 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:248 */
extern rtx_insn *gen_split_74 (rtx_insn *, rtx *);
rtx_insn *
gen_split_74 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_74\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 255 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:248 */
extern rtx_insn *gen_split_75 (rtx_insn *, rtx *);
rtx_insn *
gen_split_75 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_75\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 255 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:248 */
extern rtx_insn *gen_split_76 (rtx_insn *, rtx *);
rtx_insn *
gen_split_76 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_76\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 255 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:260 */
rtx
gen_aarch64_split_simd_movv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 264 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (V8QImode, src);
        rtx src_high_part = gen_highpart (V8QImode, src);

        emit_insn
          (gen_move_lo_quad_v16qi (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v16qi (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (V8QImode, dst);
        rtx dst_high_part = gen_highpart (V8QImode, dst);
	rtx lo = aarch64_simd_vect_par_cnst_half (V16QImode, 16, false);
	rtx hi = aarch64_simd_vect_par_cnst_half (V16QImode, 16, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v16qilow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v16qihigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:260 */
rtx
gen_aarch64_split_simd_movv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 264 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (V4HImode, src);
        rtx src_high_part = gen_highpart (V4HImode, src);

        emit_insn
          (gen_move_lo_quad_v8hi (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v8hi (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (V4HImode, dst);
        rtx dst_high_part = gen_highpart (V4HImode, dst);
	rtx lo = aarch64_simd_vect_par_cnst_half (V8HImode, 8, false);
	rtx hi = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v8hilow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v8hihigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:260 */
rtx
gen_aarch64_split_simd_movv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 264 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (V2SImode, src);
        rtx src_high_part = gen_highpart (V2SImode, src);

        emit_insn
          (gen_move_lo_quad_v4si (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v4si (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (V2SImode, dst);
        rtx dst_high_part = gen_highpart (V2SImode, dst);
	rtx lo = aarch64_simd_vect_par_cnst_half (V4SImode, 4, false);
	rtx hi = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v4silow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v4sihigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:260 */
rtx
gen_aarch64_split_simd_movv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 264 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (DImode, src);
        rtx src_high_part = gen_highpart (DImode, src);

        emit_insn
          (gen_move_lo_quad_v2di (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v2di (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (DImode, dst);
        rtx dst_high_part = gen_highpart (DImode, dst);
	rtx lo = aarch64_simd_vect_par_cnst_half (V2DImode, 2, false);
	rtx hi = aarch64_simd_vect_par_cnst_half (V2DImode, 2, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v2dilow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v2dihigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:260 */
rtx
gen_aarch64_split_simd_movv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 264 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (V4HFmode, src);
        rtx src_high_part = gen_highpart (V4HFmode, src);

        emit_insn
          (gen_move_lo_quad_v8hf (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v8hf (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (V4HFmode, dst);
        rtx dst_high_part = gen_highpart (V4HFmode, dst);
	rtx lo = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, false);
	rtx hi = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v8hflow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v8hfhigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:260 */
rtx
gen_aarch64_split_simd_movv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 264 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (V2SFmode, src);
        rtx src_high_part = gen_highpart (V2SFmode, src);

        emit_insn
          (gen_move_lo_quad_v4sf (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v4sf (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (V2SFmode, dst);
        rtx dst_high_part = gen_highpart (V2SFmode, dst);
	rtx lo = aarch64_simd_vect_par_cnst_half (V4SFmode, 4, false);
	rtx hi = aarch64_simd_vect_par_cnst_half (V4SFmode, 4, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v4sflow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v4sfhigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:260 */
rtx
gen_aarch64_split_simd_movv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 264 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (DFmode, src);
        rtx src_high_part = gen_highpart (DFmode, src);

        emit_insn
          (gen_move_lo_quad_v2df (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v2df (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (DFmode, dst);
        rtx dst_high_part = gen_highpart (DFmode, dst);
	rtx lo = aarch64_simd_vect_par_cnst_half (V2DFmode, 2, false);
	rtx hi = aarch64_simd_vect_par_cnst_half (V2DFmode, 2, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v2dflow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v2dfhigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:379 */
rtx
gen_ctzv2si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"ctzv2si2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 383 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
     emit_insn (gen_bswapv2si2 (operands[0], operands[1]));
     rtx op0_castsi2qi = simplify_gen_subreg(V8QImode, operands[0],
					     V2SImode, 0);
     emit_insn (gen_aarch64_rbitv8qi (op0_castsi2qi, op0_castsi2qi));
     emit_insn (gen_clzv2si2 (operands[0], operands[0]));
     DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_CTZ (V2SImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:379 */
rtx
gen_ctzv4si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"ctzv4si2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 383 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
     emit_insn (gen_bswapv4si2 (operands[0], operands[1]));
     rtx op0_castsi2qi = simplify_gen_subreg(V16QImode, operands[0],
					     V4SImode, 0);
     emit_insn (gen_aarch64_rbitv16qi (op0_castsi2qi, op0_castsi2qi));
     emit_insn (gen_clzv4si2 (operands[0], operands[0]));
     DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_CTZ (V4SImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:393 */
rtx
gen_xorsignv4hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"xorsignv4hf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 398 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{

  machine_mode imode = V4HImode;
  rtx v_bitmask = gen_reg_rtx (imode);
  rtx op1x = gen_reg_rtx (imode);
  rtx op2x = gen_reg_rtx (imode);

  rtx arg1 = lowpart_subreg (imode, operands[1], V4HFmode);
  rtx arg2 = lowpart_subreg (imode, operands[2], V4HFmode);

  int bits = GET_MODE_UNIT_BITSIZE (V4HFmode) - 1;

  emit_move_insn (v_bitmask,
		  aarch64_simd_gen_const_vector_dup (V4HImode,
						     HOST_WIDE_INT_M1U << bits));

  emit_insn (gen_andv4hi3 (op2x, v_bitmask, arg2));
  emit_insn (gen_xorv4hi3 (op1x, arg1, op2x));
  emit_move_insn (operands[0],
		  lowpart_subreg (V4HFmode, op1x, imode));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:393 */
rtx
gen_xorsignv8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"xorsignv8hf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 398 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{

  machine_mode imode = V8HImode;
  rtx v_bitmask = gen_reg_rtx (imode);
  rtx op1x = gen_reg_rtx (imode);
  rtx op2x = gen_reg_rtx (imode);

  rtx arg1 = lowpart_subreg (imode, operands[1], V8HFmode);
  rtx arg2 = lowpart_subreg (imode, operands[2], V8HFmode);

  int bits = GET_MODE_UNIT_BITSIZE (V8HFmode) - 1;

  emit_move_insn (v_bitmask,
		  aarch64_simd_gen_const_vector_dup (V8HImode,
						     HOST_WIDE_INT_M1U << bits));

  emit_insn (gen_andv8hi3 (op2x, v_bitmask, arg2));
  emit_insn (gen_xorv8hi3 (op1x, arg1, op2x));
  emit_move_insn (operands[0],
		  lowpart_subreg (V8HFmode, op1x, imode));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:393 */
rtx
gen_xorsignv2sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"xorsignv2sf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 398 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{

  machine_mode imode = V2SImode;
  rtx v_bitmask = gen_reg_rtx (imode);
  rtx op1x = gen_reg_rtx (imode);
  rtx op2x = gen_reg_rtx (imode);

  rtx arg1 = lowpart_subreg (imode, operands[1], V2SFmode);
  rtx arg2 = lowpart_subreg (imode, operands[2], V2SFmode);

  int bits = GET_MODE_UNIT_BITSIZE (V2SFmode) - 1;

  emit_move_insn (v_bitmask,
		  aarch64_simd_gen_const_vector_dup (V2SImode,
						     HOST_WIDE_INT_M1U << bits));

  emit_insn (gen_andv2si3 (op2x, v_bitmask, arg2));
  emit_insn (gen_xorv2si3 (op1x, arg1, op2x));
  emit_move_insn (operands[0],
		  lowpart_subreg (V2SFmode, op1x, imode));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:393 */
rtx
gen_xorsignv4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"xorsignv4sf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 398 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{

  machine_mode imode = V4SImode;
  rtx v_bitmask = gen_reg_rtx (imode);
  rtx op1x = gen_reg_rtx (imode);
  rtx op2x = gen_reg_rtx (imode);

  rtx arg1 = lowpart_subreg (imode, operands[1], V4SFmode);
  rtx arg2 = lowpart_subreg (imode, operands[2], V4SFmode);

  int bits = GET_MODE_UNIT_BITSIZE (V4SFmode) - 1;

  emit_move_insn (v_bitmask,
		  aarch64_simd_gen_const_vector_dup (V4SImode,
						     HOST_WIDE_INT_M1U << bits));

  emit_insn (gen_andv4si3 (op2x, v_bitmask, arg2));
  emit_insn (gen_xorv4si3 (op1x, arg1, op2x));
  emit_move_insn (operands[0],
		  lowpart_subreg (V4SFmode, op1x, imode));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:393 */
rtx
gen_xorsignv2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"xorsignv2df3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 398 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{

  machine_mode imode = V2DImode;
  rtx v_bitmask = gen_reg_rtx (imode);
  rtx op1x = gen_reg_rtx (imode);
  rtx op2x = gen_reg_rtx (imode);

  rtx arg1 = lowpart_subreg (imode, operands[1], V2DFmode);
  rtx arg2 = lowpart_subreg (imode, operands[2], V2DFmode);

  int bits = GET_MODE_UNIT_BITSIZE (V2DFmode) - 1;

  emit_move_insn (v_bitmask,
		  aarch64_simd_gen_const_vector_dup (V2DImode,
						     HOST_WIDE_INT_M1U << bits));

  emit_insn (gen_andv2di3 (op2x, v_bitmask, arg2));
  emit_insn (gen_xorv2di3 (op1x, arg1, op2x));
  emit_move_insn (operands[0],
		  lowpart_subreg (V2DFmode, op1x, imode));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:529 */
rtx
gen_sdot_prodv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 536 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (
    gen_aarch64_sdotv8qi (operands[3], operands[3], operands[1],
				    operands[2]));
  emit_insn (gen_rtx_SET (operands[0], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	209),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:529 */
rtx
gen_udot_prodv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 536 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (
    gen_aarch64_udotv8qi (operands[3], operands[3], operands[1],
				    operands[2]));
  emit_insn (gen_rtx_SET (operands[0], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	210),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:529 */
rtx
gen_sdot_prodv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 536 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (
    gen_aarch64_sdotv16qi (operands[3], operands[3], operands[1],
				    operands[2]));
  emit_insn (gen_rtx_SET (operands[0], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	209),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:529 */
rtx
gen_udot_prodv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 536 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (
    gen_aarch64_udotv16qi (operands[3], operands[3], operands[1],
				    operands[2]));
  emit_insn (gen_rtx_SET (operands[0], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	210),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:576 */
rtx
gen_copysignv4hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"copysignv4hf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 581 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx v_bitmask = gen_reg_rtx (V4HImode);
  int bits = GET_MODE_UNIT_BITSIZE (V4HFmode) - 1;

  emit_move_insn (v_bitmask,
		  aarch64_simd_gen_const_vector_dup (V4HImode,
						     HOST_WIDE_INT_M1U << bits));
  emit_insn (gen_aarch64_simd_bslv4hf (operands[0], v_bitmask,
					 operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:576 */
rtx
gen_copysignv8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"copysignv8hf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 581 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx v_bitmask = gen_reg_rtx (V8HImode);
  int bits = GET_MODE_UNIT_BITSIZE (V8HFmode) - 1;

  emit_move_insn (v_bitmask,
		  aarch64_simd_gen_const_vector_dup (V8HImode,
						     HOST_WIDE_INT_M1U << bits));
  emit_insn (gen_aarch64_simd_bslv8hf (operands[0], v_bitmask,
					 operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:576 */
rtx
gen_copysignv2sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"copysignv2sf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 581 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx v_bitmask = gen_reg_rtx (V2SImode);
  int bits = GET_MODE_UNIT_BITSIZE (V2SFmode) - 1;

  emit_move_insn (v_bitmask,
		  aarch64_simd_gen_const_vector_dup (V2SImode,
						     HOST_WIDE_INT_M1U << bits));
  emit_insn (gen_aarch64_simd_bslv2sf (operands[0], v_bitmask,
					 operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:576 */
rtx
gen_copysignv4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"copysignv4sf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 581 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx v_bitmask = gen_reg_rtx (V4SImode);
  int bits = GET_MODE_UNIT_BITSIZE (V4SFmode) - 1;

  emit_move_insn (v_bitmask,
		  aarch64_simd_gen_const_vector_dup (V4SImode,
						     HOST_WIDE_INT_M1U << bits));
  emit_insn (gen_aarch64_simd_bslv4sf (operands[0], v_bitmask,
					 operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:576 */
rtx
gen_copysignv2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"copysignv2df3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 581 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx v_bitmask = gen_reg_rtx (V2DImode);
  int bits = GET_MODE_UNIT_BITSIZE (V2DFmode) - 1;

  emit_move_insn (v_bitmask,
		  aarch64_simd_gen_const_vector_dup (V2DImode,
						     HOST_WIDE_INT_M1U << bits));
  emit_insn (gen_aarch64_simd_bslv2df (operands[0], v_bitmask,
					 operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:654 */
rtx
gen_rsqrtv2sf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"rsqrtv2sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 659 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_emit_approx_sqrt (operands[0], operands[1], true);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	79)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:654 */
rtx
gen_rsqrtv4sf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"rsqrtv4sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 659 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_emit_approx_sqrt (operands[0], operands[1], true);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	79)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:654 */
rtx
gen_rsqrtv2df2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"rsqrtv2df2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 659 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_emit_approx_sqrt (operands[0], operands[1], true);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	79)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:654 */
rtx
gen_rsqrtsf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"rsqrtsf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 659 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_emit_approx_sqrt (operands[0], operands[1], true);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	79)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:654 */
rtx
gen_rsqrtdf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"rsqrtdf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 659 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_emit_approx_sqrt (operands[0], operands[1], true);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	79)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:769 */
rtx
gen_ssadv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx reduc = gen_reg_rtx (V8HImode);
    emit_insn (gen_aarch64_sabdl2v16qi_3 (reduc, operands[1],
					       operands[2]));
    emit_insn (gen_aarch64_sabalv16qi_4 (reduc, operands[1],
					      operands[2], reduc));
    emit_insn (gen_aarch64_sadalpv8hi_3 (operands[3], reduc,
					      operands[3]));
    emit_move_insn (operands[0], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_USE (VOIDmode,
	operand0));
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		gen_rtx_USE (VOIDmode,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2)),
	49));
  emit_insn (gen_rtx_USE (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:769 */
rtx
gen_usadv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx reduc = gen_reg_rtx (V8HImode);
    emit_insn (gen_aarch64_uabdl2v16qi_3 (reduc, operands[1],
					       operands[2]));
    emit_insn (gen_aarch64_uabalv16qi_4 (reduc, operands[1],
					      operands[2], reduc));
    emit_insn (gen_aarch64_uadalpv8hi_3 (operands[3], reduc,
					      operands[3]));
    emit_move_insn (operands[0], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_USE (VOIDmode,
	operand0));
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		gen_rtx_USE (VOIDmode,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2)),
	70));
  emit_insn (gen_rtx_USE (VOIDmode,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:994 */
rtx
gen_ashlv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 999 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V8QImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V8QImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv8qi (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V8QImode);
      emit_insn (gen_aarch64_simd_dupv8qi (tmp,
					     convert_to_mode (QImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv8qi (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:994 */
rtx
gen_ashlv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 999 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V16QImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V16QImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv16qi (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V16QImode);
      emit_insn (gen_aarch64_simd_dupv16qi (tmp,
					     convert_to_mode (QImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv16qi (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:994 */
rtx
gen_ashlv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 999 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V4HImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V4HImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv4hi (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V4HImode);
      emit_insn (gen_aarch64_simd_dupv4hi (tmp,
					     convert_to_mode (HImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv4hi (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:994 */
rtx
gen_ashlv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 999 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V8HImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V8HImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv8hi (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V8HImode);
      emit_insn (gen_aarch64_simd_dupv8hi (tmp,
					     convert_to_mode (HImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv8hi (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:994 */
rtx
gen_ashlv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 999 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V2SImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V2SImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv2si (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V2SImode);
      emit_insn (gen_aarch64_simd_dupv2si (tmp,
					     convert_to_mode (SImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv2si (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:994 */
rtx
gen_ashlv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 999 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V4SImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V4SImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv4si (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V4SImode);
      emit_insn (gen_aarch64_simd_dupv4si (tmp,
					     convert_to_mode (SImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv4si (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:994 */
rtx
gen_ashlv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 999 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V2DImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V2DImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv2di (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V2DImode);
      emit_insn (gen_aarch64_simd_dupv2di (tmp,
					     convert_to_mode (DImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv2di (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1041 */
rtx
gen_lshrv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1046 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V8QImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V8QImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv8qi (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V8QImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv8qi (tmp1,
					     convert_to_mode (QImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv8qi_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1041 */
rtx
gen_lshrv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1046 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V16QImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V16QImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv16qi (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V16QImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv16qi (tmp1,
					     convert_to_mode (QImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv16qi_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1041 */
rtx
gen_lshrv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1046 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V4HImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V4HImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv4hi (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V4HImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv4hi (tmp1,
					     convert_to_mode (HImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv4hi_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1041 */
rtx
gen_lshrv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1046 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V8HImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V8HImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv8hi (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V8HImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv8hi (tmp1,
					     convert_to_mode (HImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv8hi_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1041 */
rtx
gen_lshrv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1046 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V2SImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V2SImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv2si (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V2SImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv2si (tmp1,
					     convert_to_mode (SImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv2si_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1041 */
rtx
gen_lshrv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1046 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V4SImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V4SImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv4si (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V4SImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv4si (tmp1,
					     convert_to_mode (SImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv4si_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1041 */
rtx
gen_lshrv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1046 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V2DImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V2DImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv2di (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V2DImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv2di (tmp1,
					     convert_to_mode (DImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv2di_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1088 */
rtx
gen_ashrv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1093 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V8QImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V8QImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv8qi (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V8QImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv8qi (tmp1,
					     convert_to_mode (QImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv8qi_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1088 */
rtx
gen_ashrv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1093 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V16QImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V16QImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv16qi (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V16QImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv16qi (tmp1,
					     convert_to_mode (QImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv16qi_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1088 */
rtx
gen_ashrv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1093 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V4HImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V4HImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv4hi (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V4HImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv4hi (tmp1,
					     convert_to_mode (HImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv4hi_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1088 */
rtx
gen_ashrv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1093 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V8HImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V8HImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv8hi (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V8HImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv8hi (tmp1,
					     convert_to_mode (HImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv8hi_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1088 */
rtx
gen_ashrv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1093 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V2SImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V2SImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv2si (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V2SImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv2si (tmp1,
					     convert_to_mode (SImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv2si_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1088 */
rtx
gen_ashrv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1093 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V4SImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V4SImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv4si (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V4SImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv4si (tmp1,
					     convert_to_mode (SImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv4si_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1088 */
rtx
gen_ashrv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1093 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V2DImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V2DImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv2di (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V2DImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv2di (tmp1,
					     convert_to_mode (DImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv2di_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1135 */
rtx
gen_vashlv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1140 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv8qi (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1135 */
rtx
gen_vashlv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1140 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv16qi (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1135 */
rtx
gen_vashlv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1140 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv4hi (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1135 */
rtx
gen_vashlv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1140 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv8hi (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1135 */
rtx
gen_vashlv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1140 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv2si (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1135 */
rtx
gen_vashlv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1140 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv4si (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1135 */
rtx
gen_vashlv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1140 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv2di (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1149 */
rtx
gen_vashrv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1154 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V8QImode);
  emit (gen_negv8qi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv8qi_signed (operands[0], operands[1],
						    neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1149 */
rtx
gen_vashrv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1154 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V16QImode);
  emit (gen_negv16qi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv16qi_signed (operands[0], operands[1],
						    neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1149 */
rtx
gen_vashrv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1154 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V4HImode);
  emit (gen_negv4hi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv4hi_signed (operands[0], operands[1],
						    neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1149 */
rtx
gen_vashrv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1154 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V8HImode);
  emit (gen_negv8hi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv8hi_signed (operands[0], operands[1],
						    neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1149 */
rtx
gen_vashrv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1154 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V2SImode);
  emit (gen_negv2si2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv2si_signed (operands[0], operands[1],
						    neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1149 */
rtx
gen_vashrv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1154 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V4SImode);
  emit (gen_negv4si2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv4si_signed (operands[0], operands[1],
						    neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1163 */
rtx
gen_aarch64_ashr_simddi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1168 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    /* An arithmetic shift right by 64 fills the result with copies of the sign
       bit, just like asr by 63 - however the standard pattern does not handle
       a shift by 64.  */
    if (INTVAL (operands[2]) == 64)
      operands[2] = GEN_INT (63);
    emit_insn (gen_ashrdi3 (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1179 */
rtx
gen_vlshrv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1184 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V8QImode);
  emit (gen_negv8qi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv8qi_unsigned (operands[0], operands[1],
						      neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1179 */
rtx
gen_vlshrv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1184 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V16QImode);
  emit (gen_negv16qi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv16qi_unsigned (operands[0], operands[1],
						      neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1179 */
rtx
gen_vlshrv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1184 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V4HImode);
  emit (gen_negv4hi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv4hi_unsigned (operands[0], operands[1],
						      neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1179 */
rtx
gen_vlshrv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1184 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V8HImode);
  emit (gen_negv8hi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv8hi_unsigned (operands[0], operands[1],
						      neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1179 */
rtx
gen_vlshrv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1184 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V2SImode);
  emit (gen_negv2si2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv2si_unsigned (operands[0], operands[1],
						      neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1179 */
rtx
gen_vlshrv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1184 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V4SImode);
  emit (gen_negv4si2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv4si_unsigned (operands[0], operands[1],
						      neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1192 */
rtx
gen_aarch64_lshr_simddi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1197 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    if (INTVAL (operands[2]) == 64)
      emit_move_insn (operands[0], const0_rtx);
    else
      emit_insn (gen_lshrdi3 (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1222 */
rtx
gen_vec_setv8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1227 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv8qi (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1222 */
rtx
gen_vec_setv16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1227 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv16qi (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1222 */
rtx
gen_vec_setv4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1227 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv4hi (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1222 */
rtx
gen_vec_setv8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1227 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv8hi (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1222 */
rtx
gen_vec_setv2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1227 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv2si (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1222 */
rtx
gen_vec_setv4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1227 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv4si (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1222 */
rtx
gen_vec_setv2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1227 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv2di (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1222 */
rtx
gen_vec_setv4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1227 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv4hf (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1222 */
rtx
gen_vec_setv8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1227 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv8hf (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1222 */
rtx
gen_vec_setv2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1227 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv2sf (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1222 */
rtx
gen_vec_setv4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1227 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv4sf (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1222 */
rtx
gen_vec_setv2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1227 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv2df (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1363 */
rtx
gen_smaxv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1368 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  enum rtx_code cmp_operator;
  rtx cmp_fmt;

  switch (SMAX)
    {
    case UMIN:
      cmp_operator = LTU;
      break;
    case SMIN:
      cmp_operator = LT;
      break;
    case UMAX:
      cmp_operator = GTU;
      break;
    case SMAX:
      cmp_operator = GT;
      break;
    default:
      gcc_unreachable ();
    }

  cmp_fmt = gen_rtx_fmt_ee (cmp_operator, V2DImode, operands[1], operands[2]);
  emit_insn (gen_vcondv2div2di (operands[0], operands[1],
              operands[2], cmp_fmt, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SMAX (V2DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1363 */
rtx
gen_sminv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1368 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  enum rtx_code cmp_operator;
  rtx cmp_fmt;

  switch (SMIN)
    {
    case UMIN:
      cmp_operator = LTU;
      break;
    case SMIN:
      cmp_operator = LT;
      break;
    case UMAX:
      cmp_operator = GTU;
      break;
    case SMAX:
      cmp_operator = GT;
      break;
    default:
      gcc_unreachable ();
    }

  cmp_fmt = gen_rtx_fmt_ee (cmp_operator, V2DImode, operands[1], operands[2]);
  emit_insn (gen_vcondv2div2di (operands[0], operands[1],
              operands[2], cmp_fmt, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SMIN (V2DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1363 */
rtx
gen_umaxv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1368 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  enum rtx_code cmp_operator;
  rtx cmp_fmt;

  switch (UMAX)
    {
    case UMIN:
      cmp_operator = LTU;
      break;
    case SMIN:
      cmp_operator = LT;
      break;
    case UMAX:
      cmp_operator = GTU;
      break;
    case SMAX:
      cmp_operator = GT;
      break;
    default:
      gcc_unreachable ();
    }

  cmp_fmt = gen_rtx_fmt_ee (cmp_operator, V2DImode, operands[1], operands[2]);
  emit_insn (gen_vcondv2div2di (operands[0], operands[1],
              operands[2], cmp_fmt, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UMAX (V2DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1363 */
rtx
gen_uminv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1368 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  enum rtx_code cmp_operator;
  rtx cmp_fmt;

  switch (UMIN)
    {
    case UMIN:
      cmp_operator = LTU;
      break;
    case SMIN:
      cmp_operator = LT;
      break;
    case UMAX:
      cmp_operator = GTU;
      break;
    case SMAX:
      cmp_operator = GT;
      break;
    default:
      gcc_unreachable ();
    }

  cmp_fmt = gen_rtx_fmt_ee (cmp_operator, V2DImode, operands[1], operands[2]);
  emit_insn (gen_vcondv2div2di (operands[0], operands[1],
              operands[2], cmp_fmt, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UMIN (V2DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1488 */
rtx
gen_move_lo_quad_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1492 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v16qi (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1488 */
rtx
gen_move_lo_quad_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1492 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v8hi (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1488 */
rtx
gen_move_lo_quad_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1492 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v4si (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1488 */
rtx
gen_move_lo_quad_v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1492 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v2di (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1488 */
rtx
gen_move_lo_quad_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1492 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v8hf (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1488 */
rtx
gen_move_lo_quad_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1492 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v4sf (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1488 */
rtx
gen_move_lo_quad_v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1492 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v2df (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1534 */
rtx
gen_move_hi_quad_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1538 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v16qi (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v16qi (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1534 */
rtx
gen_move_hi_quad_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1538 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v8hi (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v8hi (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1534 */
rtx
gen_move_hi_quad_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1538 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v4si (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v4si (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1534 */
rtx
gen_move_hi_quad_v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1538 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V2DImode, 2, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v2di (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v2di (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1534 */
rtx
gen_move_hi_quad_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1538 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v8hf (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v8hf (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1534 */
rtx
gen_move_hi_quad_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1538 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SFmode, 4, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v4sf (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v4sf (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1534 */
rtx
gen_move_hi_quad_v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1538 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V2DFmode, 2, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v2df (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v2df (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1560 */
rtx
gen_vec_pack_trunc_v4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx tempreg = gen_reg_rtx (V8HImode);
  int lo = BYTES_BIG_ENDIAN ? 2 : 1;
  int hi = BYTES_BIG_ENDIAN ? 1 : 2;

  emit_insn (gen_move_lo_quad_v8hi (tempreg, operands[lo]));
  emit_insn (gen_move_hi_quad_v8hi (tempreg, operands[hi]));
  emit_insn (gen_aarch64_simd_vec_pack_trunc_v8hi (operands[0], tempreg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1560 */
rtx
gen_vec_pack_trunc_v2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx tempreg = gen_reg_rtx (V4SImode);
  int lo = BYTES_BIG_ENDIAN ? 2 : 1;
  int hi = BYTES_BIG_ENDIAN ? 1 : 2;

  emit_insn (gen_move_lo_quad_v4si (tempreg, operands[lo]));
  emit_insn (gen_move_hi_quad_v4si (tempreg, operands[hi]));
  emit_insn (gen_aarch64_simd_vec_pack_trunc_v4si (operands[0], tempreg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1560 */
rtx
gen_vec_pack_trunc_di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx tempreg = gen_reg_rtx (V2DImode);
  int lo = BYTES_BIG_ENDIAN ? 2 : 1;
  int hi = BYTES_BIG_ENDIAN ? 1 : 2;

  emit_insn (gen_move_lo_quad_v2di (tempreg, operands[lo]));
  emit_insn (gen_move_hi_quad_v2di (tempreg, operands[hi]));
  emit_insn (gen_aarch64_simd_vec_pack_trunc_v2di (operands[0], tempreg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1618 */
rtx
gen_vec_unpacks_hi_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1622 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, true);
    emit_insn (gen_aarch64_simd_vec_unpacks_hi_v16qi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V8HImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1618 */
rtx
gen_vec_unpacku_hi_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1622 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, true);
    emit_insn (gen_aarch64_simd_vec_unpacku_hi_v16qi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V8HImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1618 */
rtx
gen_vec_unpacks_hi_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1622 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
    emit_insn (gen_aarch64_simd_vec_unpacks_hi_v8hi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V4SImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1618 */
rtx
gen_vec_unpacku_hi_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1622 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
    emit_insn (gen_aarch64_simd_vec_unpacku_hi_v8hi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V4SImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1618 */
rtx
gen_vec_unpacks_hi_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1622 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
    emit_insn (gen_aarch64_simd_vec_unpacks_hi_v4si (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V2DImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1618 */
rtx
gen_vec_unpacku_hi_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1622 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
    emit_insn (gen_aarch64_simd_vec_unpacku_hi_v4si (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V2DImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1630 */
rtx
gen_vec_unpacks_lo_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1634 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, false);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v16qi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V8HImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1630 */
rtx
gen_vec_unpacku_lo_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1634 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, false);
    emit_insn (gen_aarch64_simd_vec_unpacku_lo_v16qi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V8HImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1630 */
rtx
gen_vec_unpacks_lo_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1634 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, false);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v8hi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V4SImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1630 */
rtx
gen_vec_unpacku_lo_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1634 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, false);
    emit_insn (gen_aarch64_simd_vec_unpacku_lo_v8hi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V4SImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1630 */
rtx
gen_vec_unpacks_lo_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1634 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, false);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v4si (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V2DImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1630 */
rtx
gen_vec_unpacku_lo_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1634 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, false);
    emit_insn (gen_aarch64_simd_vec_unpacku_lo_v4si (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V2DImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1749 */
rtx
gen_vec_widen_smult_lo_v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1754 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, false);
   emit_insn (gen_aarch64_simd_vec_smult_lo_v16qi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V8HImode,
	operand1));
  emit_insn (gen_rtx_SIGN_EXTEND (V8HImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1749 */
rtx
gen_vec_widen_umult_lo_v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1754 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, false);
   emit_insn (gen_aarch64_simd_vec_umult_lo_v16qi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V8HImode,
	operand1));
  emit_insn (gen_rtx_ZERO_EXTEND (V8HImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1749 */
rtx
gen_vec_widen_smult_lo_v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1754 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, false);
   emit_insn (gen_aarch64_simd_vec_smult_lo_v8hi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V4SImode,
	operand1));
  emit_insn (gen_rtx_SIGN_EXTEND (V4SImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1749 */
rtx
gen_vec_widen_umult_lo_v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1754 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, false);
   emit_insn (gen_aarch64_simd_vec_umult_lo_v8hi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V4SImode,
	operand1));
  emit_insn (gen_rtx_ZERO_EXTEND (V4SImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1749 */
rtx
gen_vec_widen_smult_lo_v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1754 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, false);
   emit_insn (gen_aarch64_simd_vec_smult_lo_v4si (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V2DImode,
	operand1));
  emit_insn (gen_rtx_SIGN_EXTEND (V2DImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1749 */
rtx
gen_vec_widen_umult_lo_v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1754 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, false);
   emit_insn (gen_aarch64_simd_vec_umult_lo_v4si (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V2DImode,
	operand1));
  emit_insn (gen_rtx_ZERO_EXTEND (V2DImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1776 */
rtx
gen_vec_widen_smult_hi_v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1781 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, true);
   emit_insn (gen_aarch64_simd_vec_smult_hi_v16qi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;

 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V8HImode,
	operand1));
  emit_insn (gen_rtx_SIGN_EXTEND (V8HImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1776 */
rtx
gen_vec_widen_umult_hi_v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1781 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, true);
   emit_insn (gen_aarch64_simd_vec_umult_hi_v16qi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;

 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V8HImode,
	operand1));
  emit_insn (gen_rtx_ZERO_EXTEND (V8HImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1776 */
rtx
gen_vec_widen_smult_hi_v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1781 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
   emit_insn (gen_aarch64_simd_vec_smult_hi_v8hi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;

 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V4SImode,
	operand1));
  emit_insn (gen_rtx_SIGN_EXTEND (V4SImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1776 */
rtx
gen_vec_widen_umult_hi_v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1781 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
   emit_insn (gen_aarch64_simd_vec_umult_hi_v8hi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;

 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V4SImode,
	operand1));
  emit_insn (gen_rtx_ZERO_EXTEND (V4SImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1776 */
rtx
gen_vec_widen_smult_hi_v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1781 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
   emit_insn (gen_aarch64_simd_vec_smult_hi_v4si (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;

 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V2DImode,
	operand1));
  emit_insn (gen_rtx_SIGN_EXTEND (V2DImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1776 */
rtx
gen_vec_widen_umult_hi_v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1781 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
   emit_insn (gen_aarch64_simd_vec_umult_hi_v4si (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;

 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V2DImode,
	operand1));
  emit_insn (gen_rtx_ZERO_EXTEND (V2DImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1843 */
rtx
gen_divv4hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1848 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (V4HFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (V4HFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1843 */
rtx
gen_divv8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1848 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (V8HFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (V8HFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1843 */
rtx
gen_divv2sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1848 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (V2SFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (V2SFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1843 */
rtx
gen_divv4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1848 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (V4SFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (V4SFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:1843 */
rtx
gen_divv2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1848 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (V2DFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (V2DFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2098 */
rtx
gen_fixv4hfv4hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2104 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2098 */
rtx
gen_fixunsv4hfv4hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2104 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2098 */
rtx
gen_fixv8hfv8hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2104 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2098 */
rtx
gen_fixunsv8hfv8hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2104 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2098 */
rtx
gen_fixv2sfv2si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2104 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2098 */
rtx
gen_fixunsv2sfv2si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2104 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2098 */
rtx
gen_fixv4sfv4si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2104 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2098 */
rtx
gen_fixunsv4sfv4si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2104 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2098 */
rtx
gen_fixv2dfv2di2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2104 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2098 */
rtx
gen_fixunsv2dfv2di2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2104 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2106 */
rtx
gen_fix_truncv4hfv4hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2112 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2106 */
rtx
gen_fixuns_truncv4hfv4hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2112 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2106 */
rtx
gen_fix_truncv8hfv8hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2112 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2106 */
rtx
gen_fixuns_truncv8hfv8hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2112 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2106 */
rtx
gen_fix_truncv2sfv2si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2112 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2106 */
rtx
gen_fixuns_truncv2sfv2si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2112 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2106 */
rtx
gen_fix_truncv4sfv4si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2112 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2106 */
rtx
gen_fixuns_truncv4sfv4si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2112 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2106 */
rtx
gen_fix_truncv2dfv2di2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2112 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2106 */
rtx
gen_fixuns_truncv2dfv2di2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2112 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	23))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2114 */
rtx
gen_ftruncv4hf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2119 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	23)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2114 */
rtx
gen_ftruncv8hf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2119 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	23)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2114 */
rtx
gen_ftruncv2sf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2119 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	23)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2114 */
rtx
gen_ftruncv4sf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2119 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	23)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2114 */
rtx
gen_ftruncv2df2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2119 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	23)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_vec_unpacks_lo_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2184 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, false);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v8hf (operands[0],
						       operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_vec_unpacks_lo_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2184 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SFmode, 4, false);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v4sf (operands[0],
						       operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2203 */
rtx
gen_vec_unpacks_hi_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2207 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, true);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v8hf (operands[0],
						       operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2203 */
rtx
gen_vec_unpacks_hi_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2207 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SFmode, 4, true);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v4sf (operands[0],
						       operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2256 */
rtx
gen_aarch64_float_truncate_hi_v4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2261 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx (*gen) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN
			     ? gen_aarch64_float_truncate_hi_v4sf_be
			     : gen_aarch64_float_truncate_hi_v4sf_le;
  emit_insn (gen (operands[0], operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2256 */
rtx
gen_aarch64_float_truncate_hi_v8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2261 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx (*gen) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN
			     ? gen_aarch64_float_truncate_hi_v8hf_be
			     : gen_aarch64_float_truncate_hi_v8hf_le;
  emit_insn (gen (operands[0], operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2270 */
rtx
gen_vec_pack_trunc_v2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2279 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx tmp = gen_reg_rtx (V2SFmode);
    int lo = BYTES_BIG_ENDIAN ? 2 : 1;
    int hi = BYTES_BIG_ENDIAN ? 1 : 2;

    emit_insn (gen_aarch64_float_truncate_lo_v2sf (tmp, operands[lo]));
    emit_insn (gen_aarch64_float_truncate_hi_v4sf (operands[0],
						   tmp, operands[hi]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_FLOAT_TRUNCATE (V2SFmode,
	operand1),
	gen_rtx_FLOAT_TRUNCATE (V2SFmode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2291 */
rtx
gen_vec_pack_trunc_df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2300 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx tmp = gen_reg_rtx (V2SFmode);
    int lo = BYTES_BIG_ENDIAN ? 2 : 1;
    int hi = BYTES_BIG_ENDIAN ? 1 : 2;

    emit_insn (gen_move_lo_quad_v2df (tmp, operands[lo]));
    emit_insn (gen_move_hi_quad_v2df (tmp, operands[hi]));
    emit_insn (gen_aarch64_float_truncate_lo_v2sf (operands[0], tmp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2SFmode,
	gen_rtx_FLOAT_TRUNCATE (SFmode,
	operand1),
	gen_rtx_FLOAT_TRUNCATE (SFmode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2351 */
rtx
gen_reduc_plus_scal_v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_v8qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2356 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8QImode, 0);
    rtx scratch = gen_reg_rtx (V8QImode);
    emit_insn (gen_aarch64_reduc_plus_internalv8qi (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev8qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	116));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2351 */
rtx
gen_reduc_plus_scal_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_v16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2356 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V16QImode, 0);
    rtx scratch = gen_reg_rtx (V16QImode);
    emit_insn (gen_aarch64_reduc_plus_internalv16qi (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev16qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	116));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2351 */
rtx
gen_reduc_plus_scal_v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_v4hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2356 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4HImode, 0);
    rtx scratch = gen_reg_rtx (V4HImode);
    emit_insn (gen_aarch64_reduc_plus_internalv4hi (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev4hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	116));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2351 */
rtx
gen_reduc_plus_scal_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_v8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2356 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8HImode, 0);
    rtx scratch = gen_reg_rtx (V8HImode);
    emit_insn (gen_aarch64_reduc_plus_internalv8hi (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev8hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	116));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2351 */
rtx
gen_reduc_plus_scal_v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_v2si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2356 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2SImode, 0);
    rtx scratch = gen_reg_rtx (V2SImode);
    emit_insn (gen_aarch64_reduc_plus_internalv2si (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev2si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	116));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2351 */
rtx
gen_reduc_plus_scal_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_v4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2356 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4SImode, 0);
    rtx scratch = gen_reg_rtx (V4SImode);
    emit_insn (gen_aarch64_reduc_plus_internalv4si (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev4si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	116));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2351 */
rtx
gen_reduc_plus_scal_v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_v2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2356 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2DImode, 0);
    rtx scratch = gen_reg_rtx (V2DImode);
    emit_insn (gen_aarch64_reduc_plus_internalv2di (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev2di (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	116));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2402 */
rtx
gen_reduc_plus_scal_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_v4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2407 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx elt = aarch64_endian_lane_rtx (V4SFmode, 0);
  rtx scratch = gen_reg_rtx (V4SFmode);
  emit_insn (gen_aarch64_faddpv4sf (scratch, operands[1], operands[1]));
  emit_insn (gen_aarch64_faddpv4sf (scratch, scratch, scratch));
  emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	115)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smax_nan_scal_v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4HFmode, 0);
    rtx scratch = gen_reg_rtx (V4HFmode);
    emit_insn (gen_aarch64_reduc_smax_nan_internalv4hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	111));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smin_nan_scal_v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4HFmode, 0);
    rtx scratch = gen_reg_rtx (V4HFmode);
    emit_insn (gen_aarch64_reduc_smin_nan_internalv4hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	114));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smax_scal_v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4HFmode, 0);
    rtx scratch = gen_reg_rtx (V4HFmode);
    emit_insn (gen_aarch64_reduc_smax_internalv4hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	110));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smin_scal_v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4HFmode, 0);
    rtx scratch = gen_reg_rtx (V4HFmode);
    emit_insn (gen_aarch64_reduc_smin_internalv4hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	113));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smax_nan_scal_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8HFmode, 0);
    rtx scratch = gen_reg_rtx (V8HFmode);
    emit_insn (gen_aarch64_reduc_smax_nan_internalv8hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	111));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smin_nan_scal_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8HFmode, 0);
    rtx scratch = gen_reg_rtx (V8HFmode);
    emit_insn (gen_aarch64_reduc_smin_nan_internalv8hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	114));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smax_scal_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8HFmode, 0);
    rtx scratch = gen_reg_rtx (V8HFmode);
    emit_insn (gen_aarch64_reduc_smax_internalv8hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	110));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smin_scal_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8HFmode, 0);
    rtx scratch = gen_reg_rtx (V8HFmode);
    emit_insn (gen_aarch64_reduc_smin_internalv8hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	113));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smax_nan_scal_v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2SFmode, 0);
    rtx scratch = gen_reg_rtx (V2SFmode);
    emit_insn (gen_aarch64_reduc_smax_nan_internalv2sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	111));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smin_nan_scal_v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2SFmode, 0);
    rtx scratch = gen_reg_rtx (V2SFmode);
    emit_insn (gen_aarch64_reduc_smin_nan_internalv2sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	114));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smax_scal_v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2SFmode, 0);
    rtx scratch = gen_reg_rtx (V2SFmode);
    emit_insn (gen_aarch64_reduc_smax_internalv2sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	110));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smin_scal_v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2SFmode, 0);
    rtx scratch = gen_reg_rtx (V2SFmode);
    emit_insn (gen_aarch64_reduc_smin_internalv2sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	113));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smax_nan_scal_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4SFmode, 0);
    rtx scratch = gen_reg_rtx (V4SFmode);
    emit_insn (gen_aarch64_reduc_smax_nan_internalv4sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	111));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smin_nan_scal_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4SFmode, 0);
    rtx scratch = gen_reg_rtx (V4SFmode);
    emit_insn (gen_aarch64_reduc_smin_nan_internalv4sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	114));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smax_scal_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4SFmode, 0);
    rtx scratch = gen_reg_rtx (V4SFmode);
    emit_insn (gen_aarch64_reduc_smax_internalv4sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	110));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smin_scal_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4SFmode, 0);
    rtx scratch = gen_reg_rtx (V4SFmode);
    emit_insn (gen_aarch64_reduc_smin_internalv4sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	113));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smax_nan_scal_v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2DFmode, 0);
    rtx scratch = gen_reg_rtx (V2DFmode);
    emit_insn (gen_aarch64_reduc_smax_nan_internalv2df (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2df (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	111));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smin_nan_scal_v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2DFmode, 0);
    rtx scratch = gen_reg_rtx (V2DFmode);
    emit_insn (gen_aarch64_reduc_smin_nan_internalv2df (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2df (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	114));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smax_scal_v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2DFmode, 0);
    rtx scratch = gen_reg_rtx (V2DFmode);
    emit_insn (gen_aarch64_reduc_smax_internalv2df (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2df (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	110));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2444 */
rtx
gen_reduc_smin_scal_v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2449 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2DFmode, 0);
    rtx scratch = gen_reg_rtx (V2DFmode);
    emit_insn (gen_aarch64_reduc_smin_internalv2df (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2df (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	113));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_umax_scal_v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8QImode, 0);
    rtx scratch = gen_reg_rtx (V8QImode);
    emit_insn (gen_aarch64_reduc_umax_internalv8qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	119));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_umin_scal_v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8QImode, 0);
    rtx scratch = gen_reg_rtx (V8QImode);
    emit_insn (gen_aarch64_reduc_umin_internalv8qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	120));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_smax_scal_v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8QImode, 0);
    rtx scratch = gen_reg_rtx (V8QImode);
    emit_insn (gen_aarch64_reduc_smax_internalv8qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	117));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_smin_scal_v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8QImode, 0);
    rtx scratch = gen_reg_rtx (V8QImode);
    emit_insn (gen_aarch64_reduc_smin_internalv8qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	118));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_umax_scal_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V16QImode, 0);
    rtx scratch = gen_reg_rtx (V16QImode);
    emit_insn (gen_aarch64_reduc_umax_internalv16qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev16qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	119));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_umin_scal_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V16QImode, 0);
    rtx scratch = gen_reg_rtx (V16QImode);
    emit_insn (gen_aarch64_reduc_umin_internalv16qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev16qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	120));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_smax_scal_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V16QImode, 0);
    rtx scratch = gen_reg_rtx (V16QImode);
    emit_insn (gen_aarch64_reduc_smax_internalv16qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev16qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	117));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_smin_scal_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V16QImode, 0);
    rtx scratch = gen_reg_rtx (V16QImode);
    emit_insn (gen_aarch64_reduc_smin_internalv16qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev16qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	118));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_umax_scal_v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4HImode, 0);
    rtx scratch = gen_reg_rtx (V4HImode);
    emit_insn (gen_aarch64_reduc_umax_internalv4hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	119));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_umin_scal_v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4HImode, 0);
    rtx scratch = gen_reg_rtx (V4HImode);
    emit_insn (gen_aarch64_reduc_umin_internalv4hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	120));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_smax_scal_v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4HImode, 0);
    rtx scratch = gen_reg_rtx (V4HImode);
    emit_insn (gen_aarch64_reduc_smax_internalv4hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	117));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_smin_scal_v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4HImode, 0);
    rtx scratch = gen_reg_rtx (V4HImode);
    emit_insn (gen_aarch64_reduc_smin_internalv4hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	118));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_umax_scal_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8HImode, 0);
    rtx scratch = gen_reg_rtx (V8HImode);
    emit_insn (gen_aarch64_reduc_umax_internalv8hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	119));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_umin_scal_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8HImode, 0);
    rtx scratch = gen_reg_rtx (V8HImode);
    emit_insn (gen_aarch64_reduc_umin_internalv8hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	120));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_smax_scal_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8HImode, 0);
    rtx scratch = gen_reg_rtx (V8HImode);
    emit_insn (gen_aarch64_reduc_smax_internalv8hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	117));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_smin_scal_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V8HImode, 0);
    rtx scratch = gen_reg_rtx (V8HImode);
    emit_insn (gen_aarch64_reduc_smin_internalv8hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	118));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_umax_scal_v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2SImode, 0);
    rtx scratch = gen_reg_rtx (V2SImode);
    emit_insn (gen_aarch64_reduc_umax_internalv2si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	119));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_umin_scal_v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2SImode, 0);
    rtx scratch = gen_reg_rtx (V2SImode);
    emit_insn (gen_aarch64_reduc_umin_internalv2si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	120));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_smax_scal_v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2SImode, 0);
    rtx scratch = gen_reg_rtx (V2SImode);
    emit_insn (gen_aarch64_reduc_smax_internalv2si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	117));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_smin_scal_v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V2SImode, 0);
    rtx scratch = gen_reg_rtx (V2SImode);
    emit_insn (gen_aarch64_reduc_smin_internalv2si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	118));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_umax_scal_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4SImode, 0);
    rtx scratch = gen_reg_rtx (V4SImode);
    emit_insn (gen_aarch64_reduc_umax_internalv4si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	119));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_umin_scal_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4SImode, 0);
    rtx scratch = gen_reg_rtx (V4SImode);
    emit_insn (gen_aarch64_reduc_umin_internalv4si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	120));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_smax_scal_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4SImode, 0);
    rtx scratch = gen_reg_rtx (V4SImode);
    emit_insn (gen_aarch64_reduc_smax_internalv4si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	117));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2460 */
rtx
gen_reduc_smin_scal_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2465 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = aarch64_endian_lane_rtx (V4SImode, 0);
    rtx scratch = gen_reg_rtx (V4SImode);
    emit_insn (gen_aarch64_reduc_smin_internalv4si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	118));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2573 */
extern rtx_insn *gen_split_77 (rtx_insn *, rtx *);
rtx_insn *
gen_split_77 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_77\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2591 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* Split back to individual operations.  If we're before reload, and
     able to create a temporary register, do so.  If we're after reload,
     we've got an early-clobber destination register, so use that.
     Otherwise, we can't create pseudos and we can't yet guarantee that
     operands[0] is safe to write, so FAIL to split.  */

  rtx scratch;
  if (reload_completed)
    scratch = operands[0];
  else if (can_create_pseudo_p ())
    scratch = gen_reg_rtx (DImode);
  else
    FAIL;

  emit_insn (gen_xordi3 (scratch, operands[2], operands[3]));
  emit_insn (gen_anddi3 (scratch, scratch, operands[1]));
  emit_insn (gen_xordi3 (operands[0], scratch, operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (operand1, true);
  emit (copy_rtx (operand1), true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2615 */
extern rtx_insn *gen_split_78 (rtx_insn *, rtx *);
rtx_insn *
gen_split_78 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_78\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2633 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* Split back to individual operations.  If we're before reload, and
     able to create a temporary register, do so.  If we're after reload,
     we've got an early-clobber destination register, so use that.
     Otherwise, we can't create pseudos and we can't yet guarantee that
     operands[0] is safe to write, so FAIL to split.  */

  rtx scratch;
  if (reload_completed)
    scratch = operands[0];
  else if (can_create_pseudo_p ())
    scratch = gen_reg_rtx (DImode);
  else
    FAIL;

  emit_insn (gen_xordi3 (scratch, operands[2], operands[3]));
  emit_insn (gen_anddi3 (scratch, scratch, operands[1]));
  emit_insn (gen_xordi3 (operands[0], scratch, operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bslv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V8QImode))
    {
      operands[2] = gen_lowpart (V8QImode, operands[2]);
      operands[3] = gen_lowpart (V8QImode, operands[3]);
      tmp = gen_reg_rtx (V8QImode);
    }
  operands[1] = gen_lowpart (V8QImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv8qi_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V8QImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bslv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V16QImode))
    {
      operands[2] = gen_lowpart (V16QImode, operands[2]);
      operands[3] = gen_lowpart (V16QImode, operands[3]);
      tmp = gen_reg_rtx (V16QImode);
    }
  operands[1] = gen_lowpart (V16QImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv16qi_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V16QImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bslv4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V4HImode))
    {
      operands[2] = gen_lowpart (V4HImode, operands[2]);
      operands[3] = gen_lowpart (V4HImode, operands[3]);
      tmp = gen_reg_rtx (V4HImode);
    }
  operands[1] = gen_lowpart (V4HImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv4hi_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V4HImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bslv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V8HImode))
    {
      operands[2] = gen_lowpart (V8HImode, operands[2]);
      operands[3] = gen_lowpart (V8HImode, operands[3]);
      tmp = gen_reg_rtx (V8HImode);
    }
  operands[1] = gen_lowpart (V8HImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv8hi_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V8HImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bslv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V2SImode))
    {
      operands[2] = gen_lowpart (V2SImode, operands[2]);
      operands[3] = gen_lowpart (V2SImode, operands[3]);
      tmp = gen_reg_rtx (V2SImode);
    }
  operands[1] = gen_lowpart (V2SImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv2si_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V2SImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bslv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V4SImode))
    {
      operands[2] = gen_lowpart (V4SImode, operands[2]);
      operands[3] = gen_lowpart (V4SImode, operands[3]);
      tmp = gen_reg_rtx (V4SImode);
    }
  operands[1] = gen_lowpart (V4SImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv4si_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V4SImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bslv2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V2DImode))
    {
      operands[2] = gen_lowpart (V2DImode, operands[2]);
      operands[3] = gen_lowpart (V2DImode, operands[3]);
      tmp = gen_reg_rtx (V2DImode);
    }
  operands[1] = gen_lowpart (V2DImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv2di_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V2DImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bslv4hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V4HFmode))
    {
      operands[2] = gen_lowpart (V4HImode, operands[2]);
      operands[3] = gen_lowpart (V4HImode, operands[3]);
      tmp = gen_reg_rtx (V4HImode);
    }
  operands[1] = gen_lowpart (V4HImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv4hi_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V4HFmode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bslv8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V8HFmode))
    {
      operands[2] = gen_lowpart (V8HImode, operands[2]);
      operands[3] = gen_lowpart (V8HImode, operands[3]);
      tmp = gen_reg_rtx (V8HImode);
    }
  operands[1] = gen_lowpart (V8HImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv8hi_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V8HFmode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bslv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V2SFmode))
    {
      operands[2] = gen_lowpart (V2SImode, operands[2]);
      operands[3] = gen_lowpart (V2SImode, operands[3]);
      tmp = gen_reg_rtx (V2SImode);
    }
  operands[1] = gen_lowpart (V2SImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv2si_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V2SFmode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bslv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V4SFmode))
    {
      operands[2] = gen_lowpart (V4SImode, operands[2]);
      operands[3] = gen_lowpart (V4SImode, operands[3]);
      tmp = gen_reg_rtx (V4SImode);
    }
  operands[1] = gen_lowpart (V4SImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv4si_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V4SFmode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bslv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V2DFmode))
    {
      operands[2] = gen_lowpart (V2DImode, operands[2]);
      operands[3] = gen_lowpart (V2DImode, operands[3]);
      tmp = gen_reg_rtx (V2DImode);
    }
  operands[1] = gen_lowpart (V2DImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv2di_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V2DFmode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bsldi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (DImode))
    {
      operands[2] = gen_lowpart (DImode, operands[2]);
      operands[3] = gen_lowpart (DImode, operands[3]);
      tmp = gen_reg_rtx (DImode);
    }
  operands[1] = gen_lowpart (DImode, operands[1]);
  emit_insn (gen_aarch64_simd_bsldi_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (DImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2657 */
rtx
gen_aarch64_simd_bsldf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2663 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (DFmode))
    {
      operands[2] = gen_lowpart (DImode, operands[2]);
      operands[3] = gen_lowpart (DImode, operands[3]);
      tmp = gen_reg_rtx (DImode);
    }
  operands[1] = gen_lowpart (DImode, operands[1]);
  emit_insn (gen_aarch64_simd_bsldi_internal (tmp,
							 operands[1],
							 operands[2],
							 operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (DFmode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2683 */
rtx
gen_vcond_mask_v8qiv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2689 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* If we have (a = (P) ? -1 : 0);
     Then we can simply move the generated mask (result must be int).  */
  if (operands[1] == CONSTM1_RTX (V8QImode)
      && operands[2] == CONST0_RTX (V8QImode))
    emit_move_insn (operands[0], operands[3]);
  /* Similarly, (a = (P) ? 0 : -1) is just inverting the generated mask.  */
  else if (operands[1] == CONST0_RTX (V8QImode)
	   && operands[2] == CONSTM1_RTX (V8QImode))
    emit_insn (gen_one_cmplv8qi2 (operands[0], operands[3]));
  else
    {
      if (!REG_P (operands[1]))
	operands[1] = force_reg (V8QImode, operands[1]);
      if (!REG_P (operands[2]))
	operands[2] = force_reg (V8QImode, operands[2]);
      emit_insn (gen_aarch64_simd_bslv8qi (operands[0], operands[3],
					     operands[1], operands[2]));
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2683 */
rtx
gen_vcond_mask_v16qiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2689 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* If we have (a = (P) ? -1 : 0);
     Then we can simply move the generated mask (result must be int).  */
  if (operands[1] == CONSTM1_RTX (V16QImode)
      && operands[2] == CONST0_RTX (V16QImode))
    emit_move_insn (operands[0], operands[3]);
  /* Similarly, (a = (P) ? 0 : -1) is just inverting the generated mask.  */
  else if (operands[1] == CONST0_RTX (V16QImode)
	   && operands[2] == CONSTM1_RTX (V16QImode))
    emit_insn (gen_one_cmplv16qi2 (operands[0], operands[3]));
  else
    {
      if (!REG_P (operands[1]))
	operands[1] = force_reg (V16QImode, operands[1]);
      if (!REG_P (operands[2]))
	operands[2] = force_reg (V16QImode, operands[2]);
      emit_insn (gen_aarch64_simd_bslv16qi (operands[0], operands[3],
					     operands[1], operands[2]));
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2683 */
rtx
gen_vcond_mask_v4hiv4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2689 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* If we have (a = (P) ? -1 : 0);
     Then we can simply move the generated mask (result must be int).  */
  if (operands[1] == CONSTM1_RTX (V4HImode)
      && operands[2] == CONST0_RTX (V4HImode))
    emit_move_insn (operands[0], operands[3]);
  /* Similarly, (a = (P) ? 0 : -1) is just inverting the generated mask.  */
  else if (operands[1] == CONST0_RTX (V4HImode)
	   && operands[2] == CONSTM1_RTX (V4HImode))
    emit_insn (gen_one_cmplv4hi2 (operands[0], operands[3]));
  else
    {
      if (!REG_P (operands[1]))
	operands[1] = force_reg (V4HImode, operands[1]);
      if (!REG_P (operands[2]))
	operands[2] = force_reg (V4HImode, operands[2]);
      emit_insn (gen_aarch64_simd_bslv4hi (operands[0], operands[3],
					     operands[1], operands[2]));
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2683 */
rtx
gen_vcond_mask_v8hiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2689 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* If we have (a = (P) ? -1 : 0);
     Then we can simply move the generated mask (result must be int).  */
  if (operands[1] == CONSTM1_RTX (V8HImode)
      && operands[2] == CONST0_RTX (V8HImode))
    emit_move_insn (operands[0], operands[3]);
  /* Similarly, (a = (P) ? 0 : -1) is just inverting the generated mask.  */
  else if (operands[1] == CONST0_RTX (V8HImode)
	   && operands[2] == CONSTM1_RTX (V8HImode))
    emit_insn (gen_one_cmplv8hi2 (operands[0], operands[3]));
  else
    {
      if (!REG_P (operands[1]))
	operands[1] = force_reg (V8HImode, operands[1]);
      if (!REG_P (operands[2]))
	operands[2] = force_reg (V8HImode, operands[2]);
      emit_insn (gen_aarch64_simd_bslv8hi (operands[0], operands[3],
					     operands[1], operands[2]));
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2683 */
rtx
gen_vcond_mask_v2siv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2689 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* If we have (a = (P) ? -1 : 0);
     Then we can simply move the generated mask (result must be int).  */
  if (operands[1] == CONSTM1_RTX (V2SImode)
      && operands[2] == CONST0_RTX (V2SImode))
    emit_move_insn (operands[0], operands[3]);
  /* Similarly, (a = (P) ? 0 : -1) is just inverting the generated mask.  */
  else if (operands[1] == CONST0_RTX (V2SImode)
	   && operands[2] == CONSTM1_RTX (V2SImode))
    emit_insn (gen_one_cmplv2si2 (operands[0], operands[3]));
  else
    {
      if (!REG_P (operands[1]))
	operands[1] = force_reg (V2SImode, operands[1]);
      if (!REG_P (operands[2]))
	operands[2] = force_reg (V2SImode, operands[2]);
      emit_insn (gen_aarch64_simd_bslv2si (operands[0], operands[3],
					     operands[1], operands[2]));
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2683 */
rtx
gen_vcond_mask_v4siv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2689 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* If we have (a = (P) ? -1 : 0);
     Then we can simply move the generated mask (result must be int).  */
  if (operands[1] == CONSTM1_RTX (V4SImode)
      && operands[2] == CONST0_RTX (V4SImode))
    emit_move_insn (operands[0], operands[3]);
  /* Similarly, (a = (P) ? 0 : -1) is just inverting the generated mask.  */
  else if (operands[1] == CONST0_RTX (V4SImode)
	   && operands[2] == CONSTM1_RTX (V4SImode))
    emit_insn (gen_one_cmplv4si2 (operands[0], operands[3]));
  else
    {
      if (!REG_P (operands[1]))
	operands[1] = force_reg (V4SImode, operands[1]);
      if (!REG_P (operands[2]))
	operands[2] = force_reg (V4SImode, operands[2]);
      emit_insn (gen_aarch64_simd_bslv4si (operands[0], operands[3],
					     operands[1], operands[2]));
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2683 */
rtx
gen_vcond_mask_v2div2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2689 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* If we have (a = (P) ? -1 : 0);
     Then we can simply move the generated mask (result must be int).  */
  if (operands[1] == CONSTM1_RTX (V2DImode)
      && operands[2] == CONST0_RTX (V2DImode))
    emit_move_insn (operands[0], operands[3]);
  /* Similarly, (a = (P) ? 0 : -1) is just inverting the generated mask.  */
  else if (operands[1] == CONST0_RTX (V2DImode)
	   && operands[2] == CONSTM1_RTX (V2DImode))
    emit_insn (gen_one_cmplv2di2 (operands[0], operands[3]));
  else
    {
      if (!REG_P (operands[1]))
	operands[1] = force_reg (V2DImode, operands[1]);
      if (!REG_P (operands[2]))
	operands[2] = force_reg (V2DImode, operands[2]);
      emit_insn (gen_aarch64_simd_bslv2di (operands[0], operands[3],
					     operands[1], operands[2]));
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2683 */
rtx
gen_vcond_mask_v2sfv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2689 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* If we have (a = (P) ? -1 : 0);
     Then we can simply move the generated mask (result must be int).  */
  if (operands[1] == CONSTM1_RTX (V2SFmode)
      && operands[2] == CONST0_RTX (V2SFmode))
    emit_move_insn (operands[0], operands[3]);
  /* Similarly, (a = (P) ? 0 : -1) is just inverting the generated mask.  */
  else if (operands[1] == CONST0_RTX (V2SFmode)
	   && operands[2] == CONSTM1_RTX (V2SFmode))
    emit_insn (gen_one_cmplv2si2 (operands[0], operands[3]));
  else
    {
      if (!REG_P (operands[1]))
	operands[1] = force_reg (V2SFmode, operands[1]);
      if (!REG_P (operands[2]))
	operands[2] = force_reg (V2SFmode, operands[2]);
      emit_insn (gen_aarch64_simd_bslv2sf (operands[0], operands[3],
					     operands[1], operands[2]));
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2683 */
rtx
gen_vcond_mask_v4sfv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2689 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* If we have (a = (P) ? -1 : 0);
     Then we can simply move the generated mask (result must be int).  */
  if (operands[1] == CONSTM1_RTX (V4SFmode)
      && operands[2] == CONST0_RTX (V4SFmode))
    emit_move_insn (operands[0], operands[3]);
  /* Similarly, (a = (P) ? 0 : -1) is just inverting the generated mask.  */
  else if (operands[1] == CONST0_RTX (V4SFmode)
	   && operands[2] == CONSTM1_RTX (V4SFmode))
    emit_insn (gen_one_cmplv4si2 (operands[0], operands[3]));
  else
    {
      if (!REG_P (operands[1]))
	operands[1] = force_reg (V4SFmode, operands[1]);
      if (!REG_P (operands[2]))
	operands[2] = force_reg (V4SFmode, operands[2]);
      emit_insn (gen_aarch64_simd_bslv4sf (operands[0], operands[3],
					     operands[1], operands[2]));
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2683 */
rtx
gen_vcond_mask_v2dfv2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2689 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* If we have (a = (P) ? -1 : 0);
     Then we can simply move the generated mask (result must be int).  */
  if (operands[1] == CONSTM1_RTX (V2DFmode)
      && operands[2] == CONST0_RTX (V2DFmode))
    emit_move_insn (operands[0], operands[3]);
  /* Similarly, (a = (P) ? 0 : -1) is just inverting the generated mask.  */
  else if (operands[1] == CONST0_RTX (V2DFmode)
	   && operands[2] == CONSTM1_RTX (V2DFmode))
    emit_insn (gen_one_cmplv2di2 (operands[0], operands[3]));
  else
    {
      if (!REG_P (operands[1]))
	operands[1] = force_reg (V2DFmode, operands[1]);
      if (!REG_P (operands[2]))
	operands[2] = force_reg (V2DFmode, operands[2]);
      emit_insn (gen_aarch64_simd_bslv2df (operands[0], operands[3],
					     operands[1], operands[2]));
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2683 */
rtx
gen_vcond_mask_didi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2689 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  /* If we have (a = (P) ? -1 : 0);
     Then we can simply move the generated mask (result must be int).  */
  if (operands[1] == CONSTM1_RTX (DImode)
      && operands[2] == CONST0_RTX (DImode))
    emit_move_insn (operands[0], operands[3]);
  /* Similarly, (a = (P) ? 0 : -1) is just inverting the generated mask.  */
  else if (operands[1] == CONST0_RTX (DImode)
	   && operands[2] == CONSTM1_RTX (DImode))
    emit_insn (gen_one_cmpldi2 (operands[0], operands[3]));
  else
    {
      if (!REG_P (operands[1]))
	operands[1] = force_reg (DImode, operands[1]);
      if (!REG_P (operands[2]))
	operands[2] = force_reg (DImode, operands[2]);
      emit_insn (gen_aarch64_simd_bsldi (operands[0], operands[3],
					     operands[1], operands[2]));
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2714 */
rtx
gen_vec_cmpv8qiv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2720 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = operands[0];
  enum rtx_code code = GET_CODE (operands[1]);

  switch (code)
    {
    case NE:
    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      if (operands[3] == CONST0_RTX (V8QImode))
	break;

      /* Fall through.  */
    default:
      if (!REG_P (operands[3]))
	operands[3] = force_reg (V8QImode, operands[3]);

      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv8qi (mask, operands[2], operands[3]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev8qi (mask, operands[2], operands[3]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev8qi (mask, operands[2], operands[3]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv8qi (mask, operands[2], operands[3]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv8qi (mask, operands[3], operands[2]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv8qi (mask, operands[2], operands[3]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv8qi (mask, operands[3], operands[2]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv8qi (mask, operands[2], operands[3]));
      break;

    case NE:
      /* Handle NE as !EQ.  */
      emit_insn (gen_aarch64_cmeqv8qi (mask, operands[2], operands[3]));
      emit_insn (gen_one_cmplv8qi2 (mask, mask));
      break;

    case EQ:
      emit_insn (gen_aarch64_cmeqv8qi (mask, operands[2], operands[3]));
      break;

    default:
      gcc_unreachable ();
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2714 */
rtx
gen_vec_cmpv16qiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2720 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = operands[0];
  enum rtx_code code = GET_CODE (operands[1]);

  switch (code)
    {
    case NE:
    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      if (operands[3] == CONST0_RTX (V16QImode))
	break;

      /* Fall through.  */
    default:
      if (!REG_P (operands[3]))
	operands[3] = force_reg (V16QImode, operands[3]);

      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv16qi (mask, operands[2], operands[3]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev16qi (mask, operands[2], operands[3]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev16qi (mask, operands[2], operands[3]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv16qi (mask, operands[2], operands[3]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv16qi (mask, operands[3], operands[2]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv16qi (mask, operands[2], operands[3]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv16qi (mask, operands[3], operands[2]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv16qi (mask, operands[2], operands[3]));
      break;

    case NE:
      /* Handle NE as !EQ.  */
      emit_insn (gen_aarch64_cmeqv16qi (mask, operands[2], operands[3]));
      emit_insn (gen_one_cmplv16qi2 (mask, mask));
      break;

    case EQ:
      emit_insn (gen_aarch64_cmeqv16qi (mask, operands[2], operands[3]));
      break;

    default:
      gcc_unreachable ();
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2714 */
rtx
gen_vec_cmpv4hiv4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2720 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = operands[0];
  enum rtx_code code = GET_CODE (operands[1]);

  switch (code)
    {
    case NE:
    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      if (operands[3] == CONST0_RTX (V4HImode))
	break;

      /* Fall through.  */
    default:
      if (!REG_P (operands[3]))
	operands[3] = force_reg (V4HImode, operands[3]);

      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv4hi (mask, operands[2], operands[3]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev4hi (mask, operands[2], operands[3]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev4hi (mask, operands[2], operands[3]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv4hi (mask, operands[2], operands[3]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv4hi (mask, operands[3], operands[2]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv4hi (mask, operands[2], operands[3]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv4hi (mask, operands[3], operands[2]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv4hi (mask, operands[2], operands[3]));
      break;

    case NE:
      /* Handle NE as !EQ.  */
      emit_insn (gen_aarch64_cmeqv4hi (mask, operands[2], operands[3]));
      emit_insn (gen_one_cmplv4hi2 (mask, mask));
      break;

    case EQ:
      emit_insn (gen_aarch64_cmeqv4hi (mask, operands[2], operands[3]));
      break;

    default:
      gcc_unreachable ();
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2714 */
rtx
gen_vec_cmpv8hiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2720 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = operands[0];
  enum rtx_code code = GET_CODE (operands[1]);

  switch (code)
    {
    case NE:
    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      if (operands[3] == CONST0_RTX (V8HImode))
	break;

      /* Fall through.  */
    default:
      if (!REG_P (operands[3]))
	operands[3] = force_reg (V8HImode, operands[3]);

      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv8hi (mask, operands[2], operands[3]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev8hi (mask, operands[2], operands[3]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev8hi (mask, operands[2], operands[3]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv8hi (mask, operands[2], operands[3]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv8hi (mask, operands[3], operands[2]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv8hi (mask, operands[2], operands[3]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv8hi (mask, operands[3], operands[2]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv8hi (mask, operands[2], operands[3]));
      break;

    case NE:
      /* Handle NE as !EQ.  */
      emit_insn (gen_aarch64_cmeqv8hi (mask, operands[2], operands[3]));
      emit_insn (gen_one_cmplv8hi2 (mask, mask));
      break;

    case EQ:
      emit_insn (gen_aarch64_cmeqv8hi (mask, operands[2], operands[3]));
      break;

    default:
      gcc_unreachable ();
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2714 */
rtx
gen_vec_cmpv2siv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2720 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = operands[0];
  enum rtx_code code = GET_CODE (operands[1]);

  switch (code)
    {
    case NE:
    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      if (operands[3] == CONST0_RTX (V2SImode))
	break;

      /* Fall through.  */
    default:
      if (!REG_P (operands[3]))
	operands[3] = force_reg (V2SImode, operands[3]);

      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv2si (mask, operands[2], operands[3]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev2si (mask, operands[2], operands[3]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev2si (mask, operands[2], operands[3]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv2si (mask, operands[2], operands[3]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv2si (mask, operands[3], operands[2]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv2si (mask, operands[2], operands[3]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv2si (mask, operands[3], operands[2]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv2si (mask, operands[2], operands[3]));
      break;

    case NE:
      /* Handle NE as !EQ.  */
      emit_insn (gen_aarch64_cmeqv2si (mask, operands[2], operands[3]));
      emit_insn (gen_one_cmplv2si2 (mask, mask));
      break;

    case EQ:
      emit_insn (gen_aarch64_cmeqv2si (mask, operands[2], operands[3]));
      break;

    default:
      gcc_unreachable ();
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2714 */
rtx
gen_vec_cmpv4siv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2720 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = operands[0];
  enum rtx_code code = GET_CODE (operands[1]);

  switch (code)
    {
    case NE:
    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      if (operands[3] == CONST0_RTX (V4SImode))
	break;

      /* Fall through.  */
    default:
      if (!REG_P (operands[3]))
	operands[3] = force_reg (V4SImode, operands[3]);

      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv4si (mask, operands[2], operands[3]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev4si (mask, operands[2], operands[3]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev4si (mask, operands[2], operands[3]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv4si (mask, operands[2], operands[3]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv4si (mask, operands[3], operands[2]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv4si (mask, operands[2], operands[3]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv4si (mask, operands[3], operands[2]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv4si (mask, operands[2], operands[3]));
      break;

    case NE:
      /* Handle NE as !EQ.  */
      emit_insn (gen_aarch64_cmeqv4si (mask, operands[2], operands[3]));
      emit_insn (gen_one_cmplv4si2 (mask, mask));
      break;

    case EQ:
      emit_insn (gen_aarch64_cmeqv4si (mask, operands[2], operands[3]));
      break;

    default:
      gcc_unreachable ();
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2714 */
rtx
gen_vec_cmpv2div2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2720 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = operands[0];
  enum rtx_code code = GET_CODE (operands[1]);

  switch (code)
    {
    case NE:
    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      if (operands[3] == CONST0_RTX (V2DImode))
	break;

      /* Fall through.  */
    default:
      if (!REG_P (operands[3]))
	operands[3] = force_reg (V2DImode, operands[3]);

      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv2di (mask, operands[2], operands[3]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev2di (mask, operands[2], operands[3]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev2di (mask, operands[2], operands[3]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv2di (mask, operands[2], operands[3]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv2di (mask, operands[3], operands[2]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv2di (mask, operands[2], operands[3]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv2di (mask, operands[3], operands[2]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv2di (mask, operands[2], operands[3]));
      break;

    case NE:
      /* Handle NE as !EQ.  */
      emit_insn (gen_aarch64_cmeqv2di (mask, operands[2], operands[3]));
      emit_insn (gen_one_cmplv2di2 (mask, mask));
      break;

    case EQ:
      emit_insn (gen_aarch64_cmeqv2di (mask, operands[2], operands[3]));
      break;

    default:
      gcc_unreachable ();
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2714 */
rtx
gen_vec_cmpdidi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2720 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = operands[0];
  enum rtx_code code = GET_CODE (operands[1]);

  switch (code)
    {
    case NE:
    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      if (operands[3] == CONST0_RTX (DImode))
	break;

      /* Fall through.  */
    default:
      if (!REG_P (operands[3]))
	operands[3] = force_reg (DImode, operands[3]);

      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltdi (mask, operands[2], operands[3]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgedi (mask, operands[2], operands[3]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmledi (mask, operands[2], operands[3]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtdi (mask, operands[2], operands[3]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtudi (mask, operands[3], operands[2]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeudi (mask, operands[2], operands[3]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeudi (mask, operands[3], operands[2]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtudi (mask, operands[2], operands[3]));
      break;

    case NE:
      /* Handle NE as !EQ.  */
      emit_insn (gen_aarch64_cmeqdi (mask, operands[2], operands[3]));
      emit_insn (gen_one_cmpldi2 (mask, mask));
      break;

    case EQ:
      emit_insn (gen_aarch64_cmeqdi (mask, operands[2], operands[3]));
      break;

    default:
      gcc_unreachable ();
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2794 */
rtx
gen_vec_cmpv2sfv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2800 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int use_zero_form = 0;
  enum rtx_code code = GET_CODE (operands[1]);
  rtx tmp = gen_reg_rtx (V2SImode);

  rtx (*comparison) (rtx, rtx, rtx) = NULL;

  switch (code)
    {
    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      if (operands[3] == CONST0_RTX (V2SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[3]))
	operands[3] = force_reg (V2SFmode, operands[3]);

      break;
    }

  switch (code)
    {
    case LT:
      if (use_zero_form)
	{
	  comparison = gen_aarch64_cmltv2sf;
	  break;
	}
      /* Fall through.  */
    case UNLT:
      std::swap (operands[2], operands[3]);
      /* Fall through.  */
    case UNGT:
    case GT:
      comparison = gen_aarch64_cmgtv2sf;
      break;
    case LE:
      if (use_zero_form)
	{
	  comparison = gen_aarch64_cmlev2sf;
	  break;
	}
      /* Fall through.  */
    case UNLE:
      std::swap (operands[2], operands[3]);
      /* Fall through.  */
    case UNGE:
    case GE:
      comparison = gen_aarch64_cmgev2sf;
      break;
    case NE:
    case EQ:
      comparison = gen_aarch64_cmeqv2sf;
      break;
    case UNEQ:
    case ORDERED:
    case UNORDERED:
    case LTGT:
      break;
    default:
      gcc_unreachable ();
    }

  switch (code)
    {
    case UNGE:
    case UNGT:
    case UNLE:
    case UNLT:
      {
	/* All of the above must not raise any FP exceptions.  Thus we first
	   check each operand for NaNs and force any elements containing NaN to
	   zero before using them in the compare.
	   Example: UN<cc> (a, b) -> UNORDERED (a, b) |
				     (cm<cc> (isnan (a) ? 0.0 : a,
					      isnan (b) ? 0.0 : b))
	   We use the following transformations for doing the comparisions:
	   a UNGE b -> a GE b
	   a UNGT b -> a GT b
	   a UNLE b -> b GE a
	   a UNLT b -> b GT a.  */

	rtx tmp0 = gen_reg_rtx (V2SImode);
	rtx tmp1 = gen_reg_rtx (V2SImode);
	rtx tmp2 = gen_reg_rtx (V2SImode);
	emit_insn (gen_aarch64_cmeqv2sf (tmp0, operands[2], operands[2]));
	emit_insn (gen_aarch64_cmeqv2sf (tmp1, operands[3], operands[3]));
	emit_insn (gen_andv2si3 (tmp2, tmp0, tmp1));
	emit_insn (gen_andv2si3 (tmp0, tmp0,
					  lowpart_subreg (V2SImode,
							  operands[2],
							  V2SFmode)));
	emit_insn (gen_andv2si3 (tmp1, tmp1,
					  lowpart_subreg (V2SImode,
							  operands[3],
							  V2SFmode)));
	gcc_assert (comparison != NULL);
	emit_insn (comparison (operands[0],
			       lowpart_subreg (V2SFmode,
					       tmp0, V2SImode),
			       lowpart_subreg (V2SFmode,
					       tmp1, V2SImode)));
	emit_insn (gen_ornv2si3 (operands[0], tmp2, operands[0]));
      }
      break;

    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
    case NE:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 a NE b -> ~(a EQ b)  */
      gcc_assert (comparison != NULL);
      emit_insn (comparison (operands[0], operands[2], operands[3]));
      if (code == NE)
	emit_insn (gen_one_cmplv2si2 (operands[0], operands[0]));
      break;

    case LTGT:
      /* LTGT is not guranteed to not generate a FP exception.  So let's
	 go the faster way : ((a > b) || (b > a)).  */
      emit_insn (gen_aarch64_cmgtv2sf (operands[0],
					 operands[2], operands[3]));
      emit_insn (gen_aarch64_cmgtv2sf (tmp, operands[3], operands[2]));
      emit_insn (gen_iorv2si3 (operands[0], operands[0], tmp));
      break;

    case ORDERED:
    case UNORDERED:
    case UNEQ:
      /* cmeq (a, a) & cmeq (b, b).  */
      emit_insn (gen_aarch64_cmeqv2sf (operands[0],
					 operands[2], operands[2]));
      emit_insn (gen_aarch64_cmeqv2sf (tmp, operands[3], operands[3]));
      emit_insn (gen_andv2si3 (operands[0], operands[0], tmp));

      if (code == UNORDERED)
	emit_insn (gen_one_cmplv2si2 (operands[0], operands[0]));
      else if (code == UNEQ)
	{
	  emit_insn (gen_aarch64_cmeqv2sf (tmp, operands[2], operands[3]));
	  emit_insn (gen_ornv2si3 (operands[0], operands[0], tmp));
	}
      break;

    default:
      gcc_unreachable ();
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2794 */
rtx
gen_vec_cmpv4sfv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2800 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int use_zero_form = 0;
  enum rtx_code code = GET_CODE (operands[1]);
  rtx tmp = gen_reg_rtx (V4SImode);

  rtx (*comparison) (rtx, rtx, rtx) = NULL;

  switch (code)
    {
    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      if (operands[3] == CONST0_RTX (V4SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[3]))
	operands[3] = force_reg (V4SFmode, operands[3]);

      break;
    }

  switch (code)
    {
    case LT:
      if (use_zero_form)
	{
	  comparison = gen_aarch64_cmltv4sf;
	  break;
	}
      /* Fall through.  */
    case UNLT:
      std::swap (operands[2], operands[3]);
      /* Fall through.  */
    case UNGT:
    case GT:
      comparison = gen_aarch64_cmgtv4sf;
      break;
    case LE:
      if (use_zero_form)
	{
	  comparison = gen_aarch64_cmlev4sf;
	  break;
	}
      /* Fall through.  */
    case UNLE:
      std::swap (operands[2], operands[3]);
      /* Fall through.  */
    case UNGE:
    case GE:
      comparison = gen_aarch64_cmgev4sf;
      break;
    case NE:
    case EQ:
      comparison = gen_aarch64_cmeqv4sf;
      break;
    case UNEQ:
    case ORDERED:
    case UNORDERED:
    case LTGT:
      break;
    default:
      gcc_unreachable ();
    }

  switch (code)
    {
    case UNGE:
    case UNGT:
    case UNLE:
    case UNLT:
      {
	/* All of the above must not raise any FP exceptions.  Thus we first
	   check each operand for NaNs and force any elements containing NaN to
	   zero before using them in the compare.
	   Example: UN<cc> (a, b) -> UNORDERED (a, b) |
				     (cm<cc> (isnan (a) ? 0.0 : a,
					      isnan (b) ? 0.0 : b))
	   We use the following transformations for doing the comparisions:
	   a UNGE b -> a GE b
	   a UNGT b -> a GT b
	   a UNLE b -> b GE a
	   a UNLT b -> b GT a.  */

	rtx tmp0 = gen_reg_rtx (V4SImode);
	rtx tmp1 = gen_reg_rtx (V4SImode);
	rtx tmp2 = gen_reg_rtx (V4SImode);
	emit_insn (gen_aarch64_cmeqv4sf (tmp0, operands[2], operands[2]));
	emit_insn (gen_aarch64_cmeqv4sf (tmp1, operands[3], operands[3]));
	emit_insn (gen_andv4si3 (tmp2, tmp0, tmp1));
	emit_insn (gen_andv4si3 (tmp0, tmp0,
					  lowpart_subreg (V4SImode,
							  operands[2],
							  V4SFmode)));
	emit_insn (gen_andv4si3 (tmp1, tmp1,
					  lowpart_subreg (V4SImode,
							  operands[3],
							  V4SFmode)));
	gcc_assert (comparison != NULL);
	emit_insn (comparison (operands[0],
			       lowpart_subreg (V4SFmode,
					       tmp0, V4SImode),
			       lowpart_subreg (V4SFmode,
					       tmp1, V4SImode)));
	emit_insn (gen_ornv4si3 (operands[0], tmp2, operands[0]));
      }
      break;

    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
    case NE:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 a NE b -> ~(a EQ b)  */
      gcc_assert (comparison != NULL);
      emit_insn (comparison (operands[0], operands[2], operands[3]));
      if (code == NE)
	emit_insn (gen_one_cmplv4si2 (operands[0], operands[0]));
      break;

    case LTGT:
      /* LTGT is not guranteed to not generate a FP exception.  So let's
	 go the faster way : ((a > b) || (b > a)).  */
      emit_insn (gen_aarch64_cmgtv4sf (operands[0],
					 operands[2], operands[3]));
      emit_insn (gen_aarch64_cmgtv4sf (tmp, operands[3], operands[2]));
      emit_insn (gen_iorv4si3 (operands[0], operands[0], tmp));
      break;

    case ORDERED:
    case UNORDERED:
    case UNEQ:
      /* cmeq (a, a) & cmeq (b, b).  */
      emit_insn (gen_aarch64_cmeqv4sf (operands[0],
					 operands[2], operands[2]));
      emit_insn (gen_aarch64_cmeqv4sf (tmp, operands[3], operands[3]));
      emit_insn (gen_andv4si3 (operands[0], operands[0], tmp));

      if (code == UNORDERED)
	emit_insn (gen_one_cmplv4si2 (operands[0], operands[0]));
      else if (code == UNEQ)
	{
	  emit_insn (gen_aarch64_cmeqv4sf (tmp, operands[2], operands[3]));
	  emit_insn (gen_ornv4si3 (operands[0], operands[0], tmp));
	}
      break;

    default:
      gcc_unreachable ();
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2794 */
rtx
gen_vec_cmpv2dfv2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2800 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int use_zero_form = 0;
  enum rtx_code code = GET_CODE (operands[1]);
  rtx tmp = gen_reg_rtx (V2DImode);

  rtx (*comparison) (rtx, rtx, rtx) = NULL;

  switch (code)
    {
    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      if (operands[3] == CONST0_RTX (V2DFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[3]))
	operands[3] = force_reg (V2DFmode, operands[3]);

      break;
    }

  switch (code)
    {
    case LT:
      if (use_zero_form)
	{
	  comparison = gen_aarch64_cmltv2df;
	  break;
	}
      /* Fall through.  */
    case UNLT:
      std::swap (operands[2], operands[3]);
      /* Fall through.  */
    case UNGT:
    case GT:
      comparison = gen_aarch64_cmgtv2df;
      break;
    case LE:
      if (use_zero_form)
	{
	  comparison = gen_aarch64_cmlev2df;
	  break;
	}
      /* Fall through.  */
    case UNLE:
      std::swap (operands[2], operands[3]);
      /* Fall through.  */
    case UNGE:
    case GE:
      comparison = gen_aarch64_cmgev2df;
      break;
    case NE:
    case EQ:
      comparison = gen_aarch64_cmeqv2df;
      break;
    case UNEQ:
    case ORDERED:
    case UNORDERED:
    case LTGT:
      break;
    default:
      gcc_unreachable ();
    }

  switch (code)
    {
    case UNGE:
    case UNGT:
    case UNLE:
    case UNLT:
      {
	/* All of the above must not raise any FP exceptions.  Thus we first
	   check each operand for NaNs and force any elements containing NaN to
	   zero before using them in the compare.
	   Example: UN<cc> (a, b) -> UNORDERED (a, b) |
				     (cm<cc> (isnan (a) ? 0.0 : a,
					      isnan (b) ? 0.0 : b))
	   We use the following transformations for doing the comparisions:
	   a UNGE b -> a GE b
	   a UNGT b -> a GT b
	   a UNLE b -> b GE a
	   a UNLT b -> b GT a.  */

	rtx tmp0 = gen_reg_rtx (V2DImode);
	rtx tmp1 = gen_reg_rtx (V2DImode);
	rtx tmp2 = gen_reg_rtx (V2DImode);
	emit_insn (gen_aarch64_cmeqv2df (tmp0, operands[2], operands[2]));
	emit_insn (gen_aarch64_cmeqv2df (tmp1, operands[3], operands[3]));
	emit_insn (gen_andv2di3 (tmp2, tmp0, tmp1));
	emit_insn (gen_andv2di3 (tmp0, tmp0,
					  lowpart_subreg (V2DImode,
							  operands[2],
							  V2DFmode)));
	emit_insn (gen_andv2di3 (tmp1, tmp1,
					  lowpart_subreg (V2DImode,
							  operands[3],
							  V2DFmode)));
	gcc_assert (comparison != NULL);
	emit_insn (comparison (operands[0],
			       lowpart_subreg (V2DFmode,
					       tmp0, V2DImode),
			       lowpart_subreg (V2DFmode,
					       tmp1, V2DImode)));
	emit_insn (gen_ornv2di3 (operands[0], tmp2, operands[0]));
      }
      break;

    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
    case NE:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 a NE b -> ~(a EQ b)  */
      gcc_assert (comparison != NULL);
      emit_insn (comparison (operands[0], operands[2], operands[3]));
      if (code == NE)
	emit_insn (gen_one_cmplv2di2 (operands[0], operands[0]));
      break;

    case LTGT:
      /* LTGT is not guranteed to not generate a FP exception.  So let's
	 go the faster way : ((a > b) || (b > a)).  */
      emit_insn (gen_aarch64_cmgtv2df (operands[0],
					 operands[2], operands[3]));
      emit_insn (gen_aarch64_cmgtv2df (tmp, operands[3], operands[2]));
      emit_insn (gen_iorv2di3 (operands[0], operands[0], tmp));
      break;

    case ORDERED:
    case UNORDERED:
    case UNEQ:
      /* cmeq (a, a) & cmeq (b, b).  */
      emit_insn (gen_aarch64_cmeqv2df (operands[0],
					 operands[2], operands[2]));
      emit_insn (gen_aarch64_cmeqv2df (tmp, operands[3], operands[3]));
      emit_insn (gen_andv2di3 (operands[0], operands[0], tmp));

      if (code == UNORDERED)
	emit_insn (gen_one_cmplv2di2 (operands[0], operands[0]));
      else if (code == UNEQ)
	{
	  emit_insn (gen_aarch64_cmeqv2df (tmp, operands[2], operands[3]));
	  emit_insn (gen_ornv2di3 (operands[0], operands[0], tmp));
	}
      break;

    default:
      gcc_unreachable ();
    }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2967 */
rtx
gen_vec_cmpuv8qiv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2973 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_vec_cmpv8qiv8qi (operands[0], operands[1],
				      operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2967 */
rtx
gen_vec_cmpuv16qiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2973 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_vec_cmpv16qiv16qi (operands[0], operands[1],
				      operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2967 */
rtx
gen_vec_cmpuv4hiv4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2973 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_vec_cmpv4hiv4hi (operands[0], operands[1],
				      operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2967 */
rtx
gen_vec_cmpuv8hiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2973 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_vec_cmpv8hiv8hi (operands[0], operands[1],
				      operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2967 */
rtx
gen_vec_cmpuv2siv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2973 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_vec_cmpv2siv2si (operands[0], operands[1],
				      operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2967 */
rtx
gen_vec_cmpuv4siv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2973 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_vec_cmpv4siv4si (operands[0], operands[1],
				      operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2967 */
rtx
gen_vec_cmpuv2div2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2973 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_vec_cmpv2div2di (operands[0], operands[1],
				      operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2967 */
rtx
gen_vec_cmpudidi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2973 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_vec_cmpdidi (operands[0], operands[1],
				      operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2979 */
rtx
gen_vcondv8qiv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2988 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V8QImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv8qiv8qi (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v8qiv8qi (operands[0], operands[1],
						 operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V8QImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2979 */
rtx
gen_vcondv16qiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2988 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V16QImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv16qiv16qi (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v16qiv16qi (operands[0], operands[1],
						 operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V16QImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2979 */
rtx
gen_vcondv4hiv4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2988 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V4HImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv4hiv4hi (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v4hiv4hi (operands[0], operands[1],
						 operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4HImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2979 */
rtx
gen_vcondv8hiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2988 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V8HImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv8hiv8hi (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v8hiv8hi (operands[0], operands[1],
						 operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V8HImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2979 */
rtx
gen_vcondv2siv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2988 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V2SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv2siv2si (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v2siv2si (operands[0], operands[1],
						 operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2979 */
rtx
gen_vcondv4siv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2988 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V4SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv4siv4si (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v4siv4si (operands[0], operands[1],
						 operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2979 */
rtx
gen_vcondv2div2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2988 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V2DImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv2div2di (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v2div2di (operands[0], operands[1],
						 operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2979 */
rtx
gen_vcondv2sfv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2988 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V2SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv2sfv2si (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v2sfv2si (operands[0], operands[1],
						 operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2979 */
rtx
gen_vcondv4sfv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2988 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V4SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv4sfv4si (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v4sfv4si (operands[0], operands[1],
						 operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2979 */
rtx
gen_vcondv2dfv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2988 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V2DImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv2dfv2di (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v2dfv2di (operands[0], operands[1],
						 operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:2979 */
rtx
gen_vconddidi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2988 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (DImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpdidi (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_didi (operands[0], operands[1],
						 operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3009 */
rtx
gen_vcondv2siv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3018 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V2SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv2sfv2si (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v2siv2si (
						operands[0], operands[1],
						operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3009 */
rtx
gen_vcondv2sfv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3018 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V2SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv2siv2si (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v2sfv2si (
						operands[0], operands[1],
						operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3009 */
rtx
gen_vcondv4siv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3018 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V4SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv4sfv4si (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v4siv4si (
						operands[0], operands[1],
						operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3009 */
rtx
gen_vcondv4sfv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3018 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V4SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv4siv4si (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v4sfv4si (
						operands[0], operands[1],
						operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3009 */
rtx
gen_vcondv2div2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3018 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V2DImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv2dfv2di (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v2div2di (
						operands[0], operands[1],
						operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3009 */
rtx
gen_vcondv2dfv2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3018 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V2DImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv2div2di (mask, operands[3],
					     operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v2dfv2di (
						operands[0], operands[1],
						operands[2], mask));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3040 */
rtx
gen_vconduv8qiv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3049 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V8QImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv8qiv8qi (mask, operands[3],
				      operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v8qiv8qi (operands[0], operands[1],
						 operands[2], mask));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V8QImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3040 */
rtx
gen_vconduv16qiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3049 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V16QImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv16qiv16qi (mask, operands[3],
				      operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v16qiv16qi (operands[0], operands[1],
						 operands[2], mask));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V16QImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3040 */
rtx
gen_vconduv4hiv4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3049 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V4HImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv4hiv4hi (mask, operands[3],
				      operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v4hiv4hi (operands[0], operands[1],
						 operands[2], mask));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4HImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3040 */
rtx
gen_vconduv8hiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3049 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V8HImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv8hiv8hi (mask, operands[3],
				      operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v8hiv8hi (operands[0], operands[1],
						 operands[2], mask));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V8HImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3040 */
rtx
gen_vconduv2siv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3049 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V2SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv2siv2si (mask, operands[3],
				      operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v2siv2si (operands[0], operands[1],
						 operands[2], mask));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3040 */
rtx
gen_vconduv4siv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3049 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V4SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv4siv4si (mask, operands[3],
				      operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v4siv4si (operands[0], operands[1],
						 operands[2], mask));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3040 */
rtx
gen_vconduv2div2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3049 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V2DImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv2div2di (mask, operands[3],
				      operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v2div2di (operands[0], operands[1],
						 operands[2], mask));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3040 */
rtx
gen_vcondudidi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3049 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (DImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpdidi (mask, operands[3],
				      operands[4], operands[5]));
  emit_insn (gen_vcond_mask_didi (operands[0], operands[1],
						 operands[2], mask));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3069 */
rtx
gen_vconduv2sfv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3078 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V2SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv2siv2si (
						  mask, operands[3],
						  operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v2sfv2si (operands[0], operands[1],
						 operands[2], mask));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3069 */
rtx
gen_vconduv4sfv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3078 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V4SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv4siv4si (
						  mask, operands[3],
						  operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v4sfv4si (operands[0], operands[1],
						 operands[2], mask));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3069 */
rtx
gen_vconduv2dfv2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3078 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mask = gen_reg_rtx (V2DImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
     it as well as switch operands 1/2 in order to avoid the additional
     NOT instruction.  */
  if (code == NE)
    {
      operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
				    operands[4], operands[5]);
      std::swap (operands[1], operands[2]);
    }
  emit_insn (gen_vec_cmpv2div2di (
						  mask, operands[3],
						  operands[4], operands[5]));
  emit_insn (gen_vcond_mask_v2dfv2di (operands[0], operands[1],
						 operands[2], mask));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3214 */
rtx
gen_aarch64_combinev8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3219 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_combine (operands[0], operands[1], operands[2]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3214 */
rtx
gen_aarch64_combinev4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3219 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_combine (operands[0], operands[1], operands[2]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3214 */
rtx
gen_aarch64_combinev4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3219 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_combine (operands[0], operands[1], operands[2]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3214 */
rtx
gen_aarch64_combinev2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3219 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_combine (operands[0], operands[1], operands[2]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3214 */
rtx
gen_aarch64_combinev2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3219 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_combine (operands[0], operands[1], operands[2]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3214 */
rtx
gen_aarch64_combinedi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3219 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_combine (operands[0], operands[1], operands[2]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3214 */
rtx
gen_aarch64_combinedf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3219 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_combine (operands[0], operands[1], operands[2]);

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_simd_combinev8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3231 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v16qi (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v16qi (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_simd_combinev4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3231 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v8hi (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v8hi (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_simd_combinev4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3231 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v8hf (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v8hf (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_simd_combinev2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3231 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v4si (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v4si (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_simd_combinev2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3231 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v4sf (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v4sf (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_simd_combinedi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3231 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v2di (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v2di (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_simd_combinedf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3231 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v2df (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v2df (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3268 */
rtx
gen_aarch64_saddl2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, true);
  emit_insn (gen_aarch64_saddlv16qi_hi_internal (operands[0], operands[1],
                                                  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3268 */
rtx
gen_aarch64_saddl2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_saddlv8hi_hi_internal (operands[0], operands[1],
                                                  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3268 */
rtx
gen_aarch64_saddl2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_saddlv4si_hi_internal (operands[0], operands[1],
                                                  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3280 */
rtx
gen_aarch64_uaddl2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3285 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, true);
  emit_insn (gen_aarch64_uaddlv16qi_hi_internal (operands[0], operands[1],
                                                  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3280 */
rtx
gen_aarch64_uaddl2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3285 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_uaddlv8hi_hi_internal (operands[0], operands[1],
                                                  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3280 */
rtx
gen_aarch64_uaddl2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3285 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_uaddlv4si_hi_internal (operands[0], operands[1],
                                                  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3292 */
rtx
gen_aarch64_ssubl2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3297 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, true);
  emit_insn (gen_aarch64_ssublv16qi_hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3292 */
rtx
gen_aarch64_ssubl2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3297 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_ssublv8hi_hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3292 */
rtx
gen_aarch64_ssubl2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3297 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_ssublv4si_hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3304 */
rtx
gen_aarch64_usubl2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3309 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, true);
  emit_insn (gen_aarch64_usublv16qi_hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3304 */
rtx
gen_aarch64_usubl2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3309 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_usublv8hi_hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3304 */
rtx
gen_aarch64_usubl2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3309 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_usublv4si_hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3329 */
rtx
gen_widen_ssumv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3335 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, false);
    rtx temp = gen_reg_rtx (GET_MODE (operands[0]));

    emit_insn (gen_aarch64_saddwv16qi_internal (temp, operands[2],
						operands[1], p));
    emit_insn (gen_aarch64_saddw2v16qi (operands[0], temp, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3329 */
rtx
gen_widen_ssumv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3335 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, false);
    rtx temp = gen_reg_rtx (GET_MODE (operands[0]));

    emit_insn (gen_aarch64_saddwv8hi_internal (temp, operands[2],
						operands[1], p));
    emit_insn (gen_aarch64_saddw2v8hi (operands[0], temp, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3329 */
rtx
gen_widen_ssumv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3335 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, false);
    rtx temp = gen_reg_rtx (GET_MODE (operands[0]));

    emit_insn (gen_aarch64_saddwv4si_internal (temp, operands[2],
						operands[1], p));
    emit_insn (gen_aarch64_saddw2v4si (operands[0], temp, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3346 */
rtx
gen_widen_ssumv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3352 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_saddwv8qi (operands[0], operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3346 */
rtx
gen_widen_ssumv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3352 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_saddwv4hi (operands[0], operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3346 */
rtx
gen_widen_ssumv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3352 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_saddwv2si (operands[0], operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3357 */
rtx
gen_widen_usumv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3363 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, false);
    rtx temp = gen_reg_rtx (GET_MODE (operands[0]));

    emit_insn (gen_aarch64_uaddwv16qi_internal (temp, operands[2],
						 operands[1], p));
    emit_insn (gen_aarch64_uaddw2v16qi (operands[0], temp, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3357 */
rtx
gen_widen_usumv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3363 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, false);
    rtx temp = gen_reg_rtx (GET_MODE (operands[0]));

    emit_insn (gen_aarch64_uaddwv8hi_internal (temp, operands[2],
						 operands[1], p));
    emit_insn (gen_aarch64_uaddw2v8hi (operands[0], temp, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3357 */
rtx
gen_widen_usumv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3363 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, false);
    rtx temp = gen_reg_rtx (GET_MODE (operands[0]));

    emit_insn (gen_aarch64_uaddwv4si_internal (temp, operands[2],
						 operands[1], p));
    emit_insn (gen_aarch64_uaddw2v4si (operands[0], temp, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3374 */
rtx
gen_widen_usumv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3380 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_uaddwv8qi (operands[0], operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3374 */
rtx
gen_widen_usumv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3380 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_uaddwv4hi (operands[0], operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3374 */
rtx
gen_widen_usumv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3380 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_uaddwv2si (operands[0], operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3455 */
rtx
gen_aarch64_saddw2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3460 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, true);
  emit_insn (gen_aarch64_saddw2v16qi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3455 */
rtx
gen_aarch64_saddw2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3460 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_saddw2v8hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3455 */
rtx
gen_aarch64_saddw2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3460 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_saddw2v4si_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3467 */
rtx
gen_aarch64_uaddw2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3472 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, true);
  emit_insn (gen_aarch64_uaddw2v16qi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3467 */
rtx
gen_aarch64_uaddw2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3472 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_uaddw2v8hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3467 */
rtx
gen_aarch64_uaddw2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3472 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_uaddw2v4si_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3480 */
rtx
gen_aarch64_ssubw2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, true);
  emit_insn (gen_aarch64_ssubw2v16qi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3480 */
rtx
gen_aarch64_ssubw2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_ssubw2v8hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3480 */
rtx
gen_aarch64_ssubw2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_ssubw2v4si_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3492 */
rtx
gen_aarch64_usubw2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3497 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, 16, true);
  emit_insn (gen_aarch64_usubw2v16qi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3492 */
rtx
gen_aarch64_usubw2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3497 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_usubw2v8hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3492 */
rtx
gen_aarch64_usubw2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3497 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_usubw2v4si_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3506 */
rtx
gen_avgv8qi3_floor (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3506 */
rtx
gen_uavgv8qi3_floor (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3506 */
rtx
gen_avgv16qi3_floor (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3506 */
rtx
gen_uavgv16qi3_floor (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3506 */
rtx
gen_avgv4hi3_floor (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3506 */
rtx
gen_uavgv4hi3_floor (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3506 */
rtx
gen_avgv8hi3_floor (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3506 */
rtx
gen_uavgv8hi3_floor (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3506 */
rtx
gen_avgv2si3_floor (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3506 */
rtx
gen_uavgv2si3_floor (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3506 */
rtx
gen_avgv4si3_floor (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3506 */
rtx
gen_uavgv4si3_floor (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3514 */
rtx
gen_avgv8qi3_ceil (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3514 */
rtx
gen_uavgv8qi3_ceil (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3514 */
rtx
gen_avgv16qi3_ceil (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3514 */
rtx
gen_uavgv16qi3_ceil (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3514 */
rtx
gen_avgv4hi3_ceil (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3514 */
rtx
gen_uavgv4hi3_ceil (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3514 */
rtx
gen_avgv8hi3_ceil (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3514 */
rtx
gen_uavgv8hi3_ceil (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3514 */
rtx
gen_avgv2si3_ceil (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3514 */
rtx
gen_uavgv2si3_ceil (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3514 */
rtx
gen_avgv4si3_ceil (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:3514 */
rtx
gen_uavgv4si3_ceil (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4027 */
rtx
gen_aarch64_sqdmlal2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4033 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_sqdmlal2v8hi_internal (operands[0], operands[1],
						  operands[2], operands[3], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4027 */
rtx
gen_aarch64_sqdmlal2v4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4033 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_sqdmlal2v4si_internal (operands[0], operands[1],
						  operands[2], operands[3], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4040 */
rtx
gen_aarch64_sqdmlsl2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4046 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_sqdmlsl2v8hi_internal (operands[0], operands[1],
						  operands[2], operands[3], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4040 */
rtx
gen_aarch64_sqdmlsl2v4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4046 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_sqdmlsl2v4si_internal (operands[0], operands[1],
						  operands[2], operands[3], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4107 */
rtx
gen_aarch64_sqdmlal2_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4114 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_sqdmlal2_lanev8hi_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4107 */
rtx
gen_aarch64_sqdmlal2_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4114 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_sqdmlal2_lanev4si_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4122 */
rtx
gen_aarch64_sqdmlal2_laneqv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4129 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_sqdmlal2_laneqv8hi_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4122 */
rtx
gen_aarch64_sqdmlal2_laneqv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4129 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_sqdmlal2_laneqv4si_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4137 */
rtx
gen_aarch64_sqdmlsl2_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4144 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_sqdmlsl2_lanev8hi_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4137 */
rtx
gen_aarch64_sqdmlsl2_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4144 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_sqdmlsl2_lanev4si_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4152 */
rtx
gen_aarch64_sqdmlsl2_laneqv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4159 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_sqdmlsl2_laneqv8hi_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4152 */
rtx
gen_aarch64_sqdmlsl2_laneqv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4159 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_sqdmlsl2_laneqv4si_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4186 */
rtx
gen_aarch64_sqdmlal2_nv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4192 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_sqdmlal2_nv8hi_internal (operands[0], operands[1],
						    operands[2], operands[3],
						    p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4186 */
rtx
gen_aarch64_sqdmlal2_nv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4192 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_sqdmlal2_nv4si_internal (operands[0], operands[1],
						    operands[2], operands[3],
						    p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4200 */
rtx
gen_aarch64_sqdmlsl2_nv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_sqdmlsl2_nv8hi_internal (operands[0], operands[1],
						    operands[2], operands[3],
						    p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4200 */
rtx
gen_aarch64_sqdmlsl2_nv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_sqdmlsl2_nv4si_internal (operands[0], operands[1],
						    operands[2], operands[3],
						    p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4355 */
rtx
gen_aarch64_sqdmull2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_sqdmull2v8hi_internal (operands[0], operands[1],
						  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4355 */
rtx
gen_aarch64_sqdmull2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4360 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_sqdmull2v4si_internal (operands[0], operands[1],
						  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4415 */
rtx
gen_aarch64_sqdmull2_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4421 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_sqdmull2_lanev8hi_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4415 */
rtx
gen_aarch64_sqdmull2_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4421 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_sqdmull2_lanev4si_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4429 */
rtx
gen_aarch64_sqdmull2_laneqv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4435 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_sqdmull2_laneqv8hi_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4429 */
rtx
gen_aarch64_sqdmull2_laneqv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4435 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_sqdmull2_laneqv4si_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4463 */
rtx
gen_aarch64_sqdmull2_nv8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4468 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, 8, true);
  emit_insn (gen_aarch64_sqdmull2_nv8hi_internal (operands[0], operands[1],
						    operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4463 */
rtx
gen_aarch64_sqdmull2_nv4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4468 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, 4, true);
  emit_insn (gen_aarch64_sqdmull2_nv4si_internal (operands[0], operands[1],
						    operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4624 */
extern rtx_insn *gen_split_79 (rtx_insn *, rtx *);
rtx_insn *
gen_split_79 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_79\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4641 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = SELECT_CC_MODE (LT, operands[1], operands[2]);
	rtx cc_reg = aarch64_gen_compare_reg (LT, operands[1], operands[2]);
	rtx comparison = gen_rtx_LT (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LT (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4624 */
extern rtx_insn *gen_split_80 (rtx_insn *, rtx *);
rtx_insn *
gen_split_80 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_80\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4641 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = SELECT_CC_MODE (LE, operands[1], operands[2]);
	rtx cc_reg = aarch64_gen_compare_reg (LE, operands[1], operands[2]);
	rtx comparison = gen_rtx_LE (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LE (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4624 */
extern rtx_insn *gen_split_81 (rtx_insn *, rtx *);
rtx_insn *
gen_split_81 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_81\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4641 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = SELECT_CC_MODE (EQ, operands[1], operands[2]);
	rtx cc_reg = aarch64_gen_compare_reg (EQ, operands[1], operands[2]);
	rtx comparison = gen_rtx_EQ (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_EQ (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4624 */
extern rtx_insn *gen_split_82 (rtx_insn *, rtx *);
rtx_insn *
gen_split_82 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_82\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4641 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = SELECT_CC_MODE (GE, operands[1], operands[2]);
	rtx cc_reg = aarch64_gen_compare_reg (GE, operands[1], operands[2]);
	rtx comparison = gen_rtx_GE (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GE (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4624 */
extern rtx_insn *gen_split_83 (rtx_insn *, rtx *);
rtx_insn *
gen_split_83 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_83\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4641 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = SELECT_CC_MODE (GT, operands[1], operands[2]);
	rtx cc_reg = aarch64_gen_compare_reg (GT, operands[1], operands[2]);
	rtx comparison = gen_rtx_GT (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GT (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4687 */
extern rtx_insn *gen_split_84 (rtx_insn *, rtx *);
rtx_insn *
gen_split_84 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_84\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4704 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = CCmode;
	rtx cc_reg = aarch64_gen_compare_reg (LTU, operands[1], operands[2]);
	rtx comparison = gen_rtx_LTU (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LTU (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4687 */
extern rtx_insn *gen_split_85 (rtx_insn *, rtx *);
rtx_insn *
gen_split_85 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_85\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4704 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = CCmode;
	rtx cc_reg = aarch64_gen_compare_reg (LEU, operands[1], operands[2]);
	rtx comparison = gen_rtx_LEU (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LEU (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4687 */
extern rtx_insn *gen_split_86 (rtx_insn *, rtx *);
rtx_insn *
gen_split_86 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_86\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4704 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = CCmode;
	rtx cc_reg = aarch64_gen_compare_reg (GEU, operands[1], operands[2]);
	rtx comparison = gen_rtx_GEU (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GEU (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4687 */
extern rtx_insn *gen_split_87 (rtx_insn *, rtx *);
rtx_insn *
gen_split_87 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_87\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4704 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = CCmode;
	rtx cc_reg = aarch64_gen_compare_reg (GTU, operands[1], operands[2]);
	rtx comparison = gen_rtx_GTU (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GTU (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4757 */
extern rtx_insn *gen_split_88 (rtx_insn *, rtx *);
rtx_insn *
gen_split_88 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_88\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4776 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]);
	machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx);
	rtx cc_reg = aarch64_gen_compare_reg (NE, and_tree, const0_rtx);
	rtx comparison = gen_rtx_NE (mode, and_tree, const0_rtx);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_NE (DImode,
	gen_rtx_AND (DImode,
	operand1,
	operand2),
	const0_rtx))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4867 */
rtx
gen_sqrtv4hf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtv4hf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (V4HFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4867 */
rtx
gen_sqrtv8hf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtv8hf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (V8HFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4867 */
rtx
gen_sqrtv2sf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtv2sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (V2SFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4867 */
rtx
gen_sqrtv4sf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtv4sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (V4SFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4867 */
rtx
gen_sqrtv2df2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtv2df2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (V2DFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4921 */
rtx
gen_vec_load_lanesoiv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4927 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V16QImode, 16);
      emit_insn (gen_aarch64_simd_ld2v16qi (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4921 */
rtx
gen_vec_load_lanesoiv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4927 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V8HImode, 8);
      emit_insn (gen_aarch64_simd_ld2v8hi (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4921 */
rtx
gen_vec_load_lanesoiv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4927 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V4SImode, 4);
      emit_insn (gen_aarch64_simd_ld2v4si (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4921 */
rtx
gen_vec_load_lanesoiv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4927 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V2DImode, 2);
      emit_insn (gen_aarch64_simd_ld2v2di (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4921 */
rtx
gen_vec_load_lanesoiv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4927 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V8HFmode, 8);
      emit_insn (gen_aarch64_simd_ld2v8hf (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4921 */
rtx
gen_vec_load_lanesoiv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4927 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V4SFmode, 4);
      emit_insn (gen_aarch64_simd_ld2v4sf (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4921 */
rtx
gen_vec_load_lanesoiv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4927 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V2DFmode, 2);
      emit_insn (gen_aarch64_simd_ld2v2df (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4965 */
rtx
gen_vec_store_lanesoiv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4971 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V16QImode, 16);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v16qi (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4965 */
rtx
gen_vec_store_lanesoiv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4971 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V8HImode, 8);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v8hi (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4965 */
rtx
gen_vec_store_lanesoiv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4971 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V4SImode, 4);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v4si (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4965 */
rtx
gen_vec_store_lanesoiv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4971 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V2DImode, 2);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v2di (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4965 */
rtx
gen_vec_store_lanesoiv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4971 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V8HFmode, 8);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v8hf (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4965 */
rtx
gen_vec_store_lanesoiv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4971 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V4SFmode, 4);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v4sf (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:4965 */
rtx
gen_vec_store_lanesoiv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4971 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V2DFmode, 2);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v2df (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	58)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5019 */
rtx
gen_vec_load_lanesciv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5025 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V16QImode, 16);
      emit_insn (gen_aarch64_simd_ld3v16qi (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5019 */
rtx
gen_vec_load_lanesciv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5025 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V8HImode, 8);
      emit_insn (gen_aarch64_simd_ld3v8hi (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5019 */
rtx
gen_vec_load_lanesciv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5025 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V4SImode, 4);
      emit_insn (gen_aarch64_simd_ld3v4si (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5019 */
rtx
gen_vec_load_lanesciv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5025 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V2DImode, 2);
      emit_insn (gen_aarch64_simd_ld3v2di (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5019 */
rtx
gen_vec_load_lanesciv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5025 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V8HFmode, 8);
      emit_insn (gen_aarch64_simd_ld3v8hf (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5019 */
rtx
gen_vec_load_lanesciv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5025 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V4SFmode, 4);
      emit_insn (gen_aarch64_simd_ld3v4sf (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5019 */
rtx
gen_vec_load_lanesciv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5025 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V2DFmode, 2);
      emit_insn (gen_aarch64_simd_ld3v2df (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	33)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5063 */
rtx
gen_vec_store_lanesciv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5069 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V16QImode, 16);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v16qi (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5063 */
rtx
gen_vec_store_lanesciv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5069 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V8HImode, 8);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v8hi (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5063 */
rtx
gen_vec_store_lanesciv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5069 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V4SImode, 4);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v4si (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5063 */
rtx
gen_vec_store_lanesciv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5069 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V2DImode, 2);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v2di (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5063 */
rtx
gen_vec_store_lanesciv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5069 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V8HFmode, 8);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v8hf (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5063 */
rtx
gen_vec_store_lanesciv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5069 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V4SFmode, 4);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v4sf (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5063 */
rtx
gen_vec_store_lanesciv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5069 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V2DFmode, 2);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v2df (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	59)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5117 */
rtx
gen_vec_load_lanesxiv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V16QImode, 16);
      emit_insn (gen_aarch64_simd_ld4v16qi (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5117 */
rtx
gen_vec_load_lanesxiv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V8HImode, 8);
      emit_insn (gen_aarch64_simd_ld4v8hi (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5117 */
rtx
gen_vec_load_lanesxiv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V4SImode, 4);
      emit_insn (gen_aarch64_simd_ld4v4si (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5117 */
rtx
gen_vec_load_lanesxiv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V2DImode, 2);
      emit_insn (gen_aarch64_simd_ld4v2di (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5117 */
rtx
gen_vec_load_lanesxiv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V8HFmode, 8);
      emit_insn (gen_aarch64_simd_ld4v8hf (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5117 */
rtx
gen_vec_load_lanesxiv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V4SFmode, 4);
      emit_insn (gen_aarch64_simd_ld4v4sf (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5117 */
rtx
gen_vec_load_lanesxiv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V2DFmode, 2);
      emit_insn (gen_aarch64_simd_ld4v2df (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	36)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5161 */
rtx
gen_vec_store_lanesxiv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5167 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V16QImode, 16);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v16qi (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5161 */
rtx
gen_vec_store_lanesxiv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5167 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V8HImode, 8);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v8hi (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5161 */
rtx
gen_vec_store_lanesxiv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5167 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V4SImode, 4);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v4si (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5161 */
rtx
gen_vec_store_lanesxiv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5167 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V2DImode, 2);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v2di (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5161 */
rtx
gen_vec_store_lanesxiv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5167 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V8HFmode, 8);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v8hf (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5161 */
rtx
gen_vec_store_lanesxiv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5167 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V4SFmode, 4);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v4sf (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5161 */
rtx
gen_vec_store_lanesxiv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5167 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V2DFmode, 2);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v2df (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75)),
	60)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5180 */
extern rtx_insn *gen_split_89 (rtx_insn *, rtx *);
rtx_insn *
gen_split_89 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_89\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5190 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int i;
  int nregs = GET_MODE_SIZE (OImode) / UNITS_PER_VREG;
  for (i = 0; i < nregs; i++)
    {
      rtx op0 = gen_rtx_REG (V16QImode, REGNO (operands[0]) + i);
      rtx op1 = gen_rtx_REG (V16QImode, REGNO (operands[1]) + i);
      emit_insn (gen_aarch64_tbl1v16qi (op0, op1, operands[2]));
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5180 */
extern rtx_insn *gen_split_90 (rtx_insn *, rtx *);
rtx_insn *
gen_split_90 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_90\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5190 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int i;
  int nregs = GET_MODE_SIZE (CImode) / UNITS_PER_VREG;
  for (i = 0; i < nregs; i++)
    {
      rtx op0 = gen_rtx_REG (V16QImode, REGNO (operands[0]) + i);
      rtx op1 = gen_rtx_REG (V16QImode, REGNO (operands[1]) + i);
      emit_insn (gen_aarch64_tbl1v16qi (op0, op1, operands[2]));
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5180 */
extern rtx_insn *gen_split_91 (rtx_insn *, rtx *);
rtx_insn *
gen_split_91 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_91\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5190 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int i;
  int nregs = GET_MODE_SIZE (XImode) / UNITS_PER_VREG;
  for (i = 0; i < nregs; i++)
    {
      rtx op0 = gen_rtx_REG (V16QImode, REGNO (operands[0]) + i);
      rtx op1 = gen_rtx_REG (V16QImode, REGNO (operands[1]) + i);
      emit_insn (gen_aarch64_tbl1v16qi (op0, op1, operands[2]));
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5207 */
rtx
gen_movoi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5211 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (can_create_pseudo_p ())
    {
      if (GET_CODE (operands[0]) != REG)
	operands[1] = force_reg (OImode, operands[1]);
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5207 */
rtx
gen_movci (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5211 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (can_create_pseudo_p ())
    {
      if (GET_CODE (operands[0]) != REG)
	operands[1] = force_reg (CImode, operands[1]);
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5207 */
rtx
gen_movxi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5211 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (can_create_pseudo_p ())
    {
      if (GET_CODE (operands[0]) != REG)
	operands[1] = force_reg (XImode, operands[1]);
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_v8qi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_v16qi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_v4hi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_v8hi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_v2si (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_v4si (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_v2di (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_v4hf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_v8hf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_v2sf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_v4sf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_v2df (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_di (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5220 */
rtx
gen_aarch64_ld1x3df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5225 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[1]);
  emit_insn (gen_aarch64_ld1_x3_df (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_v8qi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_v16qi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_v4hi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_v8hi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_v2si (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_v4si (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_v2di (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_v4hf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_v8hf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_v2sf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_v4sf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_v2df (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_di (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5241 */
rtx
gen_aarch64_st1x2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5246 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (OImode, operands[0]);
  emit_insn (gen_aarch64_st1_x2_df (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_v8qi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_v16qi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_v4hi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_v8hi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_v2si (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_v4si (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_v2di (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_v4hf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_v8hf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_v2sf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_v4sf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_v2df (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_di (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5262 */
rtx
gen_aarch64_st1x3df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5267 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (CImode, operands[0]);
  emit_insn (gen_aarch64_st1_x3_df (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5353 */
extern rtx_insn *gen_split_92 (rtx_insn *, rtx *);
rtx_insn *
gen_split_92 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_92\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5358 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, TImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5363 */
extern rtx_insn *gen_split_93 (rtx_insn *, rtx *);
rtx_insn *
gen_split_93 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_93\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5368 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (register_operand (operands[0], CImode)
      && register_operand (operands[1], CImode))
    {
      aarch64_simd_emit_reg_reg_move (operands, TImode, 3);
      DONE;
    }
  else if (BYTES_BIG_ENDIAN)
    {
      emit_move_insn (simplify_gen_subreg (OImode, operands[0], CImode, 0),
		      simplify_gen_subreg (OImode, operands[1], CImode, 0));
      emit_move_insn (gen_lowpart (V16QImode,
				   simplify_gen_subreg (TImode, operands[0],
							CImode, 32)),
		      gen_lowpart (V16QImode,
				   simplify_gen_subreg (TImode, operands[1],
							CImode, 32)));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5391 */
extern rtx_insn *gen_split_94 (rtx_insn *, rtx *);
rtx_insn *
gen_split_94 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_94\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5396 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  if (register_operand (operands[0], XImode)
      && register_operand (operands[1], XImode))
    {
      aarch64_simd_emit_reg_reg_move (operands, TImode, 4);
      DONE;
    }
  else if (BYTES_BIG_ENDIAN)
    {
      emit_move_insn (simplify_gen_subreg (OImode, operands[0], XImode, 0),
		      simplify_gen_subreg (OImode, operands[1], XImode, 0));
      emit_move_insn (simplify_gen_subreg (OImode, operands[0], XImode, 32),
		      simplify_gen_subreg (OImode, operands[1], XImode, 32));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rv8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv8qi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv16qi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rv4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv4hi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv8hi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rv2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv2si (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv4si (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv2di (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rv4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv4hf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv8hf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rv2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv2sf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv4sf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv2df (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rdi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rdi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld2rdf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rdf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rv8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv8qi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv16qi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rv4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv4hi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv8hi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rv2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv2si (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv4si (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv2di (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rv4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv4hf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv8hf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rv2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv2sf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv4sf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv2df (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rdi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rdi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld3rdf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rdf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rv8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv8qi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv16qi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rv4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv4hi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv8hi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rv2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv2si (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv4si (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv2di (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rv4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv4hf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv8hf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rv2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv2sf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv4sf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv2df (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rdi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rdi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5415 */
rtx
gen_aarch64_ld4rdf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5420 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rdf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld2v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_ld2v8qi_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld2v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_ld2v4hi_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld2v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_ld2v4hf_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld2v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_ld2v2si_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld2v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_ld2v2sf_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_ld2di_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_ld2df_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld3v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_ld3v8qi_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld3v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_ld3v4hi_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld3v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_ld3v4hf_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld3v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_ld3v2si_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld3v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_ld3v2sf_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld3di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_ld3di_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld3df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_ld3df_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld4v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_ld4v8qi_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld4v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_ld4v4hi_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld4v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_ld4v4hf_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld4v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_ld4v2si_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld4v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_ld4v2sf_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld4di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_ld4di_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5490 */
rtx
gen_aarch64_ld4df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5495 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_ld4df_dreg (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5503 */
rtx
gen_aarch64_ld1v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5507 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V8QImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v8qi (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5503 */
rtx
gen_aarch64_ld1v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5507 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V16QImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v16qi (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5503 */
rtx
gen_aarch64_ld1v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5507 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4HImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v4hi (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5503 */
rtx
gen_aarch64_ld1v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5507 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V8HImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v8hi (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5503 */
rtx
gen_aarch64_ld1v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5507 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2SImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v2si (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5503 */
rtx
gen_aarch64_ld1v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5507 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4SImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v4si (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5503 */
rtx
gen_aarch64_ld1v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5507 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2DImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v2di (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5503 */
rtx
gen_aarch64_ld1v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5507 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4HFmode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v4hf (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5503 */
rtx
gen_aarch64_ld1v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5507 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V8HFmode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v8hf (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5503 */
rtx
gen_aarch64_ld1v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5507 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2SFmode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v2sf (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5503 */
rtx
gen_aarch64_ld1v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5507 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4SFmode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v4sf (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5503 */
rtx
gen_aarch64_ld1v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5507 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2DFmode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v2df (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld2v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v16qi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld2v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v8hi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld2v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v4si (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld2v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v2di (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld2v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v8hf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld2v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v4sf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld2v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v2df (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld3v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v16qi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld3v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v8hi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld3v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v4si (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld3v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v2di (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld3v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v8hf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld3v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v4sf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld3v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v2df (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld4v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v16qi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld4v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v8hi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld4v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v4si (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld4v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v2di (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld4v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v8hf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld4v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v4sf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5518 */
rtx
gen_aarch64_ld4v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5523 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v2df (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5531 */
rtx
gen_aarch64_ld1x2v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5536 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1v16qi_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5531 */
rtx
gen_aarch64_ld1x2v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5536 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1v8hi_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5531 */
rtx
gen_aarch64_ld1x2v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5536 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1v4si_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5531 */
rtx
gen_aarch64_ld1x2v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5536 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1v2di_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5531 */
rtx
gen_aarch64_ld1x2v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5536 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1v8hf_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5531 */
rtx
gen_aarch64_ld1x2v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5536 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1v4sf_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5531 */
rtx
gen_aarch64_ld1x2v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5536 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1v2df_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5544 */
rtx
gen_aarch64_ld1x2v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1v8qi_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5544 */
rtx
gen_aarch64_ld1x2v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1v4hi_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5544 */
rtx
gen_aarch64_ld1x2v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1v4hf_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5544 */
rtx
gen_aarch64_ld1x2v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1v2si_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5544 */
rtx
gen_aarch64_ld1x2v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1v2sf_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5544 */
rtx
gen_aarch64_ld1x2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1di_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5544 */
rtx
gen_aarch64_ld1x2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld1df_x2 (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanev8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 8, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev8qi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanev16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 16, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev16qi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanev4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 4, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev4hi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 8, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev8hi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanev2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 2, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev2si (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 4, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev4si (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanev2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 2, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev2di (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanev4hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 4, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev4hf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanev8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 8, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev8hf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanev2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 2, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev2sf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanev4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 4, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev4sf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanev2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 2, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev2df (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanedi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 1, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanedi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld2_lanedf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0, 1, NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanedf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanev8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 8, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev8qi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanev16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 16, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev16qi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanev4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 4, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev4hi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 8, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev8hi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanev2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 2, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev2si (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 4, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev4si (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanev2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 2, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev2di (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanev4hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 4, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev4hf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanev8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 8, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev8hf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanev2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 2, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev2sf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanev4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 4, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev4sf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanev2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 2, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev2df (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanedi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 1, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanedi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld3_lanedf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0, 1, NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanedf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanev8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 8, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev8qi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanev16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 16, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev16qi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanev4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 4, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev4hi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 8, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev8hi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanev2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 2, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev2si (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 4, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev4si (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanev2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 2, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev2di (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanev4hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 4, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev4hf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanev8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 8, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev8hf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanev2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 2, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev2sf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanev4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 4, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev4sf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanev2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 2, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev2df (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanedi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 1, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanedi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5558 */
rtx
gen_aarch64_ld4_lanedf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0, 1, NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanedf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregoiv8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V16QImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V16QImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V8QImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregoiv4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V8HImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V8HImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V4HImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregoiv4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V8HFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V8HFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V4HFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregoiv2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V4SImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V4SImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V2SImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregoiv2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V4SFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V4SFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V2SFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregoidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V2DImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V2DImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (DImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregoidf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V2DFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V2DFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (DFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregciv8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V16QImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V16QImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V8QImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregciv4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V8HImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V8HImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V4HImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregciv4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V8HFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V8HFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V4HFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregciv2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V4SImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V4SImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V2SImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregciv2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V4SFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V4SFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V2SFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregcidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V2DImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V2DImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (DImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregcidf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V2DFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V2DFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (DFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregxiv8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V16QImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V16QImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V8QImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregxiv4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V8HImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V8HImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V4HImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregxiv4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V8HFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V8HFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V4HFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregxiv2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V4SImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V4SImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V2SImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregxiv2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V4SFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V4SFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V2SFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregxidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V2DImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V2DImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (DImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5581 */
rtx
gen_aarch64_get_dregxidf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5586 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V2DFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V2DFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (DFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregoiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V16QImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregoiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V8HImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregoiv4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V4SImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregoiv2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V2DImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregoiv8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V8HFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregoiv4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V4SFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregoiv2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V2DFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregciv16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V16QImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregciv8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V8HImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregciv4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V4SImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregciv2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V2DImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregciv8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V8HFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregciv4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V4SFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregciv2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V2DFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregxiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V16QImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregxiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V8HImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregxiv4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V4SImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregxiv2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V2DImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregxiv8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V8HFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregxiv4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V4SFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5598 */
rtx
gen_aarch64_get_qregxiv2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V2DFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_permv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5624 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vec_perm (operands[0], operands[1],
			   operands[2], operands[3], 8);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_permv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5624 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vec_perm (operands[0], operands[1],
			   operands[2], operands[3], 16);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5719 */
extern rtx_insn *gen_split_95 (rtx_insn *, rtx *);
rtx_insn *
gen_split_95 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_95\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5728 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_combinev16qi (operands);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st2v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2v8qi_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st2v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2v4hi_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st2v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2v4hf_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st2v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2v2si_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st2v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2v2sf_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2di_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2df_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st3v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3v8qi_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st3v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3v4hi_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st3v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3v4hf_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st3v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3v2si_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st3v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3v2sf_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st3di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3di_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st3df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3df_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st4v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4v8qi_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st4v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4v4hi_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st4v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4v4hf_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st4v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4v2si_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st4v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4v2sf_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st4di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4di_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5839 */
rtx
gen_aarch64_st4df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5844 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4df_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st2v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v16qi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st2v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v8hi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st2v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v4si (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st2v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v2di (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st2v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v8hf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st2v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v4sf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st2v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v2df (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st3v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v16qi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st3v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v8hi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st3v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v4si (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st3v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v2di (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st3v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v8hf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st3v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v4sf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st3v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v2df (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st4v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v16qi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st4v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v8hi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st4v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v4si (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st4v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v2di (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st4v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v8hf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st4v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v4sf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5852 */
rtx
gen_aarch64_st4v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5857 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v2df (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanev8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev8qi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanev16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev16qi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanev4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev4hi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev8hi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanev2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev2si (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev4si (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanev2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev2di (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanev4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev4hf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanev8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev8hf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanev2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev2sf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanev4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev4sf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanev2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev2df (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanedi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanedi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st2_lanedf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanedf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanev8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev8qi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanev16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev16qi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanev4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev4hi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev8hi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanev2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev2si (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev4si (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanev2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev2di (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanev4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev4hf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanev8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev8hf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanev2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev2sf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanev4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev4sf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanev2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev2df (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanedi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanedi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st3_lanedf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanedf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanev8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev8qi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanev16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev16qi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanev4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev4hi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev8hi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanev2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev2si (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev4si (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanev2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev2di (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanev4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev4hf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanev8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev8hf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanev2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev2sf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanev4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev4sf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanev2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev2df (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanedi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanedi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5865 */
rtx
gen_aarch64_st4_lanedf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5871 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanedf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	75));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5881 */
rtx
gen_aarch64_st1v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5885 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V8QImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v8qi (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5881 */
rtx
gen_aarch64_st1v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5885 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V16QImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v16qi (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5881 */
rtx
gen_aarch64_st1v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5885 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4HImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v4hi (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5881 */
rtx
gen_aarch64_st1v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5885 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V8HImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v8hi (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5881 */
rtx
gen_aarch64_st1v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5885 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2SImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v2si (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5881 */
rtx
gen_aarch64_st1v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5885 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4SImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v4si (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5881 */
rtx
gen_aarch64_st1v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5885 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2DImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v2di (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5881 */
rtx
gen_aarch64_st1v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5885 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4HFmode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v4hf (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5881 */
rtx
gen_aarch64_st1v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5885 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V8HFmode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v8hf (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5881 */
rtx
gen_aarch64_st1v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5885 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2SFmode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v2sf (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5881 */
rtx
gen_aarch64_st1v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5885 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4SFmode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v4sf (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5881 */
rtx
gen_aarch64_st1v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5885 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2DFmode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v2df (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregoiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V16QImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregoiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V8HImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregoiv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V4SImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregoiv2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V2DImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregoiv8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V8HFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregoiv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V4SFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregoiv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V2DFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregciv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V16QImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregciv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V8HImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregciv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V4SImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregciv2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V2DImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregciv8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V8HFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregciv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V4SFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregciv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V2DFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregxiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V16QImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregxiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V8HImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregxiv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V4SImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregxiv2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V2DImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregxiv8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V8HFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregxiv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V4SFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5902 */
rtx
gen_aarch64_set_qregxiv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5908 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V2DFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5920 */
rtx
gen_vec_initv8qiqi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5924 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5920 */
rtx
gen_vec_initv16qiqi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5924 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5920 */
rtx
gen_vec_initv4hihi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5924 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5920 */
rtx
gen_vec_initv8hihi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5924 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5920 */
rtx
gen_vec_initv2sisi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5924 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5920 */
rtx
gen_vec_initv4sisi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5924 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5920 */
rtx
gen_vec_initv2didi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5924 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5920 */
rtx
gen_vec_initv4hfhf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5924 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5920 */
rtx
gen_vec_initv8hfhf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5924 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5920 */
rtx
gen_vec_initv2sfsf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5924 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5920 */
rtx
gen_vec_initv4sfsf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5924 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5920 */
rtx
gen_vec_initv2dfdf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5924 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5999 */
rtx
gen_vec_extractv8qiqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev8qi (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5999 */
rtx
gen_vec_extractv16qiqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev16qi (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5999 */
rtx
gen_vec_extractv4hihi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev4hi (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5999 */
rtx
gen_vec_extractv8hihi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev8hi (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5999 */
rtx
gen_vec_extractv2sisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev2si (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5999 */
rtx
gen_vec_extractv4sisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev4si (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5999 */
rtx
gen_vec_extractv2didi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev2di (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5999 */
rtx
gen_vec_extractv4hfhf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev4hf (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5999 */
rtx
gen_vec_extractv8hfhf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev8hf (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5999 */
rtx
gen_vec_extractv2sfsf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev2sf (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5999 */
rtx
gen_vec_extractv4sfsf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev4sf (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:5999 */
rtx
gen_vec_extractv2dfdf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6004 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev2df (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6347 */
rtx
gen_aarch64_fmlal_lowv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6355 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode,
					    2 * 2, false);
  rtx p2 = aarch64_simd_vect_par_cnst_half (V4HFmode,
					    2 * 2, false);

  emit_insn (gen_aarch64_simd_fmlal_lowv2sf (operands[0],
								operands[1],
								operands[2],
								operands[3],
								p1, p2));
  DONE;

}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	224)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6347 */
rtx
gen_aarch64_fmlsl_lowv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6355 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode,
					    2 * 2, false);
  rtx p2 = aarch64_simd_vect_par_cnst_half (V4HFmode,
					    2 * 2, false);

  emit_insn (gen_aarch64_simd_fmlsl_lowv2sf (operands[0],
								operands[1],
								operands[2],
								operands[3],
								p1, p2));
  DONE;

}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	225)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6347 */
rtx
gen_aarch64_fmlalq_lowv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6355 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode,
					    4 * 2, false);
  rtx p2 = aarch64_simd_vect_par_cnst_half (V8HFmode,
					    4 * 2, false);

  emit_insn (gen_aarch64_simd_fmlalq_lowv4sf (operands[0],
								operands[1],
								operands[2],
								operands[3],
								p1, p2));
  DONE;

}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	224)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6347 */
rtx
gen_aarch64_fmlslq_lowv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6355 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode,
					    4 * 2, false);
  rtx p2 = aarch64_simd_vect_par_cnst_half (V8HFmode,
					    4 * 2, false);

  emit_insn (gen_aarch64_simd_fmlslq_lowv4sf (operands[0],
								operands[1],
								operands[2],
								operands[3],
								p1, p2));
  DONE;

}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	225)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6370 */
rtx
gen_aarch64_fmlal_highv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6378 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 2 * 2, true);
  rtx p2 = aarch64_simd_vect_par_cnst_half (V4HFmode, 2 * 2, true);

  emit_insn (gen_aarch64_simd_fmlal_highv2sf (operands[0],
								 operands[1],
								 operands[2],
								 operands[3],
								 p1, p2));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	226)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6370 */
rtx
gen_aarch64_fmlsl_highv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6378 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 2 * 2, true);
  rtx p2 = aarch64_simd_vect_par_cnst_half (V4HFmode, 2 * 2, true);

  emit_insn (gen_aarch64_simd_fmlsl_highv2sf (operands[0],
								 operands[1],
								 operands[2],
								 operands[3],
								 p1, p2));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	227)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6370 */
rtx
gen_aarch64_fmlalq_highv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6378 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 4 * 2, true);
  rtx p2 = aarch64_simd_vect_par_cnst_half (V8HFmode, 4 * 2, true);

  emit_insn (gen_aarch64_simd_fmlalq_highv4sf (operands[0],
								 operands[1],
								 operands[2],
								 operands[3],
								 p1, p2));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	226)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6370 */
rtx
gen_aarch64_fmlslq_highv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6378 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 4 * 2, true);
  rtx p2 = aarch64_simd_vect_par_cnst_half (V8HFmode, 4 * 2, true);

  emit_insn (gen_aarch64_simd_fmlslq_highv4sf (operands[0],
								 operands[1],
								 operands[2],
								 operands[3],
								 p1, p2));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	227)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6460 */
rtx
gen_aarch64_fmlal_lane_lowv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6468 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 4, false);
    rtx lane = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlal_lane_lowv2sf (operands[0],
							    operands[1],
							    operands[2],
							    operands[3],
							    p1, lane));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	224)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6460 */
rtx
gen_aarch64_fmlsl_lane_lowv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6468 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 4, false);
    rtx lane = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlsl_lane_lowv2sf (operands[0],
							    operands[1],
							    operands[2],
							    operands[3],
							    p1, lane));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	225)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6481 */
rtx
gen_aarch64_fmlal_lane_highv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6489 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 4, true);
    rtx lane = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlal_lane_highv2sf (operands[0],
							     operands[1],
							     operands[2],
							     operands[3],
							     p1, lane));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	226)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6481 */
rtx
gen_aarch64_fmlsl_lane_highv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6489 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 4, true);
    rtx lane = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlsl_lane_highv2sf (operands[0],
							     operands[1],
							     operands[2],
							     operands[3],
							     p1, lane));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	227)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6575 */
rtx
gen_aarch64_fmlalq_laneq_lowv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6583 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, false);
    rtx lane = aarch64_endian_lane_rtx (V8HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlalq_laneq_lowv4sf (operands[0],
							      operands[1],
							      operands[2],
							      operands[3],
							      p1, lane));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	224)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6575 */
rtx
gen_aarch64_fmlslq_laneq_lowv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6583 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, false);
    rtx lane = aarch64_endian_lane_rtx (V8HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlslq_laneq_lowv4sf (operands[0],
							      operands[1],
							      operands[2],
							      operands[3],
							      p1, lane));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	225)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6595 */
rtx
gen_aarch64_fmlalq_laneq_highv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, true);
    rtx lane = aarch64_endian_lane_rtx (V8HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlalq_laneq_highv4sf (operands[0],
							       operands[1],
							       operands[2],
							       operands[3],
							       p1, lane));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	226)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6595 */
rtx
gen_aarch64_fmlslq_laneq_highv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6603 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, true);
    rtx lane = aarch64_endian_lane_rtx (V8HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlslq_laneq_highv4sf (operands[0],
							       operands[1],
							       operands[2],
							       operands[3],
							       p1, lane));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	227)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6689 */
rtx
gen_aarch64_fmlal_laneq_lowv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6697 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 4, false);
    rtx lane = aarch64_endian_lane_rtx (V8HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlal_laneq_lowv2sf (operands[0],
							     operands[1],
							     operands[2],
							     operands[3],
							     p1, lane));
    DONE;

}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	224)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6689 */
rtx
gen_aarch64_fmlsl_laneq_lowv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6697 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 4, false);
    rtx lane = aarch64_endian_lane_rtx (V8HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlsl_laneq_lowv2sf (operands[0],
							     operands[1],
							     operands[2],
							     operands[3],
							     p1, lane));
    DONE;

}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	225)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6710 */
rtx
gen_aarch64_fmlal_laneq_highv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6718 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 4, true);
    rtx lane = aarch64_endian_lane_rtx (V8HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlal_laneq_highv2sf (operands[0],
							      operands[1],
							      operands[2],
							      operands[3],
							      p1, lane));
    DONE;

}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	226)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6710 */
rtx
gen_aarch64_fmlsl_laneq_highv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6718 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V4HFmode, 4, true);
    rtx lane = aarch64_endian_lane_rtx (V8HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlsl_laneq_highv2sf (operands[0],
							      operands[1],
							      operands[2],
							      operands[3],
							      p1, lane));
    DONE;

}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	227)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6805 */
rtx
gen_aarch64_fmlalq_lane_lowv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6813 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, false);
    rtx lane = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlalq_lane_lowv4sf (operands[0],
							     operands[1],
							     operands[2],
							     operands[3],
							     p1, lane));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	224)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6805 */
rtx
gen_aarch64_fmlslq_lane_lowv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6813 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, false);
    rtx lane = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlslq_lane_lowv4sf (operands[0],
							     operands[1],
							     operands[2],
							     operands[3],
							     p1, lane));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	225)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6825 */
rtx
gen_aarch64_fmlalq_lane_highv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6833 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, true);
    rtx lane = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlalq_lane_highv4sf (operands[0],
							      operands[1],
							      operands[2],
							      operands[3],
							      p1, lane));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	226)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md:6825 */
rtx
gen_aarch64_fmlslq_lane_highv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 6833 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p1 = aarch64_simd_vect_par_cnst_half (V8HFmode, 8, true);
    rtx lane = aarch64_endian_lane_rtx (V4HFmode, INTVAL (operands[4]));

    emit_insn (gen_aarch64_simd_fmlslq_lane_highv4sf (operands[0],
							      operands[1],
							      operands[2],
							      operands[3],
							      p1, lane));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		operand4),
	227)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:23 */
rtx
gen_atomic_compare_and_swapqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 33 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_expand_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit (operand6, true);
  emit (operand7, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:23 */
rtx
gen_atomic_compare_and_swaphi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 33 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_expand_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit (operand6, true);
  emit (operand7, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:23 */
rtx
gen_atomic_compare_and_swapsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 33 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_expand_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit (operand6, true);
  emit (operand7, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:23 */
rtx
gen_atomic_compare_and_swapdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 33 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_expand_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit (operand6, true);
  emit (operand7, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:42 */
extern rtx_insn *gen_split_96 (rtx_insn *, rtx *);
rtx_insn *
gen_split_96 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_96\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 61 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:42 */
extern rtx_insn *gen_split_97 (rtx_insn *, rtx *);
rtx_insn *
gen_split_97 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_97\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 61 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:67 */
extern rtx_insn *gen_split_98 (rtx_insn *, rtx *);
rtx_insn *
gen_split_98 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_98\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 85 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:67 */
extern rtx_insn *gen_split_99 (rtx_insn *, rtx *);
rtx_insn *
gen_split_99 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_99\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 85 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:136 */
rtx
gen_atomic_exchangeqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 142 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx, rtx);

    /* Use an atomic SWP when available.  */
    if (TARGET_LSE)
      gen = gen_aarch64_atomic_exchangeqi_lse;
    else
      gen = gen_aarch64_atomic_exchangeqi;

    emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:136 */
rtx
gen_atomic_exchangehi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 142 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx, rtx);

    /* Use an atomic SWP when available.  */
    if (TARGET_LSE)
      gen = gen_aarch64_atomic_exchangehi_lse;
    else
      gen = gen_aarch64_atomic_exchangehi;

    emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:136 */
rtx
gen_atomic_exchangesi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 142 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx, rtx);

    /* Use an atomic SWP when available.  */
    if (TARGET_LSE)
      gen = gen_aarch64_atomic_exchangesi_lse;
    else
      gen = gen_aarch64_atomic_exchangesi;

    emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:136 */
rtx
gen_atomic_exchangedi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 142 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx, rtx);

    /* Use an atomic SWP when available.  */
    if (TARGET_LSE)
      gen = gen_aarch64_atomic_exchangedi_lse;
    else
      gen = gen_aarch64_atomic_exchangedi;

    emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:157 */
extern rtx_insn *gen_split_100 (rtx_insn *, rtx *);
rtx_insn *
gen_split_100 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_100\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 171 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (SET, operands[0], NULL, operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:157 */
extern rtx_insn *gen_split_101 (rtx_insn *, rtx *);
rtx_insn *
gen_split_101 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_101\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 171 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (SET, operands[0], NULL, operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:157 */
extern rtx_insn *gen_split_102 (rtx_insn *, rtx *);
rtx_insn *
gen_split_102 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_102\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 171 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (SET, operands[0], NULL, operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:157 */
extern rtx_insn *gen_split_103 (rtx_insn *, rtx *);
rtx_insn *
gen_split_103 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_103\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 171 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (SET, operands[0], NULL, operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_addqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (PLUS)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (QImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addqi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorqi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorqi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (QImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicqi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (QImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_addqi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (QImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_subqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (MINUS)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (QImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addqi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorqi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorqi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (QImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicqi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (QImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_subqi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (QImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_orqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (IOR)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (QImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addqi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorqi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorqi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (QImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicqi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (QImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_orqi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (QImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_xorqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (XOR)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (QImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addqi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorqi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorqi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (QImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicqi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (QImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_xorqi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (QImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_andqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (AND)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (QImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addqi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorqi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorqi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (QImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicqi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (QImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_andqi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (QImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_addhi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (PLUS)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (HImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addhi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorhi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorhi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (HImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bichi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (HImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_addhi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (HImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_subhi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (MINUS)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (HImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addhi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorhi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorhi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (HImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bichi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (HImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_subhi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (HImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_orhi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (IOR)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (HImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addhi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorhi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorhi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (HImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bichi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (HImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_orhi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (HImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_xorhi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (XOR)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (HImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addhi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorhi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorhi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (HImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bichi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (HImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_xorhi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (HImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_andhi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (AND)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (HImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addhi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorhi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorhi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (HImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bichi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (HImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_andhi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (HImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_addsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (PLUS)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (SImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addsi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorsi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorsi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (SImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicsi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (SImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_addsi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (SImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_subsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (MINUS)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (SImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addsi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorsi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorsi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (SImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicsi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (SImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_subsi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (SImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_orsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (IOR)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (SImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addsi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorsi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorsi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (SImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicsi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (SImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_orsi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (SImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_xorsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (XOR)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (SImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addsi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorsi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorsi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (SImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicsi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (SImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_xorsi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (SImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_andsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (AND)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (SImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_addsi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iorsi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xorsi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (SImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicsi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (SImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_andsi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (SImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_adddi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (PLUS)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (DImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_adddi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iordi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xordi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (DImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicdi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (DImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_adddi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (DImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_subdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (MINUS)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (DImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_adddi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iordi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xordi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (DImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicdi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (DImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_subdi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (DImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_ordi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (IOR)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (DImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_adddi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iordi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xordi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (DImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicdi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (DImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_ordi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (DImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_xordi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (XOR)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (DImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_adddi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iordi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xordi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (DImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicdi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (DImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_xordi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (DImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_anddi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (TARGET_LSE)
      {
	switch (AND)
	  {
	  case MINUS:
	    operands[1] = expand_simple_unop (DImode, NEG, operands[1],
					      NULL, 1);
	    /* fallthru */
	  case PLUS:
	    gen = gen_aarch64_atomic_adddi_lse;
	    break;
	  case IOR:
	    gen = gen_aarch64_atomic_iordi_lse;
	    break;
	  case XOR:
	    gen = gen_aarch64_atomic_xordi_lse;
	    break;
	  case AND:
	    operands[1] = expand_simple_unop (DImode, NOT, operands[1],
					      NULL, 1);
	    gen = gen_aarch64_atomic_bicdi_lse;
	    break;
	  default:
	    gcc_unreachable ();
	  }
	operands[1] = force_reg (DImode, operands[1]);
      }
    else
      gen = gen_aarch64_atomic_anddi;

    emit_insn (gen (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (DImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_104 (rtx_insn *, rtx *);
rtx_insn *
gen_split_104 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_104\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_105 (rtx_insn *, rtx *);
rtx_insn *
gen_split_105 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_105\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_106 (rtx_insn *, rtx *);
rtx_insn *
gen_split_106 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_106\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_107 (rtx_insn *, rtx *);
rtx_insn *
gen_split_107 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_107\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_108 (rtx_insn *, rtx *);
rtx_insn *
gen_split_108 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_108\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_109 (rtx_insn *, rtx *);
rtx_insn *
gen_split_109 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_109\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_110 (rtx_insn *, rtx *);
rtx_insn *
gen_split_110 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_110\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_111 (rtx_insn *, rtx *);
rtx_insn *
gen_split_111 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_111\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_112 (rtx_insn *, rtx *);
rtx_insn *
gen_split_112 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_112\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_113 (rtx_insn *, rtx *);
rtx_insn *
gen_split_113 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_113\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_114 (rtx_insn *, rtx *);
rtx_insn *
gen_split_114 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_114\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_115 (rtx_insn *, rtx *);
rtx_insn *
gen_split_115 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_115\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_116 (rtx_insn *, rtx *);
rtx_insn *
gen_split_116 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_116\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_117 (rtx_insn *, rtx *);
rtx_insn *
gen_split_117 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_117\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_118 (rtx_insn *, rtx *);
rtx_insn *
gen_split_118 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_118\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_119 (rtx_insn *, rtx *);
rtx_insn *
gen_split_119 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_119\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_120 (rtx_insn *, rtx *);
rtx_insn *
gen_split_120 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_120\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_121 (rtx_insn *, rtx *);
rtx_insn *
gen_split_121 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_121\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_122 (rtx_insn *, rtx *);
rtx_insn *
gen_split_122 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_122\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:245 */
extern rtx_insn *gen_split_123 (rtx_insn *, rtx *);
rtx_insn *
gen_split_123 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_123\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 259 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:300 */
extern rtx_insn *gen_split_124 (rtx_insn *, rtx *);
rtx_insn *
gen_split_124 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_124\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 315 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
     aarch64_split_atomic_op (NOT, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
     DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:300 */
extern rtx_insn *gen_split_125 (rtx_insn *, rtx *);
rtx_insn *
gen_split_125 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_125\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 315 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
     aarch64_split_atomic_op (NOT, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
     DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:300 */
extern rtx_insn *gen_split_126 (rtx_insn *, rtx *);
rtx_insn *
gen_split_126 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_126\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 315 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
     aarch64_split_atomic_op (NOT, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
     DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:300 */
extern rtx_insn *gen_split_127 (rtx_insn *, rtx *);
rtx_insn *
gen_split_127 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_127\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 315 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
     aarch64_split_atomic_op (NOT, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
     DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_addqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (PLUS)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (QImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addqi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorqi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorqi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (QImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicqi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (QImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_addqi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_PLUS (QImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_subqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (MINUS)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (QImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addqi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorqi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorqi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (QImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicqi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (QImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_subqi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_MINUS (QImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_orqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (IOR)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (QImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addqi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorqi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorqi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (QImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicqi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (QImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_orqi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_IOR (QImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_xorqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (XOR)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (QImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addqi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorqi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorqi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (QImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicqi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (QImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_xorqi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_XOR (QImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_andqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (AND)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (QImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addqi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorqi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorqi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (QImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicqi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (QImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_andqi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_AND (QImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_addhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (PLUS)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (HImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addhi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorhi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorhi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (HImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bichi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (HImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_addhi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_PLUS (HImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_subhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (MINUS)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (HImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addhi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorhi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorhi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (HImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bichi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (HImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_subhi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_MINUS (HImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_orhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (IOR)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (HImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addhi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorhi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorhi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (HImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bichi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (HImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_orhi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_IOR (HImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_xorhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (XOR)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (HImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addhi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorhi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorhi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (HImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bichi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (HImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_xorhi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_XOR (HImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_andhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (AND)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (HImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addhi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorhi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorhi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (HImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bichi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (HImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_andhi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_AND (HImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_addsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (PLUS)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (SImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addsi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorsi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorsi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (SImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicsi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (SImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_addsi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_PLUS (SImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_subsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (MINUS)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (SImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addsi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorsi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorsi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (SImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicsi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (SImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_subsi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_MINUS (SImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_orsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (IOR)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (SImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addsi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorsi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorsi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (SImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicsi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (SImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_orsi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_IOR (SImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_xorsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (XOR)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (SImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addsi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorsi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorsi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (SImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicsi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (SImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_xorsi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_XOR (SImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_andsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (AND)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (SImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_addsi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iorsi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xorsi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (SImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicsi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (SImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_andsi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_AND (SImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_adddi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (PLUS)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (DImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_adddi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iordi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xordi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (DImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicdi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (DImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_adddi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_PLUS (DImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_subdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (MINUS)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (DImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_adddi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iordi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xordi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (DImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicdi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (DImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_subdi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_MINUS (DImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_ordi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (IOR)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (DImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_adddi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iordi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xordi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (DImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicdi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (DImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_ordi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_IOR (DImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_xordi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (XOR)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (DImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_adddi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iordi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xordi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (DImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicdi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (DImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_xordi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_XOR (DImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:324 */
rtx
gen_atomic_fetch_anddi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (TARGET_LSE)
    {
      switch (AND)
        {
	case MINUS:
	  operands[2] = expand_simple_unop (DImode, NEG, operands[2],
					    NULL, 1);
	  /* fallthru */
	case PLUS:
	  gen = gen_aarch64_atomic_fetch_adddi_lse;
	  break;
	case IOR:
	  gen = gen_aarch64_atomic_fetch_iordi_lse;
	  break;
	case XOR:
	  gen = gen_aarch64_atomic_fetch_xordi_lse;
	  break;
	case AND:
	  operands[2] = expand_simple_unop (DImode, NOT, operands[2],
					    NULL, 1);
	  gen = gen_aarch64_atomic_fetch_bicdi_lse;
	  break;
	default:
	  gcc_unreachable ();
	}
      operands[2] = force_reg (DImode, operands[2]);
    }
  else
    gen = gen_aarch64_atomic_fetch_anddi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_AND (DImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_128 (rtx_insn *, rtx *);
rtx_insn *
gen_split_128 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_128\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_129 (rtx_insn *, rtx *);
rtx_insn *
gen_split_129 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_129\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_130 (rtx_insn *, rtx *);
rtx_insn *
gen_split_130 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_130\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_131 (rtx_insn *, rtx *);
rtx_insn *
gen_split_131 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_131\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_132 (rtx_insn *, rtx *);
rtx_insn *
gen_split_132 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_132\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_133 (rtx_insn *, rtx *);
rtx_insn *
gen_split_133 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_133\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_134 (rtx_insn *, rtx *);
rtx_insn *
gen_split_134 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_134\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_135 (rtx_insn *, rtx *);
rtx_insn *
gen_split_135 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_135\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_136 (rtx_insn *, rtx *);
rtx_insn *
gen_split_136 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_136\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_137 (rtx_insn *, rtx *);
rtx_insn *
gen_split_137 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_137\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_138 (rtx_insn *, rtx *);
rtx_insn *
gen_split_138 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_138\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_139 (rtx_insn *, rtx *);
rtx_insn *
gen_split_139 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_139\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_140 (rtx_insn *, rtx *);
rtx_insn *
gen_split_140 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_140\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_141 (rtx_insn *, rtx *);
rtx_insn *
gen_split_141 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_141\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_142 (rtx_insn *, rtx *);
rtx_insn *
gen_split_142 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_142\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_143 (rtx_insn *, rtx *);
rtx_insn *
gen_split_143 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_143\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_144 (rtx_insn *, rtx *);
rtx_insn *
gen_split_144 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_144\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_145 (rtx_insn *, rtx *);
rtx_insn *
gen_split_145 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_145\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_146 (rtx_insn *, rtx *);
rtx_insn *
gen_split_146 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_146\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:369 */
extern rtx_insn *gen_split_147 (rtx_insn *, rtx *);
rtx_insn *
gen_split_147 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_147\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 385 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:415 */
extern rtx_insn *gen_split_148 (rtx_insn *, rtx *);
rtx_insn *
gen_split_148 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_148\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 432 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, operands[0], operands[4], operands[1],
			    operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:415 */
extern rtx_insn *gen_split_149 (rtx_insn *, rtx *);
rtx_insn *
gen_split_149 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_149\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 432 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, operands[0], operands[4], operands[1],
			    operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:415 */
extern rtx_insn *gen_split_150 (rtx_insn *, rtx *);
rtx_insn *
gen_split_150 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_150\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 432 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, operands[0], operands[4], operands[1],
			    operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:415 */
extern rtx_insn *gen_split_151 (rtx_insn *, rtx *);
rtx_insn *
gen_split_151 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_151\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 432 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, operands[0], operands[4], operands[1],
			    operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_add_fetchqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (QImode);
      operands[2] = force_reg (QImode, operands[2]);
      emit_insn (gen_atomic_fetch_addqi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (QImode, PLUS, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_add_fetchqi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_sub_fetchqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (QImode);
      operands[2] = force_reg (QImode, operands[2]);
      emit_insn (gen_atomic_fetch_subqi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (QImode, MINUS, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_sub_fetchqi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_or_fetchqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (QImode);
      operands[2] = force_reg (QImode, operands[2]);
      emit_insn (gen_atomic_fetch_orqi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (QImode, IOR, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_or_fetchqi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_xor_fetchqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (QImode);
      operands[2] = force_reg (QImode, operands[2]);
      emit_insn (gen_atomic_fetch_xorqi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (QImode, XOR, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_xor_fetchqi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_and_fetchqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (QImode);
      operands[2] = force_reg (QImode, operands[2]);
      emit_insn (gen_atomic_fetch_andqi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (QImode, AND, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_and_fetchqi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_add_fetchhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (HImode);
      operands[2] = force_reg (HImode, operands[2]);
      emit_insn (gen_atomic_fetch_addhi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (HImode, PLUS, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_add_fetchhi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_sub_fetchhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (HImode);
      operands[2] = force_reg (HImode, operands[2]);
      emit_insn (gen_atomic_fetch_subhi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (HImode, MINUS, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_sub_fetchhi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_or_fetchhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (HImode);
      operands[2] = force_reg (HImode, operands[2]);
      emit_insn (gen_atomic_fetch_orhi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (HImode, IOR, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_or_fetchhi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_xor_fetchhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (HImode);
      operands[2] = force_reg (HImode, operands[2]);
      emit_insn (gen_atomic_fetch_xorhi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (HImode, XOR, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_xor_fetchhi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_and_fetchhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (HImode);
      operands[2] = force_reg (HImode, operands[2]);
      emit_insn (gen_atomic_fetch_andhi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (HImode, AND, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_and_fetchhi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_add_fetchsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (SImode);
      operands[2] = force_reg (SImode, operands[2]);
      emit_insn (gen_atomic_fetch_addsi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (SImode, PLUS, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_add_fetchsi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (SImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_sub_fetchsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (SImode);
      operands[2] = force_reg (SImode, operands[2]);
      emit_insn (gen_atomic_fetch_subsi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (SImode, MINUS, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_sub_fetchsi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (SImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_or_fetchsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (SImode);
      operands[2] = force_reg (SImode, operands[2]);
      emit_insn (gen_atomic_fetch_orsi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (SImode, IOR, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_or_fetchsi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (SImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_xor_fetchsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (SImode);
      operands[2] = force_reg (SImode, operands[2]);
      emit_insn (gen_atomic_fetch_xorsi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (SImode, XOR, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_xor_fetchsi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (SImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_and_fetchsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (SImode);
      operands[2] = force_reg (SImode, operands[2]);
      emit_insn (gen_atomic_fetch_andsi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (SImode, AND, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_and_fetchsi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (SImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_add_fetchdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (DImode);
      operands[2] = force_reg (DImode, operands[2]);
      emit_insn (gen_atomic_fetch_adddi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (DImode, PLUS, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_add_fetchdi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (DImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_sub_fetchdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (DImode);
      operands[2] = force_reg (DImode, operands[2]);
      emit_insn (gen_atomic_fetch_subdi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (DImode, MINUS, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_sub_fetchdi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (DImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_or_fetchdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (DImode);
      operands[2] = force_reg (DImode, operands[2]);
      emit_insn (gen_atomic_fetch_ordi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (DImode, IOR, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_or_fetchdi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (DImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_xor_fetchdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (DImode);
      operands[2] = force_reg (DImode, operands[2]);
      emit_insn (gen_atomic_fetch_xordi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (DImode, XOR, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_xor_fetchdi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (DImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:441 */
rtx
gen_atomic_and_fetchdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 448 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
  /* Use an atomic load-operate instruction when possible.  In this case
     we will re-compute the result from the original mem value. */
  if (TARGET_LSE)
    {
      rtx tmp = gen_reg_rtx (DImode);
      operands[2] = force_reg (DImode, operands[2]);
      emit_insn (gen_atomic_fetch_anddi
                 (tmp, operands[1], operands[2], operands[3]));
      tmp = expand_simple_binop (DImode, AND, tmp, operands[2],
				 operands[0], 1, OPTAB_WIDEN);
      emit_move_insn (operands[0], tmp);
    }
  else
    {
      emit_insn (gen_aarch64_atomic_and_fetchdi
                 (operands[0], operands[1], operands[2], operands[3]));
    }
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (DImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_152 (rtx_insn *, rtx *);
rtx_insn *
gen_split_152 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_152\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_153 (rtx_insn *, rtx *);
rtx_insn *
gen_split_153 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_153\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_154 (rtx_insn *, rtx *);
rtx_insn *
gen_split_154 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_154\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_155 (rtx_insn *, rtx *);
rtx_insn *
gen_split_155 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_155\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_156 (rtx_insn *, rtx *);
rtx_insn *
gen_split_156 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_156\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_157 (rtx_insn *, rtx *);
rtx_insn *
gen_split_157 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_157\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_158 (rtx_insn *, rtx *);
rtx_insn *
gen_split_158 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_158\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_159 (rtx_insn *, rtx *);
rtx_insn *
gen_split_159 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_159\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_160 (rtx_insn *, rtx *);
rtx_insn *
gen_split_160 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_160\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_161 (rtx_insn *, rtx *);
rtx_insn *
gen_split_161 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_161\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_162 (rtx_insn *, rtx *);
rtx_insn *
gen_split_162 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_162\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_163 (rtx_insn *, rtx *);
rtx_insn *
gen_split_163 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_163\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_164 (rtx_insn *, rtx *);
rtx_insn *
gen_split_164 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_164\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_165 (rtx_insn *, rtx *);
rtx_insn *
gen_split_165 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_165\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_166 (rtx_insn *, rtx *);
rtx_insn *
gen_split_166 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_166\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_167 (rtx_insn *, rtx *);
rtx_insn *
gen_split_167 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_167\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_168 (rtx_insn *, rtx *);
rtx_insn *
gen_split_168 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_168\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_169 (rtx_insn *, rtx *);
rtx_insn *
gen_split_169 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_169\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_170 (rtx_insn *, rtx *);
rtx_insn *
gen_split_170 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_170\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:469 */
extern rtx_insn *gen_split_171 (rtx_insn *, rtx *);
rtx_insn *
gen_split_171 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_171\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 485 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:492 */
extern rtx_insn *gen_split_172 (rtx_insn *, rtx *);
rtx_insn *
gen_split_172 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_172\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 509 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, NULL, operands[0], operands[1],
			    operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:492 */
extern rtx_insn *gen_split_173 (rtx_insn *, rtx *);
rtx_insn *
gen_split_173 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_173\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 509 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, NULL, operands[0], operands[1],
			    operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:492 */
extern rtx_insn *gen_split_174 (rtx_insn *, rtx *);
rtx_insn *
gen_split_174 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_174\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 509 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, NULL, operands[0], operands[1],
			    operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:492 */
extern rtx_insn *gen_split_175 (rtx_insn *, rtx *);
rtx_insn *
gen_split_175 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_175\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 509 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, NULL, operands[0], operands[1],
			    operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:602 */
rtx
gen_mem_thread_fence (rtx operand0)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[1];
    operands[0] = operand0;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 605 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    enum memmodel model = memmodel_from_int (INTVAL (operands[0]));
    if (!(is_mm_relaxed (model) || is_mm_consume (model)))
      emit_insn (gen_dmb (operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
  }
  emit (operand0, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md:613 */
rtx
gen_dmb (rtx operand0)
{
  rtx operand1;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 618 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/atomics.md"
{
    operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
    MEM_VOLATILE_P (operands[1]) = 1;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand1,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		copy_rtx (operand1),
		operand0),
	42)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:21 */
extern rtx_insn *gen_peephole2_12 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_12 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_12\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 29 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:21 */
extern rtx_insn *gen_peephole2_13 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_13 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_13\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 29 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:33 */
extern rtx_insn *gen_peephole2_14 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_14 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_14\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 41 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:33 */
extern rtx_insn *gen_peephole2_15 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_15 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_15\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 41 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:45 */
extern rtx_insn *gen_peephole2_16 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_16 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_16\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 53 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:45 */
extern rtx_insn *gen_peephole2_17 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_17 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_17\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 53 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:57 */
extern rtx_insn *gen_peephole2_18 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_18 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_18\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 65 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:57 */
extern rtx_insn *gen_peephole2_19 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_19 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_19\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 65 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_20 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_20 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_20\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_21 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_21 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_21\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_22 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_22 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_22\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_23 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_23 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_23\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_24 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_24 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_24\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_25 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_25 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_25\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_26 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_26 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_26\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_27 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_27 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_27\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_28 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_28 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_28\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_29 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_29 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_29\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_30 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_30 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_30\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_31 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_31 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_31\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_32 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_32 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_32\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_33 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_33 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_33\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_34 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_34 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_34\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_35 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_35 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_35\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_36 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_36 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_36\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_37 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_37 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_37\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_38 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_38 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_38\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_39 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_39 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_39\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_40 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_40 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_40\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_41 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_41 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_41\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_42 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_42 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_42\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_43 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_43 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_43\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_44 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_44 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_44\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_45 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_45 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_45\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_46 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_46 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_46\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_47 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_47 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_47\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_48 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_48 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_48\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_49 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_49 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_49\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_50 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_50 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_50\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_51 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_51 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_51\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_52 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_52 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_52\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_53 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_53 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_53\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_54 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_54 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_54\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:69 */
extern rtx_insn *gen_peephole2_55 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_55 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_55\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 77 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_56 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_56 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_56\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_57 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_57 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_57\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_58 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_58 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_58\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_59 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_59 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_59\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_60 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_60 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_60\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_61 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_61 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_61\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_62 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_62 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_62\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_63 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_63 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_63\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_64 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_64 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_64\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_65 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_65 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_65\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_66 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_66 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_66\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_67 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_67 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_67\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_68 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_68 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_68\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_69 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_69 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_69\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_70 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_70 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_70\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_71 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_71 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_71\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_72 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_72 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_72\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_73 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_73 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_73\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_74 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_74 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_74\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_75 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_75 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_75\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_76 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_76 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_76\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_77 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_77 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_77\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_78 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_78 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_78\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_79 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_79 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_79\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_80 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_80 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_80\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_81 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_81 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_81\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_82 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_82 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_82\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_83 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_83 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_83\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_84 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_84 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_84\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_85 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_85 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_85\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_86 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_86 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_86\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_87 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_87 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_87\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_88 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_88 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_88\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_89 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_89 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_89\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_90 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_90 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_90\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_91 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_91 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_91\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 90 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_92 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_92 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_92\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_93 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_93 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_93\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_94 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_94 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_94\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_95 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_95 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_95\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_96 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_96 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_96\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_97 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_97 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_97\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_98 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_98 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_98\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_99 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_99 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_99\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_100 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_100 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_100\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_101 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_101 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_101\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_102 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_102 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_102\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_103 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_103 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_103\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_104 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_104 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_104\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_105 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_105 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_105\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_106 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_106 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_106\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_107 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_107 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_107\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_108 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_108 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_108\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_109 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_109 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_109\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_110 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_110 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_110\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_111 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_111 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_111\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_112 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_112 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_112\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_113 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_113 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_113\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_114 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_114 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_114\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_115 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_115 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_115\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_116 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_116 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_116\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_117 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_117 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_117\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_118 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_118 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_118\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_119 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_119 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_119\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_120 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_120 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_120\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_121 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_121 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_121\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_122 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_122 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_122\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_123 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_123 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_123\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_124 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_124 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_124\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_125 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_125 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_125\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_126 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_126 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_126\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_127 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_127 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_127\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_128 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_128 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_128\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_129 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_129 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_129\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_130 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_130 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_130\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_131 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_131 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_131\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_132 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_132 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_132\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_133 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_133 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_133\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_134 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_134 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_134\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_135 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_135 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_135\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_136 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_136 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_136\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_137 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_137 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_137\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_138 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_138 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_138\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_139 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_139 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_139\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:94 */
extern rtx_insn *gen_peephole2_140 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_140 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_140\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 105 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_141 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_141 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_141\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_142 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_142 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_142\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_143 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_143 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_143\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_144 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_144 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_144\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_145 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_145 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_145\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_146 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_146 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_146\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_147 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_147 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_147\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_148 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_148 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_148\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_149 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_149 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_149\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_150 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_150 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_150\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_151 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_151 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_151\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_152 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_152 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_152\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_153 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_153 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_153\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_154 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_154 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_154\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_155 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_155 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_155\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_156 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_156 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_156\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_157 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_157 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_157\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_158 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_158 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_158\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_159 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_159 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_159\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_160 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_160 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_160\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_161 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_161 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_161\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_162 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_162 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_162\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_163 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_163 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_163\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_164 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_164 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_164\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_165 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_165 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_165\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_166 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_166 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_166\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_167 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_167 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_167\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_168 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_168 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_168\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_169 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_169 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_169\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_170 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_170 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_170\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_171 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_171 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_171\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_172 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_172 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_172\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_173 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_173 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_173\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_174 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_174 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_174\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_175 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_175 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_175\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_176 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_176 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_176\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_177 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_177 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_177\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_178 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_178 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_178\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_179 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_179 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_179\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_180 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_180 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_180\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_181 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_181 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_181\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_182 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_182 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_182\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_183 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_183 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_183\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_184 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_184 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_184\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_185 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_185 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_185\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_186 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_186 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_186\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_187 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_187 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_187\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_188 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_188 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_188\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:109 */
extern rtx_insn *gen_peephole2_189 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_189 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_189\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 120 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:127 */
extern rtx_insn *gen_peephole2_190 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_190 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_190\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 135 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1)),
		gen_rtx_SET (operand2,
	gen_rtx_SIGN_EXTEND (DImode,
	operand3)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:139 */
extern rtx_insn *gen_peephole2_191 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_191 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_191\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 147 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, true);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1)),
		gen_rtx_SET (operand2,
	gen_rtx_ZERO_EXTEND (DImode,
	operand3)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:161 */
extern rtx_insn *gen_peephole2_192 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_192 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_192\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 169 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:161 */
extern rtx_insn *gen_peephole2_193 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_193 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_193\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 169 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:161 */
extern rtx_insn *gen_peephole2_194 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_194 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_194\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 169 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:161 */
extern rtx_insn *gen_peephole2_195 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_195 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_195\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 169 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  aarch64_swap_ldrstr_operands (operands, false);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:178 */
extern rtx_insn *gen_peephole2_196 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_196 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_196\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 191 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  if (aarch64_gen_adjusted_ldpstp (operands, true, SImode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:178 */
extern rtx_insn *gen_peephole2_197 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_197 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_197\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 191 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  if (aarch64_gen_adjusted_ldpstp (operands, true, DImode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:198 */
extern rtx_insn *gen_peephole2_198 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_198 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_198\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 211 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  if (aarch64_gen_adjusted_ldpstp (operands, true, SFmode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:198 */
extern rtx_insn *gen_peephole2_199 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_199 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_199\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 211 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  if (aarch64_gen_adjusted_ldpstp (operands, true, DFmode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:218 */
extern rtx_insn *gen_peephole2_200 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_200 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_200\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 231 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  if (aarch64_gen_adjusted_ldpstp (operands, true, SImode, SIGN_EXTEND))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:238 */
extern rtx_insn *gen_peephole2_201 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_201 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_201\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 251 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  if (aarch64_gen_adjusted_ldpstp (operands, true, SImode, ZERO_EXTEND))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:258 */
extern rtx_insn *gen_peephole2_202 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_202 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_202\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 271 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  if (aarch64_gen_adjusted_ldpstp (operands, false, SImode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:258 */
extern rtx_insn *gen_peephole2_203 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_203 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_203\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 271 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  if (aarch64_gen_adjusted_ldpstp (operands, false, DImode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:278 */
extern rtx_insn *gen_peephole2_204 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_204 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_204\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 291 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  if (aarch64_gen_adjusted_ldpstp (operands, false, SFmode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md:278 */
extern rtx_insn *gen_peephole2_205 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_205 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_205\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 291 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-ldpstp.md"
{
  if (aarch64_gen_adjusted_ldpstp (operands, false, DFmode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:65 */
rtx
gen_movvnx16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 69 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use the predicated load and store patterns where possible.
       This is required for big-endian targets (see the comment at the
       head of the file) and increases the addressing choices for
       little-endian.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
        && can_create_pseudo_p ())
      {
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx16BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1],
				      gen_vec_duplicatevnx16qi);
	DONE;
      }

    /* Optimize subregs on big-endian targets: we can use REV[BHW]
       instead of going through memory.  */
    if (BYTES_BIG_ENDIAN
        && aarch64_maybe_expand_sve_subreg_move (operands[0], operands[1]))
      DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:65 */
rtx
gen_movvnx8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 69 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use the predicated load and store patterns where possible.
       This is required for big-endian targets (see the comment at the
       head of the file) and increases the addressing choices for
       little-endian.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
        && can_create_pseudo_p ())
      {
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx8BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1],
				      gen_vec_duplicatevnx8hi);
	DONE;
      }

    /* Optimize subregs on big-endian targets: we can use REV[BHW]
       instead of going through memory.  */
    if (BYTES_BIG_ENDIAN
        && aarch64_maybe_expand_sve_subreg_move (operands[0], operands[1]))
      DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:65 */
rtx
gen_movvnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 69 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use the predicated load and store patterns where possible.
       This is required for big-endian targets (see the comment at the
       head of the file) and increases the addressing choices for
       little-endian.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
        && can_create_pseudo_p ())
      {
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx4BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1],
				      gen_vec_duplicatevnx4si);
	DONE;
      }

    /* Optimize subregs on big-endian targets: we can use REV[BHW]
       instead of going through memory.  */
    if (BYTES_BIG_ENDIAN
        && aarch64_maybe_expand_sve_subreg_move (operands[0], operands[1]))
      DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:65 */
rtx
gen_movvnx2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 69 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use the predicated load and store patterns where possible.
       This is required for big-endian targets (see the comment at the
       head of the file) and increases the addressing choices for
       little-endian.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
        && can_create_pseudo_p ())
      {
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx2BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1],
				      gen_vec_duplicatevnx2di);
	DONE;
      }

    /* Optimize subregs on big-endian targets: we can use REV[BHW]
       instead of going through memory.  */
    if (BYTES_BIG_ENDIAN
        && aarch64_maybe_expand_sve_subreg_move (operands[0], operands[1]))
      DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:65 */
rtx
gen_movvnx8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 69 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use the predicated load and store patterns where possible.
       This is required for big-endian targets (see the comment at the
       head of the file) and increases the addressing choices for
       little-endian.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
        && can_create_pseudo_p ())
      {
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx8BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1],
				      gen_vec_duplicatevnx8hf);
	DONE;
      }

    /* Optimize subregs on big-endian targets: we can use REV[BHW]
       instead of going through memory.  */
    if (BYTES_BIG_ENDIAN
        && aarch64_maybe_expand_sve_subreg_move (operands[0], operands[1]))
      DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:65 */
rtx
gen_movvnx4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 69 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use the predicated load and store patterns where possible.
       This is required for big-endian targets (see the comment at the
       head of the file) and increases the addressing choices for
       little-endian.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
        && can_create_pseudo_p ())
      {
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx4BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1],
				      gen_vec_duplicatevnx4sf);
	DONE;
      }

    /* Optimize subregs on big-endian targets: we can use REV[BHW]
       instead of going through memory.  */
    if (BYTES_BIG_ENDIAN
        && aarch64_maybe_expand_sve_subreg_move (operands[0], operands[1]))
      DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:65 */
rtx
gen_movvnx2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 69 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use the predicated load and store patterns where possible.
       This is required for big-endian targets (see the comment at the
       head of the file) and increases the addressing choices for
       little-endian.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
        && can_create_pseudo_p ())
      {
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx2BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1],
				      gen_vec_duplicatevnx2df);
	DONE;
      }

    /* Optimize subregs on big-endian targets: we can use REV[BHW]
       instead of going through memory.  */
    if (BYTES_BIG_ENDIAN
        && aarch64_maybe_expand_sve_subreg_move (operands[0], operands[1]))
      DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:100 */
extern rtx_insn *gen_split_176 (rtx_insn *, rtx *);
rtx_insn *
gen_split_176 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_176\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 110 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_split_sve_subreg_move (operands[0], operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:100 */
extern rtx_insn *gen_split_177 (rtx_insn *, rtx *);
rtx_insn *
gen_split_177 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_177\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 110 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_split_sve_subreg_move (operands[0], operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:100 */
extern rtx_insn *gen_split_178 (rtx_insn *, rtx *);
rtx_insn *
gen_split_178 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_178\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 110 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_split_sve_subreg_move (operands[0], operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:100 */
extern rtx_insn *gen_split_179 (rtx_insn *, rtx *);
rtx_insn *
gen_split_179 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_179\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 110 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_split_sve_subreg_move (operands[0], operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:100 */
extern rtx_insn *gen_split_180 (rtx_insn *, rtx *);
rtx_insn *
gen_split_180 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_180\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 110 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_split_sve_subreg_move (operands[0], operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:100 */
extern rtx_insn *gen_split_181 (rtx_insn *, rtx *);
rtx_insn *
gen_split_181 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_181\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 110 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_split_sve_subreg_move (operands[0], operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:100 */
extern rtx_insn *gen_split_182 (rtx_insn *, rtx *);
rtx_insn *
gen_split_182 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_182\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 110 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_split_sve_subreg_move (operands[0], operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:147 */
rtx
gen_aarch64_sve_reload_be (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 153 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Create a PTRUE.  */
    emit_move_insn (operands[2], CONSTM1_RTX (VNx16BImode));

    /* Refer to the PTRUE in the appropriate mode for this move.  */
    machine_mode mode = GET_MODE (operands[0]);
    machine_mode pred_mode
      = aarch64_sve_pred_mode (GET_MODE_UNIT_SIZE (mode)).require ();
    rtx pred = gen_lowpart (pred_mode, operands[2]);

    /* Emit a predicated load or store.  */
    aarch64_emit_sve_pred_move (operands[0], pred, operands[1]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_CLOBBER (VOIDmode,
	operand2))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
extern rtx_insn *gen_split_183 (rtx_insn *, rtx *);
rtx_insn *
gen_split_183 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_183\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
extern rtx_insn *gen_split_184 (rtx_insn *, rtx *);
rtx_insn *
gen_split_184 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_184\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
extern rtx_insn *gen_split_185 (rtx_insn *, rtx *);
rtx_insn *
gen_split_185 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_185\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
extern rtx_insn *gen_split_186 (rtx_insn *, rtx *);
rtx_insn *
gen_split_186 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_186\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
extern rtx_insn *gen_split_187 (rtx_insn *, rtx *);
rtx_insn *
gen_split_187 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_187\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
extern rtx_insn *gen_split_188 (rtx_insn *, rtx *);
rtx_insn *
gen_split_188 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_188\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:173 */
extern rtx_insn *gen_split_189 (rtx_insn *, rtx *);
rtx_insn *
gen_split_189 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_189\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:191 */
rtx
gen_movmisalignvnx16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 195 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Equivalent to a normal move for our purpooses.  */
    emit_move_insn (operands[0], operands[1]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:191 */
rtx
gen_movmisalignvnx8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 195 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Equivalent to a normal move for our purpooses.  */
    emit_move_insn (operands[0], operands[1]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:191 */
rtx
gen_movmisalignvnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 195 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Equivalent to a normal move for our purpooses.  */
    emit_move_insn (operands[0], operands[1]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:191 */
rtx
gen_movmisalignvnx2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 195 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Equivalent to a normal move for our purpooses.  */
    emit_move_insn (operands[0], operands[1]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:191 */
rtx
gen_movmisalignvnx8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 195 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Equivalent to a normal move for our purpooses.  */
    emit_move_insn (operands[0], operands[1]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:191 */
rtx
gen_movmisalignvnx4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 195 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Equivalent to a normal move for our purpooses.  */
    emit_move_insn (operands[0], operands[1]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:191 */
rtx
gen_movmisalignvnx2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 195 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Equivalent to a normal move for our purpooses.  */
    emit_move_insn (operands[0], operands[1]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:223 */
rtx
gen_gather_loadvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx operand5;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL _Pragma ("GCC error \"gather_loadvnx4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 234 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[5] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (6,
		operand5,
		operand1,
		operand2,
		operand3,
		operand4,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode))),
	87)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:223 */
rtx
gen_gather_loadvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx operand5;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL _Pragma ("GCC error \"gather_loadvnx2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 234 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[5] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (6,
		operand5,
		operand1,
		operand2,
		operand3,
		operand4,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode))),
	87)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:223 */
rtx
gen_gather_loadvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx operand5;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL _Pragma ("GCC error \"gather_loadvnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 234 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[5] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (6,
		operand5,
		operand1,
		operand2,
		operand3,
		operand4,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode))),
	87)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:223 */
rtx
gen_gather_loadvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx operand5;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL _Pragma ("GCC error \"gather_loadvnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 234 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[5] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (6,
		operand5,
		operand1,
		operand2,
		operand3,
		operand4,
		gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode))),
	87)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:280 */
rtx
gen_scatter_storevnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx operand5;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL _Pragma ("GCC error \"scatter_storevnx4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 291 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[5] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (6,
		operand5,
		operand0,
		operand1,
		operand2,
		operand3,
		operand4),
	88)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:280 */
rtx
gen_scatter_storevnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx operand5;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL _Pragma ("GCC error \"scatter_storevnx2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 291 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[5] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (6,
		operand5,
		operand0,
		operand1,
		operand2,
		operand3,
		operand4),
	88)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:280 */
rtx
gen_scatter_storevnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx operand5;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL _Pragma ("GCC error \"scatter_storevnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 291 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[5] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (6,
		operand5,
		operand0,
		operand1,
		operand2,
		operand3,
		operand4),
	88)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:280 */
rtx
gen_scatter_storevnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx operand5;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL _Pragma ("GCC error \"scatter_storevnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 291 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[5] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (6,
		operand5,
		operand0,
		operand1,
		operand2,
		operand3,
		operand4),
	88)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx32qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx16BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx16hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx8BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx8si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx4BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx4di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx2BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx16hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx8BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx8sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx4BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx4df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx2BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx48qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx16BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx24hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx8BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx12si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx4BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx6di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx2BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx24hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx8BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx12sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx4BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx6df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx2BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx64qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx16BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx32hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx8BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx16si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx4BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx8di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx2BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx32hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx8BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx16sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx4BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:337 */
rtx
gen_movvnx8df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 341 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Big-endian loads and stores need to be done via LD1 and ST1;
       see the comment at the head of the file for details.  */
    if ((MEM_P (operands[0]) || MEM_P (operands[1]))
	&& BYTES_BIG_ENDIAN)
      {
	gcc_assert (can_create_pseudo_p ());
	aarch64_expand_sve_mem_move (operands[0], operands[1], VNx2BImode);
	DONE;
      }

    if (CONSTANT_P (operands[1]))
      {
	aarch64_expand_mov_immediate (operands[0], operands[1]);
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_190 (rtx_insn *, rtx *);
rtx_insn *
gen_split_190 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_190\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx16QImode, 2);
    else
      for (unsigned int i = 0; i < 2; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx16QImode, dest, VNx32QImode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx16QImode, src, VNx32QImode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_191 (rtx_insn *, rtx *);
rtx_insn *
gen_split_191 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_191\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx8HImode, 2);
    else
      for (unsigned int i = 0; i < 2; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx8HImode, dest, VNx16HImode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx8HImode, src, VNx16HImode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_192 (rtx_insn *, rtx *);
rtx_insn *
gen_split_192 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_192\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx4SImode, 2);
    else
      for (unsigned int i = 0; i < 2; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx4SImode, dest, VNx8SImode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx4SImode, src, VNx8SImode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_193 (rtx_insn *, rtx *);
rtx_insn *
gen_split_193 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_193\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx2DImode, 2);
    else
      for (unsigned int i = 0; i < 2; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx2DImode, dest, VNx4DImode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx2DImode, src, VNx4DImode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_194 (rtx_insn *, rtx *);
rtx_insn *
gen_split_194 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_194\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx8HFmode, 2);
    else
      for (unsigned int i = 0; i < 2; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx8HFmode, dest, VNx16HFmode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx8HFmode, src, VNx16HFmode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_195 (rtx_insn *, rtx *);
rtx_insn *
gen_split_195 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_195\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx4SFmode, 2);
    else
      for (unsigned int i = 0; i < 2; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx4SFmode, dest, VNx8SFmode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx4SFmode, src, VNx8SFmode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_196 (rtx_insn *, rtx *);
rtx_insn *
gen_split_196 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_196\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx2DFmode, 2);
    else
      for (unsigned int i = 0; i < 2; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx2DFmode, dest, VNx4DFmode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx2DFmode, src, VNx4DFmode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_197 (rtx_insn *, rtx *);
rtx_insn *
gen_split_197 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_197\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx16QImode, 3);
    else
      for (unsigned int i = 0; i < 3; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx16QImode, dest, VNx48QImode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx16QImode, src, VNx48QImode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_198 (rtx_insn *, rtx *);
rtx_insn *
gen_split_198 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_198\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx8HImode, 3);
    else
      for (unsigned int i = 0; i < 3; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx8HImode, dest, VNx24HImode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx8HImode, src, VNx24HImode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_199 (rtx_insn *, rtx *);
rtx_insn *
gen_split_199 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_199\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx4SImode, 3);
    else
      for (unsigned int i = 0; i < 3; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx4SImode, dest, VNx12SImode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx4SImode, src, VNx12SImode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_200 (rtx_insn *, rtx *);
rtx_insn *
gen_split_200 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_200\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx2DImode, 3);
    else
      for (unsigned int i = 0; i < 3; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx2DImode, dest, VNx6DImode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx2DImode, src, VNx6DImode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_201 (rtx_insn *, rtx *);
rtx_insn *
gen_split_201 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_201\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx8HFmode, 3);
    else
      for (unsigned int i = 0; i < 3; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx8HFmode, dest, VNx24HFmode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx8HFmode, src, VNx24HFmode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_202 (rtx_insn *, rtx *);
rtx_insn *
gen_split_202 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_202\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx4SFmode, 3);
    else
      for (unsigned int i = 0; i < 3; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx4SFmode, dest, VNx12SFmode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx4SFmode, src, VNx12SFmode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_203 (rtx_insn *, rtx *);
rtx_insn *
gen_split_203 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_203\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx2DFmode, 3);
    else
      for (unsigned int i = 0; i < 3; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx2DFmode, dest, VNx6DFmode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx2DFmode, src, VNx6DFmode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_204 (rtx_insn *, rtx *);
rtx_insn *
gen_split_204 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_204\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx16QImode, 4);
    else
      for (unsigned int i = 0; i < 4; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx16QImode, dest, VNx64QImode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx16QImode, src, VNx64QImode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_205 (rtx_insn *, rtx *);
rtx_insn *
gen_split_205 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_205\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx8HImode, 4);
    else
      for (unsigned int i = 0; i < 4; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx8HImode, dest, VNx32HImode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx8HImode, src, VNx32HImode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_206 (rtx_insn *, rtx *);
rtx_insn *
gen_split_206 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_206\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx4SImode, 4);
    else
      for (unsigned int i = 0; i < 4; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx4SImode, dest, VNx16SImode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx4SImode, src, VNx16SImode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_207 (rtx_insn *, rtx *);
rtx_insn *
gen_split_207 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_207\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx2DImode, 4);
    else
      for (unsigned int i = 0; i < 4; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx2DImode, dest, VNx8DImode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx2DImode, src, VNx8DImode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_208 (rtx_insn *, rtx *);
rtx_insn *
gen_split_208 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_208\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx8HFmode, 4);
    else
      for (unsigned int i = 0; i < 4; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx8HFmode, dest, VNx32HFmode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx8HFmode, src, VNx32HFmode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_209 (rtx_insn *, rtx *);
rtx_insn *
gen_split_209 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_209\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx4SFmode, 4);
    else
      for (unsigned int i = 0; i < 4; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx4SFmode, dest, VNx16SFmode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx4SFmode, src, VNx16SFmode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:382 */
extern rtx_insn *gen_split_210 (rtx_insn *, rtx *);
rtx_insn *
gen_split_210 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_210\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 387 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx dest = operands[0];
    rtx src = operands[1];
    if (REG_P (dest) && REG_P (src))
      aarch64_simd_emit_reg_reg_move (operands, VNx2DFmode, 4);
    else
      for (unsigned int i = 0; i < 4; ++i)
	{
	  rtx subdest = simplify_gen_subreg (VNx2DFmode, dest, VNx8DFmode,
					     i * BYTES_PER_SVE_VECTOR);
	  rtx subsrc = simplify_gen_subreg (VNx2DFmode, src, VNx8DFmode,
					    i * BYTES_PER_SVE_VECTOR);
	  emit_insn (gen_rtx_SET (subdest, subsrc));
	}
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_211 (rtx_insn *, rtx *);
rtx_insn *
gen_split_211 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_211\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 2; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx16QImode, operands[0],
					   VNx32QImode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx16QImode, operands[2],
					  VNx32QImode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_212 (rtx_insn *, rtx *);
rtx_insn *
gen_split_212 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_212\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 2; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx8HImode, operands[0],
					   VNx16HImode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx8HImode, operands[2],
					  VNx16HImode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_213 (rtx_insn *, rtx *);
rtx_insn *
gen_split_213 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_213\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 2; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx4SImode, operands[0],
					   VNx8SImode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx4SImode, operands[2],
					  VNx8SImode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_214 (rtx_insn *, rtx *);
rtx_insn *
gen_split_214 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_214\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 2; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx2DImode, operands[0],
					   VNx4DImode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx2DImode, operands[2],
					  VNx4DImode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_215 (rtx_insn *, rtx *);
rtx_insn *
gen_split_215 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_215\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 2; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx8HFmode, operands[0],
					   VNx16HFmode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx8HFmode, operands[2],
					  VNx16HFmode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_216 (rtx_insn *, rtx *);
rtx_insn *
gen_split_216 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_216\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 2; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx4SFmode, operands[0],
					   VNx8SFmode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx4SFmode, operands[2],
					  VNx8SFmode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_217 (rtx_insn *, rtx *);
rtx_insn *
gen_split_217 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_217\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 2; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx2DFmode, operands[0],
					   VNx4DFmode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx2DFmode, operands[2],
					  VNx4DFmode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_218 (rtx_insn *, rtx *);
rtx_insn *
gen_split_218 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_218\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 3; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx16QImode, operands[0],
					   VNx48QImode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx16QImode, operands[2],
					  VNx48QImode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_219 (rtx_insn *, rtx *);
rtx_insn *
gen_split_219 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_219\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 3; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx8HImode, operands[0],
					   VNx24HImode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx8HImode, operands[2],
					  VNx24HImode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_220 (rtx_insn *, rtx *);
rtx_insn *
gen_split_220 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_220\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 3; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx4SImode, operands[0],
					   VNx12SImode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx4SImode, operands[2],
					  VNx12SImode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_221 (rtx_insn *, rtx *);
rtx_insn *
gen_split_221 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_221\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 3; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx2DImode, operands[0],
					   VNx6DImode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx2DImode, operands[2],
					  VNx6DImode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_222 (rtx_insn *, rtx *);
rtx_insn *
gen_split_222 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_222\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 3; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx8HFmode, operands[0],
					   VNx24HFmode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx8HFmode, operands[2],
					  VNx24HFmode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_223 (rtx_insn *, rtx *);
rtx_insn *
gen_split_223 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_223\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 3; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx4SFmode, operands[0],
					   VNx12SFmode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx4SFmode, operands[2],
					  VNx12SFmode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_224 (rtx_insn *, rtx *);
rtx_insn *
gen_split_224 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_224\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 3; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx2DFmode, operands[0],
					   VNx6DFmode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx2DFmode, operands[2],
					  VNx6DFmode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_225 (rtx_insn *, rtx *);
rtx_insn *
gen_split_225 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_225\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 4; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx16QImode, operands[0],
					   VNx64QImode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx16QImode, operands[2],
					  VNx64QImode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_226 (rtx_insn *, rtx *);
rtx_insn *
gen_split_226 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_226\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 4; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx8HImode, operands[0],
					   VNx32HImode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx8HImode, operands[2],
					  VNx32HImode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_227 (rtx_insn *, rtx *);
rtx_insn *
gen_split_227 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_227\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 4; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx4SImode, operands[0],
					   VNx16SImode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx4SImode, operands[2],
					  VNx16SImode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_228 (rtx_insn *, rtx *);
rtx_insn *
gen_split_228 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_228\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 4; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx2DImode, operands[0],
					   VNx8DImode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx2DImode, operands[2],
					  VNx8DImode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_229 (rtx_insn *, rtx *);
rtx_insn *
gen_split_229 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_229\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 4; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx8HFmode, operands[0],
					   VNx32HFmode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx8HFmode, operands[2],
					  VNx32HFmode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_230 (rtx_insn *, rtx *);
rtx_insn *
gen_split_230 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_230\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 4; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx4SFmode, operands[0],
					   VNx16SFmode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx4SFmode, operands[2],
					  VNx16SFmode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:407 */
extern rtx_insn *gen_split_231 (rtx_insn *, rtx *);
rtx_insn *
gen_split_231 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_231\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 419 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    for (unsigned int i = 0; i < 4; ++i)
      {
	rtx subdest = simplify_gen_subreg (VNx2DFmode, operands[0],
					   VNx8DFmode,
					   i * BYTES_PER_SVE_VECTOR);
	rtx subsrc = simplify_gen_subreg (VNx2DFmode, operands[2],
					  VNx8DFmode,
					  i * BYTES_PER_SVE_VECTOR);
	aarch64_emit_sve_pred_move (subdest, operands[1], subsrc);
      }
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:435 */
rtx
gen_movvnx16bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 439 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (VNx16BImode, operands[1]);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:435 */
rtx
gen_movvnx8bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 439 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (VNx8BImode, operands[1]);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:435 */
rtx
gen_movvnx4bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 439 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (VNx4BImode, operands[1]);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:435 */
rtx
gen_movvnx2bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 439 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (VNx2BImode, operands[1]);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:461 */
rtx
gen_vec_extractvnx16biqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 468 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx tmp = gen_reg_rtx (VNx16QImode);
    emit_insn (gen_aarch64_sve_dupvnx16qi_const (tmp, operands[1],
						CONST1_RTX (VNx16QImode),
						CONST0_RTX (VNx16QImode)));
    emit_insn (gen_vec_extractvnx16qiqi (operands[0], tmp, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_REG (VNx16QImode,
	32));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:461 */
rtx
gen_vec_extractvnx8bihi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 468 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx tmp = gen_reg_rtx (VNx8HImode);
    emit_insn (gen_aarch64_sve_dupvnx8hi_const (tmp, operands[1],
						CONST1_RTX (VNx8HImode),
						CONST0_RTX (VNx8HImode)));
    emit_insn (gen_vec_extractvnx8hihi (operands[0], tmp, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_REG (VNx8HImode,
	32));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:461 */
rtx
gen_vec_extractvnx4bisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 468 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx tmp = gen_reg_rtx (VNx4SImode);
    emit_insn (gen_aarch64_sve_dupvnx4si_const (tmp, operands[1],
						CONST1_RTX (VNx4SImode),
						CONST0_RTX (VNx4SImode)));
    emit_insn (gen_vec_extractvnx4sisi (operands[0], tmp, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_REG (VNx4SImode,
	32));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:461 */
rtx
gen_vec_extractvnx2bidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 468 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx tmp = gen_reg_rtx (VNx2DImode);
    emit_insn (gen_aarch64_sve_dupvnx2di_const (tmp, operands[1],
						CONST1_RTX (VNx2DImode),
						CONST0_RTX (VNx2DImode)));
    emit_insn (gen_vec_extractvnx2didi (operands[0], tmp, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit_insn (gen_rtx_REG (VNx2DImode,
	32));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:478 */
rtx
gen_vec_extractvnx16qiqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 484 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    poly_int64 val;
    if (poly_int_rtx_p (operands[2], &val)
	&& known_eq (val, GET_MODE_NUNITS (VNx16QImode) - 1))
      {
	/* The last element can be extracted with a LASTB and a false
	   predicate.  */
	rtx sel = force_reg (VNx16BImode, CONST0_RTX (VNx16BImode));
	emit_insn (gen_extract_last_vnx16qi (operands[0], sel, operands[1]));
	DONE;
      }
    if (!CONST_INT_P (operands[2]))
      {
	/* Create an index with operand[2] as the base and -1 as the step.
	   It will then be zero for the element we care about.  */
	rtx index = gen_lowpart (QImode, operands[2]);
	index = force_reg (QImode, index);
	rtx series = gen_reg_rtx (VNx16QImode);
	emit_insn (gen_vec_seriesvnx16qi (series, index, constm1_rtx));

	/* Get a predicate that is true for only that element.  */
	rtx zero = CONST0_RTX (VNx16QImode);
	rtx cmp = gen_rtx_EQ (VNx16QImode, series, zero);
	rtx sel = gen_reg_rtx (VNx16BImode);
	emit_insn (gen_vec_cmpvnx16qivnx16bi (sel, cmp, series, zero));

	/* Select the element using LASTB.  */
	emit_insn (gen_extract_last_vnx16qi (operands[0], sel, operands[1]));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:478 */
rtx
gen_vec_extractvnx8hihi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 484 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    poly_int64 val;
    if (poly_int_rtx_p (operands[2], &val)
	&& known_eq (val, GET_MODE_NUNITS (VNx8HImode) - 1))
      {
	/* The last element can be extracted with a LASTB and a false
	   predicate.  */
	rtx sel = force_reg (VNx8BImode, CONST0_RTX (VNx8BImode));
	emit_insn (gen_extract_last_vnx8hi (operands[0], sel, operands[1]));
	DONE;
      }
    if (!CONST_INT_P (operands[2]))
      {
	/* Create an index with operand[2] as the base and -1 as the step.
	   It will then be zero for the element we care about.  */
	rtx index = gen_lowpart (HImode, operands[2]);
	index = force_reg (HImode, index);
	rtx series = gen_reg_rtx (VNx8HImode);
	emit_insn (gen_vec_seriesvnx8hi (series, index, constm1_rtx));

	/* Get a predicate that is true for only that element.  */
	rtx zero = CONST0_RTX (VNx8HImode);
	rtx cmp = gen_rtx_EQ (VNx8HImode, series, zero);
	rtx sel = gen_reg_rtx (VNx8BImode);
	emit_insn (gen_vec_cmpvnx8hivnx8bi (sel, cmp, series, zero));

	/* Select the element using LASTB.  */
	emit_insn (gen_extract_last_vnx8hi (operands[0], sel, operands[1]));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:478 */
rtx
gen_vec_extractvnx4sisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 484 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    poly_int64 val;
    if (poly_int_rtx_p (operands[2], &val)
	&& known_eq (val, GET_MODE_NUNITS (VNx4SImode) - 1))
      {
	/* The last element can be extracted with a LASTB and a false
	   predicate.  */
	rtx sel = force_reg (VNx4BImode, CONST0_RTX (VNx4BImode));
	emit_insn (gen_extract_last_vnx4si (operands[0], sel, operands[1]));
	DONE;
      }
    if (!CONST_INT_P (operands[2]))
      {
	/* Create an index with operand[2] as the base and -1 as the step.
	   It will then be zero for the element we care about.  */
	rtx index = gen_lowpart (SImode, operands[2]);
	index = force_reg (SImode, index);
	rtx series = gen_reg_rtx (VNx4SImode);
	emit_insn (gen_vec_seriesvnx4si (series, index, constm1_rtx));

	/* Get a predicate that is true for only that element.  */
	rtx zero = CONST0_RTX (VNx4SImode);
	rtx cmp = gen_rtx_EQ (VNx4SImode, series, zero);
	rtx sel = gen_reg_rtx (VNx4BImode);
	emit_insn (gen_vec_cmpvnx4sivnx4bi (sel, cmp, series, zero));

	/* Select the element using LASTB.  */
	emit_insn (gen_extract_last_vnx4si (operands[0], sel, operands[1]));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:478 */
rtx
gen_vec_extractvnx2didi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 484 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    poly_int64 val;
    if (poly_int_rtx_p (operands[2], &val)
	&& known_eq (val, GET_MODE_NUNITS (VNx2DImode) - 1))
      {
	/* The last element can be extracted with a LASTB and a false
	   predicate.  */
	rtx sel = force_reg (VNx2BImode, CONST0_RTX (VNx2BImode));
	emit_insn (gen_extract_last_vnx2di (operands[0], sel, operands[1]));
	DONE;
      }
    if (!CONST_INT_P (operands[2]))
      {
	/* Create an index with operand[2] as the base and -1 as the step.
	   It will then be zero for the element we care about.  */
	rtx index = gen_lowpart (DImode, operands[2]);
	index = force_reg (DImode, index);
	rtx series = gen_reg_rtx (VNx2DImode);
	emit_insn (gen_vec_seriesvnx2di (series, index, constm1_rtx));

	/* Get a predicate that is true for only that element.  */
	rtx zero = CONST0_RTX (VNx2DImode);
	rtx cmp = gen_rtx_EQ (VNx2DImode, series, zero);
	rtx sel = gen_reg_rtx (VNx2BImode);
	emit_insn (gen_vec_cmpvnx2divnx2bi (sel, cmp, series, zero));

	/* Select the element using LASTB.  */
	emit_insn (gen_extract_last_vnx2di (operands[0], sel, operands[1]));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:478 */
rtx
gen_vec_extractvnx8hfhf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 484 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    poly_int64 val;
    if (poly_int_rtx_p (operands[2], &val)
	&& known_eq (val, GET_MODE_NUNITS (VNx8HFmode) - 1))
      {
	/* The last element can be extracted with a LASTB and a false
	   predicate.  */
	rtx sel = force_reg (VNx8BImode, CONST0_RTX (VNx8BImode));
	emit_insn (gen_extract_last_vnx8hf (operands[0], sel, operands[1]));
	DONE;
      }
    if (!CONST_INT_P (operands[2]))
      {
	/* Create an index with operand[2] as the base and -1 as the step.
	   It will then be zero for the element we care about.  */
	rtx index = gen_lowpart (HImode, operands[2]);
	index = force_reg (HImode, index);
	rtx series = gen_reg_rtx (VNx8HImode);
	emit_insn (gen_vec_seriesvnx8hi (series, index, constm1_rtx));

	/* Get a predicate that is true for only that element.  */
	rtx zero = CONST0_RTX (VNx8HImode);
	rtx cmp = gen_rtx_EQ (VNx8HImode, series, zero);
	rtx sel = gen_reg_rtx (VNx8BImode);
	emit_insn (gen_vec_cmpvnx8hivnx8bi (sel, cmp, series, zero));

	/* Select the element using LASTB.  */
	emit_insn (gen_extract_last_vnx8hf (operands[0], sel, operands[1]));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:478 */
rtx
gen_vec_extractvnx4sfsf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 484 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    poly_int64 val;
    if (poly_int_rtx_p (operands[2], &val)
	&& known_eq (val, GET_MODE_NUNITS (VNx4SFmode) - 1))
      {
	/* The last element can be extracted with a LASTB and a false
	   predicate.  */
	rtx sel = force_reg (VNx4BImode, CONST0_RTX (VNx4BImode));
	emit_insn (gen_extract_last_vnx4sf (operands[0], sel, operands[1]));
	DONE;
      }
    if (!CONST_INT_P (operands[2]))
      {
	/* Create an index with operand[2] as the base and -1 as the step.
	   It will then be zero for the element we care about.  */
	rtx index = gen_lowpart (SImode, operands[2]);
	index = force_reg (SImode, index);
	rtx series = gen_reg_rtx (VNx4SImode);
	emit_insn (gen_vec_seriesvnx4si (series, index, constm1_rtx));

	/* Get a predicate that is true for only that element.  */
	rtx zero = CONST0_RTX (VNx4SImode);
	rtx cmp = gen_rtx_EQ (VNx4SImode, series, zero);
	rtx sel = gen_reg_rtx (VNx4BImode);
	emit_insn (gen_vec_cmpvnx4sivnx4bi (sel, cmp, series, zero));

	/* Select the element using LASTB.  */
	emit_insn (gen_extract_last_vnx4sf (operands[0], sel, operands[1]));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:478 */
rtx
gen_vec_extractvnx2dfdf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 484 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    poly_int64 val;
    if (poly_int_rtx_p (operands[2], &val)
	&& known_eq (val, GET_MODE_NUNITS (VNx2DFmode) - 1))
      {
	/* The last element can be extracted with a LASTB and a false
	   predicate.  */
	rtx sel = force_reg (VNx2BImode, CONST0_RTX (VNx2BImode));
	emit_insn (gen_extract_last_vnx2df (operands[0], sel, operands[1]));
	DONE;
      }
    if (!CONST_INT_P (operands[2]))
      {
	/* Create an index with operand[2] as the base and -1 as the step.
	   It will then be zero for the element we care about.  */
	rtx index = gen_lowpart (DImode, operands[2]);
	index = force_reg (DImode, index);
	rtx series = gen_reg_rtx (VNx2DImode);
	emit_insn (gen_vec_seriesvnx2di (series, index, constm1_rtx));

	/* Get a predicate that is true for only that element.  */
	rtx zero = CONST0_RTX (VNx2DImode);
	rtx cmp = gen_rtx_EQ (VNx2DImode, series, zero);
	rtx sel = gen_reg_rtx (VNx2BImode);
	emit_insn (gen_vec_cmpvnx2divnx2bi (sel, cmp, series, zero));

	/* Select the element using LASTB.  */
	emit_insn (gen_extract_last_vnx2df (operands[0], sel, operands[1]));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:520 */
extern rtx_insn *gen_split_232 (rtx_insn *, rtx *);
rtx_insn *
gen_split_232 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_232\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 544 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_note (NOTE_INSN_DELETED);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:520 */
extern rtx_insn *gen_split_233 (rtx_insn *, rtx *);
rtx_insn *
gen_split_233 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_233\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 544 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_note (NOTE_INSN_DELETED);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:520 */
extern rtx_insn *gen_split_234 (rtx_insn *, rtx *);
rtx_insn *
gen_split_234 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_234\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 544 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_note (NOTE_INSN_DELETED);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:520 */
extern rtx_insn *gen_split_235 (rtx_insn *, rtx *);
rtx_insn *
gen_split_235 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_235\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 544 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_note (NOTE_INSN_DELETED);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:520 */
extern rtx_insn *gen_split_236 (rtx_insn *, rtx *);
rtx_insn *
gen_split_236 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_236\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 544 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_note (NOTE_INSN_DELETED);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:520 */
extern rtx_insn *gen_split_237 (rtx_insn *, rtx *);
rtx_insn *
gen_split_237 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_237\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 544 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_note (NOTE_INSN_DELETED);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:520 */
extern rtx_insn *gen_split_238 (rtx_insn *, rtx *);
rtx_insn *
gen_split_238 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_238\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 544 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_note (NOTE_INSN_DELETED);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:622 */
rtx
gen_vec_duplicatevnx16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 629 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (MEM_P (operands[1]))
      {
	rtx ptrue = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
	emit_insn (gen_sve_ld1rvnx16qi (operands[0], ptrue, operands[1],
				       CONST0_RTX (VNx16QImode)));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx16QImode,
	operand1)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (VNx16BImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:622 */
rtx
gen_vec_duplicatevnx8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 629 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (MEM_P (operands[1]))
      {
	rtx ptrue = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
	emit_insn (gen_sve_ld1rvnx8hi (operands[0], ptrue, operands[1],
				       CONST0_RTX (VNx8HImode)));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx8HImode,
	operand1)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (VNx8BImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:622 */
rtx
gen_vec_duplicatevnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 629 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (MEM_P (operands[1]))
      {
	rtx ptrue = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
	emit_insn (gen_sve_ld1rvnx4si (operands[0], ptrue, operands[1],
				       CONST0_RTX (VNx4SImode)));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx4SImode,
	operand1)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (VNx4BImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:622 */
rtx
gen_vec_duplicatevnx2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 629 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (MEM_P (operands[1]))
      {
	rtx ptrue = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
	emit_insn (gen_sve_ld1rvnx2di (operands[0], ptrue, operands[1],
				       CONST0_RTX (VNx2DImode)));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx2DImode,
	operand1)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (VNx2BImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:622 */
rtx
gen_vec_duplicatevnx8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 629 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (MEM_P (operands[1]))
      {
	rtx ptrue = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
	emit_insn (gen_sve_ld1rvnx8hf (operands[0], ptrue, operands[1],
				       CONST0_RTX (VNx8HFmode)));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx8HFmode,
	operand1)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (VNx8BImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:622 */
rtx
gen_vec_duplicatevnx4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 629 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (MEM_P (operands[1]))
      {
	rtx ptrue = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
	emit_insn (gen_sve_ld1rvnx4sf (operands[0], ptrue, operands[1],
				       CONST0_RTX (VNx4SFmode)));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx4SFmode,
	operand1)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (VNx4BImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:622 */
rtx
gen_vec_duplicatevnx2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 629 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (MEM_P (operands[1]))
      {
	rtx ptrue = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
	emit_insn (gen_sve_ld1rvnx2df (operands[0], ptrue, operands[1],
				       CONST0_RTX (VNx2DFmode)));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx2DFmode,
	operand1)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (VNx2BImode)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:644 */
extern rtx_insn *gen_split_239 (rtx_insn *, rtx *);
rtx_insn *
gen_split_239 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_239\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 656 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (GET_CODE (operands[2]) == SCRATCH)
      operands[2] = gen_reg_rtx (VNx16BImode);
    emit_move_insn (operands[2], CONSTM1_RTX (VNx16BImode));
    emit_insn (gen_sve_ld1rvnx16qi (operands[0], operands[2], operands[1],
				   CONST0_RTX (VNx16QImode)));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:644 */
extern rtx_insn *gen_split_240 (rtx_insn *, rtx *);
rtx_insn *
gen_split_240 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_240\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 656 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (GET_CODE (operands[2]) == SCRATCH)
      operands[2] = gen_reg_rtx (VNx8BImode);
    emit_move_insn (operands[2], CONSTM1_RTX (VNx8BImode));
    emit_insn (gen_sve_ld1rvnx8hi (operands[0], operands[2], operands[1],
				   CONST0_RTX (VNx8HImode)));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:644 */
extern rtx_insn *gen_split_241 (rtx_insn *, rtx *);
rtx_insn *
gen_split_241 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_241\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 656 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (GET_CODE (operands[2]) == SCRATCH)
      operands[2] = gen_reg_rtx (VNx4BImode);
    emit_move_insn (operands[2], CONSTM1_RTX (VNx4BImode));
    emit_insn (gen_sve_ld1rvnx4si (operands[0], operands[2], operands[1],
				   CONST0_RTX (VNx4SImode)));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:644 */
extern rtx_insn *gen_split_242 (rtx_insn *, rtx *);
rtx_insn *
gen_split_242 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_242\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 656 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (GET_CODE (operands[2]) == SCRATCH)
      operands[2] = gen_reg_rtx (VNx2BImode);
    emit_move_insn (operands[2], CONSTM1_RTX (VNx2BImode));
    emit_insn (gen_sve_ld1rvnx2di (operands[0], operands[2], operands[1],
				   CONST0_RTX (VNx2DImode)));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:644 */
extern rtx_insn *gen_split_243 (rtx_insn *, rtx *);
rtx_insn *
gen_split_243 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_243\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 656 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (GET_CODE (operands[2]) == SCRATCH)
      operands[2] = gen_reg_rtx (VNx8BImode);
    emit_move_insn (operands[2], CONSTM1_RTX (VNx8BImode));
    emit_insn (gen_sve_ld1rvnx8hf (operands[0], operands[2], operands[1],
				   CONST0_RTX (VNx8HFmode)));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:644 */
extern rtx_insn *gen_split_244 (rtx_insn *, rtx *);
rtx_insn *
gen_split_244 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_244\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 656 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (GET_CODE (operands[2]) == SCRATCH)
      operands[2] = gen_reg_rtx (VNx4BImode);
    emit_move_insn (operands[2], CONSTM1_RTX (VNx4BImode));
    emit_insn (gen_sve_ld1rvnx4sf (operands[0], operands[2], operands[1],
				   CONST0_RTX (VNx4SFmode)));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:644 */
extern rtx_insn *gen_split_245 (rtx_insn *, rtx *);
rtx_insn *
gen_split_245 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_245\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 656 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    if (GET_CODE (operands[2]) == SCRATCH)
      operands[2] = gen_reg_rtx (VNx2BImode);
    emit_move_insn (operands[2], CONSTM1_RTX (VNx2BImode));
    emit_insn (gen_sve_ld1rvnx2df (operands[0], operands[2], operands[1],
				   CONST0_RTX (VNx2DFmode)));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:698 */
rtx
gen_vec_duplicatevnx16bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 702 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx tmp = gen_reg_rtx (DImode);
    rtx op1 = gen_lowpart (DImode, operands[1]);
    emit_insn (gen_ashldi3 (tmp, op1, gen_int_mode (63, DImode)));
    emit_insn (gen_while_ultdivnx16bi (operands[0], const0_rtx, tmp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx16BImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:698 */
rtx
gen_vec_duplicatevnx8bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 702 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx tmp = gen_reg_rtx (DImode);
    rtx op1 = gen_lowpart (DImode, operands[1]);
    emit_insn (gen_ashldi3 (tmp, op1, gen_int_mode (63, DImode)));
    emit_insn (gen_while_ultdivnx8bi (operands[0], const0_rtx, tmp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx8BImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:698 */
rtx
gen_vec_duplicatevnx4bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 702 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx tmp = gen_reg_rtx (DImode);
    rtx op1 = gen_lowpart (DImode, operands[1]);
    emit_insn (gen_ashldi3 (tmp, op1, gen_int_mode (63, DImode)));
    emit_insn (gen_while_ultdivnx4bi (operands[0], const0_rtx, tmp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx4BImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:698 */
rtx
gen_vec_duplicatevnx2bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 702 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx tmp = gen_reg_rtx (DImode);
    rtx op1 = gen_lowpart (DImode, operands[1]);
    emit_insn (gen_ashldi3 (tmp, op1, gen_int_mode (63, DImode)));
    emit_insn (gen_while_ultdivnx2bi (operands[0], const0_rtx, tmp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (VNx2BImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx32qivnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx32qivnx16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx16hivnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx16hivnx8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx8sivnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx8sivnx4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx4divnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx4divnx2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx16hfvnx8hf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx16hfvnx8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx8sfvnx4sf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx8sfvnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx4dfvnx2df (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx4dfvnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx48qivnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx48qivnx16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx48QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx24hivnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx24hivnx8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx24HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx12sivnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx12sivnx4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx12SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx6divnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx6divnx2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx6DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx24hfvnx8hf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx24hfvnx8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx24HFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx12sfvnx4sf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx12sfvnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx12SFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx6dfvnx2df (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx6dfvnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx6DFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx64qivnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx64qivnx16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx32hivnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx32hivnx8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx16sivnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx16sivnx4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx8divnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx8divnx2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx32hfvnx8hf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx32hfvnx8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx16sfvnx4sf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx16sfvnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:739 */
rtx
gen_vec_load_lanesvnx8dfvnx2df (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesvnx8dfvnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 746 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	98)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx32qivnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx32qivnx16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32QImode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx16hivnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx16hivnx8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HImode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx8sivnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx8sivnx4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SImode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx4divnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx4divnx2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DImode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx16hfvnx8hf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx16hfvnx8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16HFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx8sfvnx4sf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx8sfvnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8SFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx4dfvnx2df (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx4dfvnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4DFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx48qivnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx48qivnx16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx48QImode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx24hivnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx24hivnx8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx24HImode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx12sivnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx12sivnx4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx12SImode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx6divnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx6divnx2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx6DImode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx24hfvnx8hf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx24hfvnx8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx24HFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx12sfvnx4sf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx12sfvnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx12SFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx6dfvnx2df (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx6dfvnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx6DFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx64qivnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx64qivnx16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx64QImode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx32hivnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx32hivnx8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HImode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx16sivnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx16sivnx4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SImode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx8divnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx8divnx2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DImode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx32hfvnx8hf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx32hfvnx8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx32HFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx16sfvnx4sf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx16sfvnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16SFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:767 */
rtx
gen_vec_store_lanesvnx8dfvnx2df (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesvnx8dfvnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 775 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8DFmode,
	gen_rtvec (3,
		operand2,
		operand1,
		copy_rtx (operand0)),
	99)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:792 */
rtx
gen_vec_permvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 798 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_perm (operands[0], operands[1],
				 operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:792 */
rtx
gen_vec_permvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 798 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_perm (operands[0], operands[1],
				 operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:792 */
rtx
gen_vec_permvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 798 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_perm (operands[0], operands[1],
				 operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:792 */
rtx
gen_vec_permvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 798 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_perm (operands[0], operands[1],
				 operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:792 */
rtx
gen_vec_permvnx8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 798 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_perm (operands[0], operands[1],
				 operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:792 */
rtx
gen_vec_permvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 798 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_perm (operands[0], operands[1],
				 operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:792 */
rtx
gen_vec_permvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 798 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_perm (operands[0], operands[1],
				 operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:925 */
rtx
gen_mulvnx16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 934 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_MULT (VNx16QImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:925 */
rtx
gen_mulvnx8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 934 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_MULT (VNx8HImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:925 */
rtx
gen_mulvnx4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 934 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_MULT (VNx4SImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:925 */
rtx
gen_mulvnx2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 934 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_MULT (VNx2DImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:943 */
extern rtx_insn *gen_split_246 (rtx_insn *, rtx *);
rtx_insn *
gen_split_246 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_246\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 961 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (VNx16QImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:943 */
extern rtx_insn *gen_split_247 (rtx_insn *, rtx *);
rtx_insn *
gen_split_247 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_247\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 961 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (VNx8HImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:943 */
extern rtx_insn *gen_split_248 (rtx_insn *, rtx *);
rtx_insn *
gen_split_248 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_248\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 961 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (VNx4SImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:943 */
extern rtx_insn *gen_split_249 (rtx_insn *, rtx *);
rtx_insn *
gen_split_249 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_249\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 961 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (VNx2DImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1012 */
rtx
gen_smulvnx16qi3_highpart (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1021 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	235)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1012 */
rtx
gen_umulvnx16qi3_highpart (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1021 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	236)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1012 */
rtx
gen_smulvnx8hi3_highpart (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1021 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	235)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1012 */
rtx
gen_umulvnx8hi3_highpart (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1021 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	236)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1012 */
rtx
gen_smulvnx4si3_highpart (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1021 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	235)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1012 */
rtx
gen_umulvnx4si3_highpart (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1021 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	236)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1012 */
rtx
gen_smulvnx2di3_highpart (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1021 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	235)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1012 */
rtx
gen_umulvnx2di3_highpart (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1021 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	236)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1043 */
rtx
gen_divvnx4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1052 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_DIV (VNx4SImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1043 */
rtx
gen_udivvnx4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1052 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UDIV (VNx4SImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1043 */
rtx
gen_divvnx2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1052 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_DIV (VNx2DImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1043 */
rtx
gen_udivvnx2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1052 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UDIV (VNx2DImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_absvnx16qi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_ABS (VNx16QImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_negvnx16qi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_NEG (VNx16QImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_one_cmplvnx16qi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_NOT (VNx16QImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_popcountvnx16qi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"popcountvnx16qi2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_POPCOUNT (VNx16QImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_absvnx8hi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_ABS (VNx8HImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_negvnx8hi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_NEG (VNx8HImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_one_cmplvnx8hi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_NOT (VNx8HImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_popcountvnx8hi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"popcountvnx8hi2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_POPCOUNT (VNx8HImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_absvnx4si2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_ABS (VNx4SImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_negvnx4si2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_NEG (VNx4SImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_one_cmplvnx4si2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_NOT (VNx4SImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_popcountvnx4si2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"popcountvnx4si2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_POPCOUNT (VNx4SImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_absvnx2di2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_ABS (VNx2DImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_negvnx2di2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_NEG (VNx2DImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_one_cmplvnx2di2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_NOT (VNx2DImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1075 */
rtx
gen_popcountvnx2di2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"popcountvnx2di2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1082 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_POPCOUNT (VNx2DImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1144 */
rtx
gen_iorvnx16bi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1152 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_IOR (VNx16BImode,
	operand1,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1144 */
rtx
gen_xorvnx16bi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1152 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_XOR (VNx16BImode,
	operand1,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1144 */
rtx
gen_iorvnx8bi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1152 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_IOR (VNx8BImode,
	operand1,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1144 */
rtx
gen_xorvnx8bi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1152 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_XOR (VNx8BImode,
	operand1,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1144 */
rtx
gen_iorvnx4bi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1152 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_IOR (VNx4BImode,
	operand1,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1144 */
rtx
gen_xorvnx4bi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1152 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_XOR (VNx4BImode,
	operand1,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1144 */
rtx
gen_iorvnx2bi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1152 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_IOR (VNx2BImode,
	operand1,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1144 */
rtx
gen_xorvnx2bi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1152 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_XOR (VNx2BImode,
	operand1,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1193 */
rtx
gen_one_cmplvnx16bi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1199 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_NOT (VNx16BImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1193 */
rtx
gen_one_cmplvnx8bi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1199 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_NOT (VNx8BImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1193 */
rtx
gen_one_cmplvnx4bi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1199 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_NOT (VNx4BImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1193 */
rtx
gen_one_cmplvnx2bi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1199 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_NOT (VNx2BImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1239 */
rtx
gen_vashlvnx16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1248 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_ASHIFT (VNx16QImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1239 */
rtx
gen_vashrvnx16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1248 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_ASHIFTRT (VNx16QImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1239 */
rtx
gen_vlshrvnx16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1248 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_LSHIFTRT (VNx16QImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1239 */
rtx
gen_vashlvnx8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1248 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_ASHIFT (VNx8HImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1239 */
rtx
gen_vashrvnx8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1248 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_ASHIFTRT (VNx8HImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1239 */
rtx
gen_vlshrvnx8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1248 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_LSHIFTRT (VNx8HImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1239 */
rtx
gen_vashlvnx4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1248 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_ASHIFT (VNx4SImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1239 */
rtx
gen_vashrvnx4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1248 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_ASHIFTRT (VNx4SImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1239 */
rtx
gen_vlshrvnx4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1248 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_LSHIFTRT (VNx4SImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1239 */
rtx
gen_vashlvnx2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1248 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_ASHIFT (VNx2DImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1239 */
rtx
gen_vashrvnx2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1248 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_ASHIFTRT (VNx2DImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1239 */
rtx
gen_vlshrvnx2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1248 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_LSHIFTRT (VNx2DImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1257 */
extern rtx_insn *gen_split_250 (rtx_insn *, rtx *);
rtx_insn *
gen_split_250 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_250\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (VNx16QImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1257 */
extern rtx_insn *gen_split_251 (rtx_insn *, rtx *);
rtx_insn *
gen_split_251 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_251\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (VNx16QImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1257 */
extern rtx_insn *gen_split_252 (rtx_insn *, rtx *);
rtx_insn *
gen_split_252 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_252\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (VNx16QImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1257 */
extern rtx_insn *gen_split_253 (rtx_insn *, rtx *);
rtx_insn *
gen_split_253 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_253\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (VNx8HImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1257 */
extern rtx_insn *gen_split_254 (rtx_insn *, rtx *);
rtx_insn *
gen_split_254 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_254\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (VNx8HImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1257 */
extern rtx_insn *gen_split_255 (rtx_insn *, rtx *);
rtx_insn *
gen_split_255 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_255\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (VNx8HImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1257 */
extern rtx_insn *gen_split_256 (rtx_insn *, rtx *);
rtx_insn *
gen_split_256 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_256\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (VNx4SImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1257 */
extern rtx_insn *gen_split_257 (rtx_insn *, rtx *);
rtx_insn *
gen_split_257 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_257\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (VNx4SImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1257 */
extern rtx_insn *gen_split_258 (rtx_insn *, rtx *);
rtx_insn *
gen_split_258 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_258\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (VNx4SImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1257 */
extern rtx_insn *gen_split_259 (rtx_insn *, rtx *);
rtx_insn *
gen_split_259 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_259\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (VNx2DImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1257 */
extern rtx_insn *gen_split_260 (rtx_insn *, rtx *);
rtx_insn *
gen_split_260 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_260\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (VNx2DImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1257 */
extern rtx_insn *gen_split_261 (rtx_insn *, rtx *);
rtx_insn *
gen_split_261 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_261\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1273 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (VNx2DImode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1291 */
rtx
gen_ashlvnx16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1296 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx amount;
    if (CONST_INT_P (operands[2]))
      {
	amount = gen_const_vec_duplicate (VNx16QImode, operands[2]);
	if (!aarch64_sve_lshift_operand (operands[2], VNx16QImode))
	  amount = force_reg (VNx16QImode, amount);
      }
    else
      {
	amount = gen_reg_rtx (VNx16QImode);
	emit_insn (gen_vec_duplicatevnx16qi (amount,
					    convert_to_mode (QImode,
							     operands[2], 0)));
      }
    emit_insn (gen_vashlvnx16qi3 (operands[0], operands[1], amount));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (VNx16QImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1291 */
rtx
gen_ashrvnx16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1296 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx amount;
    if (CONST_INT_P (operands[2]))
      {
	amount = gen_const_vec_duplicate (VNx16QImode, operands[2]);
	if (!aarch64_sve_rshift_operand (operands[2], VNx16QImode))
	  amount = force_reg (VNx16QImode, amount);
      }
    else
      {
	amount = gen_reg_rtx (VNx16QImode);
	emit_insn (gen_vec_duplicatevnx16qi (amount,
					    convert_to_mode (QImode,
							     operands[2], 0)));
      }
    emit_insn (gen_vashrvnx16qi3 (operands[0], operands[1], amount));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (VNx16QImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1291 */
rtx
gen_lshrvnx16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1296 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx amount;
    if (CONST_INT_P (operands[2]))
      {
	amount = gen_const_vec_duplicate (VNx16QImode, operands[2]);
	if (!aarch64_sve_rshift_operand (operands[2], VNx16QImode))
	  amount = force_reg (VNx16QImode, amount);
      }
    else
      {
	amount = gen_reg_rtx (VNx16QImode);
	emit_insn (gen_vec_duplicatevnx16qi (amount,
					    convert_to_mode (QImode,
							     operands[2], 0)));
      }
    emit_insn (gen_vlshrvnx16qi3 (operands[0], operands[1], amount));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (VNx16QImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1291 */
rtx
gen_ashlvnx8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1296 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx amount;
    if (CONST_INT_P (operands[2]))
      {
	amount = gen_const_vec_duplicate (VNx8HImode, operands[2]);
	if (!aarch64_sve_lshift_operand (operands[2], VNx8HImode))
	  amount = force_reg (VNx8HImode, amount);
      }
    else
      {
	amount = gen_reg_rtx (VNx8HImode);
	emit_insn (gen_vec_duplicatevnx8hi (amount,
					    convert_to_mode (HImode,
							     operands[2], 0)));
      }
    emit_insn (gen_vashlvnx8hi3 (operands[0], operands[1], amount));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (VNx8HImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1291 */
rtx
gen_ashrvnx8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1296 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx amount;
    if (CONST_INT_P (operands[2]))
      {
	amount = gen_const_vec_duplicate (VNx8HImode, operands[2]);
	if (!aarch64_sve_rshift_operand (operands[2], VNx8HImode))
	  amount = force_reg (VNx8HImode, amount);
      }
    else
      {
	amount = gen_reg_rtx (VNx8HImode);
	emit_insn (gen_vec_duplicatevnx8hi (amount,
					    convert_to_mode (HImode,
							     operands[2], 0)));
      }
    emit_insn (gen_vashrvnx8hi3 (operands[0], operands[1], amount));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (VNx8HImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1291 */
rtx
gen_lshrvnx8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1296 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx amount;
    if (CONST_INT_P (operands[2]))
      {
	amount = gen_const_vec_duplicate (VNx8HImode, operands[2]);
	if (!aarch64_sve_rshift_operand (operands[2], VNx8HImode))
	  amount = force_reg (VNx8HImode, amount);
      }
    else
      {
	amount = gen_reg_rtx (VNx8HImode);
	emit_insn (gen_vec_duplicatevnx8hi (amount,
					    convert_to_mode (HImode,
							     operands[2], 0)));
      }
    emit_insn (gen_vlshrvnx8hi3 (operands[0], operands[1], amount));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (VNx8HImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1291 */
rtx
gen_ashlvnx4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1296 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx amount;
    if (CONST_INT_P (operands[2]))
      {
	amount = gen_const_vec_duplicate (VNx4SImode, operands[2]);
	if (!aarch64_sve_lshift_operand (operands[2], VNx4SImode))
	  amount = force_reg (VNx4SImode, amount);
      }
    else
      {
	amount = gen_reg_rtx (VNx4SImode);
	emit_insn (gen_vec_duplicatevnx4si (amount,
					    convert_to_mode (SImode,
							     operands[2], 0)));
      }
    emit_insn (gen_vashlvnx4si3 (operands[0], operands[1], amount));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (VNx4SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1291 */
rtx
gen_ashrvnx4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1296 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx amount;
    if (CONST_INT_P (operands[2]))
      {
	amount = gen_const_vec_duplicate (VNx4SImode, operands[2]);
	if (!aarch64_sve_rshift_operand (operands[2], VNx4SImode))
	  amount = force_reg (VNx4SImode, amount);
      }
    else
      {
	amount = gen_reg_rtx (VNx4SImode);
	emit_insn (gen_vec_duplicatevnx4si (amount,
					    convert_to_mode (SImode,
							     operands[2], 0)));
      }
    emit_insn (gen_vashrvnx4si3 (operands[0], operands[1], amount));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (VNx4SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1291 */
rtx
gen_lshrvnx4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1296 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx amount;
    if (CONST_INT_P (operands[2]))
      {
	amount = gen_const_vec_duplicate (VNx4SImode, operands[2]);
	if (!aarch64_sve_rshift_operand (operands[2], VNx4SImode))
	  amount = force_reg (VNx4SImode, amount);
      }
    else
      {
	amount = gen_reg_rtx (VNx4SImode);
	emit_insn (gen_vec_duplicatevnx4si (amount,
					    convert_to_mode (SImode,
							     operands[2], 0)));
      }
    emit_insn (gen_vlshrvnx4si3 (operands[0], operands[1], amount));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (VNx4SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1291 */
rtx
gen_ashlvnx2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1296 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx amount;
    if (CONST_INT_P (operands[2]))
      {
	amount = gen_const_vec_duplicate (VNx2DImode, operands[2]);
	if (!aarch64_sve_lshift_operand (operands[2], VNx2DImode))
	  amount = force_reg (VNx2DImode, amount);
      }
    else
      {
	amount = gen_reg_rtx (VNx2DImode);
	emit_insn (gen_vec_duplicatevnx2di (amount,
					    convert_to_mode (DImode,
							     operands[2], 0)));
      }
    emit_insn (gen_vashlvnx2di3 (operands[0], operands[1], amount));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (VNx2DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1291 */
rtx
gen_ashrvnx2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1296 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx amount;
    if (CONST_INT_P (operands[2]))
      {
	amount = gen_const_vec_duplicate (VNx2DImode, operands[2]);
	if (!aarch64_sve_rshift_operand (operands[2], VNx2DImode))
	  amount = force_reg (VNx2DImode, amount);
      }
    else
      {
	amount = gen_reg_rtx (VNx2DImode);
	emit_insn (gen_vec_duplicatevnx2di (amount,
					    convert_to_mode (DImode,
							     operands[2], 0)));
      }
    emit_insn (gen_vashrvnx2di3 (operands[0], operands[1], amount));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (VNx2DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1291 */
rtx
gen_lshrvnx2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1296 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx amount;
    if (CONST_INT_P (operands[2]))
      {
	amount = gen_const_vec_duplicate (VNx2DImode, operands[2]);
	if (!aarch64_sve_rshift_operand (operands[2], VNx2DImode))
	  amount = force_reg (VNx2DImode, amount);
      }
    else
      {
	amount = gen_reg_rtx (VNx2DImode);
	emit_insn (gen_vec_duplicatevnx2di (amount,
					    convert_to_mode (DImode,
							     operands[2], 0)));
      }
    emit_insn (gen_vlshrvnx2di3 (operands[0], operands[1], amount));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (VNx2DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
extern rtx_insn *gen_split_262 (rtx_insn *, rtx *);
rtx_insn *
gen_split_262 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_262\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1368 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn (gen_while_ultsivnx16bi_cc
	       (operands[0], CONSTM1_RTX (VNx16BImode),
		operands[2], operands[3]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
extern rtx_insn *gen_split_263 (rtx_insn *, rtx *);
rtx_insn *
gen_split_263 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_263\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1368 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn (gen_while_ultdivnx16bi_cc
	       (operands[0], CONSTM1_RTX (VNx16BImode),
		operands[2], operands[3]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
extern rtx_insn *gen_split_264 (rtx_insn *, rtx *);
rtx_insn *
gen_split_264 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_264\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1368 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn (gen_while_ultsivnx8bi_cc
	       (operands[0], CONSTM1_RTX (VNx8BImode),
		operands[2], operands[3]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
extern rtx_insn *gen_split_265 (rtx_insn *, rtx *);
rtx_insn *
gen_split_265 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_265\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1368 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn (gen_while_ultdivnx8bi_cc
	       (operands[0], CONSTM1_RTX (VNx8BImode),
		operands[2], operands[3]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
extern rtx_insn *gen_split_266 (rtx_insn *, rtx *);
rtx_insn *
gen_split_266 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_266\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1368 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn (gen_while_ultsivnx4bi_cc
	       (operands[0], CONSTM1_RTX (VNx4BImode),
		operands[2], operands[3]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
extern rtx_insn *gen_split_267 (rtx_insn *, rtx *);
rtx_insn *
gen_split_267 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_267\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1368 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn (gen_while_ultdivnx4bi_cc
	       (operands[0], CONSTM1_RTX (VNx4BImode),
		operands[2], operands[3]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
extern rtx_insn *gen_split_268 (rtx_insn *, rtx *);
rtx_insn *
gen_split_268 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_268\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1368 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn (gen_while_ultsivnx2bi_cc
	       (operands[0], CONSTM1_RTX (VNx2BImode),
		operands[2], operands[3]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1348 */
extern rtx_insn *gen_split_269 (rtx_insn *, rtx *);
rtx_insn *
gen_split_269 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_269\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1368 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn (gen_while_ultdivnx2bi_cc
	       (operands[0], CONSTM1_RTX (VNx2BImode),
		operands[2], operands[3]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_270 (rtx_insn *, rtx *);
rtx_insn *
gen_split_270 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_270\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_LT (VNx16BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_271 (rtx_insn *, rtx *);
rtx_insn *
gen_split_271 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_271\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_LE (VNx16BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_272 (rtx_insn *, rtx *);
rtx_insn *
gen_split_272 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_272\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_EQ (VNx16BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_273 (rtx_insn *, rtx *);
rtx_insn *
gen_split_273 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_273\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_NE (VNx16BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_274 (rtx_insn *, rtx *);
rtx_insn *
gen_split_274 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_274\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_GE (VNx16BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_275 (rtx_insn *, rtx *);
rtx_insn *
gen_split_275 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_275\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_GT (VNx16BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_276 (rtx_insn *, rtx *);
rtx_insn *
gen_split_276 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_276\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_LTU (VNx16BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_277 (rtx_insn *, rtx *);
rtx_insn *
gen_split_277 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_277\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_LEU (VNx16BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_278 (rtx_insn *, rtx *);
rtx_insn *
gen_split_278 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_278\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_GEU (VNx16BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_279 (rtx_insn *, rtx *);
rtx_insn *
gen_split_279 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_279\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx16BImode,
	gen_rtx_GTU (VNx16BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_280 (rtx_insn *, rtx *);
rtx_insn *
gen_split_280 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_280\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_LT (VNx8BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_281 (rtx_insn *, rtx *);
rtx_insn *
gen_split_281 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_281\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_LE (VNx8BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_282 (rtx_insn *, rtx *);
rtx_insn *
gen_split_282 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_282\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_EQ (VNx8BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_283 (rtx_insn *, rtx *);
rtx_insn *
gen_split_283 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_283\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_NE (VNx8BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_284 (rtx_insn *, rtx *);
rtx_insn *
gen_split_284 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_284\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_GE (VNx8BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_285 (rtx_insn *, rtx *);
rtx_insn *
gen_split_285 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_285\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_GT (VNx8BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_286 (rtx_insn *, rtx *);
rtx_insn *
gen_split_286 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_286\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_LTU (VNx8BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_287 (rtx_insn *, rtx *);
rtx_insn *
gen_split_287 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_287\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_LEU (VNx8BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_288 (rtx_insn *, rtx *);
rtx_insn *
gen_split_288 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_288\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_GEU (VNx8BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_289 (rtx_insn *, rtx *);
rtx_insn *
gen_split_289 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_289\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_GTU (VNx8BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_290 (rtx_insn *, rtx *);
rtx_insn *
gen_split_290 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_290\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_LT (VNx4BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_291 (rtx_insn *, rtx *);
rtx_insn *
gen_split_291 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_291\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_LE (VNx4BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_292 (rtx_insn *, rtx *);
rtx_insn *
gen_split_292 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_292\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_EQ (VNx4BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_293 (rtx_insn *, rtx *);
rtx_insn *
gen_split_293 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_293\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_NE (VNx4BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_294 (rtx_insn *, rtx *);
rtx_insn *
gen_split_294 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_294\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_GE (VNx4BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_295 (rtx_insn *, rtx *);
rtx_insn *
gen_split_295 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_295\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_GT (VNx4BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_296 (rtx_insn *, rtx *);
rtx_insn *
gen_split_296 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_296\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_LTU (VNx4BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_297 (rtx_insn *, rtx *);
rtx_insn *
gen_split_297 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_297\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_LEU (VNx4BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_298 (rtx_insn *, rtx *);
rtx_insn *
gen_split_298 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_298\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_GEU (VNx4BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_299 (rtx_insn *, rtx *);
rtx_insn *
gen_split_299 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_299\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_GTU (VNx4BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_300 (rtx_insn *, rtx *);
rtx_insn *
gen_split_300 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_300\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_LT (VNx2BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_301 (rtx_insn *, rtx *);
rtx_insn *
gen_split_301 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_301\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_LE (VNx2BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_302 (rtx_insn *, rtx *);
rtx_insn *
gen_split_302 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_302\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_EQ (VNx2BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_303 (rtx_insn *, rtx *);
rtx_insn *
gen_split_303 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_303\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_NE (VNx2BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_304 (rtx_insn *, rtx *);
rtx_insn *
gen_split_304 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_304\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_GE (VNx2BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_305 (rtx_insn *, rtx *);
rtx_insn *
gen_split_305 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_305\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_GT (VNx2BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_306 (rtx_insn *, rtx *);
rtx_insn *
gen_split_306 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_306\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_LTU (VNx2BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_307 (rtx_insn *, rtx *);
rtx_insn *
gen_split_307 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_307\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_LEU (VNx2BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_308 (rtx_insn *, rtx *);
rtx_insn *
gen_split_308 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_308\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_GEU (VNx2BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1446 */
extern rtx_insn *gen_split_309 (rtx_insn *, rtx *);
rtx_insn *
gen_split_309 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_309\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_GTU (VNx2BImode,
	operand2,
	operand3),
	operand4)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_310 (rtx_insn *, rtx *);
rtx_insn *
gen_split_310 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_310\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_LT (VNx8BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_311 (rtx_insn *, rtx *);
rtx_insn *
gen_split_311 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_311\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_LE (VNx8BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_312 (rtx_insn *, rtx *);
rtx_insn *
gen_split_312 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_312\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_EQ (VNx8BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_313 (rtx_insn *, rtx *);
rtx_insn *
gen_split_313 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_313\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_NE (VNx8BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_314 (rtx_insn *, rtx *);
rtx_insn *
gen_split_314 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_314\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_GE (VNx8BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_315 (rtx_insn *, rtx *);
rtx_insn *
gen_split_315 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_315\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_GT (VNx8BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_316 (rtx_insn *, rtx *);
rtx_insn *
gen_split_316 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_316\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_LT (VNx4BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_317 (rtx_insn *, rtx *);
rtx_insn *
gen_split_317 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_317\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_LE (VNx4BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_318 (rtx_insn *, rtx *);
rtx_insn *
gen_split_318 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_318\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_EQ (VNx4BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_319 (rtx_insn *, rtx *);
rtx_insn *
gen_split_319 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_319\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_NE (VNx4BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_320 (rtx_insn *, rtx *);
rtx_insn *
gen_split_320 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_320\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_GE (VNx4BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_321 (rtx_insn *, rtx *);
rtx_insn *
gen_split_321 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_321\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_GT (VNx4BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_322 (rtx_insn *, rtx *);
rtx_insn *
gen_split_322 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_322\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_LT (VNx2BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_323 (rtx_insn *, rtx *);
rtx_insn *
gen_split_323 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_323\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_LE (VNx2BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_324 (rtx_insn *, rtx *);
rtx_insn *
gen_split_324 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_324\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_EQ (VNx2BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_325 (rtx_insn *, rtx *);
rtx_insn *
gen_split_325 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_325\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_NE (VNx2BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_326 (rtx_insn *, rtx *);
rtx_insn *
gen_split_326 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_326\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_GE (VNx2BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1520 */
extern rtx_insn *gen_split_327 (rtx_insn *, rtx *);
rtx_insn *
gen_split_327 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_327\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_GT (VNx2BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1541 */
extern rtx_insn *gen_split_328 (rtx_insn *, rtx *);
rtx_insn *
gen_split_328 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_328\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx8BImode,
	gen_rtx_UNORDERED (VNx8BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1541 */
extern rtx_insn *gen_split_329 (rtx_insn *, rtx *);
rtx_insn *
gen_split_329 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_329\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx4BImode,
	gen_rtx_UNORDERED (VNx4BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1541 */
extern rtx_insn *gen_split_330 (rtx_insn *, rtx *);
rtx_insn *
gen_split_330 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_330\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_AND (VNx2BImode,
	gen_rtx_UNORDERED (VNx2BImode,
	operand2,
	operand3),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1632 */
rtx
gen_vcondvnx16qivnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1641 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx16QImode, VNx16QImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1632 */
rtx
gen_vcondvnx8hivnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1641 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx8HImode, VNx8HImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1632 */
rtx
gen_vcondvnx4sivnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1641 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx4SImode, VNx4SImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1632 */
rtx
gen_vcondvnx2divnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1641 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx2DImode, VNx2DImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1632 */
rtx
gen_vcondvnx8hfvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1641 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx8HFmode, VNx8HImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1632 */
rtx
gen_vcondvnx4sfvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1641 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx4SFmode, VNx4SImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1632 */
rtx
gen_vcondvnx2dfvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1641 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx2DFmode, VNx2DImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1649 */
rtx
gen_vconduvnx16qivnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1658 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx16QImode, VNx16QImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx16QImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1649 */
rtx
gen_vconduvnx8hivnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1658 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx8HImode, VNx8HImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1649 */
rtx
gen_vconduvnx4sivnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1658 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx4SImode, VNx4SImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1649 */
rtx
gen_vconduvnx2divnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1658 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx2DImode, VNx2DImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1649 */
rtx
gen_vconduvnx8hfvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1658 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx8HFmode, VNx8HImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx8HFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1649 */
rtx
gen_vconduvnx4sfvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1658 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx4SFmode, VNx4SImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1649 */
rtx
gen_vconduvnx2dfvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1658 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx2DFmode, VNx2DImode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1667 */
rtx
gen_vcondvnx4sivnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1676 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx4SImode, VNx4SFmode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1667 */
rtx
gen_vcondvnx2divnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1676 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx2DImode, VNx2DFmode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1667 */
rtx
gen_vcondvnx4sfvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1676 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx4SFmode, VNx4SFmode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx4SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1667 */
rtx
gen_vcondvnx2dfvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1676 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vcond (VNx2DFmode, VNx2DFmode, operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (VNx2DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1685 */
rtx
gen_vec_cmpvnx16qivnx16bi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1693 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_cmp_int (operands[0], GET_CODE (operands[1]),
				    operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VNx16BImode,
		operand2,
		operand3)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1685 */
rtx
gen_vec_cmpvnx8hivnx8bi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1693 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_cmp_int (operands[0], GET_CODE (operands[1]),
				    operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VNx8BImode,
		operand2,
		operand3)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1685 */
rtx
gen_vec_cmpvnx4sivnx4bi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1693 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_cmp_int (operands[0], GET_CODE (operands[1]),
				    operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VNx4BImode,
		operand2,
		operand3)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1685 */
rtx
gen_vec_cmpvnx2divnx2bi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1693 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_cmp_int (operands[0], GET_CODE (operands[1]),
				    operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VNx2BImode,
		operand2,
		operand3)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1703 */
rtx
gen_vec_cmpuvnx16qivnx16bi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1711 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_cmp_int (operands[0], GET_CODE (operands[1]),
				    operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VNx16BImode,
		operand2,
		operand3)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1703 */
rtx
gen_vec_cmpuvnx8hivnx8bi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1711 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_cmp_int (operands[0], GET_CODE (operands[1]),
				    operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VNx8BImode,
		operand2,
		operand3)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1703 */
rtx
gen_vec_cmpuvnx4sivnx4bi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1711 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_cmp_int (operands[0], GET_CODE (operands[1]),
				    operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VNx4BImode,
		operand2,
		operand3)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1703 */
rtx
gen_vec_cmpuvnx2divnx2bi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1711 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_cmp_int (operands[0], GET_CODE (operands[1]),
				    operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VNx2BImode,
		operand2,
		operand3)),
		gen_hard_reg_clobber (CCmode, 66))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1721 */
rtx
gen_vec_cmpvnx8hfvnx8bi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1727 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_cmp_float (operands[0], GET_CODE (operands[1]),
				      operands[2], operands[3], false);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VNx8BImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1721 */
rtx
gen_vec_cmpvnx4sfvnx4bi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1727 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_cmp_float (operands[0], GET_CODE (operands[1]),
				      operands[2], operands[3], false);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VNx4BImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1721 */
rtx
gen_vec_cmpvnx2dfvnx2bi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1727 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    aarch64_expand_sve_vec_cmp_float (operands[0], GET_CODE (operands[1]),
				      operands[2], operands[3], false);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VNx2BImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1735 */
rtx
gen_cbranchvnx16bi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1744 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx ptrue = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
    rtx pred;
    if (operands[2] == CONST0_RTX (VNx16BImode))
      pred = operands[1];
    else
      {
	pred = gen_reg_rtx (VNx16BImode);
	emit_insn (gen_pred_xorvnx16bi3 (pred, ptrue, operands[1],
					operands[2]));
      }
    emit_insn (gen_ptest_ptruevnx16bi (ptrue, pred));
    operands[1] = gen_rtx_REG (CCmode, CC_REGNUM);
    operands[2] = const0_rtx;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1735 */
rtx
gen_cbranchvnx8bi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1744 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx ptrue = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
    rtx pred;
    if (operands[2] == CONST0_RTX (VNx8BImode))
      pred = operands[1];
    else
      {
	pred = gen_reg_rtx (VNx8BImode);
	emit_insn (gen_pred_xorvnx8bi3 (pred, ptrue, operands[1],
					operands[2]));
      }
    emit_insn (gen_ptest_ptruevnx8bi (ptrue, pred));
    operands[1] = gen_rtx_REG (CCmode, CC_REGNUM);
    operands[2] = const0_rtx;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1735 */
rtx
gen_cbranchvnx4bi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1744 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx ptrue = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
    rtx pred;
    if (operands[2] == CONST0_RTX (VNx4BImode))
      pred = operands[1];
    else
      {
	pred = gen_reg_rtx (VNx4BImode);
	emit_insn (gen_pred_xorvnx4bi3 (pred, ptrue, operands[1],
					operands[2]));
      }
    emit_insn (gen_ptest_ptruevnx4bi (ptrue, pred));
    operands[1] = gen_rtx_REG (CCmode, CC_REGNUM);
    operands[2] = const0_rtx;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1735 */
rtx
gen_cbranchvnx2bi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1744 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx ptrue = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
    rtx pred;
    if (operands[2] == CONST0_RTX (VNx2BImode))
      pred = operands[1];
    else
      {
	pred = gen_reg_rtx (VNx2BImode);
	emit_insn (gen_pred_xorvnx2bi3 (pred, ptrue, operands[1],
					operands[2]));
      }
    emit_insn (gen_ptest_ptruevnx2bi (ptrue, pred));
    operands[1] = gen_rtx_REG (CCmode, CC_REGNUM);
    operands[2] = const0_rtx;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_smaxvnx16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMAX (VNx16QImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_sminvnx16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMIN (VNx16QImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_umaxvnx16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UMAX (VNx16QImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_uminvnx16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UMIN (VNx16QImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_smaxvnx8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMAX (VNx8HImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_sminvnx8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMIN (VNx8HImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_umaxvnx8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UMAX (VNx8HImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_uminvnx8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UMIN (VNx8HImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_smaxvnx4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMAX (VNx4SImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_sminvnx4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMIN (VNx4SImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_umaxvnx4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UMAX (VNx4SImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_uminvnx4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UMIN (VNx4SImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_smaxvnx2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMAX (VNx2DImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_sminvnx2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMIN (VNx2DImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_umaxvnx2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UMAX (VNx2DImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1762 */
rtx
gen_uminvnx2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1770 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UMIN (VNx2DImode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1791 */
rtx
gen_smaxvnx8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1799 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMAX (VNx8HFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1791 */
rtx
gen_sminvnx8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1799 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMIN (VNx8HFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1791 */
rtx
gen_smaxvnx4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1799 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMAX (VNx4SFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1791 */
rtx
gen_sminvnx4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1799 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMIN (VNx4SFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1791 */
rtx
gen_smaxvnx2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1799 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMAX (VNx2DFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1791 */
rtx
gen_sminvnx2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1799 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_SMIN (VNx2DFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1820 */
rtx
gen_smax_nanvnx8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1829 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	109)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1820 */
rtx
gen_smin_nanvnx8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1829 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	112)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1820 */
rtx
gen_fmaxvnx8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"fmaxvnx8hf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1829 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	207)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1820 */
rtx
gen_fminvnx8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"fminvnx8hf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1829 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	208)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1820 */
rtx
gen_smax_nanvnx4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1829 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	109)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1820 */
rtx
gen_smin_nanvnx4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1829 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	112)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1820 */
rtx
gen_fmaxvnx4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"fmaxvnx4sf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1829 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	207)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1820 */
rtx
gen_fminvnx4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"fminvnx4sf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1829 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	208)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1820 */
rtx
gen_smax_nanvnx2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1829 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	109)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1820 */
rtx
gen_smin_nanvnx2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1829 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	112)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1820 */
rtx
gen_fmaxvnx2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"fmaxvnx2df3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1829 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	207)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1820 */
rtx
gen_fminvnx2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"fminvnx2df3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1829 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	208)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_addvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_PLUS (VNx16QImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_subvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_MINUS (VNx16QImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_mulvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_MULT (VNx16QImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_smaxvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_SMAX (VNx16QImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_umaxvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UMAX (VNx16QImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_sminvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_SMIN (VNx16QImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_uminvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UMIN (VNx16QImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_andvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_AND (VNx16QImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_iorvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_IOR (VNx16QImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_xorvnx16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_XOR (VNx16QImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_addvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_PLUS (VNx8HImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_subvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_MINUS (VNx8HImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_mulvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_MULT (VNx8HImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_smaxvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_SMAX (VNx8HImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_umaxvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UMAX (VNx8HImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_sminvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_SMIN (VNx8HImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_uminvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UMIN (VNx8HImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_andvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_AND (VNx8HImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_iorvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_IOR (VNx8HImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_xorvnx8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_XOR (VNx8HImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_addvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_PLUS (VNx4SImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_subvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_MINUS (VNx4SImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_mulvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_MULT (VNx4SImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_smaxvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_SMAX (VNx4SImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_umaxvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UMAX (VNx4SImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_sminvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_SMIN (VNx4SImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_uminvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UMIN (VNx4SImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_andvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_AND (VNx4SImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_iorvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_IOR (VNx4SImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_xorvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_XOR (VNx4SImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_addvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_PLUS (VNx2DImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_subvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_MINUS (VNx2DImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_mulvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_MULT (VNx2DImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_smaxvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_SMAX (VNx2DImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_umaxvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UMAX (VNx2DImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_sminvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_SMIN (VNx2DImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_uminvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UMIN (VNx2DImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_andvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_AND (VNx2DImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_iorvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_IOR (VNx2DImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1851 */
rtx
gen_cond_xorvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_XOR (VNx2DImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1863 */
rtx
gen_cond_divvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_DIV (VNx4SImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1863 */
rtx
gen_cond_udivvnx4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UDIV (VNx4SImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1863 */
rtx
gen_cond_divvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_DIV (VNx2DImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:1863 */
rtx
gen_cond_udivvnx2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UDIV (VNx2DImode,
	operand2,
	operand3),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2032 */
extern rtx_insn *gen_split_331 (rtx_insn *, rtx *);
rtx_insn *
gen_split_331 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_331\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx16QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_fmt_ee (GET_CODE (operand5), GET_MODE (operand5),
		copy_rtx (operand0),
		operand3),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2032 */
extern rtx_insn *gen_split_332 (rtx_insn *, rtx *);
rtx_insn *
gen_split_332 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_332\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_fmt_ee (GET_CODE (operand5), GET_MODE (operand5),
		copy_rtx (operand0),
		operand3),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2032 */
extern rtx_insn *gen_split_333 (rtx_insn *, rtx *);
rtx_insn *
gen_split_333 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_333\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_fmt_ee (GET_CODE (operand5), GET_MODE (operand5),
		copy_rtx (operand0),
		operand3),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2032 */
extern rtx_insn *gen_split_334 (rtx_insn *, rtx *);
rtx_insn *
gen_split_334 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_334\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_fmt_ee (GET_CODE (operand5), GET_MODE (operand5),
		copy_rtx (operand0),
		operand3),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2073 */
rtx
gen_reduc_plus_scal_vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_vnx16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2079 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	116)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2073 */
rtx
gen_reduc_plus_scal_vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_vnx8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2079 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	116)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2073 */
rtx
gen_reduc_plus_scal_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_vnx4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2079 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	116)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2073 */
rtx
gen_reduc_plus_scal_vnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_vnx2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2079 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	116)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2095 */
rtx
gen_reduc_plus_scal_vnx8hf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_vnx8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2101 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	115)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2095 */
rtx
gen_reduc_plus_scal_vnx4sf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_vnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2101 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	115)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2095 */
rtx
gen_reduc_plus_scal_vnx2df (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_plus_scal_vnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2101 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	115)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_umax_scal_vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	119)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_umin_scal_vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	120)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_smax_scal_vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	117)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_smin_scal_vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	118)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_umax_scal_vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	119)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_umin_scal_vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	120)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_smax_scal_vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	117)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_smin_scal_vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	118)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_umax_scal_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	119)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_umin_scal_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	120)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_smax_scal_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	117)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_smin_scal_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	118)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_umax_scal_vnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	119)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_umin_scal_vnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	120)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_smax_scal_vnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	117)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2117 */
rtx
gen_reduc_smin_scal_vnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2123 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	118)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2139 */
rtx
gen_reduc_smax_nan_scal_vnx8hf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2145 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	111)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2139 */
rtx
gen_reduc_smin_nan_scal_vnx8hf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2145 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	114)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2139 */
rtx
gen_reduc_smax_scal_vnx8hf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2145 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	110)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2139 */
rtx
gen_reduc_smin_scal_vnx8hf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2145 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	113)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2139 */
rtx
gen_reduc_smax_nan_scal_vnx4sf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2145 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	111)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2139 */
rtx
gen_reduc_smin_nan_scal_vnx4sf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2145 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	114)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2139 */
rtx
gen_reduc_smax_scal_vnx4sf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2145 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	110)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2139 */
rtx
gen_reduc_smin_scal_vnx4sf (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2145 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	113)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2139 */
rtx
gen_reduc_smax_nan_scal_vnx2df (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2145 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	111)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2139 */
rtx
gen_reduc_smin_nan_scal_vnx2df (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2145 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	114)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2139 */
rtx
gen_reduc_smax_scal_vnx2df (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2145 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	110)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2139 */
rtx
gen_reduc_smin_scal_vnx2df (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2145 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand2,
		operand1),
	113)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2160 */
rtx
gen_reduc_and_scal_vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_and_scal_vnx16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2166 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	229)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2160 */
rtx
gen_reduc_ior_scal_vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_ior_scal_vnx16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2166 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	230)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2160 */
rtx
gen_reduc_xor_scal_vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_xor_scal_vnx16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2166 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx16BImode, CONSTM1_RTX (VNx16BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand2,
		operand1),
	231)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2160 */
rtx
gen_reduc_and_scal_vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_and_scal_vnx8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2166 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	229)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2160 */
rtx
gen_reduc_ior_scal_vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_ior_scal_vnx8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2166 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	230)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2160 */
rtx
gen_reduc_xor_scal_vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_xor_scal_vnx8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2166 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand2,
		operand1),
	231)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2160 */
rtx
gen_reduc_and_scal_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_and_scal_vnx4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2166 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	229)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2160 */
rtx
gen_reduc_ior_scal_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_ior_scal_vnx4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2166 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	230)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2160 */
rtx
gen_reduc_xor_scal_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_xor_scal_vnx4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2166 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand2,
		operand1),
	231)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2160 */
rtx
gen_reduc_and_scal_vnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_and_scal_vnx2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2166 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	229)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2160 */
rtx
gen_reduc_ior_scal_vnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_ior_scal_vnx2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2166 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	230)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2160 */
rtx
gen_reduc_xor_scal_vnx2di (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"reduc_xor_scal_vnx2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2166 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand2,
		operand1),
	231)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2181 */
rtx
gen_fold_left_plus_vnx8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"fold_left_plus_vnx8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2188 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (3,
		operand3,
		operand1,
		operand2),
	102)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2181 */
rtx
gen_fold_left_plus_vnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"fold_left_plus_vnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2188 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (3,
		operand3,
		operand1,
		operand2),
	102)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2181 */
rtx
gen_fold_left_plus_vnx2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"fold_left_plus_vnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2188 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (3,
		operand3,
		operand1,
		operand2),
	102)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2220 */
rtx
gen_addvnx8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2229 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_PLUS (VNx8HFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2220 */
rtx
gen_addvnx4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2229 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_PLUS (VNx4SFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2220 */
rtx
gen_addvnx2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2229 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_PLUS (VNx2DFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2235 */
extern rtx_insn *gen_split_335 (rtx_insn *, rtx *);
rtx_insn *
gen_split_335 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_335\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (VNx8HFmode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2235 */
extern rtx_insn *gen_split_336 (rtx_insn *, rtx *);
rtx_insn *
gen_split_336 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_336\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (VNx4SFmode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2235 */
extern rtx_insn *gen_split_337 (rtx_insn *, rtx *);
rtx_insn *
gen_split_337 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_337\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (VNx2DFmode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2256 */
rtx
gen_subvnx8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2265 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_MINUS (VNx8HFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2256 */
rtx
gen_subvnx4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2265 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_MINUS (VNx4SFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2256 */
rtx
gen_subvnx2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2265 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_MINUS (VNx2DFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2271 */
extern rtx_insn *gen_split_338 (rtx_insn *, rtx *);
rtx_insn *
gen_split_338 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_338\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MINUS (VNx8HFmode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2271 */
extern rtx_insn *gen_split_339 (rtx_insn *, rtx *);
rtx_insn *
gen_split_339 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_339\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MINUS (VNx4SFmode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2271 */
extern rtx_insn *gen_split_340 (rtx_insn *, rtx *);
rtx_insn *
gen_split_340 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_340\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MINUS (VNx2DFmode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2296 */
rtx
gen_mulvnx8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2305 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_MULT (VNx8HFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2296 */
rtx
gen_mulvnx4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2305 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_MULT (VNx4SFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2296 */
rtx
gen_mulvnx2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2305 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_MULT (VNx2DFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2311 */
extern rtx_insn *gen_split_341 (rtx_insn *, rtx *);
rtx_insn *
gen_split_341 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_341\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (VNx8HFmode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2311 */
extern rtx_insn *gen_split_342 (rtx_insn *, rtx *);
rtx_insn *
gen_split_342 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_342\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (VNx4SFmode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2311 */
extern rtx_insn *gen_split_343 (rtx_insn *, rtx *);
rtx_insn *
gen_split_343 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_343\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (VNx2DFmode,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2342 */
rtx
gen_fmavnx8hf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL _Pragma ("GCC error \"fmavnx8hf4 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2351 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[4] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand4,
		gen_rtx_FMA (VNx8HFmode,
	operand1,
	operand2,
	operand3)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2342 */
rtx
gen_fmavnx4sf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL _Pragma ("GCC error \"fmavnx4sf4 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2351 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[4] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand4,
		gen_rtx_FMA (VNx4SFmode,
	operand1,
	operand2,
	operand3)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2342 */
rtx
gen_fmavnx2df4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL _Pragma ("GCC error \"fmavnx2df4 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2351 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[4] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand4,
		gen_rtx_FMA (VNx2DFmode,
	operand1,
	operand2,
	operand3)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2374 */
rtx
gen_fnmavnx8hf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL _Pragma ("GCC error \"fnmavnx8hf4 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2384 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[4] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand4,
		gen_rtx_FMA (VNx8HFmode,
	gen_rtx_NEG (VNx8HFmode,
	operand1),
	operand2,
	operand3)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2374 */
rtx
gen_fnmavnx4sf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL _Pragma ("GCC error \"fnmavnx4sf4 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2384 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[4] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand4,
		gen_rtx_FMA (VNx4SFmode,
	gen_rtx_NEG (VNx4SFmode,
	operand1),
	operand2,
	operand3)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2374 */
rtx
gen_fnmavnx2df4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL _Pragma ("GCC error \"fnmavnx2df4 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2384 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[4] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand4,
		gen_rtx_FMA (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	operand1),
	operand2,
	operand3)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2408 */
rtx
gen_fmsvnx8hf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL _Pragma ("GCC error \"fmsvnx8hf4 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2418 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[4] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand4,
		gen_rtx_FMA (VNx8HFmode,
	operand1,
	operand2,
	gen_rtx_NEG (VNx8HFmode,
	operand3))),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2408 */
rtx
gen_fmsvnx4sf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL _Pragma ("GCC error \"fmsvnx4sf4 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2418 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[4] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand4,
		gen_rtx_FMA (VNx4SFmode,
	operand1,
	operand2,
	gen_rtx_NEG (VNx4SFmode,
	operand3))),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2408 */
rtx
gen_fmsvnx2df4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL _Pragma ("GCC error \"fmsvnx2df4 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2418 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[4] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand4,
		gen_rtx_FMA (VNx2DFmode,
	operand1,
	operand2,
	gen_rtx_NEG (VNx2DFmode,
	operand3))),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2442 */
rtx
gen_fnmsvnx8hf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL _Pragma ("GCC error \"fnmsvnx8hf4 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2453 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[4] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand4,
		gen_rtx_FMA (VNx8HFmode,
	gen_rtx_NEG (VNx8HFmode,
	operand1),
	operand2,
	gen_rtx_NEG (VNx8HFmode,
	operand3))),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2442 */
rtx
gen_fnmsvnx4sf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL _Pragma ("GCC error \"fnmsvnx4sf4 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2453 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[4] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand4,
		gen_rtx_FMA (VNx4SFmode,
	gen_rtx_NEG (VNx4SFmode,
	operand1),
	operand2,
	gen_rtx_NEG (VNx4SFmode,
	operand3))),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2442 */
rtx
gen_fnmsvnx2df4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx operand4;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL _Pragma ("GCC error \"fnmsvnx2df4 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2453 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[4] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand4,
		gen_rtx_FMA (VNx2DFmode,
	gen_rtx_NEG (VNx2DFmode,
	operand1),
	operand2,
	gen_rtx_NEG (VNx2DFmode,
	operand3))),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2478 */
rtx
gen_divvnx8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2486 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_DIV (VNx8HFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2478 */
rtx
gen_divvnx4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2486 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_DIV (VNx4SFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2478 */
rtx
gen_divvnx2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2486 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_DIV (VNx2DFmode,
	operand1,
	operand2)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2508 */
rtx
gen_absvnx8hf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2515 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_ABS (VNx8HFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2508 */
rtx
gen_negvnx8hf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2515 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_NEG (VNx8HFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2508 */
rtx
gen_sqrtvnx8hf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtvnx8hf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2515 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_SQRT (VNx8HFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2508 */
rtx
gen_absvnx4sf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2515 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_ABS (VNx4SFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2508 */
rtx
gen_negvnx4sf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2515 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_NEG (VNx4SFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2508 */
rtx
gen_sqrtvnx4sf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtvnx4sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2515 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_SQRT (VNx4SFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2508 */
rtx
gen_absvnx2df2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2515 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_ABS (VNx2DFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2508 */
rtx
gen_negvnx2df2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2515 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_NEG (VNx2DFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2508 */
rtx
gen_sqrtvnx2df2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtvnx2df2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2515 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_SQRT (VNx2DFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_btruncvnx8hf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"btruncvnx8hf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (1,
		operand1),
	23)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_ceilvnx8hf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"ceilvnx8hf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (1,
		operand1),
	21)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_floorvnx8hf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"floorvnx8hf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (1,
		operand1),
	19)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_frintnvnx8hf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (1,
		operand1),
	20)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_nearbyintvnx8hf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"nearbyintvnx8hf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (1,
		operand1),
	18)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_rintvnx8hf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"rintvnx8hf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (1,
		operand1),
	22)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_roundvnx8hf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"roundvnx8hf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (1,
		operand1),
	17)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_btruncvnx4sf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"btruncvnx4sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand1),
	23)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_ceilvnx4sf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"ceilvnx4sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand1),
	21)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_floorvnx4sf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"floorvnx4sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand1),
	19)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_frintnvnx4sf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand1),
	20)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_nearbyintvnx4sf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"nearbyintvnx4sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand1),
	18)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_rintvnx4sf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"rintvnx4sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand1),
	22)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_roundvnx4sf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"roundvnx4sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand1),
	17)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_btruncvnx2df2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"btruncvnx2df2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (1,
		operand1),
	23)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_ceilvnx2df2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"ceilvnx2df2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (1,
		operand1),
	21)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_floorvnx2df2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"floorvnx2df2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (1,
		operand1),
	19)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_frintnvnx2df2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (1,
		operand1),
	20)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_nearbyintvnx2df2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"nearbyintvnx2df2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (1,
		operand1),
	18)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_rintvnx2df2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"rintvnx2df2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (1,
		operand1),
	22)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2532 */
rtx
gen_roundvnx2df2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"roundvnx2df2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2540 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (1,
		operand1),
	17)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2559 */
rtx
gen_fix_truncvnx8hfvnx8hi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2567 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_FIX (VNx8HImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2559 */
rtx
gen_fixuns_truncvnx8hfvnx8hi2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2567 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSIGNED_FIX (VNx8HImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2559 */
rtx
gen_fix_truncvnx4sfvnx4si2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2567 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_FIX (VNx4SImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2559 */
rtx
gen_fixuns_truncvnx4sfvnx4si2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2567 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSIGNED_FIX (VNx4SImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2559 */
rtx
gen_fix_truncvnx2dfvnx2di2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2567 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_FIX (VNx2DImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2559 */
rtx
gen_fixuns_truncvnx2dfvnx2di2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2567 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSIGNED_FIX (VNx2DImode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2610 */
rtx
gen_floatvnx8hivnx8hf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2618 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_FLOAT (VNx8HFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2610 */
rtx
gen_floatunsvnx8hivnx8hf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2618 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx8BImode, CONSTM1_RTX (VNx8BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSIGNED_FLOAT (VNx8HFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2610 */
rtx
gen_floatvnx4sivnx4sf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2618 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_FLOAT (VNx4SFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2610 */
rtx
gen_floatunsvnx4sivnx4sf2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2618 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSIGNED_FLOAT (VNx4SFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2610 */
rtx
gen_floatvnx2divnx2df2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2618 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_FLOAT (VNx2DFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2610 */
rtx
gen_floatunsvnx2divnx2df2 (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2618 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[2] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		gen_rtx_UNSIGNED_FLOAT (VNx2DFmode,
	operand1)),
	89)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2691 */
rtx
gen_vec_unpacks_hi_vnx16bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2696 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_punpkhi_vnx16bi
		: gen_aarch64_sve_punpklo_vnx16bi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (1,
		operand1),
	91));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2691 */
rtx
gen_vec_unpacku_hi_vnx16bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2696 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_punpkhi_vnx16bi
		: gen_aarch64_sve_punpklo_vnx16bi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (1,
		operand1),
	92));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2691 */
rtx
gen_vec_unpacks_lo_vnx16bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2696 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_punpkhi_vnx16bi
		: gen_aarch64_sve_punpklo_vnx16bi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (1,
		operand1),
	93));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2691 */
rtx
gen_vec_unpacku_lo_vnx16bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2696 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_punpkhi_vnx16bi
		: gen_aarch64_sve_punpklo_vnx16bi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx8BImode,
	gen_rtvec (1,
		operand1),
	94));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2691 */
rtx
gen_vec_unpacks_hi_vnx8bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2696 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_punpkhi_vnx8bi
		: gen_aarch64_sve_punpklo_vnx8bi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (1,
		operand1),
	91));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2691 */
rtx
gen_vec_unpacku_hi_vnx8bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2696 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_punpkhi_vnx8bi
		: gen_aarch64_sve_punpklo_vnx8bi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (1,
		operand1),
	92));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2691 */
rtx
gen_vec_unpacks_lo_vnx8bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2696 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_punpkhi_vnx8bi
		: gen_aarch64_sve_punpklo_vnx8bi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (1,
		operand1),
	93));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2691 */
rtx
gen_vec_unpacku_lo_vnx8bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2696 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_punpkhi_vnx8bi
		: gen_aarch64_sve_punpklo_vnx8bi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx4BImode,
	gen_rtvec (1,
		operand1),
	94));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2691 */
rtx
gen_vec_unpacks_hi_vnx4bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2696 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_punpkhi_vnx4bi
		: gen_aarch64_sve_punpklo_vnx4bi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (1,
		operand1),
	91));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2691 */
rtx
gen_vec_unpacku_hi_vnx4bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2696 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_punpkhi_vnx4bi
		: gen_aarch64_sve_punpklo_vnx4bi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (1,
		operand1),
	92));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2691 */
rtx
gen_vec_unpacks_lo_vnx4bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2696 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_punpkhi_vnx4bi
		: gen_aarch64_sve_punpklo_vnx4bi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (1,
		operand1),
	93));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2691 */
rtx
gen_vec_unpacku_lo_vnx4bi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2696 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_punpkhi_vnx4bi
		: gen_aarch64_sve_punpklo_vnx4bi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx2BImode,
	gen_rtvec (1,
		operand1),
	94));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2717 */
rtx
gen_vec_unpacks_hi_vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2721 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_sunpkhi_vnx16qi
		: gen_aarch64_sve_sunpklo_vnx16qi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (1,
		operand1),
	91));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2717 */
rtx
gen_vec_unpacku_hi_vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2721 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_uunpkhi_vnx16qi
		: gen_aarch64_sve_uunpklo_vnx16qi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (1,
		operand1),
	92));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2717 */
rtx
gen_vec_unpacks_lo_vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2721 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_sunpkhi_vnx16qi
		: gen_aarch64_sve_sunpklo_vnx16qi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (1,
		operand1),
	93));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2717 */
rtx
gen_vec_unpacku_lo_vnx16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2721 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_uunpkhi_vnx16qi
		: gen_aarch64_sve_uunpklo_vnx16qi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx8HImode,
	gen_rtvec (1,
		operand1),
	94));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2717 */
rtx
gen_vec_unpacks_hi_vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2721 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_sunpkhi_vnx8hi
		: gen_aarch64_sve_sunpklo_vnx8hi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand1),
	91));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2717 */
rtx
gen_vec_unpacku_hi_vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2721 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_uunpkhi_vnx8hi
		: gen_aarch64_sve_uunpklo_vnx8hi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand1),
	92));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2717 */
rtx
gen_vec_unpacks_lo_vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2721 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_sunpkhi_vnx8hi
		: gen_aarch64_sve_sunpklo_vnx8hi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand1),
	93));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2717 */
rtx
gen_vec_unpacku_lo_vnx8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2721 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_uunpkhi_vnx8hi
		: gen_aarch64_sve_uunpklo_vnx8hi)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (1,
		operand1),
	94));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2717 */
rtx
gen_vec_unpacks_hi_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2721 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_sunpkhi_vnx4si
		: gen_aarch64_sve_sunpklo_vnx4si)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand1),
	91));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2717 */
rtx
gen_vec_unpacku_hi_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2721 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_uunpkhi_vnx4si
		: gen_aarch64_sve_uunpklo_vnx4si)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand1),
	92));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2717 */
rtx
gen_vec_unpacks_lo_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2721 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_sunpkhi_vnx4si
		: gen_aarch64_sve_sunpklo_vnx4si)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand1),
	93));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2717 */
rtx
gen_vec_unpacku_lo_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2721 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_uunpkhi_vnx4si
		: gen_aarch64_sve_uunpklo_vnx4si)
	       (operands[0], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand1),
	94));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2742 */
rtx
gen_vec_unpacks_lo_vnx8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2747 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use ZIP to do the unpack, since we don't care about the upper halves
       and since it has the nice property of not needing any subregs.
       If using UUNPK* turns out to be preferable, we could model it as
       a ZIP whose first operand is zero.  */
    rtx temp = gen_reg_rtx (VNx8HFmode);
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_zip2vnx8hf
		: gen_aarch64_sve_zip1vnx8hf)
		(temp, operands[1], operands[1]));
    rtx ptrue = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
    emit_insn (gen_aarch64_sve_extendvnx8hfvnx4sf2 (operands[0],
						     ptrue, temp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (1,
		operand1),
	94));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2742 */
rtx
gen_vec_unpacks_hi_vnx8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2747 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use ZIP to do the unpack, since we don't care about the upper halves
       and since it has the nice property of not needing any subregs.
       If using UUNPK* turns out to be preferable, we could model it as
       a ZIP whose first operand is zero.  */
    rtx temp = gen_reg_rtx (VNx8HFmode);
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_zip2vnx8hf
		: gen_aarch64_sve_zip1vnx8hf)
		(temp, operands[1], operands[1]));
    rtx ptrue = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
    emit_insn (gen_aarch64_sve_extendvnx8hfvnx4sf2 (operands[0],
						     ptrue, temp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (1,
		operand1),
	92));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2742 */
rtx
gen_vec_unpacks_lo_vnx4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2747 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use ZIP to do the unpack, since we don't care about the upper halves
       and since it has the nice property of not needing any subregs.
       If using UUNPK* turns out to be preferable, we could model it as
       a ZIP whose first operand is zero.  */
    rtx temp = gen_reg_rtx (VNx4SFmode);
    emit_insn ((BYTES_BIG_ENDIAN
		? gen_aarch64_sve_zip2vnx4sf
		: gen_aarch64_sve_zip1vnx4sf)
		(temp, operands[1], operands[1]));
    rtx ptrue = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
    emit_insn (gen_aarch64_sve_extendvnx4sfvnx2df2 (operands[0],
						     ptrue, temp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand1),
	94));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2742 */
rtx
gen_vec_unpacks_hi_vnx4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2747 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use ZIP to do the unpack, since we don't care about the upper halves
       and since it has the nice property of not needing any subregs.
       If using UUNPK* turns out to be preferable, we could model it as
       a ZIP whose first operand is zero.  */
    rtx temp = gen_reg_rtx (VNx4SFmode);
    emit_insn ((!BYTES_BIG_ENDIAN
		? gen_aarch64_sve_zip2vnx4sf
		: gen_aarch64_sve_zip1vnx4sf)
		(temp, operands[1], operands[1]));
    rtx ptrue = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
    emit_insn (gen_aarch64_sve_extendvnx4sfvnx2df2 (operands[0],
						     ptrue, temp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand1),
	92));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2767 */
rtx
gen_vec_unpacks_float_lo_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2773 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use ZIP to do the unpack, since we don't care about the upper halves
       and since it has the nice property of not needing any subregs.
       If using UUNPK* turns out to be preferable, we could model it as
       a ZIP whose first operand is zero.  */
    rtx temp = gen_reg_rtx (VNx4SImode);
    emit_insn ((BYTES_BIG_ENDIAN
	        ? gen_aarch64_sve_zip2vnx4si
	        : gen_aarch64_sve_zip1vnx4si)
	       (temp, operands[1], operands[1]));
    rtx ptrue = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
    emit_insn (gen_aarch64_sve_floatvnx4sivnx2df2 (operands[0],
							       ptrue, temp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_FLOAT (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand1),
	94)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2767 */
rtx
gen_vec_unpacks_float_hi_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2773 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use ZIP to do the unpack, since we don't care about the upper halves
       and since it has the nice property of not needing any subregs.
       If using UUNPK* turns out to be preferable, we could model it as
       a ZIP whose first operand is zero.  */
    rtx temp = gen_reg_rtx (VNx4SImode);
    emit_insn ((!BYTES_BIG_ENDIAN
	        ? gen_aarch64_sve_zip2vnx4si
	        : gen_aarch64_sve_zip1vnx4si)
	       (temp, operands[1], operands[1]));
    rtx ptrue = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
    emit_insn (gen_aarch64_sve_floatvnx4sivnx2df2 (operands[0],
							       ptrue, temp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_FLOAT (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand1),
	92)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2767 */
rtx
gen_vec_unpacku_float_lo_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2773 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use ZIP to do the unpack, since we don't care about the upper halves
       and since it has the nice property of not needing any subregs.
       If using UUNPK* turns out to be preferable, we could model it as
       a ZIP whose first operand is zero.  */
    rtx temp = gen_reg_rtx (VNx4SImode);
    emit_insn ((BYTES_BIG_ENDIAN
	        ? gen_aarch64_sve_zip2vnx4si
	        : gen_aarch64_sve_zip1vnx4si)
	       (temp, operands[1], operands[1]));
    rtx ptrue = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
    emit_insn (gen_aarch64_sve_floatunsvnx4sivnx2df2 (operands[0],
							       ptrue, temp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSIGNED_FLOAT (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand1),
	94)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2767 */
rtx
gen_vec_unpacku_float_hi_vnx4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2773 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    /* Use ZIP to do the unpack, since we don't care about the upper halves
       and since it has the nice property of not needing any subregs.
       If using UUNPK* turns out to be preferable, we could model it as
       a ZIP whose first operand is zero.  */
    rtx temp = gen_reg_rtx (VNx4SImode);
    emit_insn ((!BYTES_BIG_ENDIAN
	        ? gen_aarch64_sve_zip2vnx4si
	        : gen_aarch64_sve_zip1vnx4si)
	       (temp, operands[1], operands[1]));
    rtx ptrue = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
    emit_insn (gen_aarch64_sve_floatunsvnx4sivnx2df2 (operands[0],
							       ptrue, temp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSIGNED_FLOAT (VNx2DFmode,
	gen_rtx_UNSPEC (VNx2DImode,
	gen_rtvec (1,
		operand1),
	92)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2816 */
rtx
gen_vec_pack_trunc_vnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2832 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx4BImode, CONSTM1_RTX (VNx4BImode));
    operands[4] = gen_reg_rtx (VNx8HFmode);
    operands[5] = gen_reg_rtx (VNx8HFmode);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (1,
		operand1),
	96)),
	89)));
  emit_insn (gen_rtx_SET (operand5,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		copy_rtx (operand3),
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (1,
		operand2),
	96)),
	89)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		copy_rtx (operand4),
		copy_rtx (operand5)),
	179)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2816 */
rtx
gen_vec_pack_trunc_vnx2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2832 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
    operands[4] = gen_reg_rtx (VNx4SFmode);
    operands[5] = gen_reg_rtx (VNx4SFmode);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand1),
	96)),
	89)));
  emit_insn (gen_rtx_SET (operand5,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		copy_rtx (operand3),
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (1,
		operand2),
	96)),
	89)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		copy_rtx (operand4),
		copy_rtx (operand5)),
	179)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2840 */
rtx
gen_vec_pack_sfix_trunc_vnx2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2854 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
    operands[4] = gen_reg_rtx (VNx4SImode);
    operands[5] = gen_reg_rtx (VNx4SImode);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_FIX (VNx4SImode,
	operand1)),
	89)));
  emit_insn (gen_rtx_SET (operand5,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		copy_rtx (operand3),
		gen_rtx_FIX (VNx4SImode,
	operand2)),
	89)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		copy_rtx (operand4),
		copy_rtx (operand5)),
	179)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2840 */
rtx
gen_vec_pack_ufix_trunc_vnx2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2854 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    operands[3] = force_reg (VNx2BImode, CONSTM1_RTX (VNx2BImode));
    operands[4] = gen_reg_rtx (VNx4SImode);
    operands[5] = gen_reg_rtx (VNx4SImode);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand4,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		operand3,
		gen_rtx_UNSIGNED_FIX (VNx4SImode,
	operand1)),
	89)));
  emit_insn (gen_rtx_SET (operand5,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		copy_rtx (operand3),
		gen_rtx_UNSIGNED_FIX (VNx4SImode,
	operand2)),
	89)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SImode,
	gen_rtvec (2,
		copy_rtx (operand4),
		copy_rtx (operand5)),
	179)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_addvnx8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	237),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_subvnx8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	238),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_mulvnx8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	239),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_divvnx8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	240),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_smaxvnx8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	241),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_sminvnx8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	242),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_addvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	237),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_subvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	238),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_mulvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	239),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_divvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	240),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_smaxvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	241),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_sminvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	242),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_addvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	237),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_subvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	238),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_mulvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	239),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_divvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	240),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_smaxvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	241),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2862 */
rtx
gen_cond_sminvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		operand2,
		operand3),
	242),
		operand4),
	228));
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_344 (rtx_insn *, rtx *);
rtx_insn *
gen_split_344 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_344\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	237),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_345 (rtx_insn *, rtx *);
rtx_insn *
gen_split_345 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_345\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	238),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_346 (rtx_insn *, rtx *);
rtx_insn *
gen_split_346 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_346\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	239),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_347 (rtx_insn *, rtx *);
rtx_insn *
gen_split_347 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_347\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	240),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_348 (rtx_insn *, rtx *);
rtx_insn *
gen_split_348 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_348\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	241),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_349 (rtx_insn *, rtx *);
rtx_insn *
gen_split_349 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_349\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	242),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_350 (rtx_insn *, rtx *);
rtx_insn *
gen_split_350 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_350\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	237),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_351 (rtx_insn *, rtx *);
rtx_insn *
gen_split_351 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_351\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	238),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_352 (rtx_insn *, rtx *);
rtx_insn *
gen_split_352 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_352\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	239),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_353 (rtx_insn *, rtx *);
rtx_insn *
gen_split_353 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_353\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	240),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_354 (rtx_insn *, rtx *);
rtx_insn *
gen_split_354 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_354\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	241),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_355 (rtx_insn *, rtx *);
rtx_insn *
gen_split_355 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_355\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	242),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_356 (rtx_insn *, rtx *);
rtx_insn *
gen_split_356 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_356\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	237),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_357 (rtx_insn *, rtx *);
rtx_insn *
gen_split_357 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_357\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	238),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_358 (rtx_insn *, rtx *);
rtx_insn *
gen_split_358 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_358\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	239),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_359 (rtx_insn *, rtx *);
rtx_insn *
gen_split_359 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_359\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	240),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_360 (rtx_insn *, rtx *);
rtx_insn *
gen_split_360 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_360\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	241),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2947 */
extern rtx_insn *gen_split_361 (rtx_insn *, rtx *);
rtx_insn *
gen_split_361 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_361\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand4),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (2,
		copy_rtx (operand0),
		operand3),
	242),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2975 */
rtx
gen_cond_fmavnx8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL _Pragma ("GCC error \"cond_fmavnx8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2987 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	243),
		operand5),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2975 */
rtx
gen_cond_fnmavnx8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL _Pragma ("GCC error \"cond_fnmavnx8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2987 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	244),
		operand5),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2975 */
rtx
gen_cond_fnmsvnx8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL _Pragma ("GCC error \"cond_fnmsvnx8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2987 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	245),
		operand5),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2975 */
rtx
gen_cond_fmsvnx8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL _Pragma ("GCC error \"cond_fmsvnx8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2987 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	246),
		operand5),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2975 */
rtx
gen_cond_fmavnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL _Pragma ("GCC error \"cond_fmavnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2987 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	243),
		operand5),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2975 */
rtx
gen_cond_fnmavnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL _Pragma ("GCC error \"cond_fnmavnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2987 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	244),
		operand5),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2975 */
rtx
gen_cond_fnmsvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL _Pragma ("GCC error \"cond_fnmsvnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2987 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	245),
		operand5),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2975 */
rtx
gen_cond_fmsvnx4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL _Pragma ("GCC error \"cond_fmsvnx4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2987 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	246),
		operand5),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2975 */
rtx
gen_cond_fmavnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL _Pragma ("GCC error \"cond_fmavnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2987 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	243),
		operand5),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2975 */
rtx
gen_cond_fnmavnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL _Pragma ("GCC error \"cond_fnmavnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2987 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	244),
		operand5),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2975 */
rtx
gen_cond_fnmsvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL _Pragma ("GCC error \"cond_fnmsvnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2987 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	245),
		operand5),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:2975 */
rtx
gen_cond_fmsvnx2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL _Pragma ("GCC error \"cond_fmsvnx2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2987 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
  /* Swap the multiplication operands if the fallback value is the
     second of the two.  */
  if (rtx_equal_p (operands[3], operands[5]))
    std::swap (operands[2], operands[3]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		operand4),
	246),
		operand5),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3034 */
extern rtx_insn *gen_split_362 (rtx_insn *, rtx *);
rtx_insn *
gen_split_362 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_362\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3065 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		operand4,
		operand5),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		copy_rtx (operand0)),
	243),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3034 */
extern rtx_insn *gen_split_363 (rtx_insn *, rtx *);
rtx_insn *
gen_split_363 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_363\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3065 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		operand4,
		operand5),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		copy_rtx (operand0)),
	244),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3034 */
extern rtx_insn *gen_split_364 (rtx_insn *, rtx *);
rtx_insn *
gen_split_364 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_364\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3065 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		operand4,
		operand5),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		copy_rtx (operand0)),
	245),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3034 */
extern rtx_insn *gen_split_365 (rtx_insn *, rtx *);
rtx_insn *
gen_split_365 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_365\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3065 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand1,
		operand4,
		operand5),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx8HFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		copy_rtx (operand0)),
	246),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3034 */
extern rtx_insn *gen_split_366 (rtx_insn *, rtx *);
rtx_insn *
gen_split_366 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_366\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3065 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		operand4,
		operand5),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		copy_rtx (operand0)),
	243),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3034 */
extern rtx_insn *gen_split_367 (rtx_insn *, rtx *);
rtx_insn *
gen_split_367 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_367\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3065 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		operand4,
		operand5),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		copy_rtx (operand0)),
	244),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3034 */
extern rtx_insn *gen_split_368 (rtx_insn *, rtx *);
rtx_insn *
gen_split_368 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_368\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3065 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		operand4,
		operand5),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		copy_rtx (operand0)),
	245),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3034 */
extern rtx_insn *gen_split_369 (rtx_insn *, rtx *);
rtx_insn *
gen_split_369 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_369\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3065 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand1,
		operand4,
		operand5),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx4SFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		copy_rtx (operand0)),
	246),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3034 */
extern rtx_insn *gen_split_370 (rtx_insn *, rtx *);
rtx_insn *
gen_split_370 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_370\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3065 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		operand4,
		operand5),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		copy_rtx (operand0)),
	243),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3034 */
extern rtx_insn *gen_split_371 (rtx_insn *, rtx *);
rtx_insn *
gen_split_371 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_371\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3065 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		operand4,
		operand5),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		copy_rtx (operand0)),
	244),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3034 */
extern rtx_insn *gen_split_372 (rtx_insn *, rtx *);
rtx_insn *
gen_split_372 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_372\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3065 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		operand4,
		operand5),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		copy_rtx (operand0)),
	245),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3034 */
extern rtx_insn *gen_split_373 (rtx_insn *, rtx *);
rtx_insn *
gen_split_373 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_373\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3065 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand1,
		operand4,
		operand5),
	228)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		copy_rtx (operand1),
		gen_rtx_UNSPEC (VNx2DFmode,
	gen_rtvec (3,
		operand2,
		operand3,
		copy_rtx (operand0)),
	246),
		copy_rtx (operand0)),
	228)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3082 */
rtx
gen_copysignvnx8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"copysignvnx8hf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3087 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx sign = gen_reg_rtx (VNx8HImode);
    rtx mant = gen_reg_rtx (VNx8HImode);
    rtx int_res = gen_reg_rtx (VNx8HImode);
    int bits = GET_MODE_UNIT_BITSIZE (VNx8HFmode) - 1;

    rtx arg1 = lowpart_subreg (VNx8HImode, operands[1], VNx8HFmode);
    rtx arg2 = lowpart_subreg (VNx8HImode, operands[2], VNx8HFmode);

    emit_insn (gen_andvnx8hi3
	       (sign, arg2,
		aarch64_simd_gen_const_vector_dup (VNx8HImode,
						   HOST_WIDE_INT_M1U
						   << bits)));
    emit_insn (gen_andvnx8hi3
	       (mant, arg1,
		aarch64_simd_gen_const_vector_dup (VNx8HImode,
						   ~(HOST_WIDE_INT_M1U
						     << bits))));
    emit_insn (gen_iorvnx8hi3 (int_res, sign, mant));
    emit_move_insn (operands[0], gen_lowpart (VNx8HFmode, int_res));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3082 */
rtx
gen_copysignvnx4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"copysignvnx4sf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3087 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx sign = gen_reg_rtx (VNx4SImode);
    rtx mant = gen_reg_rtx (VNx4SImode);
    rtx int_res = gen_reg_rtx (VNx4SImode);
    int bits = GET_MODE_UNIT_BITSIZE (VNx4SFmode) - 1;

    rtx arg1 = lowpart_subreg (VNx4SImode, operands[1], VNx4SFmode);
    rtx arg2 = lowpart_subreg (VNx4SImode, operands[2], VNx4SFmode);

    emit_insn (gen_andvnx4si3
	       (sign, arg2,
		aarch64_simd_gen_const_vector_dup (VNx4SImode,
						   HOST_WIDE_INT_M1U
						   << bits)));
    emit_insn (gen_andvnx4si3
	       (mant, arg1,
		aarch64_simd_gen_const_vector_dup (VNx4SImode,
						   ~(HOST_WIDE_INT_M1U
						     << bits))));
    emit_insn (gen_iorvnx4si3 (int_res, sign, mant));
    emit_move_insn (operands[0], gen_lowpart (VNx4SFmode, int_res));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3082 */
rtx
gen_copysignvnx2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"copysignvnx2df3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3087 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx sign = gen_reg_rtx (VNx2DImode);
    rtx mant = gen_reg_rtx (VNx2DImode);
    rtx int_res = gen_reg_rtx (VNx2DImode);
    int bits = GET_MODE_UNIT_BITSIZE (VNx2DFmode) - 1;

    rtx arg1 = lowpart_subreg (VNx2DImode, operands[1], VNx2DFmode);
    rtx arg2 = lowpart_subreg (VNx2DImode, operands[2], VNx2DFmode);

    emit_insn (gen_andvnx2di3
	       (sign, arg2,
		aarch64_simd_gen_const_vector_dup (VNx2DImode,
						   HOST_WIDE_INT_M1U
						   << bits)));
    emit_insn (gen_andvnx2di3
	       (mant, arg1,
		aarch64_simd_gen_const_vector_dup (VNx2DImode,
						   ~(HOST_WIDE_INT_M1U
						     << bits))));
    emit_insn (gen_iorvnx2di3 (int_res, sign, mant));
    emit_move_insn (operands[0], gen_lowpart (VNx2DFmode, int_res));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3112 */
rtx
gen_xorsignvnx8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"xorsignvnx8hf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3117 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx sign = gen_reg_rtx (VNx8HImode);
    rtx int_res = gen_reg_rtx (VNx8HImode);
    int bits = GET_MODE_UNIT_BITSIZE (VNx8HFmode) - 1;

    rtx arg1 = lowpart_subreg (VNx8HImode, operands[1], VNx8HFmode);
    rtx arg2 = lowpart_subreg (VNx8HImode, operands[2], VNx8HFmode);

    emit_insn (gen_andvnx8hi3
	       (sign, arg2,
		aarch64_simd_gen_const_vector_dup (VNx8HImode,
						   HOST_WIDE_INT_M1U
						   << bits)));
    emit_insn (gen_xorvnx8hi3 (int_res, arg1, sign));
    emit_move_insn (operands[0], gen_lowpart (VNx8HFmode, int_res));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3112 */
rtx
gen_xorsignvnx4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"xorsignvnx4sf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3117 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx sign = gen_reg_rtx (VNx4SImode);
    rtx int_res = gen_reg_rtx (VNx4SImode);
    int bits = GET_MODE_UNIT_BITSIZE (VNx4SFmode) - 1;

    rtx arg1 = lowpart_subreg (VNx4SImode, operands[1], VNx4SFmode);
    rtx arg2 = lowpart_subreg (VNx4SImode, operands[2], VNx4SFmode);

    emit_insn (gen_andvnx4si3
	       (sign, arg2,
		aarch64_simd_gen_const_vector_dup (VNx4SImode,
						   HOST_WIDE_INT_M1U
						   << bits)));
    emit_insn (gen_xorvnx4si3 (int_res, arg1, sign));
    emit_move_insn (operands[0], gen_lowpart (VNx4SFmode, int_res));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md:3112 */
rtx
gen_xorsignvnx2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"xorsignvnx2df3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3117 "../../../../../../../work-shared/gcc-9.2.0-r0/gcc-9.2.0/gcc/config/aarch64/aarch64-sve.md"
{
    rtx sign = gen_reg_rtx (VNx2DImode);
    rtx int_res = gen_reg_rtx (VNx2DImode);
    int bits = GET_MODE_UNIT_BITSIZE (VNx2DFmode) - 1;

    rtx arg1 = lowpart_subreg (VNx2DImode, operands[1], VNx2DFmode);
    rtx arg2 = lowpart_subreg (VNx2DImode, operands[2], VNx2DFmode);

    emit_insn (gen_andvnx2di3
	       (sign, arg2,
		aarch64_simd_gen_const_vector_dup (VNx2DImode,
						   HOST_WIDE_INT_M1U
						   << bits)));
    emit_insn (gen_xorvnx2di3 (int_res, arg1, sign));
    emit_move_insn (operands[0], gen_lowpart (VNx2DFmode, int_res));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}



void
add_clobbers (rtx pattern ATTRIBUTE_UNUSED, int insn_code_number)
{
  switch (insn_code_number)
    {
    case 4346:
    case 4345:
    case 4344:
    case 4343:
    case 4342:
    case 4341:
    case 4340:
    case 4339:
    case 4338:
    case 4337:
    case 3930:
    case 3927:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (VNx2BImode));
      break;

    case 4336:
    case 4335:
    case 4334:
    case 4333:
    case 4332:
    case 4331:
    case 4330:
    case 4329:
    case 4328:
    case 4327:
    case 3929:
    case 3926:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (VNx4BImode));
      break;

    case 4326:
    case 4325:
    case 4324:
    case 4323:
    case 4322:
    case 4321:
    case 4320:
    case 4319:
    case 4318:
    case 4317:
    case 3928:
    case 3925:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (VNx8BImode));
      break;

    case 4316:
    case 4315:
    case 4314:
    case 4313:
    case 4312:
    case 4311:
    case 4310:
    case 4309:
    case 4308:
    case 4307:
    case 3924:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (VNx16BImode));
      break;

    case 3730:
    case 3710:
    case 3709:
    case 3708:
    case 3707:
    case 3706:
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      XVECEXP (pattern, 0, 4) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3729:
    case 3705:
    case 3704:
    case 3703:
    case 3702:
    case 3701:
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      XVECEXP (pattern, 0, 4) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3728:
    case 3700:
    case 3699:
    case 3698:
    case 3697:
    case 3696:
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode));
      XVECEXP (pattern, 0, 4) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3727:
    case 3695:
    case 3694:
    case 3693:
    case 3692:
    case 3691:
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode));
      XVECEXP (pattern, 0, 4) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3678:
    case 3677:
    case 3676:
    case 3675:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode));
      break;

    case 3674:
    case 3673:
    case 3672:
    case 3671:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode));
      break;

    case 3690:
    case 3670:
    case 3669:
    case 3668:
    case 3667:
    case 3666:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3689:
    case 3665:
    case 3664:
    case 3663:
    case 3662:
    case 3661:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3688:
    case 3660:
    case 3659:
    case 3658:
    case 3657:
    case 3656:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode));
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3687:
    case 3655:
    case 3654:
    case 3653:
    case 3652:
    case 3651:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode));
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3754:
    case 3753:
    case 3752:
    case 3751:
    case 3750:
    case 3749:
    case 3748:
    case 3747:
    case 3746:
    case 3745:
    case 3744:
    case 3743:
    case 3742:
    case 3741:
    case 3740:
    case 3739:
    case 3738:
    case 3737:
    case 3736:
    case 3735:
    case 3734:
    case 3733:
    case 3732:
    case 3731:
    case 3646:
    case 3645:
    case 3644:
    case 3643:
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3638:
    case 3637:
    case 3636:
    case 3635:
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3686:
    case 3685:
    case 3684:
    case 3683:
    case 1080:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      break;

    case 3682:
    case 3681:
    case 3680:
    case 3679:
    case 1079:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 1064:
    case 1063:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (DImode, 30);
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 3) = gen_hard_reg_clobber_high (TImode, 32);
      XVECEXP (pattern, 0, 4) = gen_hard_reg_clobber_high (TImode, 33);
      XVECEXP (pattern, 0, 5) = gen_hard_reg_clobber_high (TImode, 34);
      XVECEXP (pattern, 0, 6) = gen_hard_reg_clobber_high (TImode, 35);
      XVECEXP (pattern, 0, 7) = gen_hard_reg_clobber_high (TImode, 36);
      XVECEXP (pattern, 0, 8) = gen_hard_reg_clobber_high (TImode, 37);
      XVECEXP (pattern, 0, 9) = gen_hard_reg_clobber_high (TImode, 38);
      XVECEXP (pattern, 0, 10) = gen_hard_reg_clobber_high (TImode, 39);
      XVECEXP (pattern, 0, 11) = gen_hard_reg_clobber_high (TImode, 40);
      XVECEXP (pattern, 0, 12) = gen_hard_reg_clobber_high (TImode, 41);
      XVECEXP (pattern, 0, 13) = gen_hard_reg_clobber_high (TImode, 42);
      XVECEXP (pattern, 0, 14) = gen_hard_reg_clobber_high (TImode, 43);
      XVECEXP (pattern, 0, 15) = gen_hard_reg_clobber_high (TImode, 44);
      XVECEXP (pattern, 0, 16) = gen_hard_reg_clobber_high (TImode, 45);
      XVECEXP (pattern, 0, 17) = gen_hard_reg_clobber_high (TImode, 46);
      XVECEXP (pattern, 0, 18) = gen_hard_reg_clobber_high (TImode, 47);
      XVECEXP (pattern, 0, 19) = gen_hard_reg_clobber_high (TImode, 48);
      XVECEXP (pattern, 0, 20) = gen_hard_reg_clobber_high (TImode, 49);
      XVECEXP (pattern, 0, 21) = gen_hard_reg_clobber_high (TImode, 50);
      XVECEXP (pattern, 0, 22) = gen_hard_reg_clobber_high (TImode, 51);
      XVECEXP (pattern, 0, 23) = gen_hard_reg_clobber_high (TImode, 52);
      XVECEXP (pattern, 0, 24) = gen_hard_reg_clobber_high (TImode, 53);
      XVECEXP (pattern, 0, 25) = gen_hard_reg_clobber_high (TImode, 54);
      XVECEXP (pattern, 0, 26) = gen_hard_reg_clobber_high (TImode, 55);
      XVECEXP (pattern, 0, 27) = gen_hard_reg_clobber_high (TImode, 56);
      XVECEXP (pattern, 0, 28) = gen_hard_reg_clobber_high (TImode, 57);
      XVECEXP (pattern, 0, 29) = gen_hard_reg_clobber_high (TImode, 58);
      XVECEXP (pattern, 0, 30) = gen_hard_reg_clobber_high (TImode, 59);
      XVECEXP (pattern, 0, 31) = gen_hard_reg_clobber_high (TImode, 60);
      XVECEXP (pattern, 0, 32) = gen_hard_reg_clobber_high (TImode, 61);
      XVECEXP (pattern, 0, 33) = gen_hard_reg_clobber_high (TImode, 62);
      XVECEXP (pattern, 0, 34) = gen_hard_reg_clobber_high (TImode, 63);
      XVECEXP (pattern, 0, 35) = gen_hard_reg_clobber (VNx2BImode, 68);
      XVECEXP (pattern, 0, 36) = gen_hard_reg_clobber (VNx2BImode, 69);
      XVECEXP (pattern, 0, 37) = gen_hard_reg_clobber (VNx2BImode, 70);
      XVECEXP (pattern, 0, 38) = gen_hard_reg_clobber (VNx2BImode, 71);
      XVECEXP (pattern, 0, 39) = gen_hard_reg_clobber (VNx2BImode, 72);
      XVECEXP (pattern, 0, 40) = gen_hard_reg_clobber (VNx2BImode, 73);
      XVECEXP (pattern, 0, 41) = gen_hard_reg_clobber (VNx2BImode, 74);
      XVECEXP (pattern, 0, 42) = gen_hard_reg_clobber (VNx2BImode, 75);
      XVECEXP (pattern, 0, 43) = gen_hard_reg_clobber (VNx2BImode, 76);
      XVECEXP (pattern, 0, 44) = gen_hard_reg_clobber (VNx2BImode, 77);
      XVECEXP (pattern, 0, 45) = gen_hard_reg_clobber (VNx2BImode, 78);
      XVECEXP (pattern, 0, 46) = gen_hard_reg_clobber (VNx2BImode, 79);
      XVECEXP (pattern, 0, 47) = gen_hard_reg_clobber (VNx2BImode, 80);
      XVECEXP (pattern, 0, 48) = gen_hard_reg_clobber (VNx2BImode, 81);
      XVECEXP (pattern, 0, 49) = gen_hard_reg_clobber (VNx2BImode, 82);
      XVECEXP (pattern, 0, 50) = gen_hard_reg_clobber (VNx2BImode, 83);
      XVECEXP (pattern, 0, 51) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      break;

    case 1062:
    case 1061:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (DImode, 30);
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      break;

    case 1046:
    case 1045:
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (DImode, 30);
      break;

    case 41:
    case 40:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (DImode, 30);
      break;

    case 4466:
    case 4465:
    case 4464:
    case 4463:
    case 4462:
    case 4461:
    case 4460:
    case 4459:
    case 4458:
    case 4457:
    case 4456:
    case 4455:
    case 4454:
    case 4453:
    case 4452:
    case 4451:
    case 4450:
    case 4449:
    case 4448:
    case 4447:
    case 4446:
    case 4445:
    case 4444:
    case 4443:
    case 4442:
    case 4441:
    case 4440:
    case 4439:
    case 4438:
    case 4437:
    case 4436:
    case 4435:
    case 4434:
    case 4433:
    case 4432:
    case 4431:
    case 4430:
    case 4429:
    case 4428:
    case 4427:
    case 4426:
    case 4425:
    case 4424:
    case 4423:
    case 4422:
    case 4421:
    case 4420:
    case 4419:
    case 4418:
    case 4417:
    case 4416:
    case 4415:
    case 4414:
    case 4413:
    case 4412:
    case 4411:
    case 4410:
    case 4409:
    case 4408:
    case 4407:
    case 4406:
    case 4405:
    case 4404:
    case 4403:
    case 4402:
    case 4401:
    case 4400:
    case 4399:
    case 4398:
    case 4397:
    case 4396:
    case 4395:
    case 4394:
    case 4393:
    case 4392:
    case 4391:
    case 4390:
    case 4389:
    case 4388:
    case 4387:
    case 4306:
    case 4305:
    case 4304:
    case 4303:
    case 4302:
    case 4301:
    case 4300:
    case 4299:
    case 4298:
    case 4297:
    case 4296:
    case 4295:
    case 4294:
    case 4293:
    case 4292:
    case 4291:
    case 4290:
    case 4289:
    case 4288:
    case 4287:
    case 4286:
    case 4285:
    case 4284:
    case 4283:
    case 4282:
    case 4281:
    case 4280:
    case 4279:
    case 4278:
    case 4277:
    case 4276:
    case 4275:
    case 4274:
    case 4273:
    case 4272:
    case 4271:
    case 4270:
    case 4269:
    case 4268:
    case 4267:
    case 4258:
    case 4257:
    case 4256:
    case 4255:
    case 4254:
    case 4253:
    case 4252:
    case 4251:
    case 3011:
    case 2999:
    case 2998:
    case 2997:
    case 2996:
    case 2962:
    case 2961:
    case 2960:
    case 2959:
    case 2958:
    case 490:
    case 489:
    case 488:
    case 487:
    case 39:
    case 38:
    case 37:
    case 36:
    case 35:
    case 34:
    case 33:
    case 32:
    case 31:
    case 30:
    case 29:
    case 28:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (CCmode, 66);
      break;

    default:
      gcc_unreachable ();
    }
}


int
added_clobbers_hard_reg_p (int insn_code_number)
{
  switch (insn_code_number)
    {
    case 4346:
    case 4345:
    case 4344:
    case 4343:
    case 4342:
    case 4341:
    case 4340:
    case 4339:
    case 4338:
    case 4337:
    case 3930:
    case 3927:
    case 4336:
    case 4335:
    case 4334:
    case 4333:
    case 4332:
    case 4331:
    case 4330:
    case 4329:
    case 4328:
    case 4327:
    case 3929:
    case 3926:
    case 4326:
    case 4325:
    case 4324:
    case 4323:
    case 4322:
    case 4321:
    case 4320:
    case 4319:
    case 4318:
    case 4317:
    case 3928:
    case 3925:
    case 4316:
    case 4315:
    case 4314:
    case 4313:
    case 4312:
    case 4311:
    case 4310:
    case 4309:
    case 4308:
    case 4307:
    case 3924:
    case 3678:
    case 3677:
    case 3676:
    case 3675:
    case 3674:
    case 3673:
    case 3672:
    case 3671:
    case 3638:
    case 3637:
    case 3636:
    case 3635:
    case 3686:
    case 3685:
    case 3684:
    case 3683:
    case 1080:
    case 3682:
    case 3681:
    case 3680:
    case 3679:
    case 1079:
      return 0;

    case 3730:
    case 3710:
    case 3709:
    case 3708:
    case 3707:
    case 3706:
    case 3729:
    case 3705:
    case 3704:
    case 3703:
    case 3702:
    case 3701:
    case 3728:
    case 3700:
    case 3699:
    case 3698:
    case 3697:
    case 3696:
    case 3727:
    case 3695:
    case 3694:
    case 3693:
    case 3692:
    case 3691:
    case 3690:
    case 3670:
    case 3669:
    case 3668:
    case 3667:
    case 3666:
    case 3689:
    case 3665:
    case 3664:
    case 3663:
    case 3662:
    case 3661:
    case 3688:
    case 3660:
    case 3659:
    case 3658:
    case 3657:
    case 3656:
    case 3687:
    case 3655:
    case 3654:
    case 3653:
    case 3652:
    case 3651:
    case 3754:
    case 3753:
    case 3752:
    case 3751:
    case 3750:
    case 3749:
    case 3748:
    case 3747:
    case 3746:
    case 3745:
    case 3744:
    case 3743:
    case 3742:
    case 3741:
    case 3740:
    case 3739:
    case 3738:
    case 3737:
    case 3736:
    case 3735:
    case 3734:
    case 3733:
    case 3732:
    case 3731:
    case 3646:
    case 3645:
    case 3644:
    case 3643:
    case 1064:
    case 1063:
    case 1062:
    case 1061:
    case 1046:
    case 1045:
    case 41:
    case 40:
    case 4466:
    case 4465:
    case 4464:
    case 4463:
    case 4462:
    case 4461:
    case 4460:
    case 4459:
    case 4458:
    case 4457:
    case 4456:
    case 4455:
    case 4454:
    case 4453:
    case 4452:
    case 4451:
    case 4450:
    case 4449:
    case 4448:
    case 4447:
    case 4446:
    case 4445:
    case 4444:
    case 4443:
    case 4442:
    case 4441:
    case 4440:
    case 4439:
    case 4438:
    case 4437:
    case 4436:
    case 4435:
    case 4434:
    case 4433:
    case 4432:
    case 4431:
    case 4430:
    case 4429:
    case 4428:
    case 4427:
    case 4426:
    case 4425:
    case 4424:
    case 4423:
    case 4422:
    case 4421:
    case 4420:
    case 4419:
    case 4418:
    case 4417:
    case 4416:
    case 4415:
    case 4414:
    case 4413:
    case 4412:
    case 4411:
    case 4410:
    case 4409:
    case 4408:
    case 4407:
    case 4406:
    case 4405:
    case 4404:
    case 4403:
    case 4402:
    case 4401:
    case 4400:
    case 4399:
    case 4398:
    case 4397:
    case 4396:
    case 4395:
    case 4394:
    case 4393:
    case 4392:
    case 4391:
    case 4390:
    case 4389:
    case 4388:
    case 4387:
    case 4306:
    case 4305:
    case 4304:
    case 4303:
    case 4302:
    case 4301:
    case 4300:
    case 4299:
    case 4298:
    case 4297:
    case 4296:
    case 4295:
    case 4294:
    case 4293:
    case 4292:
    case 4291:
    case 4290:
    case 4289:
    case 4288:
    case 4287:
    case 4286:
    case 4285:
    case 4284:
    case 4283:
    case 4282:
    case 4281:
    case 4280:
    case 4279:
    case 4278:
    case 4277:
    case 4276:
    case 4275:
    case 4274:
    case 4273:
    case 4272:
    case 4271:
    case 4270:
    case 4269:
    case 4268:
    case 4267:
    case 4258:
    case 4257:
    case 4256:
    case 4255:
    case 4254:
    case 4253:
    case 4252:
    case 4251:
    case 3011:
    case 2999:
    case 2998:
    case 2997:
    case 2996:
    case 2962:
    case 2961:
    case 2960:
    case 2959:
    case 2958:
    case 490:
    case 489:
    case 488:
    case 487:
    case 39:
    case 38:
    case 37:
    case 36:
    case 35:
    case 34:
    case 33:
    case 32:
    case 31:
    case 30:
    case 29:
    case 28:
      return 1;

    default:
      gcc_unreachable ();
    }
}

insn_code
maybe_code_for_aarch64_reload_movcp (machine_mode arg0, machine_mode arg1)
{
  if (arg0 == E_SFmode
      && arg1 == E_SImode)
    return CODE_FOR_aarch64_reload_movcpsfsi;
  if (arg0 == E_SFmode
      && arg1 == E_DImode)
    return CODE_FOR_aarch64_reload_movcpsfdi;
  if (arg0 == E_DFmode
      && arg1 == E_SImode)
    return CODE_FOR_aarch64_reload_movcpdfsi;
  if (arg0 == E_DFmode
      && arg1 == E_DImode)
    return CODE_FOR_aarch64_reload_movcpdfdi;
  if (arg0 == E_TFmode
      && arg1 == E_SImode)
    return CODE_FOR_aarch64_reload_movcptfsi;
  if (arg0 == E_TFmode
      && arg1 == E_DImode)
    return CODE_FOR_aarch64_reload_movcptfdi;
  if (arg0 == E_V8QImode
      && arg1 == E_SImode)
    return CODE_FOR_aarch64_reload_movcpv8qisi;
  if (arg0 == E_V16QImode
      && arg1 == E_SImode)
    return CODE_FOR_aarch64_reload_movcpv16qisi;
  if (arg0 == E_V4HImode
      && arg1 == E_SImode)
    return CODE_FOR_aarch64_reload_movcpv4hisi;
  if (arg0 == E_V8HImode
      && arg1 == E_SImode)
    return CODE_FOR_aarch64_reload_movcpv8hisi;
  if (arg0 == E_V2SImode
      && arg1 == E_SImode)
    return CODE_FOR_aarch64_reload_movcpv2sisi;
  if (arg0 == E_V4SImode
      && arg1 == E_SImode)
    return CODE_FOR_aarch64_reload_movcpv4sisi;
  if (arg0 == E_V2DImode
      && arg1 == E_SImode)
    return CODE_FOR_aarch64_reload_movcpv2disi;
  if (arg0 == E_V2SFmode
      && arg1 == E_SImode)
    return CODE_FOR_aarch64_reload_movcpv2sfsi;
  if (arg0 == E_V4SFmode
      && arg1 == E_SImode)
    return CODE_FOR_aarch64_reload_movcpv4sfsi;
  if (arg0 == E_V2DFmode
      && arg1 == E_SImode)
    return CODE_FOR_aarch64_reload_movcpv2dfsi;
  if (arg0 == E_V8QImode
      && arg1 == E_DImode)
    return CODE_FOR_aarch64_reload_movcpv8qidi;
  if (arg0 == E_V16QImode
      && arg1 == E_DImode)
    return CODE_FOR_aarch64_reload_movcpv16qidi;
  if (arg0 == E_V4HImode
      && arg1 == E_DImode)
    return CODE_FOR_aarch64_reload_movcpv4hidi;
  if (arg0 == E_V8HImode
      && arg1 == E_DImode)
    return CODE_FOR_aarch64_reload_movcpv8hidi;
  if (arg0 == E_V2SImode
      && arg1 == E_DImode)
    return CODE_FOR_aarch64_reload_movcpv2sidi;
  if (arg0 == E_V4SImode
      && arg1 == E_DImode)
    return CODE_FOR_aarch64_reload_movcpv4sidi;
  if (arg0 == E_V2DImode
      && arg1 == E_DImode)
    return CODE_FOR_aarch64_reload_movcpv2didi;
  if (arg0 == E_V2SFmode
      && arg1 == E_DImode)
    return CODE_FOR_aarch64_reload_movcpv2sfdi;
  if (arg0 == E_V4SFmode
      && arg1 == E_DImode)
    return CODE_FOR_aarch64_reload_movcpv4sfdi;
  if (arg0 == E_V2DFmode
      && arg1 == E_DImode)
    return CODE_FOR_aarch64_reload_movcpv2dfdi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_reload_movcp (machine_mode arg0, machine_mode arg1, rtx x0, rtx x1, rtx x2)
{
  insn_code code = maybe_code_for_aarch64_reload_movcp (arg0, arg1);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1, x2);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_reload_mov (machine_mode arg0)
{
  if (arg0 == E_TImode)
    return CODE_FOR_aarch64_reload_movti;
  if (arg0 == E_TFmode)
    return CODE_FOR_aarch64_reload_movtf;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_reload_mov (machine_mode arg0, rtx x0, rtx x1, rtx x2)
{
  insn_code code = maybe_code_for_aarch64_reload_mov (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1, x2);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_movdi_low (machine_mode arg0)
{
  if (arg0 == E_TImode)
    return CODE_FOR_aarch64_movdi_tilow;
  if (arg0 == E_TFmode)
    return CODE_FOR_aarch64_movdi_tflow;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_movdi_low (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_aarch64_movdi_low (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_movdi_high (machine_mode arg0)
{
  if (arg0 == E_TImode)
    return CODE_FOR_aarch64_movdi_tihigh;
  if (arg0 == E_TFmode)
    return CODE_FOR_aarch64_movdi_tfhigh;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_movdi_high (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_aarch64_movdi_high (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_movhigh_di (machine_mode arg0)
{
  if (arg0 == E_TImode)
    return CODE_FOR_aarch64_movtihigh_di;
  if (arg0 == E_TFmode)
    return CODE_FOR_aarch64_movtfhigh_di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_movhigh_di (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_aarch64_movhigh_di (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_movlow_di (machine_mode arg0)
{
  if (arg0 == E_TImode)
    return CODE_FOR_aarch64_movtilow_di;
  if (arg0 == E_TFmode)
    return CODE_FOR_aarch64_movtflow_di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_movlow_di (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_aarch64_movlow_di (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_probe_sve_stack_clash (machine_mode arg0)
{
  if (arg0 == E_SImode)
    return CODE_FOR_probe_sve_stack_clash_si;
  if (arg0 == E_DImode)
    return CODE_FOR_probe_sve_stack_clash_di;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_probe_sve_stack_clash (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)
{
  insn_code code = maybe_code_for_probe_sve_stack_clash (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1, x2, x3, x4);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_despeculate_copy (machine_mode arg0)
{
  if (arg0 == E_QImode)
    return CODE_FOR_despeculate_copyqi;
  if (arg0 == E_HImode)
    return CODE_FOR_despeculate_copyhi;
  if (arg0 == E_SImode)
    return CODE_FOR_despeculate_copysi;
  if (arg0 == E_DImode)
    return CODE_FOR_despeculate_copydi;
  if (arg0 == E_TImode)
    return CODE_FOR_despeculate_copyti;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_despeculate_copy (machine_mode arg0, rtx x0, rtx x1, rtx x2)
{
  insn_code code = maybe_code_for_despeculate_copy (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1, x2);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_split_simd_mov (machine_mode arg0)
{
  if (arg0 == E_V16QImode)
    return CODE_FOR_aarch64_split_simd_movv16qi;
  if (arg0 == E_V8HImode)
    return CODE_FOR_aarch64_split_simd_movv8hi;
  if (arg0 == E_V4SImode)
    return CODE_FOR_aarch64_split_simd_movv4si;
  if (arg0 == E_V2DImode)
    return CODE_FOR_aarch64_split_simd_movv2di;
  if (arg0 == E_V8HFmode)
    return CODE_FOR_aarch64_split_simd_movv8hf;
  if (arg0 == E_V4SFmode)
    return CODE_FOR_aarch64_split_simd_movv4sf;
  if (arg0 == E_V2DFmode)
    return CODE_FOR_aarch64_split_simd_movv2df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_split_simd_mov (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_aarch64_split_simd_mov (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_rsqrte (machine_mode arg0)
{
  if (arg0 == E_V4HFmode)
    return CODE_FOR_aarch64_rsqrtev4hf;
  if (arg0 == E_V8HFmode)
    return CODE_FOR_aarch64_rsqrtev8hf;
  if (arg0 == E_V2SFmode)
    return CODE_FOR_aarch64_rsqrtev2sf;
  if (arg0 == E_V4SFmode)
    return CODE_FOR_aarch64_rsqrtev4sf;
  if (arg0 == E_V2DFmode)
    return CODE_FOR_aarch64_rsqrtev2df;
  if (arg0 == E_HFmode)
    return CODE_FOR_aarch64_rsqrtehf;
  if (arg0 == E_SFmode)
    return CODE_FOR_aarch64_rsqrtesf;
  if (arg0 == E_DFmode)
    return CODE_FOR_aarch64_rsqrtedf;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_rsqrte (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_aarch64_rsqrte (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_rsqrts (machine_mode arg0)
{
  if (arg0 == E_V4HFmode)
    return CODE_FOR_aarch64_rsqrtsv4hf;
  if (arg0 == E_V8HFmode)
    return CODE_FOR_aarch64_rsqrtsv8hf;
  if (arg0 == E_V2SFmode)
    return CODE_FOR_aarch64_rsqrtsv2sf;
  if (arg0 == E_V4SFmode)
    return CODE_FOR_aarch64_rsqrtsv4sf;
  if (arg0 == E_V2DFmode)
    return CODE_FOR_aarch64_rsqrtsv2df;
  if (arg0 == E_HFmode)
    return CODE_FOR_aarch64_rsqrtshf;
  if (arg0 == E_SFmode)
    return CODE_FOR_aarch64_rsqrtssf;
  if (arg0 == E_DFmode)
    return CODE_FOR_aarch64_rsqrtsdf;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_rsqrts (machine_mode arg0, rtx x0, rtx x1, rtx x2)
{
  insn_code code = maybe_code_for_aarch64_rsqrts (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1, x2);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_simd_combine (machine_mode arg0)
{
  if (arg0 == E_V8QImode)
    return CODE_FOR_aarch64_simd_combinev8qi;
  if (arg0 == E_V4HImode)
    return CODE_FOR_aarch64_simd_combinev4hi;
  if (arg0 == E_V4HFmode)
    return CODE_FOR_aarch64_simd_combinev4hf;
  if (arg0 == E_V2SImode)
    return CODE_FOR_aarch64_simd_combinev2si;
  if (arg0 == E_V2SFmode)
    return CODE_FOR_aarch64_simd_combinev2sf;
  if (arg0 == E_DImode)
    return CODE_FOR_aarch64_simd_combinedi;
  if (arg0 == E_DFmode)
    return CODE_FOR_aarch64_simd_combinedf;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_simd_combine (machine_mode arg0, rtx x0, rtx x1, rtx x2)
{
  insn_code code = maybe_code_for_aarch64_simd_combine (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1, x2);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_frecpe (machine_mode arg0)
{
  if (arg0 == E_V4HFmode)
    return CODE_FOR_aarch64_frecpev4hf;
  if (arg0 == E_V8HFmode)
    return CODE_FOR_aarch64_frecpev8hf;
  if (arg0 == E_V2SFmode)
    return CODE_FOR_aarch64_frecpev2sf;
  if (arg0 == E_V4SFmode)
    return CODE_FOR_aarch64_frecpev4sf;
  if (arg0 == E_V2DFmode)
    return CODE_FOR_aarch64_frecpev2df;
  if (arg0 == E_HFmode)
    return CODE_FOR_aarch64_frecpehf;
  if (arg0 == E_SFmode)
    return CODE_FOR_aarch64_frecpesf;
  if (arg0 == E_DFmode)
    return CODE_FOR_aarch64_frecpedf;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_frecpe (machine_mode arg0, rtx x0, rtx x1)
{
  insn_code code = maybe_code_for_aarch64_frecpe (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_frecps (machine_mode arg0)
{
  if (arg0 == E_V4HFmode)
    return CODE_FOR_aarch64_frecpsv4hf;
  if (arg0 == E_V8HFmode)
    return CODE_FOR_aarch64_frecpsv8hf;
  if (arg0 == E_V2SFmode)
    return CODE_FOR_aarch64_frecpsv2sf;
  if (arg0 == E_V4SFmode)
    return CODE_FOR_aarch64_frecpsv4sf;
  if (arg0 == E_V2DFmode)
    return CODE_FOR_aarch64_frecpsv2df;
  if (arg0 == E_HFmode)
    return CODE_FOR_aarch64_frecpshf;
  if (arg0 == E_SFmode)
    return CODE_FOR_aarch64_frecpssf;
  if (arg0 == E_DFmode)
    return CODE_FOR_aarch64_frecpsdf;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_frecps (machine_mode arg0, rtx x0, rtx x1, rtx x2)
{
  insn_code code = maybe_code_for_aarch64_frecps (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1, x2);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_atomic_compare_and_swap (machine_mode arg0)
{
  if (arg0 == E_QImode)
    return CODE_FOR_atomic_compare_and_swapqi;
  if (arg0 == E_HImode)
    return CODE_FOR_atomic_compare_and_swaphi;
  if (arg0 == E_SImode)
    return CODE_FOR_atomic_compare_and_swapsi;
  if (arg0 == E_DImode)
    return CODE_FOR_atomic_compare_and_swapdi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_atomic_compare_and_swap (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6, rtx x7)
{
  insn_code code = maybe_code_for_atomic_compare_and_swap (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6, x7);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_compare_and_swap (machine_mode arg0)
{
  if (arg0 == E_QImode)
    return CODE_FOR_aarch64_compare_and_swapqi;
  if (arg0 == E_HImode)
    return CODE_FOR_aarch64_compare_and_swaphi;
  if (arg0 == E_SImode)
    return CODE_FOR_aarch64_compare_and_swapsi;
  if (arg0 == E_DImode)
    return CODE_FOR_aarch64_compare_and_swapdi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_compare_and_swap (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3, rtx x4, rtx x5, rtx x6)
{
  insn_code code = maybe_code_for_aarch64_compare_and_swap (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1, x2, x3, x4, x5, x6);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_compare_and_swap_lse (machine_mode arg0)
{
  if (arg0 == E_QImode)
    return CODE_FOR_aarch64_compare_and_swapqi_lse;
  if (arg0 == E_HImode)
    return CODE_FOR_aarch64_compare_and_swaphi_lse;
  if (arg0 == E_SImode)
    return CODE_FOR_aarch64_compare_and_swapsi_lse;
  if (arg0 == E_DImode)
    return CODE_FOR_aarch64_compare_and_swapdi_lse;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_compare_and_swap_lse (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3)
{
  insn_code code = maybe_code_for_aarch64_compare_and_swap_lse (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1, x2, x3);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_load_exclusive (machine_mode arg0)
{
  if (arg0 == E_QImode)
    return CODE_FOR_aarch64_load_exclusiveqi;
  if (arg0 == E_HImode)
    return CODE_FOR_aarch64_load_exclusivehi;
  if (arg0 == E_SImode)
    return CODE_FOR_aarch64_load_exclusivesi;
  if (arg0 == E_DImode)
    return CODE_FOR_aarch64_load_exclusivedi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_load_exclusive (machine_mode arg0, rtx x0, rtx x1, rtx x2)
{
  insn_code code = maybe_code_for_aarch64_load_exclusive (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1, x2);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_store_exclusive (machine_mode arg0)
{
  if (arg0 == E_QImode)
    return CODE_FOR_aarch64_store_exclusiveqi;
  if (arg0 == E_HImode)
    return CODE_FOR_aarch64_store_exclusivehi;
  if (arg0 == E_SImode)
    return CODE_FOR_aarch64_store_exclusivesi;
  if (arg0 == E_DImode)
    return CODE_FOR_aarch64_store_exclusivedi;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_store_exclusive (machine_mode arg0, rtx x0, rtx x1, rtx x2, rtx x3)
{
  insn_code code = maybe_code_for_aarch64_store_exclusive (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1, x2, x3);
  else
    return NULL_RTX;
}

insn_code
maybe_code_for_aarch64_pred_mov (machine_mode arg0)
{
  if (arg0 == E_VNx16QImode)
    return CODE_FOR_aarch64_pred_movvnx16qi;
  if (arg0 == E_VNx8HImode)
    return CODE_FOR_aarch64_pred_movvnx8hi;
  if (arg0 == E_VNx4SImode)
    return CODE_FOR_aarch64_pred_movvnx4si;
  if (arg0 == E_VNx2DImode)
    return CODE_FOR_aarch64_pred_movvnx2di;
  if (arg0 == E_VNx8HFmode)
    return CODE_FOR_aarch64_pred_movvnx8hf;
  if (arg0 == E_VNx4SFmode)
    return CODE_FOR_aarch64_pred_movvnx4sf;
  if (arg0 == E_VNx2DFmode)
    return CODE_FOR_aarch64_pred_movvnx2df;
  if (arg0 == E_VNx32QImode)
    return CODE_FOR_aarch64_pred_movvnx32qi;
  if (arg0 == E_VNx16HImode)
    return CODE_FOR_aarch64_pred_movvnx16hi;
  if (arg0 == E_VNx8SImode)
    return CODE_FOR_aarch64_pred_movvnx8si;
  if (arg0 == E_VNx4DImode)
    return CODE_FOR_aarch64_pred_movvnx4di;
  if (arg0 == E_VNx16HFmode)
    return CODE_FOR_aarch64_pred_movvnx16hf;
  if (arg0 == E_VNx8SFmode)
    return CODE_FOR_aarch64_pred_movvnx8sf;
  if (arg0 == E_VNx4DFmode)
    return CODE_FOR_aarch64_pred_movvnx4df;
  if (arg0 == E_VNx48QImode)
    return CODE_FOR_aarch64_pred_movvnx48qi;
  if (arg0 == E_VNx24HImode)
    return CODE_FOR_aarch64_pred_movvnx24hi;
  if (arg0 == E_VNx12SImode)
    return CODE_FOR_aarch64_pred_movvnx12si;
  if (arg0 == E_VNx6DImode)
    return CODE_FOR_aarch64_pred_movvnx6di;
  if (arg0 == E_VNx24HFmode)
    return CODE_FOR_aarch64_pred_movvnx24hf;
  if (arg0 == E_VNx12SFmode)
    return CODE_FOR_aarch64_pred_movvnx12sf;
  if (arg0 == E_VNx6DFmode)
    return CODE_FOR_aarch64_pred_movvnx6df;
  if (arg0 == E_VNx64QImode)
    return CODE_FOR_aarch64_pred_movvnx64qi;
  if (arg0 == E_VNx32HImode)
    return CODE_FOR_aarch64_pred_movvnx32hi;
  if (arg0 == E_VNx16SImode)
    return CODE_FOR_aarch64_pred_movvnx16si;
  if (arg0 == E_VNx8DImode)
    return CODE_FOR_aarch64_pred_movvnx8di;
  if (arg0 == E_VNx32HFmode)
    return CODE_FOR_aarch64_pred_movvnx32hf;
  if (arg0 == E_VNx16SFmode)
    return CODE_FOR_aarch64_pred_movvnx16sf;
  if (arg0 == E_VNx8DFmode)
    return CODE_FOR_aarch64_pred_movvnx8df;
  return CODE_FOR_nothing;
}

rtx
maybe_gen_aarch64_pred_mov (machine_mode arg0, rtx x0, rtx x1, rtx x2)
{
  insn_code code = maybe_code_for_aarch64_pred_mov (arg0);
  if (code != CODE_FOR_nothing)
    return GEN_FCN (code) (x0, x1, x2);
  else
    return NULL_RTX;
}
