Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
using ZynqMP SoC firmware interface
For Bitstream configuration on ZynqMp Soc uses processor configuration
port(PCAP) to configure the programmable logic(PL) through PS by using
FW interface.

Required properties:
- compatible: should contain "xlnx,zynqmp-pcap-fpga"
- clocks: phandle for clocks required operation
- clock-names: name for the clock, should be "ref_clk"

Example:
	zynqmp_pcap: pcap {
		compatible = "xlnx,zynqmp-pcap-fpga";
		clocks = <&clkc 41>;
		clock-names = "ref_clk";
	};
