mipicsiss: XCsiSs_Config Struct Reference

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XCsiSs_Config Struct Reference
Csiss_v1_1

MIPI CSI Rx Subsystem configuration structure. More...

## Data Fields
u32 | DeviceId
| DeviceId is the unique ID of the device. More...
UINTPTR | BaseAddr
     BaseAddress is the physical base address
of the subsystem address range More...
UINTPTR | HighAddr
     HighAddress is the physical MAX address
of the subsystem address range More...
u32 | IsIicPresent
| Flag for IIC presence in subsystem. More...
u32 | LanesPresent
| Number of PPI Lanes in the design. More...
u32 | PixelCount
| Number of Pixels per clock 1,2,4. More...
u32 | PixelFormat
| The pixel format selected from all RGB, RAW and YUV422 8bit options. More...
u32 | VcNo
| Number of Virtual Channels supported by system. More...
u32 | CsiBuffDepth
| Line buffer Depth set. More...
u32 | IsEmbNonImgPresent
| Flag for presence of Embedded Non Image data. More...
u32 | IsDphyRegIntfcPresent
| Flag for DPHY register interface presence. More...
u32 | DphyLineRate
| DPHY Line Rate ranging from 80-1500 Mbps. More...
u32 | EnableCrc
| CRC Calculation optimization enabled. More...
u32 | EnableActiveLanes
| Active Lanes programming optimization enabled. More...
CsiRxSsSubCore | IicInfo
| IIC sub-core configuration. More...
CsiRxSsSubCore | CsiInfo
| CSI sub-core configuration. More...
CsiRxSsSubCore | DphyInfo
| DPHY sub-core configuration. More...

## Detailed Description

MIPI CSI Rx Subsystem configuration structure.

Each subsystem device should have a configuration structure associated that defines the MAX supported sub-cores within subsystem

## Field Documentation

UINTPTR XCsiSs_Config::BaseAddr

     BaseAddress is the physical base address

of the subsystem address range

Referenced by CsiSs_IntrExample(), CsiSs_SelfTestExample(), InitializeCsiRxSs(), InitializeDemosaic(), and XCsiSs_CfgInitialize().

u32 XCsiSs_Config::CsiBuffDepth

Line buffer Depth set.

CsiRxSsSubCore XCsiSs_Config::CsiInfo

CSI sub-core configuration.

u32 XCsiSs_Config::DeviceId

DeviceId is the unique ID of the device.

CsiRxSsSubCore XCsiSs_Config::DphyInfo

DPHY sub-core configuration.

u32 XCsiSs_Config::DphyLineRate

DPHY Line Rate ranging from 80-1500 Mbps.

u32 XCsiSs_Config::EnableActiveLanes

Active Lanes programming optimization enabled.

u32 XCsiSs_Config::EnableCrc

CRC Calculation optimization enabled.

UINTPTR XCsiSs_Config::HighAddr

     HighAddress is the physical MAX address

of the subsystem address range

CsiRxSsSubCore XCsiSs_Config::IicInfo

IIC sub-core configuration.

u32 XCsiSs_Config::IsDphyRegIntfcPresent

Flag for DPHY register interface presence.

Referenced by XCsiSs_Activate(), XCsiSs_CfgInitialize(), and XCsiSs_ReportCoreInfo().

u32 XCsiSs_Config::IsEmbNonImgPresent

Flag for presence of Embedded Non Image data.

u32 XCsiSs_Config::IsIicPresent

Flag for IIC presence in subsystem.

u32 XCsiSs_Config::LanesPresent

Number of PPI Lanes in the design.

Referenced by XCsiSs_GetLaneInfo().

u32 XCsiSs_Config::PixelCount

Number of Pixels per clock 1,2,4.

u32 XCsiSs_Config::PixelFormat

The pixel format selected from all RGB, RAW and YUV422 8bit options.

Referenced by SetColorDepth().

u32 XCsiSs_Config::VcNo

Number of Virtual Channels supported by system.

This can range from 1 - 4 to ALL