xxvethernet: xxxvethernet_hw.h File Reference

| xxvethernet Xilinx SDK Drivers API Documentation

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Macros
xxxvethernet_hw.h File Reference

## Macros
#define | XXxvEthernet_ReadReg(BaseAddress, RegOffset) (Xil_In32(((BaseAddress) + (RegOffset))))
| XXxvEthernet_ReadReg returns the value read from the register specified by RegOffset. More...
#define | XXxvEthernet_WriteReg(BaseAddress, RegOffset, Data) Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
| XXxvEthernet_WriteReg, writes Data to the register specified by RegOffset. More...
XXV Ethernet registers offset
#define | XXE_GRR_OFFSET 0x00000000
#define | XXE_RST_OFFSET 0x00000004
#define | XXE_MODE_OFFSET 0x00000008
#define | XXE_TXCFG_OFFSET 0x0000000C
#define | XXE_RXCFG_OFFSET 0x00000014
#define | XXE_RXMTU_OFFSET 0x00000018
#define | XXE_TICK_OFFSET 0x00000020
#define | XXE_REV_OFFSET 0x00000024
#define | XXE_USXGMII_AN_OFFSET 0x000000C8
#define | XXE_RSFEC_OFFSET 0x000000D0
#define | XXE_FEC_OFFSET 0x000000D4
#define | XXE_ANCR1_OFFSET 0x000000E0
#define | XXE_ANCR2_OFFSET 0x000000E4
#define | XXE_ANACR_OFFSET 0x000000F8
#define | XXE_LTCR_OFFSET 0x00000100
#define | XXE_LTTR_OFFSET 0x00000104
#define | XXE_LTPR_OFFSET 0x00000108
#define | XXE_LTIR_OFFSET 0x0000010C
#define | XXE_LTSR_OFFSET 0x00000110
#define | XXE_LTCOR_OFFSET 0x00000130
#define | XXE_USR0_OFFSET 0x00000184
#define | XXE_USR1_OFFSET 0x00000188
Xxv Ethernet status registers offset
#define | XXE_CORESPEEDSR_OFFSET 0x00000180
#define | XXE_TXSR_OFFSET 0x00000400
#define | XXE_RXSR_OFFSET 0x00000404
#define | XXE_SR_OFFSET 0x00000408
#define | XXE_RXBLSR_OFFSET 0x0000040C
#define | XXE_ANSR_OFFSET 0x00000458
#define | XXE_ANASR_OFFSET 0x0000045C
MODE register masks
#define | XXE_MODE_LCLLPBK_MASK 0x80000000
TXCFG register masks
#define | XXE_TXCFG_TX_MASK 0x00000001
#define | XXE_TXCFG_FCS_MASK 0x00000002
RXCFG register masks
#define | XXE_RXCFG_RX_MASK 0x00000001
#define | XXE_RXCFG_DEL_FCS_MASK 0x00000002
#define | XXE_RXCFG_IGN_FCS_MASK 0x00000004
USXGMII Auto negotiation register masks
#define | XXE_USXGMII_ANBYPASS_MASK 0x00000001
#define | XXE_USXGMII_ANENABLE_MASK 0x00000020
#define | XXE_USXGMII_ANMAINRESET_MASK 0x00000040
#define | XXE_USXGMII_ANRESTART_MASK 0x00000080
#define | XXE_USXGMII_RATE_MASK 0x00000700
#define | XXE_USXGMII_ANA_MASK 0x00010000
#define | XXE_USXGMII_ANA_SPEED_MASK 0x0E000000
#define | XXE_USXGMII_ANA_FD_MASK 0x10000000
#define | XXE_USXGMII_ANACK_MASK 0x40000000
#define | XXE_USXGMII_LINK_STS_MASK 0x80000000
#define | XXE_USXGMII_RATE_10M_MASK 0x0
#define | XXE_USXGMII_RATE_100M_MASK 0x1
#define | XXE_USXGMII_RATE_1G_MASK 0x2
#define | XXE_USXGMII_RATE_10G_MASK 0x3
#define | XXE_USXGMII_RATE_2G5_MASK 0x4
#define | XXE_USXGMII_RATE_SHIFT 8
#define | XXE_USXGMII_SPEED_SHIFT 25
RXMTU register masks
#define | XXE_RXMTU_MIN_JUM_MASK 0x000000FF
#define | XXE_RXMTU_MAX_JUM_MASK 0x7FFF0000
RXBLSR register masks
#define | XXE_RXBLKLCK_MASK 0x00000001
TICK register masks
#define | XXE_TICK_STATEN_MASK 0x00000001
AN status register masks
#define | XXE_AN_COMP_MASK 0x00000004
#define | XXE_USXGMII_AN_COMP_MASK 0x00010000
AN ability register masks
#define | XXE_ANA_10GKR_MASK 0x00000004
Reset and Address Filter (RAF) Register bit definitions.
These bits are associated with the XAE_RAF_OFFSET register.
#define | XXE_RAF_STATSRST_MASK 0x00002000
| Statistics Counter Reset. More...
#define | XXE_RAF_RXBADFRMEN_MASK 0x00004000
| Receive Bad Frame Enable. More...
Transmit Inter-Frame Gap Adjustment Register (TFGP) bit definitions
#define | XXE_TFGP_IFGP_MASK 0x0000007F
| Transmit inter-frame gap adjustment value. More...
Other Constant definitions used in the driver
#define | XXE_SPEED_10_GBPS 10
| Speed of 10 Gbps. More...
#define | XXE_LOOPS_TO_COME_OUT_OF_RST 10000
| Number of loops in the driver API to wait for before returning a failure case. More...
#define | XXE_RST_DELAY_LOOPCNT_VAL 10000
| Timeout in ticks used while checking if the core had come out of reset. More...