sysmon: xsysmon_hw.h File Reference

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Macros
xsysmon_hw.h File Reference

## Macros
#define | XSysMon_ReadReg(BaseAddress, RegOffset) (Xil_In32((BaseAddress) + (RegOffset)))
| Read a register of the System Monitor/ADC device. More...
#define | XSysMon_WriteReg(BaseAddress, RegOffset, Data) (Xil_Out32((BaseAddress) + (RegOffset), (Data)))
| Write a register of the System Monitor/ADC device. More...
Register offsets
The following constants provide access to each of the registers of the System Monitor/ADC device.
#define | XSM_SRR_OFFSET 0x00
| Software Reset Register. More...
#define | XSM_SR_OFFSET 0x04
| Status Register. More...
#define | XSM_AOR_OFFSET 0x08
| Alarm Output Register. More...
#define | XSM_CONVST_OFFSET 0x0C
| ADC Convert Start Register. More...
#define | XSM_ARR_OFFSET 0x10
| ADC Reset Register. More...
#define | XSM_GIER_OFFSET 0x5C
| Global Interrupt Enable. More...
#define | XSM_IPISR_OFFSET 0x60
| Interrupt Status Register. More...
#define | XSM_IPIER_OFFSET 0x68
| Interrupt Enable register. More...
#define | XSM_TEMP_OFFSET (XSM_IP_OFFSET + 0x200)
| On-chip Temperature Reg. More...
#define | XSM_VCCINT_OFFSET (XSM_IP_OFFSET + 0x204)
| On-chip VCCINT Data Reg. More...
#define | XSM_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x208)
| On-chip VCCAUX Data Reg. More...
#define | XSM_VPVN_OFFSET (XSM_IP_OFFSET + 0x20C)
| ADC out of VP/VN. More...
#define | XSM_VREFP_OFFSET (XSM_IP_OFFSET + 0x210)
| On-chip VREFP Data Reg. More...
#define | XSM_VREFN_OFFSET (XSM_IP_OFFSET + 0x214)
| On-chip VREFN Data Reg. More...
#define | XSM_VBRAM_OFFSET (XSM_IP_OFFSET + 0x218)
| On-chip VBRAM Data,7-series/Zynq. More...
#define | XSM_SUPPLY_CALIB_OFFSET (XSM_IP_OFFSET + 0x220)
| Supply Offset Data Reg. More...
#define | XSM_ADC_CALIB_OFFSET (XSM_IP_OFFSET + 0x224)
| ADC Offset Data Reg. More...
#define | XSM_GAINERR_CALIB_OFFSET (XSM_IP_OFFSET + 0x228)
| Gain Error Data Reg. More...
#define | XSM_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x22C)
| PS VCCPINT Data Reg - Zynq. More...
#define | XSM_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x230)
| PS VCCPAUX Data Reg - Zynq. More...
#define | XSM_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x234)
| PS VCCPDRO Data Reg - Zynq. More...
#define | XSM_VUSR0_OFFSET (XSM_IP_OFFSET + 0x400)
| VUSER0 Supply - Ultrascale. More...
#define | XSM_VUSR1_OFFSET (XSM_IP_OFFSET + 0x404)
| VUSER0 Supply - Ultrascale. More...
#define | XSM_VUSR2_OFFSET (XSM_IP_OFFSET + 0x408)
| VUSER0 Supply - Ultrascale. More...
#define | XSM_VUSR3_OFFSET (XSM_IP_OFFSET + 0x40C)
| VUSER0 Supply - Ultrascale. More...
#define | XSM_AUX00_OFFSET (XSM_IP_OFFSET + 0x240)
| ADC out of VAUXP0/VAUXN0. More...
#define | XSM_AUX01_OFFSET (XSM_IP_OFFSET + 0x244)
| ADC out of VAUXP1/VAUXN1. More...
#define | XSM_AUX02_OFFSET (XSM_IP_OFFSET + 0x248)
| ADC out of VAUXP2/VAUXN2. More...
#define | XSM_AUX03_OFFSET (XSM_IP_OFFSET + 0x24C)
| ADC out of VAUXP3/VAUXN3. More...
#define | XSM_AUX04_OFFSET (XSM_IP_OFFSET + 0x250)
| ADC out of VAUXP4/VAUXN4. More...
#define | XSM_AUX05_OFFSET (XSM_IP_OFFSET + 0x254)
| ADC out of VAUXP5/VAUXN5. More...
#define | XSM_AUX06_OFFSET (XSM_IP_OFFSET + 0x258)
| ADC out of VAUXP6/VAUXN6. More...
#define | XSM_AUX07_OFFSET (XSM_IP_OFFSET + 0x25C)
| ADC out of VAUXP7/VAUXN7. More...
#define | XSM_AUX08_OFFSET (XSM_IP_OFFSET + 0x260)
| ADC out of VAUXP8/VAUXN8. More...
#define | XSM_AUX09_OFFSET (XSM_IP_OFFSET + 0x264)
| ADC out of VAUXP9/VAUXN9. More...
#define | XSM_AUX10_OFFSET (XSM_IP_OFFSET + 0x268)
| ADC out of VAUXP10/VAUXN10. More...
#define | XSM_AUX11_OFFSET (XSM_IP_OFFSET + 0x26C)
| ADC out of VAUXP11/VAUXN11. More...
#define | XSM_AUX12_OFFSET (XSM_IP_OFFSET + 0x270)
| ADC out of VAUXP12/VAUXN12. More...
#define | XSM_AUX13_OFFSET (XSM_IP_OFFSET + 0x274)
| ADC out of VAUXP13/VAUXN13. More...
#define | XSM_AUX14_OFFSET (XSM_IP_OFFSET + 0x278)
| ADC out of VAUXP14/VAUXN14. More...
#define | XSM_AUX15_OFFSET (XSM_IP_OFFSET + 0x27C)
| ADC out of VAUXP15/VAUXN15. More...
#define | XSM_MAX_TEMP_OFFSET (XSM_IP_OFFSET + 0x280)
| Maximum Temperature Reg. More...
#define | XSM_MAX_VCCINT_OFFSET (XSM_IP_OFFSET + 0x284)
| Maximum VCCINT Register. More...
#define | XSM_MAX_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x288)
| Maximum VCCAUX Register. More...
#define | XSM_MAX_VBRAM_OFFSET (XSM_IP_OFFSET + 0x28C)
| Maximum VBRAM Reg, 7 Series/Zynq. More...
#define | XSM_MIN_TEMP_OFFSET (XSM_IP_OFFSET + 0x290)
| Minimum Temperature Reg. More...
#define | XSM_MIN_VCCINT_OFFSET (XSM_IP_OFFSET + 0x294)
| Minimum VCCINT Register. More...
#define | XSM_MIN_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x298)
| Minimum VCCAUX Register. More...
#define | XSM_MIN_VBRAM_OFFSET (XSM_IP_OFFSET + 0x29C)
| Maximum VBRAM Reg, 7 Series/Zynq. More...
#define | XSM_MAX_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x2A0)
| Max VCCPINT Register, Zynq. More...
#define | XSM_MAX_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x2A4)
| Max VCCPAUX Register, Zynq. More...
#define | XSM_MAX_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x2A8)
| Max VCCPDRO Register, Zynq. More...
#define | XSM_MIN_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x2AC)
| Min VCCPINT Register, Zynq. More...
#define | XSM_MIN_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x2B0)
| Min VCCPAUX Register, Zynq. More...
#define | XSM_MIN_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x2B4)
| Min VCCPDRO Register, Zynq. More...
#define | XSM_MAX_VUSR0_OFFSET (XSM_IP_OFFSET + 0x480)
| Maximum VUSER0 Supply Reg. More...
#define | XSM_MAX_VUSR1_OFFSET (XSM_IP_OFFSET + 0x484)
| Maximum VUSER1 Supply Reg. More...
#define | XSM_MAX_VUSR2_OFFSET (XSM_IP_OFFSET + 0x488)
| Maximum VUSER2 Supply Reg. More...
#define | XSM_MAX_VUSR3_OFFSET (XSM_IP_OFFSET + 0x48C)
| Maximum VUSER3 Supply Reg. More...
#define | XSM_MIN_VUSR0_OFFSET (XSM_IP_OFFSET + 0x4A0)
| Minimum VUSER0 Supply Reg. More...
#define | XSM_MIN_VUSR1_OFFSET (XSM_IP_OFFSET + 0x4A4)
| Minimum VUSER1 Supply Reg. More...
#define | XSM_MIN_VUSR2_OFFSET (XSM_IP_OFFSET + 0x4A8)
| Minimum VUSER2 Supply Reg. More...
#define | XSM_MIN_VUSR3_OFFSET (XSM_IP_OFFSET + 0x4AC)
| Minimum VUSER3 Supply Reg. More...
#define | XSM_FLAG_REG_OFFSET (XSM_IP_OFFSET + 0x2FC)
| General Status. More...
#define | XSM_CFR0_OFFSET (XSM_IP_OFFSET + 0x300)
| Configuration Register 0. More...
#define | XSM_CFR1_OFFSET (XSM_IP_OFFSET + 0x304)
| Configuration Register 1. More...
#define | XSM_CFR2_OFFSET (XSM_IP_OFFSET + 0x308)
| Configuration Register 2. More...
#define | XSM_SEQ00_OFFSET (XSM_IP_OFFSET + 0x320)
| Seq Reg 00 Adc Channel Selection. More...
#define | XSM_SEQ01_OFFSET (XSM_IP_OFFSET + 0x324)
| Seq Reg 01 Adc Channel Selection. More...
#define | XSM_SEQ02_OFFSET (XSM_IP_OFFSET + 0x328)
| Seq Reg 02 Adc Average Enable. More...
#define | XSM_SEQ03_OFFSET (XSM_IP_OFFSET + 0x32C)
| Seq Reg 03 Adc Average Enable. More...
#define | XSM_SEQ04_OFFSET (XSM_IP_OFFSET + 0x330)
| Seq Reg 04 Adc Input Mode Select. More...
#define | XSM_SEQ05_OFFSET (XSM_IP_OFFSET + 0x334)
| Seq Reg 05 Adc Input Mode Select. More...
#define | XSM_SEQ06_OFFSET (XSM_IP_OFFSET + 0x338)
| Seq Reg 06 Adc Acquisition Select. More...
#define | XSM_SEQ07_OFFSET (XSM_IP_OFFSET + 0x33C)
| Seq Reg 07 Adc Acquisition Select. More...
#define | XSM_SEQ08_OFFSET (XSM_IP_OFFSET + 0x318)
| Seq Reg 08 Adc Channel Selection. More...
#define | XSM_SEQ09_OFFSET (XSM_IP_OFFSET + 0x31C)
| Seq Reg 09 Adc Average Enable. More...
#define | XSM_ATR_TEMP_UPPER_OFFSET (XSM_IP_OFFSET + 0x340)
| Temp Upper Alarm Register. More...
#define | XSM_ATR_VCCINT_UPPER_OFFSET (XSM_IP_OFFSET + 0x344)
| VCCINT Upper Alarm Reg. More...
#define | XSM_ATR_VCCAUX_UPPER_OFFSET (XSM_IP_OFFSET + 0x348)
| VCCAUX Upper Alarm Reg. More...
#define | XSM_ATR_OT_UPPER_OFFSET (XSM_IP_OFFSET + 0x34C)
| Over Temp Upper Alarm Reg. More...
#define | XSM_ATR_TEMP_LOWER_OFFSET (XSM_IP_OFFSET + 0x350)
| Temp Lower Alarm Register. More...
#define | XSM_ATR_VCCINT_LOWER_OFFSET (XSM_IP_OFFSET + 0x354)
| VCCINT Lower Alarm Reg. More...
#define | XSM_ATR_VCCAUX_LOWER_OFFSET (XSM_IP_OFFSET + 0x358)
| VCCAUX Lower Alarm Reg. More...
#define | XSM_ATR_OT_LOWER_OFFSET (XSM_IP_OFFSET + 0x35C)
| Over Temp Lower Alarm Reg. More...
#define | XSM_ATR_VBRAM_UPPER_OFFSET (XSM_IP_OFFSET + 0x360)
| VBBAM Upper Alarm,7 Series. More...
#define | XSM_ATR_VCCPINT_UPPER_OFFSET (XSM_IP_OFFSET + 0x364)
| VCCPINT Upper Alarm, Zynq. More...
#define | XSM_ATR_VCCPAUX_UPPER_OFFSET (XSM_IP_OFFSET + 0x368)
| VCCPAUX Upper Alarm, Zynq. More...
#define | XSM_ATR_VCCPDRO_UPPER_OFFSET (XSM_IP_OFFSET + 0x36C)
| VCCPDRO Upper Alarm, Zynq. More...
#define | XSM_ATR_VBRAM_LOWER_OFFSET (XSM_IP_OFFSET + 0x370)
| VRBAM Lower Alarm, 7 Series. More...
#define | XSM_ATR_VCCPINT_LOWER_OFFSET (XSM_IP_OFFSET + 0x374)
| VCCPINT Lower Alarm, Zynq. More...
#define | XSM_ATR_VCCPAUX_LOWER_OFFSET (XSM_IP_OFFSET + 0x378)
| VCCPAUX Lower Alarm, Zynq. More...
#define | XSM_ATR_VCCPDRO_LOWER_OFFSET (XSM_IP_OFFSET + 0x37C)
| VCCPDRO Lower Alarm, Zynq. More...
#define | XSM_ATR_VUSR0_UPPER_OFFSET (XSM_IP_OFFSET + 0x380)
| VUSER0 Upper Alarm Reg. More...
#define | XSM_ATR_VUSR1_UPPER_OFFSET (XSM_IP_OFFSET + 0x384)
| VUSER1 Upper Alarm Reg. More...
#define | XSM_ATR_VUSR2_UPPER_OFFSET (XSM_IP_OFFSET + 0x388)
| VUSER2 Upper Alarm Reg. More...
#define | XSM_ATR_VUSR3_UPPER_OFFSET (XSM_IP_OFFSET + 0x38C)
| VUSER3 Upper Alarm Reg. More...
#define | XSM_ATR_VUSR0_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A0)
| VUSER0 Lower Alarm Reg. More...
#define | XSM_ATR_VUSR1_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A4)
| VUSER1 Lower Alarm Reg. More...
#define | XSM_ATR_VUSR2_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A8)
| VUSER2 Lower Alarm Reg. More...
#define | XSM_ATR_VUSR3_LOWER_OFFSET (XSM_IP_OFFSET + 0x3AC)
| VUSER3 Lower Alarm Reg. More...
System Monitor/ADC Software Reset Register (SRR) mask(s)
#define | XSM_SRR_IPRST_MASK 0x0000000A
| Device Reset Mask. More...
System Monitor/ADC Status Register (SR) mask(s)
#define | XSM_SR_JTAG_BUSY_MASK 0x00000400
| JTAG is busy. More...
#define | XSM_SR_JTAG_MODIFIED_MASK 0x00000200
| JTAG Write has occurred. More...
#define | XSM_SR_JTAG_LOCKED_MASK 0x00000100
| JTAG is locked. More...
#define | XSM_SR_BUSY_MASK 0x00000080
| ADC is busy in conversion. More...
#define | XSM_SR_EOS_MASK 0x00000040
| End of Sequence. More...
#define | XSM_SR_EOC_MASK 0x00000020
| End of Conversion. More...
#define | XSM_SR_CH_MASK 0x0000001F
| Input ADC channel. More...
System Monitor/ADC Alarm Output Register (AOR) mask(s)
#define | XSM_AOR_ALARM_ALL_MASK 0x00001FFF
| Mask for all Alarms. More...
#define | XSM_AOR_VUSR3_MASK 0x00001000
| ALM11 - VUSER3 Alarm Mask. More...
#define | XSM_AOR_VUSR2_MASK 0x00000800
| ALM10 - VUSER2 Alarm Mask. More...
#define | XSM_AOR_VUSR1_MASK 0x00000400
| ALM9 - VUSER1 Alarm Mask. More...
#define | XSM_AOR_VUSR0_MASK 0x00000200
| ALM8 - VUSER0 Alarm Mask. More...
#define | XSM_AOR_ALL_MASK 0x00000100
| ALM7 - All Alarms 0 to 6. More...
#define | XSM_AOR_VCCPDRO_MASK 0x00000080
| ALM6 - VCCPDRO Mask, Zynq. More...
#define | XSM_AOR_VCCPAUX_MASK 0x00000040
| ALM5 - VCCPAUX Mask, Zynq. More...
#define | XSM_AOR_VCCPINT_MASK 0x00000020
| ALM4 - VCCPINT Mask, Zynq. More...
#define | XSM_AOR_VBRAM_MASK 0x00000010
| ALM3 - VBRAM Output Mask. More...
#define | XSM_AOR_VCCAUX_MASK 0x00000008
| ALM2 - VCCAUX Output Mask. More...
#define | XSM_AOR_VCCINT_MASK 0x00000004
| ALM1 - VCCINT Alarm Mask. More...
#define | XSM_AOR_TEMP_MASK 0x00000002
| ALM0 - Temp sensor Alarm Mask. More...
#define | XSM_AOR_OT_MASK 0x00000001
| Over Temp Alarm Output. More...
System Monitor/ADC CONVST Register (CONVST) mask(s)
#define | XSM_CONVST_CONVST_MASK 0x00000001
| Conversion Start Mask. More...
#define | XSM_CONVST_TEMPUPDT_MASK 0x00000002
| Temperature Update Enable Mask. More...
#define | XSM_CONVST_WAITCYCLES_SHIFT 2
| Wait Cycles Shift. More...
#define | XSM_CONVST_WAITCYCLES_MASK 0x0003FFFC
| Wait Cycles Mask. More...
#define | XSM_CONVST_WAITCYCLES_DEFAULT 0x03E8
| Wait Cycles default value. More...
System Monitor/ADC Reset Register (ARR) mask(s)
#define | XSM_ARR_RST_MASK 0x00000001
| ADC Reset bit mask. More...
Global Interrupt Enable Register (GIER) mask(s)
#define | XSM_GIER_GIE_MASK 0x80000000
| Global interrupt enable. More...
System Monitor/ADC device Interrupt Status/Enable Registers
Interrupt Status Register (IPISR) This register holds the interrupt status flags for the device. Interrupt Enable Register (IPIER) This register is used to enable interrupt sources for the device. Writing a '1' to a bit in this register enables the corresponding Interrupt. Writing a '0' to a bit in this register disables the corresponding Interrupt IPISR/IPIER registers have the same bit definitions and are only defined once.
#define | XSM_IPIXR_VBRAM_MASK 0x00000400
| ALM3 - VBRAM Output Mask. More...
#define | XSM_IPIXR_TEMP_DEACTIVE_MASK 0x00000200
| Alarm 0 DEACTIVE. More...
#define | XSM_IPIXR_OT_DEACTIVE_MASK 0x00000100
| Over Temp DEACTIVE. More...
#define | XSM_IPIXR_JTAG_MODIFIED_MASK 0x00000080
| JTAG Modified. More...
#define | XSM_IPIXR_JTAG_LOCKED_MASK 0x00000040
| JTAG Locked. More...
#define | XSM_IPIXR_EOC_MASK 0x00000020
| End Of Conversion. More...
#define | XSM_IPIXR_EOS_MASK 0x00000010
| End Of Sequence. More...
#define | XSM_IPIXR_VCCAUX_MASK 0x00000008
| Alarm 2 - VCCAUX. More...
#define | XSM_IPIXR_VCCINT_MASK 0x00000004
| Alarm 1 - VCCINT. More...
#define | XSM_IPIXR_TEMP_MASK 0x00000002
| Alarm 0 - Temp ACTIVE. More...
#define | XSM_IPIXR_OT_MASK 0x00000001
| Over Temperature ACTIVE. More...
#define | XSM_IPIXR_VUSR0_MASK 0x00004000
| Alarm 8 VUSER0. More...
#define | XSM_IPIXR_VUSR1_MASK 0x00008000
| Alarm 9 VUSER1. More...
#define | XSM_IPIXR_VUSR2_MASK 0x00010000
| Alarm 10 VUSER2. More...
#define | XSM_IPIXR_VUSR3_MASK 0x00020000
| Alarm 11 VUSER3. More...
#define | XSM_IPIXR_ALL_MASK 0x0003C7FF
| Mask of all interrupts. More...
Mask for all ADC converted data including Minimum/Maximum Measurements
      and Threshold data.
#define | XSM_ADCDATA_MAX_MASK 0x03FF
Configuration Register 0 (CFR0) mask(s)
#define | XSM_CFR0_CAL_AVG_MASK 0x8000
| Averaging enable Mask. More...
#define | XSM_CFR0_AVG_VALID_MASK 0x3000
| Averaging bit Mask. More...
#define | XSM_CFR0_AVG1_MASK 0x0000
| No Averaging. More...
#define | XSM_CFR0_AVG16_MASK 0x1000
| Average 16 samples. More...
#define | XSM_CFR0_AVG64_MASK 0x2000
| Average 64 samples. More...
#define | XSM_CFR0_AVG256_MASK 0x3000
| Average 256 samples. More...
#define | XSM_CFR0_AVG_SHIFT 12
| Shift for the Averaging bits. More...
#define | XSM_CFR0_MUX_MASK 0x0800
| External Mux Mask Enable. More...
#define | XSM_CFR0_DU_MASK 0x0400
| Bipolar/Unipolar mode. More...
#define | XSM_CFR0_EC_MASK 0x0200
| Event driven/Continuous mode. More...
#define | XSM_CFR0_ACQ_MASK 0x0100
| Add acquisition by 6 ADCCLK. More...
#define | XSM_CFR0_CHANNEL_MASK 0x003F
| Channel number bit Mask. More...
Configuration Register 1 (CFR1) mask(s)
#define | XSM_CFR1_SEQ_VALID_MASK 0xF000
| Sequence bit Mask. More...
#define | XSM_CFR1_SEQ_SAFEMODE_MASK 0x0000
| Default Safe Mode. More...
#define | XSM_CFR1_SEQ_ONEPASS_MASK 0x1000
| Onepass through Seq. More...
#define | XSM_CFR1_SEQ_CONTINPASS_MASK 0x2000
| Continuous Cycling Seq. More...
#define | XSM_CFR1_SEQ_SINGCHAN_MASK 0x3000
| Single channel - No Seq. More...
#define | XSM_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000
| Simultaneous Sampling Mask. More...
#define | XSM_CFR1_SEQ_INDEPENDENT_MASK 0x8000
| Independent Mode. More...
#define | XSM_CFR1_SEQ_SHIFT 12
| Sequence bit shift. More...
#define | XSM_CFR1_ALM_VCCPDRO_MASK 0x0800
| Alarm 6 - VCCPDRO, Zynq. More...
#define | XSM_CFR1_ALM_VCCPAUX_MASK 0x0400
| Alarm 5 - VCCPAUX, Zynq. More...
#define | XSM_CFR1_ALM_VCCPINT_MASK 0x0200
| Alarm 4 - VCCPINT, Zynq. More...
#define | XSM_CFR1_ALM_VBRAM_MASK 0x0100
| Alarm 3 - VBRAM Enable 7 Series and Zynq. More...
#define | XSM_CFR1_CAL_VALID_MASK 0x00F0
| Valid Calibration Mask. More...
#define | XSM_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080
| Calibration 3 -Power Supply Gain/Offset Enable. More...
#define | XSM_CFR1_CAL_PS_OFFSET_MASK 0x0040
| Calibration 2 -Power Supply Offset Enable. More...
#define | XSM_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020
| Calibration 1 -ADC Gain Offset Enable. More...
#define | XSM_CFR1_CAL_ADC_OFFSET_MASK 0x0010
| Calibration 0 -ADC Offset Enable. More...
#define | XSM_CFR1_CAL_DISABLE_MASK 0x0000
| No Calibration. More...
#define | XSM_CFR1_ALM_ALL_MASK 0x0F0F
| Mask for all alarms. More...
#define | XSM_CFR1_ALM_VCCAUX_MASK 0x0008
| Alarm 2 - VCCAUX Enable. More...
#define | XSM_CFR1_ALM_VCCINT_MASK 0x0004
| Alarm 1 - VCCINT Enable. More...
#define | XSM_CFR1_ALM_TEMP_MASK 0x0002
| Alarm 0 - Temperature. More...
#define | XSM_CFR1_OT_MASK 0x0001
| Over Temperature Enable. More...
Configuration Register 2 (CFR2) mask(s)
#define | XSM_CFR2_CD_VALID_MASK 0xFF00
| Clock Divisor bit Mask. More...
#define | XSM_CFR2_CD_SHIFT 8
| Num of shift on division. More...
#define | XSM_CFR2_CD_MIN 8
| Minimum value of divisor. More...
#define | XSM_CFR2_CD_MAX 255
| Maximum value of divisor. More...
#define | XSM_CFR2_PD_MASK 0x0030
| Power Down Mask. More...
#define | XSM_CFR2_PD_XADC_MASK 0x0030
| Power Down XADC Mask. More...
#define | XSM_CFR2_PD_ADC1_MASK 0x0020
| Power Down XADC Mask. More...
#define | XSM_CFR2_PD_SHIFT 4
| Power Down Shift. More...
Configuration Register 3 (CFR3) mask(s)
#define | XSM_CFR3_ALM_ALL_MASK 0x000F
| Mask for all alarms. More...
#define | XSM_CFR3_ALM_VUSR3_MASK 0x0008
| VUSER 0 Supply. More...
#define | XSM_CFR3_ALM_VUSR2_MASK 0x0004
| VUSER 1 Supply. More...
#define | XSM_CFR3_ALM_VUSR1_MASK 0x0002
| VUSER 2 Supply. More...
#define | XSM_CFR3_ALM_VUSR0_MASK 0x0001
| VUSER 3 Supply. More...
#define | XSM_CFR_ALM_ALL_MASK 0xF0F0F
Alarm masks for channels in Configuration registers 1 and 3
#define | XSM_CFR_ALM_VUSR3_MASK 0x00080000
| VUSER 0 Supply. More...
#define | XSM_CFR_ALM_VUSR2_MASK 0x00040000
| VUSER 1 Supply. More...
#define | XSM_CFR_ALM_VUSR1_MASK 0x00020000
| VUSER 2 Supply. More...
#define | XSM_CFR_ALM_VUSR0_MASK 0x00010000
| VUSER 3 Supply. More...
#define | XSM_CFR_ALM_VCCPDRO_MASK 0x0800
| Alarm 6 - VCCPDRO, Zynq. More...
#define | XSM_CFR_ALM_VCCPAUX_MASK 0x0400
| Alarm 5 - VCCPAUX, Zynq. More...
#define | XSM_CFR_ALM_VCCPINT_MASK 0x0200
| Alarm 4 - VCCPINT, Zynq. More...
#define | XSM_CFR_ALM_VBRAM_MASK 0x0100
| Alarm 3 - VBRAM Enable 7 Series and Zynq. More...
#define | XSM_CFR_ALM_VCCAUX_MASK 0x0008
| Alarm 2 - VCCAUX Enable. More...
#define | XSM_CFR_ALM_VCCINT_MASK 0x0004
| Alarm 1 - VCCINT Enable. More...
#define | XSM_CFR_ALM_TEMP_MASK 0x0002
| Alarm 0 - Temperature. More...
#define | XSM_CFR_OT_MASK 0x0001
| Over Temperature Enable. More...
Sequence Register (SEQ) Bit Definitions
#define | XSM_SEQ_CH_CALIB 0x00000001
| ADC Calibration Channel. More...
#define | XSM_SEQ_CH_VCCPINT 0x00000020
| VCCPINT, Zynq Only. More...
#define | XSM_SEQ_CH_VCCPAUX 0x00000040
| VCCPAUX, Zynq Only. More...
#define | XSM_SEQ_CH_VCCPDRO 0x00000080
| VCCPDRO, Zynq Only. More...
#define | XSM_SEQ_CH_TEMP 0x00000100
| On Chip Temperature Channel. More...
#define | XSM_SEQ_CH_VCCINT 0x00000200
| VCCINT Channel. More...
#define | XSM_SEQ_CH_VCCAUX 0x00000400
| VCCAUX Channel. More...
#define | XSM_SEQ_CH_VPVN 0x00000800
| VP/VN analog inputs Channel. More...
#define | XSM_SEQ_CH_VREFP 0x00001000
| VREFP Channel. More...
#define | XSM_SEQ_CH_VREFN 0x00002000
| VREFN Channel. More...
#define | XSM_SEQ_CH_VBRAM 0x00004000
| VBRAM Channel, 7 series/Zynq. More...
#define | XSM_SEQ_CH_AUX00 0x00010000
| 1st Aux Channel More...
#define | XSM_SEQ_CH_AUX01 0x00020000
| 2nd Aux Channel More...
#define | XSM_SEQ_CH_AUX02 0x00040000
| 3rd Aux Channel More...
#define | XSM_SEQ_CH_AUX03 0x00080000
| 4th Aux Channel More...
#define | XSM_SEQ_CH_AUX04 0x00100000
| 5th Aux Channel More...
#define | XSM_SEQ_CH_AUX05 0x00200000
| 6th Aux Channel More...
#define | XSM_SEQ_CH_AUX06 0x00400000
| 7th Aux Channel More...
#define | XSM_SEQ_CH_AUX07 0x00800000
| 8th Aux Channel More...
#define | XSM_SEQ_CH_AUX08 0x01000000
| 9th Aux Channel More...
#define | XSM_SEQ_CH_AUX09 0x02000000
| 10th Aux Channel More...
#define | XSM_SEQ_CH_AUX10 0x04000000
| 11th Aux Channel More...
#define | XSM_SEQ_CH_AUX11 0x08000000
| 12th Aux Channel More...
#define | XSM_SEQ_CH_AUX12 0x10000000
| 13th Aux Channel More...
#define | XSM_SEQ_CH_AUX13 0x20000000
| 14th Aux Channel More...
#define | XSM_SEQ_CH_AUX14 0x40000000
| 15th Aux Channel More...
#define | XSM_SEQ_CH_AUX15 0x80000000
| 16th Aux Channel More...
#define | XSM_SEQ_CH_VUSR0 0x100000000
| VUSER0 Channel. More...
#define | XSM_SEQ_CH_VUSR1 0x200000000
| VUSER1 Channel. More...
#define | XSM_SEQ_CH_VUSR2 0x400000000
| VUSER2 Channel. More...
#define | XSM_SEQ_CH_VUSR3 0x800000000
| VUSER3 Channel. More...
#define | XSM_SEQ00_CH_VALID_MASK 0x7FE1
| Mask for the valid channels. More...
#define | XSM_SEQ01_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XSM_SEQ02_CH_VALID_MASK 0x7FE0
| Mask for the valid channels. More...
#define | XSM_SEQ03_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XSM_SEQ04_CH_VALID_MASK 0x0800
| Mask for the valid channels. More...
#define | XSM_SEQ05_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XSM_SEQ06_CH_VALID_MASK 0x0800
| Mask for the valid channels. More...
#define | XSM_SEQ07_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XSM_SEQ08_CH_VALID_MASK 0x000F
| Mask for the valid channels. More...
#define | XSM_SEQ09_CH_VALID_MASK 0x000F
| Mask for the valid channels. More...
#define | XSM_SEQ_CH_AUX_SHIFT 16
| Shift for the Aux Channel. More...
#define | XSM_SEQ_CH_VUSR_SHIFT 32
| Shift for the Aux Channel. More...
OT Upper Alarm Threshold Register Bit Definitions
#define | XSM_ATR_OT_UPPER_ENB_MASK 0x000F
| Mask for OT enable. More...
#define | XSM_ATR_OT_UPPER_VAL_MASK 0xFFF0
| Mask for OT value. More...
#define | XSM_ATR_OT_UPPER_VAL_SHIFT 4
| Shift for OT value. More...
#define | XSM_ATR_OT_UPPER_ENB_VAL 0x0003
| Value for OT enable. More...
#define | XSM_ATR_OT_UPPER_VAL_MAX 0x0FFF
| Max OT value. More...