dsi: Dsi_v1_1

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Data Structures | Macros | Typedefs | Enumerations | Functions
Dsi_v1_1

## Data Structures
struct | XDsi_ShortPacket
| This typedef contains the Short Packet information from the Generic Short Packet Register. More...
struct | XDsiTx_CmdModePkt
| MIPI DSI Command Mode configuration structure. More...
struct | XDsi_VideoTiming
| Video timing structure. More...
struct | XDsi_Config
| The configuration structure for DSI Controller This structure passes the hardware building information to the driver. More...
struct | XDsi_ConfigParameters
| The structure to read DSI controller & Configurable Parameters. More...
struct | XDsi
| The XDsi driver instance data. More...

## Macros
#define | NUM_PACKETS 64
| DSI Long packet supports upto 255 word counts - i.e 64 writes into data fifo. More...
#define | XDSI_MAX_LANES 4
| Max Lanes supported by DSI. More...

## Typedefs
typedef void(* | XDsi_Callback )(void *CallbackRef, u32 Mask)
| Callback type for all interrupts defined. More...

## Enumerations
enum | XDsi_DsiModeType
enum | XDsi_CmdModePktType
enum | XDsi_VideoMode
| Video Timing Mode by default Non-burst mode with Sync Events. More...

## Functions
u32 | XDsi_CfgInitialize (XDsi *InstancePtr, XDsi_Config *CfgPtr, UINTPTR EffectiveAddr)
| Initialize the XDsi instance provided by the caller based on the given Config structure. More...
void | XDsi_Reset (XDsi *InstancePtr)
| This function will do a reset of the IP. More...
u32 | XDsi_DefaultConfigure (XDsi *InstancePtr)
| This function will configure protocol reg with video mode, Blank packet mode, Blank packet Type, End of Transmisstion packet. More...
u32 | XDsi_Activate (XDsi *InstancePtr, XDsi_Selection Flag)
| This function will enable/disable the IP Core to start processing. More...
void | XDsi_SendShortPacket (XDsi *InstancePtr, XDsi_ShortPacket *ShortPacket)
| This function will send the short packet to DSI controller Generic Short Packet Register. More...
void | XDsi_SendLongPacket (XDsi *InstancePtr, XDsiTx_CmdModePkt *CmdPacket)
int | XDsi_SendCmdModePkt (XDsi *InstancePtr, XDsiTx_CmdModePkt *CmdPktData)
int | XDsi_SetMode (XDsi *InstancePtr, XDsi_DsiModeType mode)
void | XDsi_GetConfigParams (XDsi *InstancePtr, XDsi_ConfigParameters *ConfigInfo)
| This function will get the information from the GUI settings and other protocol control register values like video mode, Blank packet type, Packet Mode, EOTP value. More...
s32 | XDsi_SetVideoInterfaceTiming (XDsi *InstancePtr, XDsi_VideoMode VideoMode, XVidC_VideoMode Resolution, u16 BurstPacketSize)
| This function Set Timning mode and Resolution as per that it populate with Peripheral Timing Parameters from the video common library. More...
s32 | XDsi_SetCustomVideoInterfaceTiming (XDsi *InstancePtr, XDsi_VideoMode VideoMode, XDsi_VideoTiming *Timing)
| XDsi_SetCustomVideoInterfaceTiming Set Timning mode and Resolution as per user input. More...
XDsi_Config * | XDsi_LookupConfig (u32 DeviceId)
| Look up the hardware configuration for a device instance. More...
u32 | XDsi_SelfTest (XDsi *InstancePtr)
| Runs a self-test on the driver/device. More...
s32 | XDsi_SetCallback (XDsi *InstancePtr, u32 HandleType, void *CallbackFunc, void *CallbackRef)
| This routine installs an asynchronous callback function for the given HandlerType: More...
void | XDsi_InterruptEnable (XDsi *InstancePtr, u32 Mask)
| This function will enable the interrupts present in the interrupt mask passed onto the function. More...
void | XDsi_InterruptDisable (XDsi *InstancePtr, u32 Mask)
| This function will disable the interrupts present in the interrupt mask passed onto the function. More...
u32 | XDsi_InterruptGetEnabled (XDsi *InstancePtr)
| This function will get the interrupt mask set (enabled) in the DSI core. More...
u32 | XDsi_InterruptGetStatus (XDsi *InstancePtr)
| This function will get the list of interrupts Invoked in the Interrupt Status Register of the DSI core. More...
void | XDsi_InterruptClear (XDsi *InstancePtr, u32 Mask)
| This function will clear the interrupts set in the Interrupt Status Register of the DSI core. More...
void | XDsi_IntrHandler (void *InstancePtr)
| This function is the interrupt handler for the DSI core. More...

## Device registers
Register sets of MIPI DSI Tx
#define | XDSI_CCR_OFFSET 0x00000000
| Core Configuration Register Offset. More...
#define | XDSI_PCR_OFFSET 0x00000004
| Protocol Configuration Register Offset. More...
#define | XDSI_GIER_OFFSET 0x00000020
| Global Interrupt Register Offset. More...
#define | XDSI_ISR_OFFSET 0x00000024
| Interrupt Status Register. More...
#define | XDSI_IER_OFFSET 0x00000028
| Interrupt Enable Register. More...
#define | XDSI_STATUS_OFFSET 0x0000002C
| Status Register. More...
#define | XDSI_COMMAND_OFFSET 0x00000030
| Packet Entry to command Queue. More...
#define | XDSI_DATA_OFFSET 0x00000034
| Packet Data to data Queue. More...
#define | XDSI_TIME1_OFFSET 0x00000050
| Time 1 Offset. More...
#define | XDSI_TIME2_OFFSET 0x00000054
| Time 2 Offset. More...
#define | XDSI_TIME3_OFFSET 0x00000058
| Time 3 Offset. More...
#define | XDSI_TIME4_OFFSET 0x0000005C
| Time 4 Offset. More...
#define | XDSI_LTIME_OFFSET 0x00000060
| Total Line Timing Offset. More...
#define | XDSI_BLLP_TIME_OFFSET 0x00000064
| BLLP Time duration Offset. More...

## Core configuration register masks and shifts
This register is used for the enabling/disabling and resetting the core of DSI Tx Controller
#define | XDSI_CCR_RESET_CMD_FIFO_MASK 0x00000020
| Command FIFO Reset bit Mask. More...
#define | XDSI_CCR_RESET_DATA_FIFO_MASK 0x00000010
| Data FIFO Reset bit Mask. More...
#define | XDSI_CCR_CRREADY_MASK 0x00000004
| Controller Ready bit Mask. More...
#define | XDSI_CCR_SOFTRESET_MASK 0x00000002
| Soft Reset core bit Mask. More...
#define | XDSI_CCR_COREENB_MASK 0x00000001
| Enable/Disable core Mask. More...
#define | XDSI_CCR_CORECMDMODE_MASK 0x00000008
| Enable/Disable Command/video mode Mask. More...
#define | XDSI_CCR_CORECMDMODE_SHIFT 3
| Shift for selection of command/video mode. More...
#define | XDSI_CCR_CRREADY_SHIFT 2
| Shift for Controller Ready. More...
#define | XDSI_CCR_SOFTRESET_SHIFT 1
| Shift for Soft reset. More...
#define | XDSI_CCR_COREENB_SHIFT 0
| Shift for Core Enable. More...

## Bitmasks and shifts of Protocol control register
This register reports the number of lanes configured during core generation and number of lanes actively used.
#define | XDSI_PCR_EOTPENABLE_MASK 0x00002000
| End of Transmission Mask bit. More...
#define | XDSI_PCR_PIXELFORMAT_MASK 0x00001F80
| Pixel Format Type Bit Mask. More...
#define | XDSI_PCR_BLLPMODE_MASK 0x00000040
| Blank packet Mode Bit Mask. More...
#define | XDSI_PCR_BLLPTYPE_MASK 0x00000020
| Blank packet type Bit Mask. More...
#define | XDSI_PCR_VIDEOMODE_MASK 0x00000018
| Video mode Type Bit Mask. More...
#define | XDSI_PCR_ACTLANES_MASK 0x00000003
| Active lanes in core. More...
#define | XDSI_PCR_EOTPENABLE_SHIFT 13
| Shift for EOTP Enable. More...
#define | XDSI_PCR_PIXELFORMAT_SHIFT 7
| Shift for pixel format. More...
#define | XDSI_PCR_BLLPMODE_SHIFT 6
| Shift for Blank packet Type. More...
#define | XDSI_PCR_BLLPTYPE_SHIFT 5
| Shift for Blank packet Type. More...
#define | XDSI_PCR_VIDEOMODE_SHIFT 3
| Shift for Max Lanes. More...
#define | XDSI_PCR_ACTLANES_SHIFT 0
| Shift for Active Lanes. More...

## Bitmasks and shift of XDSI_STSTUS_OFFSET
This register used to get Command Queue Vacancy
#define | XDSI_UNDER_PROCESS_MASK 0x00001000
| Command Underprocess. More...
#define | XDSI_INPOGRESS_MASK 0x00000800
| Command InProgress. More...
#define | XDSI_WAIT_FOR_DATA_MASK 0x00000400
| Wait for Long packet data. More...
#define | XDSI_FIFO_EMPTY_MASK 0x00000200
| FIFO EMPTY. More...
#define | XDSI_FIFO_FULL_MASK 0x00000100
| FIFO FULL. More...
#define | XDSI_RDY_FOR_LONG_MASK 0x00000080
| Readiness for Long packet. More...
#define | XDSI_RDY_FOR_SHORT_MASK 0x00000040
| Readiness for short packet. More...
#define | XDSI_CMDQ_MASK 0x0000003F
| Command Queue Vacancy. More...
#define | XDSI_UNDER_PROCESS_SHIFT 12
| Command Underprocess. More...
#define | XDSI_INPOGRESS_SHIFT 11
| Command InProgress. More...
#define | XDSI_WAIT_FOR_DATA_SHIFT 10
| Wait for Long packet data. More...
#define | XDSI_FIFO_EMPTY_SHIFT 9
| FIFO EMPTY. More...
#define | XDSI_FIFO_FULL_SHIFT 8
| FIFO FULL. More...
#define | XDSI_RDY_FOR_LONGPKT_SHIFT 7
| Readiness for Long packet. More...
#define | XDSI_RDY_FOR_SHORTPKT_SHIFT 6
| Command Queue Vacancy. More...
#define | XDSI_CMDQ_SHIFT 0
| Shift for Command Queue. More...

## Bitmasks and shift of XDSI_TIME1_OFFSET
This register used to set timing parameters HSA and BLLP
#define | XDSI_TIME1_HSA_MASK 0xFFFF0000
| Horizontal timing parameter HSA mask. More...
#define | XDSI_TIME1_BLLP_BURST_MASK 0x0000FFFF
| BLLP Packet size Mask bit. More...
#define | XDSI_TIME1_HSA_SHIFT 16
| Shift for HSA. More...
#define | XDSI_TIME1_BLLP_BURST_SHIFT 0
| Shift for BLLP. More...

## Bitmasks and shift of XDSI_TIME2_OFFSET
This register used to set timing parameters
#define | XDSI_TIME2_HACT_MASK 0xFFFF0000
| Horizontal timing parameter HACT Bit Mask. More...
#define | XDSI_TIME2_VACT_MASK 0x0000FFFF
| Vertical timing parameter VACT. More...
#define | XDSI_TIME2_HACT_SHIFT 16
| Shift for HACT. More...
#define | XDSI_TIME2_VACT_SHIFT 0
| Shift for VACT. More...

## Bitmasks and shift of XDSI_TIME3_OFFSET
This register used to set timing parameters
#define | XDSI_TIME3_HBP_MASK 0xFFFF0000
| Horizontal timing parameter HBP Bit Mask. More...
#define | XDSI_TIME3_HFP_MASK 0x0000FFFF
| Horizontal timing parameter HFP. More...
#define | XDSI_TIME3_HBP_SHIFT 16
| Shift for HBP. More...
#define | XDSI_TIME3_HFP_SHIFT 0
| Shift for HFP. More...

## Bitmasks and offset of XDSI_TIME4_OFFSET
This register used to set Vertical timing parameters
#define | XDSI_TIME4_VSA_MASK 0x00FF0000
| Time 4 Vertical Sync Active Mask. More...
#define | XDSI_TIME4_VBP_MASK 0x0000FF00
| Vertical timing parameter1 VBP. More...
#define | XDSI_TIME4_VFP_MASK 0x000000FF
| Vertical timing parameter1 VFP. More...
#define | XDSI_TIME4_VSA_SHIFT 16
| Shift for VSA. More...
#define | XDSI_TIME4_VBP_SHIFT 8
| Shift for VBP. More...
#define | XDSI_TIME4_VFP_SHIFT 0
| Shift for VFP. More...

## Bitmasks and offsets of XDSI_GIER_OFFSET register
This register contains the global interrupt enable bit.
#define | XDSI_GIER_GIE_MASK 0x00000001
| Global Interrupt Enable bit. More...
#define | XDSI_GIER_GIE_SHIFT 0
| Shift bits for Global Interrupt Enable. More...
#define | XDSI_GIER_SET 1
| Enable the Global Interrupts. More...
#define | XDSI_GIER_RESET 0
| Disable the Global Interrupts. More...

## Bitmasks and offsets of XDSI_ISR_OFFSET register
This register contains the interrupt status.
#define | XDSI_ISR_CMDQ_FIFO_FULL_MASK 0x00000004
| Command queue vacancy full. More...
#define | XDSI_ISR_DATA_ID_ERR_MASK 0x00000002
| Unsupport datatype Error. More...
#define | XDSI_ISR_PXL_UNDR_RUN_MASK 0x00000001
| Pixel under run error. More...
#define | XDSI_ISR_ALLINTR_MASK 0x00000007
| All interrupts mask. More...
#define | XDSI_ISR_DATA_ID_ERR_SHIFT 1
| Shift for Unsupport Data Type. More...
#define | XDSI_ISR_PXL_UNDR_RUN_SHIFT 0
| Shift for Pixel under run. More...

## Bitmasks and offsets of XDSI_IER_OFFSET register
This register contains the interrupt enable masks
#define | XDSI_IER_CMDQ_FIFO_FULL_MASK 0x00000004
| Command queue vacancy full. More...
#define | XDSI_IER_DATA_ID_ERR_MASK 0x00000002
| Un supported data type. More...
#define | XDSI_IER_PXL_UNDR_RUN_MASK 0x00000001
| Pixel Under run. More...
#define | XDSI_IER_ALLINTR_MASK 0x00000007
| All interrupts mask. More...
#define | XDSI_IER_DATA_ID_ERR_SHIFT 1
| Shift for Unsupport data type. More...
#define | XDSI_IER_PXL_UNDR_RUN_SHIFT 0
| Shift for Pixel under run. More...

## Bitmasks and offsets of XDSI_COMMAND_OFFSET register
This register contains the short packet command TBD as now
#define | XDSI_SPKTR_DT_MASK 0x0000003F
| Data Type. More...
#define | XDSI_SPKTR_VC_MASK 0x000000C0
| Virtual channel number. More...
#define | XDSI_SPKTR_BYTE1_MASK 0x0000FF00
| BYTE1 mask. More...
#define | XDSI_SPKTR_BYTE2_MASK 0x00FF0000
| BYTE2 maks. More...
#define | XDSI_SPKTR_DT_SHIFT 0
| Shift for DataType. More...
#define | XDSI_SPKTR_VC_SHIFT 6
| Shift for VC. More...
#define | XDSI_SPKTR_BYTE1_SHIFT 8
| Shift for BYTE1. More...
#define | XDSI_SPKTR_BYTE2_SHIFT 16
| Shift for BYTE2. More...

## Bitmasks and offsets of XDSI_LTIME_OFFSET register
This register contains the Total Line Time
#define | XDSI_LTIME_MASK 0xFFFFFFFF
| Total Line time. More...
#define | XDSI_LTIME_SHIFT 0
| Shift for DataType. More...

## Bitmasks and offsets of XDSI_BBLP_SIZE_OFFSET register
This register contains the BLLP Time duration
#define | XDSI_BLLP_TIME_MASK 0xFFFFFFFF
| BLLP Size. More...
#define | XDSI_BLLP_TIME_SHIFT 0
| Shift for BLLP. More...

## Macro Definition Documentation

#define NUM_PACKETS 64

DSI Long packet supports upto 255 word counts - i.e 64 writes into data fifo.

#define XDSI_BLLP_TIME_MASK 0xFFFFFFFF

BLLP Size.

Referenced by XDsi_GetConfigParams().

#define XDSI_BLLP_TIME_OFFSET 0x00000064

BLLP Time duration Offset.

Referenced by XDsi_GetConfigParams().

#define XDSI_BLLP_TIME_SHIFT 0

Shift for BLLP.

Referenced by XDsi_GetConfigParams().

#define XDSI_CCR_CORECMDMODE_MASK 0x00000008

Enable/Disable Command/video mode Mask.

#define XDSI_CCR_CORECMDMODE_SHIFT 3

Shift for selection of command/video mode.

#define XDSI_CCR_COREENB_MASK 0x00000001

Enable/Disable core Mask.

#define XDSI_CCR_COREENB_SHIFT 0

Shift for Core Enable.

#define XDSI_CCR_CRREADY_MASK 0x00000004

Controller Ready bit Mask.

#define XDSI_CCR_CRREADY_SHIFT 2

Shift for Controller Ready.

#define XDSI_CCR_OFFSET 0x00000000

Core Configuration Register Offset.

#define XDSI_CCR_RESET_CMD_FIFO_MASK 0x00000020

Command FIFO Reset bit Mask.

#define XDSI_CCR_RESET_DATA_FIFO_MASK 0x00000010

Data FIFO Reset bit Mask.

#define XDSI_CCR_SOFTRESET_MASK 0x00000002

Soft Reset core bit Mask.

#define XDSI_CCR_SOFTRESET_SHIFT 1

Shift for Soft reset.

#define XDSI_CMDQ_MASK 0x0000003F

Command Queue Vacancy.

#define XDSI_CMDQ_SHIFT 0

Shift for Command Queue.

#define XDSI_COMMAND_OFFSET 0x00000030

Packet Entry to command Queue.

Referenced by XDsi_SendShortPacket().

#define XDSI_DATA_OFFSET 0x00000034

Packet Data to data Queue.

Referenced by XDsi_SendLongPacket().

#define XDSI_FIFO_EMPTY_MASK 0x00000200

FIFO EMPTY.

#define XDSI_FIFO_EMPTY_SHIFT 9

FIFO EMPTY.

#define XDSI_FIFO_FULL_MASK 0x00000100

FIFO FULL.

#define XDSI_FIFO_FULL_SHIFT 8

FIFO FULL.

#define XDSI_GIER_GIE_MASK 0x00000001

Global Interrupt Enable bit.

#define XDSI_GIER_GIE_SHIFT 0

Shift bits for Global Interrupt Enable.

#define XDSI_GIER_OFFSET 0x00000020

Global Interrupt Register Offset.

#define XDSI_GIER_RESET 0

Disable the Global Interrupts.

#define XDSI_GIER_SET 1

Enable the Global Interrupts.

#define XDSI_IER_ALLINTR_MASK 0x00000007

All interrupts mask.

Referenced by XDsi_InterruptClear(), XDsi_InterruptDisable(), and XDsi_InterruptEnable().

#define XDSI_IER_CMDQ_FIFO_FULL_MASK 0x00000004

Command queue vacancy full.

Referenced by XDsi_IntrHandler().

#define XDSI_IER_DATA_ID_ERR_MASK 0x00000002

Un supported data type.

Referenced by XDsi_IntrHandler().

#define XDSI_IER_DATA_ID_ERR_SHIFT 1

Shift for Unsupport data type.

#define XDSI_IER_OFFSET 0x00000028

Interrupt Enable Register.

#define XDSI_IER_PXL_UNDR_RUN_MASK 0x00000001

Pixel Under run.

Referenced by XDsi_IntrHandler().

#define XDSI_IER_PXL_UNDR_RUN_SHIFT 0

Shift for Pixel under run.

#define XDSI_INPOGRESS_MASK 0x00000800

Command InProgress.

#define XDSI_INPOGRESS_SHIFT 11

Command InProgress.

#define XDSI_ISR_ALLINTR_MASK 0x00000007

All interrupts mask.

#define XDSI_ISR_CMDQ_FIFO_FULL_MASK 0x00000004

Command queue vacancy full.

#define XDSI_ISR_DATA_ID_ERR_MASK 0x00000002

Unsupport datatype Error.

#define XDSI_ISR_DATA_ID_ERR_SHIFT 1

Shift for Unsupport Data Type.

#define XDSI_ISR_OFFSET 0x00000024

Interrupt Status Register.

#define XDSI_ISR_PXL_UNDR_RUN_MASK 0x00000001

Pixel under run error.

#define XDSI_ISR_PXL_UNDR_RUN_SHIFT 0

Shift for Pixel under run.

#define XDSI_LTIME_MASK 0xFFFFFFFF

Total Line time.

Referenced by XDsi_GetConfigParams().

#define XDSI_LTIME_OFFSET 0x00000060

Total Line Timing Offset.

Referenced by XDsi_GetConfigParams().

#define XDSI_LTIME_SHIFT 0

Shift for DataType.

Referenced by XDsi_GetConfigParams().

#define XDSI_MAX_LANES 4

Max Lanes supported by DSI.

#define XDSI_PCR_ACTLANES_MASK 0x00000003

Active lanes in core.

Referenced by XDsi_SelfTest().

#define XDSI_PCR_ACTLANES_SHIFT 0

Shift for Active Lanes.

Referenced by XDsi_SelfTest().

#define XDSI_PCR_BLLPMODE_MASK 0x00000040

Blank packet Mode Bit Mask.

Referenced by XDsi_DefaultConfigure(), and XDsi_GetConfigParams().

#define XDSI_PCR_BLLPMODE_SHIFT 6

Shift for Blank packet Type.

Referenced by XDsi_DefaultConfigure(), and XDsi_GetConfigParams().

#define XDSI_PCR_BLLPTYPE_MASK 0x00000020

Blank packet type Bit Mask.

Referenced by XDsi_DefaultConfigure(), and XDsi_GetConfigParams().

#define XDSI_PCR_BLLPTYPE_SHIFT 5

Shift for Blank packet Type.

Referenced by XDsi_DefaultConfigure(), and XDsi_GetConfigParams().

#define XDSI_PCR_EOTPENABLE_MASK 0x00002000

End of Transmission Mask bit.

Referenced by XDsi_DefaultConfigure(), and XDsi_GetConfigParams().

#define XDSI_PCR_EOTPENABLE_SHIFT 13

Shift for EOTP Enable.

Referenced by XDsi_DefaultConfigure(), and XDsi_GetConfigParams().

#define XDSI_PCR_OFFSET 0x00000004

Protocol Configuration Register Offset.

Referenced by XDsi_DefaultConfigure(), XDsi_GetConfigParams(), XDsi_SelfTest(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_PCR_PIXELFORMAT_MASK 0x00001F80

Pixel Format Type Bit Mask.

#define XDSI_PCR_PIXELFORMAT_SHIFT 7

Shift for pixel format.

#define XDSI_PCR_VIDEOMODE_MASK 0x00000018

Video mode Type Bit Mask.

Referenced by XDsi_DefaultConfigure(), XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_PCR_VIDEOMODE_SHIFT 3

Shift for Max Lanes.

Referenced by XDsi_DefaultConfigure(), XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_RDY_FOR_LONG_MASK 0x00000080

Readiness for Long packet.

#define XDSI_RDY_FOR_LONGPKT_SHIFT 7

Readiness for Long packet.

#define XDSI_RDY_FOR_SHORT_MASK 0x00000040

Readiness for short packet.

#define XDSI_RDY_FOR_SHORTPKT_SHIFT 6

Command Queue Vacancy.

#define XDSI_SPKTR_BYTE1_MASK 0x0000FF00

BYTE1 mask.

#define XDSI_SPKTR_BYTE1_SHIFT 8

Shift for BYTE1.

Referenced by XDsi_SendShortPacket().

#define XDSI_SPKTR_BYTE2_MASK 0x00FF0000

BYTE2 maks.

#define XDSI_SPKTR_BYTE2_SHIFT 16

Shift for BYTE2.

Referenced by XDsi_SendShortPacket().

#define XDSI_SPKTR_DT_MASK 0x0000003F

Data Type.

#define XDSI_SPKTR_DT_SHIFT 0

Shift for DataType.

#define XDSI_SPKTR_VC_MASK 0x000000C0

Virtual channel number.

#define XDSI_SPKTR_VC_SHIFT 6

Shift for VC.

Referenced by XDsi_SendShortPacket().

#define XDSI_STATUS_OFFSET 0x0000002C

Status Register.

#define XDSI_TIME1_BLLP_BURST_MASK 0x0000FFFF

BLLP Packet size Mask bit.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME1_BLLP_BURST_SHIFT 0

Shift for BLLP.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME1_HSA_MASK 0xFFFF0000

Horizontal timing parameter HSA mask.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME1_HSA_SHIFT 16

Shift for HSA.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME1_OFFSET 0x00000050

Time 1 Offset.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME2_HACT_MASK 0xFFFF0000

Horizontal timing parameter HACT Bit Mask.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME2_HACT_SHIFT 16

Shift for HACT.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME2_OFFSET 0x00000054

Time 2 Offset.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME2_VACT_MASK 0x0000FFFF

Vertical timing parameter VACT.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME2_VACT_SHIFT 0

Shift for VACT.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME3_HBP_MASK 0xFFFF0000

Horizontal timing parameter HBP Bit Mask.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME3_HBP_SHIFT 16

Shift for HBP.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME3_HFP_MASK 0x0000FFFF

Horizontal timing parameter HFP.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME3_HFP_SHIFT 0

Shift for HFP.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME3_OFFSET 0x00000058

Time 3 Offset.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME4_OFFSET 0x0000005C

Time 4 Offset.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME4_VBP_MASK 0x0000FF00

Vertical timing parameter1 VBP.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME4_VBP_SHIFT 8

Shift for VBP.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME4_VFP_MASK 0x000000FF

Vertical timing parameter1 VFP.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME4_VFP_SHIFT 0

Shift for VFP.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME4_VSA_MASK 0x00FF0000

Time 4 Vertical Sync Active Mask.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_TIME4_VSA_SHIFT 16

Shift for VSA.

Referenced by XDsi_GetConfigParams(), XDsi_SetCustomVideoInterfaceTiming(), and XDsi_SetVideoInterfaceTiming().

#define XDSI_UNDER_PROCESS_MASK 0x00001000

Command Underprocess.

#define XDSI_UNDER_PROCESS_SHIFT 12

Command Underprocess.

#define XDSI_WAIT_FOR_DATA_MASK 0x00000400

Wait for Long packet data.

#define XDSI_WAIT_FOR_DATA_SHIFT 10

Wait for Long packet data.

## Typedef Documentation

typedef void(* XDsi_Callback)(void *CallbackRef, u32 Mask)

Callback type for all interrupts defined.

Parameters

  CallBackRef | is a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked.
  Mask | is a bit mask indicating the cause of the event. For current core version, this parameter is "OR" of 0 or more XDSI_ISR_*_MASK constants defined in xdsi_hw.h.

Returns
  None.

Note
  None.

## Enumeration Type Documentation

enum XDsi_CmdModePktType

- This typedef contains the type of Command mode Packet

enum XDsi_DsiModeType

- This typedef contains the DSI mode selection

enum XDsi_VideoMode

Video Timing Mode by default Non-burst mode with Sync Events.

## Function Documentation

u32 XDsi_Activate | ( | XDsi * | InstancePtr,
|  | XDsi_Selection | Flag
| ) |  |

This function will enable/disable the IP Core to start processing.

Parameters

  InstancePtr | is the XDsi instance to operate on.
  Flag | will be used to indicate Enable or Disable action.

Returns
  - XST_SUCCESS On enabling/disabling the core.

- XST_INVALID_PARAM if user passes invalid parameter.

Note
  None.

References XDsi::IsReady.

u32 XDsi_CfgInitialize | ( | XDsi * | InstancePtr,
|  | XDsi_Config * | CfgPtr,
|  | UINTPTR | EffectiveAddr
| ) |  |

Initialize the XDsi instance provided by the caller based on the given Config structure.

Parameters

  InstancePtr | is the XDsi instance to operate on.
  CfgPtr | is the device configuration structure containing information about a specific DSI.
  EffectiveAddr | is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.

Returns
  - XST_SUCCESS Initialization was successful.
  - XST_FAILURE Initialization was unsuccessful.

Note
  None.

References XDsi_Config::BaseAddr, XDsi::CmdQFIFOFullCallback, XDsi::Config, XDsi::ErrorCallback, XDsi::IsReady, XDsi::PixelDataUnderrunCallback, and XDsi::UnSupportedDataTypeCallback.

Referenced by DsiSelfTestExample().

u32 XDsi_DefaultConfigure | ( | XDsi * | InstancePtr | ) |

This function will configure protocol reg with video mode, Blank packet mode, Blank packet Type, End of Transmisstion packet.

Parameters

  InstancePtr | is the XDsi instance to operate on.

Returns
  - XST_SUCCESS On enabling the core.

Note
  None.

References XDsi::BlankPacketType, XDsi::BLLPMode, XDsi::EoTp, XDsi::IsReady, XDsi::VideoMode, XDSI_PCR_BLLPMODE_MASK, XDSI_PCR_BLLPMODE_SHIFT, XDSI_PCR_BLLPTYPE_MASK, XDSI_PCR_BLLPTYPE_SHIFT, XDSI_PCR_EOTPENABLE_MASK, XDSI_PCR_EOTPENABLE_SHIFT, XDSI_PCR_OFFSET, XDSI_PCR_VIDEOMODE_MASK, and XDSI_PCR_VIDEOMODE_SHIFT.

void XDsi_GetConfigParams | ( | XDsi * | InstancePtr,
|  | XDsi_ConfigParameters * | ConfigInfo
| ) |  |

This function will get the information from the GUI settings and other protocol control register values like video mode, Blank packet type, Packet Mode, EOTP value.

Parameters

  InstancePtr | is the XDsi instance to operate on
  ConfigInfo | is going to be filled up by this function and returned to the caller.

Returns
  None.

Note
  None.

References XDsi_Config::BaseAddr, XDsi_ConfigParameters::BlankPacketType, XDsi_VideoTiming::BLLPBurst, XDsi_ConfigParameters::BLLPMode, XDsi_ConfigParameters::BLLPTime, XDsi_ConfigParameters::Config, XDsi::Config, XDsi_ConfigParameters::EoTp, XDsi_VideoTiming::HActive, XDsi_VideoTiming::HBackPorch, XDsi_VideoTiming::HFrontPorch, XDsi_VideoTiming::HSyncWidth, XDsi_ConfigParameters::LineTime, XDsi_ConfigParameters::Timing, XDsi_VideoTiming::VActive, XDsi_VideoTiming::VBackPorch, XDsi_VideoTiming::VFrontPorch, XDsi_ConfigParameters::VideoMode, XDsi_VideoTiming::VSyncWidth, XDSI_BLLP_TIME_MASK, XDSI_BLLP_TIME_OFFSET, XDSI_BLLP_TIME_SHIFT, XDSI_LTIME_MASK, XDSI_LTIME_OFFSET, XDSI_LTIME_SHIFT, XDSI_PCR_BLLPMODE_MASK, XDSI_PCR_BLLPMODE_SHIFT, XDSI_PCR_BLLPTYPE_MASK, XDSI_PCR_BLLPTYPE_SHIFT, XDSI_PCR_EOTPENABLE_MASK, XDSI_PCR_EOTPENABLE_SHIFT, XDSI_PCR_OFFSET, XDSI_PCR_VIDEOMODE_MASK, XDSI_PCR_VIDEOMODE_SHIFT, XDSI_TIME1_BLLP_BURST_MASK, XDSI_TIME1_BLLP_BURST_SHIFT, XDSI_TIME1_HSA_MASK, XDSI_TIME1_HSA_SHIFT, XDSI_TIME1_OFFSET, XDSI_TIME2_HACT_MASK, XDSI_TIME2_HACT_SHIFT, XDSI_TIME2_OFFSET, XDSI_TIME2_VACT_MASK, XDSI_TIME2_VACT_SHIFT, XDSI_TIME3_HBP_MASK, XDSI_TIME3_HBP_SHIFT, XDSI_TIME3_HFP_MASK, XDSI_TIME3_HFP_SHIFT, XDSI_TIME3_OFFSET, XDSI_TIME4_OFFSET, XDSI_TIME4_VBP_MASK, XDSI_TIME4_VBP_SHIFT, XDSI_TIME4_VFP_MASK, XDSI_TIME4_VFP_SHIFT, XDSI_TIME4_VSA_MASK, and XDSI_TIME4_VSA_SHIFT.

void XDsi_InterruptClear | ( | XDsi * | InstancePtr,
|  | u32 | Mask
| ) |  |

This function will clear the interrupts set in the Interrupt Status Register of the DSI core.

Parameters

  InstancePtr | is the XDsi instance to operate on
  Mask | is Interrupt Mask with bits set for corresponding interrupt to be cleared in the Interrupt Status register

Returns
  None

Note
  None

References XDSI_IER_ALLINTR_MASK.

Referenced by XDsi_IntrHandler().

void XDsi_InterruptDisable | ( | XDsi * | InstancePtr,
|  | u32 | Mask
| ) |  |

This function will disable the interrupts present in the interrupt mask passed onto the function.

Parameters

  InstancePtr | is the XDsi instance to operate on
  Mask | is the interrupt mask which need to be enabled in core

Returns
  None

Note
  None

References XDSI_IER_ALLINTR_MASK.

void XDsi_InterruptEnable | ( | XDsi * | InstancePtr,
|  | u32 | Mask
| ) |  |

This function will enable the interrupts present in the interrupt mask passed onto the function.

Parameters

  InstancePtr | is the XDsi instance to operate on
  Mask | is the interrupt mask which need to be enabled in core

Returns
  None

Note
  None

References XDSI_IER_ALLINTR_MASK.

u32 XDsi_InterruptGetEnabled | ( | XDsi * | InstancePtr | ) |

This function will get the interrupt mask set (enabled) in the DSI core.

Parameters

  InstancePtr | is the XDsi instance to operate on

Returns
  Interrupt Mask with bits set for corresponding interrupt in Interrupt enable register

Note
  None

u32 XDsi_InterruptGetStatus | ( | XDsi * | InstancePtr | ) |

This function will get the list of interrupts Invoked in the Interrupt Status Register of the DSI core.

Parameters

  InstancePtr | is the XDsi instance to operate on

Returns
  Interrupt Mask with bits set for corresponding interrupt in Interrupt Status register

Note
  None

Referenced by XDsi_IntrHandler().

void XDsi_IntrHandler | ( | void * | InstancePtr | ) |

This function is the interrupt handler for the DSI core.

This handler reads the Invoked interrupt from the Interrupt Status register determines the source of the interrupts and calls the respective callbacks for the interrupts that are enabled in Interrupt Enable register and finally clears the interrupts.

The application is responsible for connecting this function to the interrupt system. Application beyond this core is also responsible for providing callbacks to handle interrupts and installing the callbacks using XDsi_SetCallback() during initialization phase.

Parameters

  InstancePtr | is a pointer to the XDsi core instance.

Returns
  None.

Note
  Interrupt should be enabled to execute interrupt handler.

References XDsi::CmdQFIFOFullCallback, XDsi::CmdQFIFOFullRef, XDsi::IsReady, XDsi::PixelDataUnderrunCallback, XDsi::PixelDataUnderrundRef, XDsi::UnsupportDataTypeRef, XDsi::UnSupportedDataTypeCallback, XDSI_IER_CMDQ_FIFO_FULL_MASK, XDSI_IER_DATA_ID_ERR_MASK, XDSI_IER_PXL_UNDR_RUN_MASK, XDsi_InterruptClear(), and XDsi_InterruptGetStatus().

XDsi_Config * XDsi_LookupConfig | ( | u32 | DeviceId | ) |

Look up the hardware configuration for a device instance.

Parameters

  DeviceId | is the unique device ID of the device to lookup for

Returns
  The reference to the configuration record in the configuration table (in xdsi_g.c) corresponding to the Device ID or if not found, a NULL pointer is returned.

Note
  None

Referenced by DsiSelfTestExample().

void XDsi_Reset | ( | XDsi * | InstancePtr | ) |

This function will do a reset of the IP.

Register ISR gets reset. Internal FIFO(command queue) gets flushed. FSM stops processing further packets. Controller gracefully ends by waiting for the current sub-block in operation to complete its task and mark next byte as LP byte to end the transfer. Once soft reset is released, controller start from VSS packet. (that is new video frame)

Parameters

  InstancePtr | is the XDsi instance to operate on.

Returns
  None.

Note
  None.

u32 XDsi_SelfTest | ( | XDsi * | InstancePtr | ) |

Runs a self-test on the driver/device.

This test checks if the LaneCount present in register matches the one from the generated file.

Parameters

  InstancePtr | is a pointer to the XDsi instance.

Returns
  - XST_SUCCESS if self-test was successful
  - XST_FAILURE if the read value was not equal to GUI parameter

Note
  None

References XDsi_Config::BaseAddr, XDsi::Config, XDsi_Config::DsiLanes, XDsi::IsReady, XDSI_PCR_ACTLANES_MASK, XDSI_PCR_ACTLANES_SHIFT, and XDSI_PCR_OFFSET.

Referenced by DsiSelfTestExample().

int XDsi_SendCmdModePkt | ( | XDsi * | InstancePtr,
|  | XDsiTx_CmdModePkt * | CmdPktData
| ) |  |

- This function sets the mode to send short packet.
- Parameters

    InstancePtr | is the XDsiTxSs instance to operate on

- Parameters

    CmdPacket | is the cmd mode short pkt structure to operate on

- Returns
    - XST_SUCCESS is returned if DSI mode packet was successfully sent
  - XST_FAILURE is returned if DSI mode packet is not found
- Note
    None.

References XDsiTx_CmdModePkt::CmdPkt, XDsiTx_CmdModePkt::SpktData, XDsi_SendLongPacket(), and XDsi_SendShortPacket().

void XDsi_SendLongPacket | ( | XDsi * | InstancePtr,
|  | XDsiTx_CmdModePkt * | CmdPacket
| ) |  |

- This function will send the long packet.
- Parameters

    InstancePtr | is the XDsiTxSs instance to operate on

- Parameters

    CmdPacket | is the cmd mode long packet structure to operate on

- Returns
    None
- Note
    None.

References XDsi_Config::BaseAddr, XDsi::Config, XDsi_ShortPacket::Data0, XDsiTx_CmdModePkt::LongPktData, XDsiTx_CmdModePkt::SpktData, XDSI_DATA_OFFSET, and XDsi_SendShortPacket().

Referenced by XDsi_SendCmdModePkt().

void XDsi_SendShortPacket | ( | XDsi * | InstancePtr,
|  | XDsi_ShortPacket * | ShortPacket
| ) |  |

This function will send the short packet to DSI controller Generic Short Packet Register.

Application will fill up this structure and use this API to send short packet

Parameters

  InstancePtr | is the XDsi instance to operate on
  ShortPacket | is going to be filled up by this function and returned to the caller.

Returns
  None.

Note
  None.

References XDsi_Config::BaseAddr, XDsi::Config, XDsi_ShortPacket::Data0, XDsi_ShortPacket::Data1, XDsi_ShortPacket::DataType, XDsi_ShortPacket::VcId, XDSI_COMMAND_OFFSET, XDSI_SPKTR_BYTE1_SHIFT, XDSI_SPKTR_BYTE2_SHIFT, and XDSI_SPKTR_VC_SHIFT.

Referenced by XDsi_SendCmdModePkt(), and XDsi_SendLongPacket().

s32 XDsi_SetCallback | ( | XDsi * | InstancePtr,
|  | u32 | HandleType,
|  | void * | CallbackFunc,
|  | void * | CallbackRef
| ) |  |

This routine installs an asynchronous callback function for the given HandlerType:

    HandlerType                     Invoked by this driver when:
    -----------------------  --------------------------------------------------
    XDSI_HANDLER_UNSUPPORT_DATATYPE Un support data type detected
    XDSI_HANDLER_PIXELDATA_UNDERRUN Byte stream FIFO starves for Pixel during
                                      HACT transmission
    XDSI_HANDLER_OTHERERROR  Any other type of interrupt has occured like
                               Stream Line Buffer Full, Incorrect Lanes, etc
    XDSI_HANDLER_CMDQ_FIFOFULL Command queue FIFO full

Parameters

  InstancePtr | is the XDsi instance to operate on
  HandleType | is the type of call back to be registered.
  CallbackFunc | is the pointer to a call back funtion which is called when a particular event occurs.
  CallbackRef | is a void pointer to data to be referenced to by the CallbackFunc

Returns
  - XST_SUCCESS when handler is installed.

- XST_INVALID_PARAM when HandlerType is invalid.

Note
  Invoking this function for a handler that already has been installed replaces it with the new handler.

References XDsi::CmdQFIFOFullCallback, XDsi::CmdQFIFOFullRef, XDsi::ErrorCallback, XDsi::ErrRef, XDsi::IsReady, XDsi::PixelDataUnderrunCallback, XDsi::PixelDataUnderrundRef, XDsi::UnsupportDataTypeRef, and XDsi::UnSupportedDataTypeCallback.

s32 XDsi_SetCustomVideoInterfaceTiming | ( | XDsi * | InstancePtr,
|  | XDsi_VideoMode | VideoMode,
|  | XDsi_VideoTiming * | Timing
| ) |  |

XDsi_SetCustomVideoInterfaceTiming Set Timning mode and Resolution as per user input.

Parameters

  InstancePtr | is the XDsi instance to operate on
  VideoMode | Specifies mode of Interfacing
  Timing | Video Timing parameters

Returns
  - XST_SUCCESS is returned if Video interfacing was successfully set.

Note
  None.

References XDsi_Config::BaseAddr, XDsi_VideoTiming::BLLPBurst, XDsi::Config, XDsi_VideoTiming::HActive, XDsi_VideoTiming::HBackPorch, XDsi_VideoTiming::HFrontPorch, XDsi_VideoTiming::HSyncWidth, XDsi_VideoTiming::VActive, XDsi_VideoTiming::VBackPorch, XDsi_VideoTiming::VFrontPorch, XDsi_VideoTiming::VSyncWidth, XDSI_PCR_OFFSET, XDSI_PCR_VIDEOMODE_MASK, XDSI_PCR_VIDEOMODE_SHIFT, XDSI_TIME1_BLLP_BURST_MASK, XDSI_TIME1_BLLP_BURST_SHIFT, XDSI_TIME1_HSA_MASK, XDSI_TIME1_HSA_SHIFT, XDSI_TIME1_OFFSET, XDSI_TIME2_HACT_MASK, XDSI_TIME2_HACT_SHIFT, XDSI_TIME2_OFFSET, XDSI_TIME2_VACT_MASK, XDSI_TIME2_VACT_SHIFT, XDSI_TIME3_HBP_MASK, XDSI_TIME3_HBP_SHIFT, XDSI_TIME3_HFP_MASK, XDSI_TIME3_HFP_SHIFT, XDSI_TIME3_OFFSET, XDSI_TIME4_OFFSET, XDSI_TIME4_VBP_MASK, XDSI_TIME4_VBP_SHIFT, XDSI_TIME4_VFP_MASK, XDSI_TIME4_VFP_SHIFT, XDSI_TIME4_VSA_MASK, and XDSI_TIME4_VSA_SHIFT.

int XDsi_SetMode | ( | XDsi * | InstancePtr,
|  | XDsi_DsiModeType | mode
| ) |  |

- This function sets the mode to send short packet.
- Parameters

    InstancePtr | is the XDsiTxSs instance to operate on

- Parameters

    mode | is the DSI mode (video or command) to operate on

- Returns
    - XST_SUCCESS is returned if DSI mode(command/video) was successfully set
  - XST_INVALID_PARAM is returned if DSI mode is not found
- Note
    None.

s32 XDsi_SetVideoInterfaceTiming | ( | XDsi * | InstancePtr,
|  | XDsi_VideoMode | VideoMode,
|  | XVidC_VideoMode | Resolution,
|  | u16 | BurstPacketSize
| ) |  |

This function Set Timning mode and Resolution as per that it populate with Peripheral Timing Parameters from the video common library.

Parameters

  InstancePtr | is the XDsi instance to operate on
  VideoMode | Specifies mode of Interfacing
  Resolution | sets the resolution
  BurstPacketSize | sets the packet size

Returns
  - XST_SUCCESS is returned if Video interfacing was successfully set
  - XST_FAILURE is returned if TimingMode is not found

Note
  None.

References XDsi_Config::BaseAddr, XDsi::Config, XDSI_PCR_OFFSET, XDSI_PCR_VIDEOMODE_MASK, XDSI_PCR_VIDEOMODE_SHIFT, XDSI_TIME1_BLLP_BURST_MASK, XDSI_TIME1_BLLP_BURST_SHIFT, XDSI_TIME1_HSA_MASK, XDSI_TIME1_HSA_SHIFT, XDSI_TIME1_OFFSET, XDSI_TIME2_HACT_MASK, XDSI_TIME2_HACT_SHIFT, XDSI_TIME2_OFFSET, XDSI_TIME2_VACT_MASK, XDSI_TIME2_VACT_SHIFT, XDSI_TIME3_HBP_MASK, XDSI_TIME3_HBP_SHIFT, XDSI_TIME3_HFP_MASK, XDSI_TIME3_HFP_SHIFT, XDSI_TIME3_OFFSET, XDSI_TIME4_OFFSET, XDSI_TIME4_VBP_MASK, XDSI_TIME4_VBP_SHIFT, XDSI_TIME4_VFP_MASK, XDSI_TIME4_VFP_SHIFT, XDSI_TIME4_VSA_MASK, and XDSI_TIME4_VSA_SHIFT.