vphy: Xvphy_v1_9

| vphy Xilinx SDK Drivers API Documentation

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Xvphy_v1_9

## Data Structures
struct | XVphy_PllParam
| This typedef contains configuration information for CPLL/QPLL programming. More...
struct | XVphy_Channel
| This typedef contains configuration information for PLL type and its reference clock. More...
struct | XVphy_Mmcm
| This typedef contains configuration information for MMCM programming. More...
struct | XVphy_Quad
| This typedef represents a GT quad. More...
struct | XVphy_Log
| This typedef contains the logging mechanism for debug. More...
struct | XVphy_Config
| This typedef contains configuration information for the Video PHY core. More...
struct | XVphy
| The XVphy driver instance data. More...

## Macros
#define | XVphy_ReadReg(BaseAddress, RegOffset) XVphy_In32((BaseAddress) + (RegOffset))
| This is a low-level function that reads from the specified register. More...
#define | XVphy_WriteReg(BaseAddress, RegOffset, Data) XVphy_Out32((BaseAddress) + (RegOffset), (Data))
| This is a low-level function that writes to the specified register. More...

## Typedefs
typedef void(* | XVphy_IntrHandler )(void *InstancePtr)
| Callback type which represents the handler for interrupts. More...
typedef void(* | XVphy_TimerHandler )(void *InstancePtr, u32 MicroSeconds)
| Callback type which represents a custom timer wait handler. More...
typedef void(* | XVphy_Callback )(void *CallbackRef)
| Generic callback type. More...
typedef void(* | XVphy_ErrorCallback )(void *CallbackRef)
| Error callback type. More...

## Enumerations
enum | XVphy_ProtocolType
| This typedef enumerates the various protocols handled by the Video PHY controller (VPHY). More...
enum | XVphy_IntrHandlerType
| This typedef enumerates the list of available interrupt handler types. More...
enum | XVphy_HdmiHandlerType { XVPHY_HDMI_HANDLER_TXINIT = 1, XVPHY_HDMI_HANDLER_TXREADY, XVPHY_HDMI_HANDLER_RXINIT, XVPHY_HDMI_HANDLER_RXREADY }
| This typedef enumerates the list of available hdmi handler types. More...
enum | XVphy_PllType
| This typedef enumerates the different PLL types for a given GT channel. More...
enum | XVphy_ChannelId
| This typedef enumerates the available channels. More...
enum | XVphy_PllRefClkSelType
| This typedef enumerates the available reference clocks for the PLL clock selection multiplexer. More...
enum | XVphy_SysClkDataSelType
| This typedef enumerates the available reference clocks used to drive the RX/TX datapaths. More...
enum | XVphy_SysClkOutSelType
| This typedef enumerates the available reference clocks used to drive the RX/TX output clocks. More...
enum | XVphy_OutClkSelType
| This typedef enumerates the available clocks that are used as multiplexer input selections for the RX/TX output clock. More...
enum | XVphy_GtState { XVPHY_GT_STATE_IDLE, XVPHY_GT_STATE_LOCK, XVPHY_GT_STATE_RESET, XVPHY_GT_STATE_ALIGN, XVPHY_GT_STATE_READY }
enum | XVphy_LogEvent { XVPHY_LOG_EVT_NONE = 1, XVPHY_LOG_EVT_QPLL_EN, XVPHY_LOG_EVT_QPLL_RST, XVPHY_LOG_EVT_QPLL_LOCK, XVPHY_LOG_EVT_QPLL_RECONFIG, XVPHY_LOG_EVT_QPLL0_EN, XVPHY_LOG_EVT_QPLL0_RST, XVPHY_LOG_EVT_QPLL0_LOCK, XVPHY_LOG_EVT_QPLL0_RECONFIG, XVPHY_LOG_EVT_QPLL1_EN, XVPHY_LOG_EVT_QPLL1_RST, XVPHY_LOG_EVT_QPLL1_LOCK, XVPHY_LOG_EVT_QPLL1_RECONFIG, XVPHY_LOG_EVT_PLL0_EN, XVPHY_LOG_EVT_PLL0_RST, XVPHY_LOG_EVT_PLL0_LOCK, XVPHY_LOG_EVT_PLL0_RECONFIG, XVPHY_LOG_EVT_PLL1_EN, XVPHY_LOG_EVT_PLL1_RST, XVPHY_LOG_EVT_PLL1_LOCK, XVPHY_LOG_EVT_PLL1_RECONFIG, XVPHY_LOG_EVT_CPLL_EN, XVPHY_LOG_EVT_CPLL_RST, XVPHY_LOG_EVT_CPLL_LOCK, XVPHY_LOG_EVT_CPLL_RECONFIG, XVPHY_LOG_EVT_TXPLL_EN, XVPHY_LOG_EVT_TXPLL_RST, XVPHY_LOG_EVT_RXPLL_EN, XVPHY_LOG_EVT_RXPLL_RST, XVPHY_LOG_EVT_GTRX_RST, XVPHY_LOG_EVT_GTTX_RST, XVPHY_LOG_EVT_VID_TX_RST, XVPHY_LOG_EVT_VID_RX_RST, XVPHY_LOG_EVT_TX_ALIGN, XVPHY_LOG_EVT_TX_ALIGN_TMOUT, XVPHY_LOG_EVT_TX_TMR, XVPHY_LOG_EVT_RX_TMR, XVPHY_LOG_EVT_GT_RECONFIG, XVPHY_LOG_EVT_GT_TX_RECONFIG, XVPHY_LOG_EVT_GT_RX_RECONFIG, XVPHY_LOG_EVT_INIT, XVPHY_LOG_EVT_TXPLL_RECONFIG, XVPHY_LOG_EVT_RXPLL_RECONFIG, XVPHY_LOG_EVT_RXPLL_LOCK, XVPHY_LOG_EVT_TXPLL_LOCK, XVPHY_LOG_EVT_TX_RST_DONE, XVPHY_LOG_EVT_RX_RST_DONE, XVPHY_LOG_EVT_TX_FREQ, XVPHY_LOG_EVT_RX_FREQ, XVPHY_LOG_EVT_DRU_EN, XVPHY_LOG_EVT_GT_PLL_LAYOUT, XVPHY_LOG_EVT_GT_UNBONDED, XVPHY_LOG_EVT_1PPC_ERR, XVPHY_LOG_EVT_PPC_MSMTCH_ERR, XVPHY_LOG_EVT_VDCLK_HIGH_ERR, XVPHY_LOG_EVT_NO_DRU, XVPHY_LOG_EVT_GT_QPLL_CFG_ERR, XVPHY_LOG_EVT_GT_CPLL_CFG_ERR, XVPHY_LOG_EVT_VD_NOT_SPRTD_ERR, XVPHY_LOG_EVT_MMCM_ERR, XVPHY_LOG_EVT_HDMI20_ERR, XVPHY_LOG_EVT_NO_QPLL_ERR, XVPHY_LOG_EVT_DRU_CLK_ERR, XVPHY_LOG_EVT_USRCLK_ERR, XVPHY_LOG_EVT_DUMMY }
enum | XVphy_ErrType { XVPHY_ERR_QPLL_CFG = 0x1, XVPHY_ERR_CPLL_CFG = 0x2, XVPHY_ERR_NO_DRU = 0x4, XVPHY_ERR_VD_NOT_SPRTD = 0x8, XVPHY_ERR_MMCM_CFG = 0x10, XVPHY_ERR_PLL_LAYOUT = 0x20, XVPHY_ERR_BONDED_DRU = 0x40, XVPHY_ERR_NO_QPLL = 0x80, XVPHY_ERR_DRU_CLK = 0x100, XVPHY_ERR_USRCLK = 0x200 }
enum | XVphy_HdmiTx_Patgen { XVPHY_Patgen_Ratio_10 = 0x1, XVPHY_Patgen_Ratio_20 = 0x2, XVPHY_Patgen_Ratio_30 = 0x3, XVPHY_Patgen_Ratio_40 = 0x4, XVPHY_Patgen_Ratio_50 = 0x5 }
enum | XVphy_PrbsPattern { XVPHY_PRBSSEL_STD_MODE = 0x0, XVPHY_PRBSSEL_PRBS7 = 0x1, XVPHY_PRBSSEL_PRBS15 = 0x2, XVPHY_PRBSSEL_PRBS23 = 0x3, XVPHY_PRBSSEL_PRBS31 = 0x4 }
| This typedef enumerates the available PRBS patterns available from the. More...

## Functions
void | XVphy_CfgInitialize (XVphy *InstancePtr, XVphy_Config *ConfigPtr, UINTPTR EffectiveAddr)
| This function retrieves the configuration for this Video PHY instance and fills in the InstancePtr->Config structure. More...
u32 | XVphy_PllInitialize (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_PllRefClkSelType QpllRefClkSel, XVphy_PllRefClkSelType CpllxRefClkSel, XVphy_PllType TxPllSelect, XVphy_PllType RxPllSelect)
| This function will initialize the PLL selection for a given channel. More...
u32 | XVphy_GetVersion (XVphy *InstancePtr)
| This function will obtian the IP version. More...
void | XVphy_WaitUs (XVphy *InstancePtr, u32 MicroSeconds)
| This function is the delay/sleep function for the XVphy driver. More...
u32 | XVphy_CfgLineRate (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u64 LineRateHz)
| Configure the channel's line rate. More...
XVphy_PllType | XVphy_GetPllType (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_ChannelId ChId)
| Obtain the channel's PLL reference clock selection. More...
u64 | XVphy_GetLineRateHz (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
| This function will return the line rate in Hz for a given channel / quad. More...
u32 | XVphy_ResetGtPll (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u8 Hold)
| This function will reset the GT's PLL logic. More...
u32 | XVphy_ResetGtTxRx (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u8 Hold)
| This function will reset the GT's TX/RX logic. More...
u32 | XVphy_SetPolarity (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u8 Polarity)
| This function will set/clear the TX/RX polarity bit. More...
u32 | XVphy_SetPrbsSel (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, XVphy_PrbsPattern Pattern)
| This function will set the TX/RXPRBSEL of the GT. More...
u32 | XVphy_TxPrbsForceError (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u8 ForceErr)
| This function will set the TX/RXPRBSEL of the GT. More...
void | XVphy_SetTxVoltageSwing (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u8 Vs)
| This function will set the TX voltage swing value for a given channel. More...
void | XVphy_SetTxPreEmphasis (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u8 Pe)
| This function will set the TX pre-emphasis value for a given channel. More...
void | XVphy_SetTxPostCursor (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u8 Pc)
| This function will set the TX post-curosr value for a given channel. More...
void | XVphy_SetRxLpm (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u8 Enable)
| This function will enable or disable the LPM logic in the Video PHY core. More...
u32 | XVphy_DrpWr (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u16 Addr, u16 Val)
| This function will initiate a write DRP transaction. More...
u16 | XVphy_DrpRd (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u16 Addr, u16 *RetVal)
| This function will initiate a read DRP transaction. More...
void | XVphy_MmcmPowerDown (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, u8 Hold)
| This function will power down the mixed-mode clock manager (MMCM) core. More...
void | XVphy_MmcmStart (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir)
| This function will start the mixed-mode clock manager (MMCM) core. More...
void | XVphy_IBufDsEnable (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, u8 Enable)
| This function enables the TX or RX IBUFDS peripheral. More...
void | XVphy_Clkout1OBufTdsEnable (XVphy *InstancePtr, XVphy_DirectionType Dir, u8 Enable)
| This function enables the TX or RX CLKOUT1 OBUFTDS peripheral. More...
u32 | XVphy_IsBonded (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
| This function returns true when the RX and TX are bonded and are running from the same (RX) reference clock. More...
void | XVphy_SetErrorCallback (XVphy *InstancePtr, void *CallbackFunc, void *CallbackRef)
| This function installs a callback function for the VPHY error conditions. More...
void | XVphy_LogDisplay (XVphy *InstancePtr)
| This function will print the entire log. More...
void | XVphy_LogReset (XVphy *InstancePtr)
| This function will reset the driver's logginc mechanism. More...
u16 | XVphy_LogRead (XVphy *InstancePtr)
| This function will read the last event from the log. More...
void | XVphy_LogWrite (XVphy *InstancePtr, XVphy_LogEvent Evt, u8 Data)
| This function will insert an event in the driver's logginc mechanism. More...
void | XVphy_InterruptHandler (XVphy *InstancePtr)
| This function is the interrupt handler for the XVphy driver. More...
u32 | XVphy_SelfTest (XVphy *InstancePtr)
| This function runs a self-test on the XVphy driver/device. More...
XVphy_Config * | XVphy_LookupConfig (u16 DeviceId)
| This function looks for the device configuration based on the unique device ID. More...
void | XVphy_RegisterDebug (XVphy *InstancePtr)
| This function prints out Video PHY register and GT Channel and Common DRP register contents. More...
void | XVphy_Ch2Ids (XVphy *InstancePtr, XVphy_ChannelId ChId, u8 *Id0, u8 *Id1)
| This function will set the channel IDs to correspond with the supplied channel ID based on the protocol. More...
XVphy_SysClkDataSelType | Pll2SysClkData (XVphy_PllType PllSelect)
| This function will translate from XVphy_PllType to XVphy_SysClkDataSelType. More...
XVphy_SysClkOutSelType | Pll2SysClkOut (XVphy_PllType PllSelect)
| This function will translate from XVphy_PllType to XVphy_SysClkOutSelType. More...
u32 | XVphy_PllCalculator (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u32 PllClkInFreqHz)
| This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency. More...
u32 | XVphy_WriteCfgRefClkSelReg (XVphy *InstancePtr, u8 QuadId)
| This function writes the current software configuration for the reference clock selections to hardware for the specified quad on all channels. More...
void | XVphy_CfgPllRefClkSel (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_PllRefClkSelType RefClkSel)
| Configure the PLL reference clock selection for the specified channel(s). More...
void | XVphy_CfgSysClkDataSel (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_SysClkDataSelType SysClkDataSel)
| Configure the SYSCLKDATA reference clock selection for the direction. More...
void | XVphy_CfgSysClkOutSel (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_SysClkOutSelType SysClkOutSel)
| Configure the SYSCLKOUT reference clock selection for the direction. More...
u32 | XVphy_ClkCalcParams (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u32 PllClkInFreqHz)
| This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency. More...
u32 | XVphy_OutDivReconfig (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir)
| This function will set the current output divider configuration over DRP. More...
u32 | XVphy_DirReconfig (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir)
| This function will set the current RX/TX configuration over DRP. More...
u32 | XVphy_ClkReconfig (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
| This function will set the current clocking settings for each channel to hardware based on the configuration stored in the driver's instance. More...
XVphy_ChannelId | XVphy_GetRcfgChId (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_PllType PllType)
| Obtain the reconfiguration channel ID for given PLL type. More...
u32 | XVphy_GetQuadRefClkFreq (XVphy *InstancePtr, u8 QuadId, XVphy_PllRefClkSelType RefClkType)
| Obtain the current reference clock frequency for the quad based on the reference clock type. More...
XVphy_SysClkDataSelType | XVphy_GetSysClkDataSel (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_ChannelId ChId)
| Obtain the current [RT]XSYSCLKSEL[0] configuration. More...
XVphy_SysClkOutSelType | XVphy_GetSysClkOutSel (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_ChannelId ChId)
| Obtain the current [RT]XSYSCLKSEL[1] configuration. More...
u32 | XVphy_IsPllLocked (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
| This function will check the status of a PLL lock on the specified channel. More...
u32 | XVphy_GtUserRdyEnable (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u8 Hold)
| This function will reset and enable the Video PHY's user core logic. More...
u32 | XVphy_MmcmWriteParameters (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir)
| This function will write the mixed-mode clock manager (MMCM) values currently stored in the driver's instance structure to hardware . More...
void | XVphy_MmcmReset (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, u8 Hold)
| This function will reset the mixed-mode clock manager (MMCM) core. More...
void | XVphy_MmcmLockedMaskEnable (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, u8 Enable)
| This function will reset the mixed-mode clock manager (MMCM) core. More...
u8 | XVphy_MmcmLocked (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir)
| This function will get the lock status of the mixed-mode clock manager (MMCM) core. More...
void | XVphy_SetBufgGtDiv (XVphy *InstancePtr, XVphy_DirectionType Dir, u8 Div)
| This function obtains the divider value of the BUFG_GT peripheral. More...
u32 | XVphy_PowerDownGtPll (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u8 Hold)
| This function will power down the specified GT PLL. More...
void | XVphy_SetIntrHandler (XVphy *InstancePtr, XVphy_IntrHandlerType HandlerType, XVphy_IntrHandler CallbackFunc, void *CallbackRef)
| This function installs a callback function for the specified handler type. More...
void | XVphy_IntrEnable (XVphy *InstancePtr, XVphy_IntrHandlerType Intr)
| This function enables interrupts associated with the specified interrupt type. More...
void | XVphy_IntrDisable (XVphy *InstancePtr, XVphy_IntrHandlerType Intr)
| This function disabled interrupts associated with the specified interrupt type. More...
void | XVphy_CfgErrIntr (XVphy *InstancePtr, XVphy_ErrType ErrIrq, u8 Set)
| This function configures the error IRQ register based on the condition to generate an ERR_IRQ event. More...
u64 | XVphy_GetPllVcoFreqHz (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir)
| This function calculates the PLL VCO operating frequency. More...
u8 | XVphy_GetRefClkSourcesCount (XVphy *InstancePtr)
| This function returns the number of active reference clock sources based in the CFG. More...
u8 | XVphy_IsHDMI (XVphy *InstancePtr, XVphy_DirectionType Dir)
| This function checks if Instance is HDMI 2.0 or HDMI 2.1. More...
void | XVphy_ErrorHandler (XVphy *InstancePtr)
| This function is the error condition handler. More...

## VPHY core registers: General registers.
Address mapping for the Video PHY core.
#define | XVPHY_VERSION_REG 0x000
#define | XVPHY_BANK_SELECT_REG 0x00C
#define | XVPHY_REF_CLK_SEL_REG 0x010
#define | XVPHY_PLL_RESET_REG 0x014
#define | XVPHY_PLL_LOCK_STATUS_REG 0x018
#define | XVPHY_TX_INIT_REG 0x01C
#define | XVPHY_TX_INIT_STATUS_REG 0x020
#define | XVPHY_RX_INIT_REG 0x024
#define | XVPHY_RX_INIT_STATUS_REG 0x028
#define | XVPHY_IBUFDS_GTXX_CTRL_REG 0x02C
#define | XVPHY_POWERDOWN_CONTROL_REG 0x030
#define | XVPHY_LOOPBACK_CONTROL_REG 0x038

## VPHY core registers: Dynamic reconfiguration port (DRP) registers.
#define | XVPHY_DRP_CONTROL_CH1_REG 0x040
#define | XVPHY_DRP_CONTROL_CH2_REG 0x044
#define | XVPHY_DRP_CONTROL_CH3_REG 0x048
#define | XVPHY_DRP_CONTROL_CH4_REG 0x04C
#define | XVPHY_DRP_STATUS_CH1_REG 0x050
#define | XVPHY_DRP_STATUS_CH2_REG 0x054
#define | XVPHY_DRP_STATUS_CH3_REG 0x058
#define | XVPHY_DRP_STATUS_CH4_REG 0x05C
#define | XVPHY_DRP_CONTROL_COMMON_REG 0x060
#define | XVPHY_DRP_STATUS_COMMON_REG 0x064
#define | XVPHY_DRP_CONTROL_TXMMCM_REG 0x124
#define | XVPHY_DRP_STATUS_TXMMCM_REG 0x128
#define | XVPHY_DRP_CONTROL_RXMMCM_REG 0x144
#define | XVPHY_DRP_STATUS_RXMMCM_REG 0x148

## VPHY core registers: CPLL Calibration registers.
#define | XVPHY_CPLL_CAL_PERIOD_REG 0x068
#define | XVPHY_CPLL_CAL_TOL_REG 0x06C

## VPHY core registers: Transmitter function registers.
#define | XVPHY_TX_CONTROL_REG 0x070
#define | XVPHY_TX_BUFFER_BYPASS_REG 0x074
#define | XVPHY_TX_STATUS_REG 0x078
#define | XVPHY_TX_DRIVER_CH12_REG 0x07C
#define | XVPHY_TX_DRIVER_CH34_REG 0x080

## VPHY core registers: Receiver function registers.
#define | XVPHY_RX_CONTROL_REG 0x100
#define | XVPHY_RX_STATUS_REG 0x104
#define | XVPHY_RX_EQ_CDR_REG 0x108
#define | XVPHY_RX_TDLOCK_REG 0x10C

## VPHY core registers: Interrupt registers.
#define | XVPHY_ERR_IRQ 0x03C
#define | XVPHY_INTR_EN_REG 0x110
#define | XVPHY_INTR_DIS_REG 0x114
#define | XVPHY_INTR_MASK_REG 0x118
#define | XVPHY_INTR_STS_REG 0x11C

## User clocking registers: MMCM and BUFGGT registers.
#define | XVPHY_MMCM_TXUSRCLK_CTRL_REG 0x0120
#define | XVPHY_MMCM_TXUSRCLK_REG1 0x0124
#define | XVPHY_MMCM_TXUSRCLK_REG2 0x0128
#define | XVPHY_MMCM_TXUSRCLK_REG3 0x012C
#define | XVPHY_MMCM_TXUSRCLK_REG4 0x0130
#define | XVPHY_BUFGGT_TXUSRCLK_REG 0x0134
#define | XVPHY_MISC_TXUSRCLK_REG 0x0138
#define | XVPHY_MMCM_RXUSRCLK_CTRL_REG 0x0140
#define | XVPHY_MMCM_RXUSRCLK_REG1 0x0144
#define | XVPHY_MMCM_RXUSRCLK_REG2 0x0148
#define | XVPHY_MMCM_RXUSRCLK_REG3 0x014C
#define | XVPHY_MMCM_RXUSRCLK_REG4 0x0150
#define | XVPHY_BUFGGT_RXUSRCLK_REG 0x0154
#define | XVPHY_MISC_RXUSRCLK_REG 0x0158

## Clock detector (HDMI) registers.
#define | XVPHY_CLKDET_CTRL_REG 0x0200
#define | XVPHY_CLKDET_STAT_REG 0x0204
#define | XVPHY_CLKDET_FREQ_TMR_TO_REG 0x0208
#define | XVPHY_CLKDET_FREQ_TX_REG 0x020C
#define | XVPHY_CLKDET_FREQ_RX_REG 0x0210
#define | XVPHY_CLKDET_TMR_TX_REG 0x0214
#define | XVPHY_CLKDET_TMR_RX_REG 0x0218
#define | XVPHY_CLKDET_FREQ_DRU_REG 0x021C

## Data recovery unit registers (HDMI).
#define | XVPHY_DRU_CTRL_REG 0x0300
#define | XVPHY_DRU_STAT_REG 0x0304
#define | XVPHY_DRU_CFREQ_L_REG(Ch) (0x0308 + (12 * (Ch - 1)))
#define | XVPHY_DRU_CFREQ_H_REG(Ch) (0x030C + (12 * (Ch - 1)))
#define | XVPHY_DRU_GAIN_REG(Ch) (0x0310 + (12 * (Ch - 1)))

## TMDS Clock Pattern Generator registers (HDMI).
#define | XVPHY_PATGEN_CTRL_REG 0x0340

## VPHY core masks, shifts, and register values.
#define | XVPHY_VERSION_INTER_REV_MASK 0x000000FF
| Internal revision. More...
#define | XVPHY_VERSION_CORE_PATCH_MASK 0x00000F00
| Core patch details. More...
#define | XVPHY_VERSION_CORE_PATCH_SHIFT 8
| Shift bits for core patch details. More...
#define | XVPHY_VERSION_CORE_VER_REV_MASK 0x0000F000
| Core version revision. More...
#define | XVPHY_VERSION_CORE_VER_REV_SHIFT 12
| Shift bits for core version revision. More...
#define | XVPHY_VERSION_CORE_VER_MNR_MASK 0x00FF0000
| Core minor version. More...
#define | XVPHY_VERSION_CORE_VER_MNR_SHIFT 16
| Shift bits for core minor version. More...
#define | XVPHY_VERSION_CORE_VER_MJR_MASK 0xFF000000
| Core major version. More...
#define | XVPHY_VERSION_CORE_VER_MJR_SHIFT 24
| Shift bits for core major version. More...
#define | XVPHY_BANK_SELECT_TX_MASK 0x00F
#define | XVPHY_BANK_SELECT_RX_MASK 0xF00
#define | XVPHY_BANK_SELECT_RX_SHIFT 8
#define | XVPHY_REF_CLK_SEL_QPLL0_MASK 0x0000000F
#define | XVPHY_REF_CLK_SEL_CPLL_MASK 0x000000F0
#define | XVPHY_REF_CLK_SEL_CPLL_SHIFT 4
#define | XVPHY_REF_CLK_SEL_QPLL1_MASK 0x00000F00
#define | XVPHY_REF_CLK_SEL_QPLL1_SHIFT 8
#define | XVPHY_REF_CLK_SEL_XPLL_GTREFCLK0 1
#define | XVPHY_REF_CLK_SEL_XPLL_GTREFCLK1 2
#define | XVPHY_REF_CLK_SEL_XPLL_GTNORTHREFCLK0 3
#define | XVPHY_REF_CLK_SEL_XPLL_GTNORTHREFCLK1 4
#define | XVPHY_REF_CLK_SEL_XPLL_GTSOUTHREFCLK0 5
#define | XVPHY_REF_CLK_SEL_XPLL_GTSOUTHREFCLK1 6
#define | XVPHY_REF_CLK_SEL_XPLL_GTEASTREFCLK0 3
#define | XVPHY_REF_CLK_SEL_XPLL_GTEASTREFCLK1 4
#define | XVPHY_REF_CLK_SEL_XPLL_GTWESTREFCLK0 5
#define | XVPHY_REF_CLK_SEL_XPLL_GTWESTREFCLK1 6
#define | XVPHY_REF_CLK_SEL_XPLL_GTGREFCLK 7
#define | XVPHY_REF_CLK_SEL_SYSCLKSEL_MASK 0x0F000000
#define | XVPHY_REF_CLK_SEL_SYSCLKSEL_SHIFT 24
#define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL0 0
#define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL1 1
#define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_CPLL 0
#define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL 1
#define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL0 3
#define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL1 2
#define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CH 0
#define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN 1
#define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN0 2
#define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN1 3
#define | XVPHY_REF_CLK_SEL_RXSYSCLKSEL_OUT_MASK(G)
#define | XVPHY_REF_CLK_SEL_TXSYSCLKSEL_OUT_MASK(G)
#define | XVPHY_REF_CLK_SEL_RXSYSCLKSEL_DATA_MASK(G)
#define | XVPHY_REF_CLK_SEL_TXSYSCLKSEL_DATA_MASK(G)
#define | XVPHY_REF_CLK_SEL_RXSYSCLKSEL_OUT_SHIFT(G)
#define | XVPHY_REF_CLK_SEL_TXSYSCLKSEL_OUT_SHIFT(G)
#define | XVPHY_REF_CLK_SEL_RXSYSCLKSEL_DATA_SHIFT(G)
#define | XVPHY_REF_CLK_SEL_TXSYSCLKSEL_DATA_SHIFT(G)
#define | XVPHY_PLL_RESET_CPLL_MASK 0x1
#define | XVPHY_PLL_RESET_QPLL0_MASK 0x2
#define | XVPHY_PLL_RESET_QPLL1_MASK 0x4
#define | XVPHY_PLL_LOCK_STATUS_CPLL_MASK(Ch) (0x01 << (Ch - 1))
#define | XVPHY_PLL_LOCK_STATUS_QPLL0_MASK 0x10
#define | XVPHY_PLL_LOCK_STATUS_QPLL1_MASK 0x20
#define | XVPHY_PLL_LOCK_STATUS_CPLL_ALL_MASK
#define | XVPHY_PLL_LOCK_STATUS_CPLL_HDMI_MASK
#define | XVPHY_TXRX_INIT_GTRESET_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XVPHY_TXRX_INIT_PMARESET_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XVPHY_TXRX_INIT_PCSRESET_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XVPHY_TX_INIT_USERRDY_MASK(Ch) (0x08 << (8 * (Ch - 1)))
#define | XVPHY_RX_INIT_USERRDY_MASK(Ch) (0x40 << (8 * (Ch - 1)))
#define | XVPHY_TXRX_INIT_PLLGTRESET_MASK(Ch) (0x80 << (8 * (Ch - 1)))
#define | XVPHY_TXRX_INIT_GTRESET_ALL_MASK
#define | XVPHY_TX_INIT_USERRDY_ALL_MASK
#define | XVPHY_RX_INIT_USERRDY_ALL_MASK
#define | XVPHY_TXRX_INIT_PLLGTRESET_ALL_MASK
#define | XVPHY_TXRX_INIT_STATUS_RESETDONE_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XVPHY_TXRX_INIT_STATUS_PMARESETDONE_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XVPHY_TXRX_INIT_STATUS_POWERGOOD_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XVPHY_TXRX_INIT_STATUS_RESETDONE_ALL_MASK
#define | XVPHY_TXRX_INIT_STATUS_PMARESETDONE_ALL_MASK
#define | XVPHY_IBUFDS_GTXX_CTRL_GTREFCLK0_CEB_MASK 0x1
#define | XVPHY_IBUFDS_GTXX_CTRL_GTREFCLK1_CEB_MASK 0x2
#define | XVPHY_POWERDOWN_CONTROL_CPLLPD_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XVPHY_POWERDOWN_CONTROL_QPLL0PD_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XVPHY_POWERDOWN_CONTROL_QPLL1PD_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XVPHY_POWERDOWN_CONTROL_RXPD_MASK(Ch) (0x18 << (8 * (Ch - 1)))
#define | XVPHY_POWERDOWN_CONTROL_RXPD_SHIFT(Ch) (3 + (8 * (Ch - 1)))
#define | XVPHY_POWERDOWN_CONTROL_TXPD_MASK(Ch) (0x60 << (8 * (Ch - 1)))
#define | XVPHY_POWERDOWN_CONTROL_TXPD_SHIFT(Ch) (5 + (8 * (Ch - 1)))
#define | XVPHY_LOOPBACK_CONTROL_CH_MASK(Ch) (0x03 << (8 * (Ch - 1)))
#define | XVPHY_LOOPBACK_CONTROL_CH_SHIFT(Ch) (8 * (Ch - 1))
#define | XVPHY_DRP_CONTROL_DRPADDR_MASK 0x00000FFF
#define | XVPHY_DRP_CONTROL_DRPEN_MASK 0x00001000
#define | XVPHY_DRP_CONTROL_DRPWE_MASK 0x00002000
#define | XVPHY_DRP_CONTROL_DRPRESET_MASK 0x00004000
#define | XVPHY_DRP_CONTROL_DRPDI_MASK 0xFFFF0000
#define | XVPHY_DRP_CONTROL_DRPDI_SHIFT 16
#define | XVPHY_DRP_STATUS_DRPO_MASK 0x0FFFF
#define | XVPHY_DRP_STATUS_DRPRDY_MASK 0x10000
#define | XVPHY_DRP_STATUS_DRPBUSY_MASK 0x20000
#define | XVPHY_CPLL_CAL_PERIOD_MASK 0x3FFFF
#define | XVPHY_CPLL_CAL_TOL_MASK 0x3FFFF
#define | XVPHY_TX_CONTROL_TX8B10BEN_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XVPHY_TX_CONTROL_TX8B10BEN_ALL_MASK
#define | XVPHY_TX_CONTROL_TXPOLARITY_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XVPHY_TX_CONTROL_TXPOLARITY_ALL_MASK
#define | XVPHY_TX_CONTROL_TXPRBSSEL_MASK(Ch) (0x5C << (8 * (Ch - 1)))
#define | XVPHY_TX_CONTROL_TXPRBSSEL_ALL_MASK
#define | XVPHY_TX_CONTROL_TXPRBSSEL_SHIFT(Ch) (2 + (8 * (Ch - 1)))
#define | XVPHY_TX_CONTROL_TXPRBSFORCEERR_MASK(Ch) (0x20 << (8 * (Ch - 1)))
#define | XVPHY_TX_CONTROL_TXPRBSFORCEERR_ALL_MASK
#define | XVPHY_TX_BUFFER_BYPASS_TXPHDLYRESET_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XVPHY_TX_BUFFER_BYPASS_TXPHALIGN_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XVPHY_TX_BUFFER_BYPASS_TXPHALIGNEN_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XVPHY_TX_BUFFER_BYPASS_TXPHDLYPD_MASK(Ch) (0x08 << (8 * (Ch - 1)))
#define | XVPHY_TX_BUFFER_BYPASS_TXPHINIT_MASK(Ch) (0x10 << (8 * (Ch - 1)))
#define | XVPHY_TX_BUFFER_BYPASS_TXDLYRESET_MASK(Ch) (0x20 << (8 * (Ch - 1)))
#define | XVPHY_TX_BUFFER_BYPASS_TXDLYBYPASS_MASK(Ch) (0x40 << (8 * (Ch - 1)))
#define | XVPHY_TX_BUFFER_BYPASS_TXDLYEN_MASK(Ch) (0x80 << (8 * (Ch - 1)))
#define | XVPHY_TX_STATUS_TXPHALIGNDONE_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XVPHY_TX_STATUS_TXPHINITDONE_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XVPHY_TX_STATUS_TXDLYRESETDONE_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XVPHY_TX_STATUS_TXBUFSTATUS_MASK(Ch) (0x18 << (8 * (Ch - 1)))
#define | XVPHY_TX_STATUS_TXBUFSTATUS_SHIFT(Ch) (3 + (8 * (Ch - 1)))
#define | XVPHY_TX_DRIVER_TXDIFFCTRL_MASK(Ch) (0x000F << (16 * ((Ch - 1) % 2)))
#define | XVPHY_TX_DRIVER_TXDIFFCTRL_SHIFT(Ch) (16 * ((Ch - 1) % 2))
#define | XVPHY_TX_DRIVER_TXELECIDLE_MASK(Ch) (0x0010 << (16 * ((Ch - 1) % 2)))
#define | XVPHY_TX_DRIVER_TXELECIDLE_SHIFT(Ch) (4 + (16 * ((Ch - 1) % 2)))
#define | XVPHY_TX_DRIVER_TXINHIBIT_MASK(Ch) (0x0020 << (16 * ((Ch - 1) % 2)))
#define | XVPHY_TX_DRIVER_TXINHIBIT_SHIFT(Ch) (5 + (16 * ((Ch - 1) % 2)))
#define | XVPHY_TX_DRIVER_TXPOSTCURSOR_MASK(Ch) (0x07C0 << (16 * ((Ch - 1) % 2)))
#define | XVPHY_TX_DRIVER_TXPOSTCURSOR_SHIFT(Ch) (6 + (16 * ((Ch - 1) % 2)))
#define | XVPHY_TX_DRIVER_TXPRECURSOR_MASK(Ch) (0xF800 << (16 * ((Ch - 1) % 2)))
#define | XVPHY_TX_DRIVER_TXPRECURSOR_SHIFT(Ch) (11 + (16 * ((Ch - 1) % 2)))
#define | XVPHY_RX_CONTROL_RX8B10BEN_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XVPHY_RX_CONTROL_RX8B10BEN_ALL_MASK
#define | XVPHY_RX_CONTROL_RXPOLARITY_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XVPHY_RX_CONTROL_RXPOLARITY_ALL_MASK
#define | XVPHY_RX_CONTROL_RXPRBSCNTRESET_MASK(Ch) (0x08 << (8 * (Ch - 1)))
#define | XVPHY_RX_CONTROL_RXPRBSSEL_MASK(Ch) (0xF0 << (8 * (Ch - 1)))
#define | XVPHY_RX_CONTROL_RXPRBSSEL_ALL_MASK
#define | XVPHY_RX_CONTROL_RXPRBSSEL_SHIFT(Ch) (4 + (8 * (Ch - 1)))
#define | XVPHY_RX_STATUS_RXCDRLOCK_MASK(Ch) (0x1 << (8 * (Ch - 1)))
#define | XVPHY_RX_STATUS_RXBUFSTATUS_MASK(Ch) (0xE << (8 * (Ch - 1)))
#define | XVPHY_RX_STATUS_RXBUFSTATUS_SHIFT(Ch) (1 + (8 * (Ch - 1)))
#define | XVPHY_RX_CONTROL_RXLPMEN_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XVPHY_RX_STATUS_RXCDRHOLD_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XVPHY_RX_STATUS_RXOSOVRDEN_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XVPHY_RX_STATUS_RXLPMLFKLOVRDEN_MASK(Ch) (0x08 << (8 * (Ch - 1)))
#define | XVPHY_RX_STATUS_RXLPMHFOVRDEN_MASK(Ch) (0x10 << (8 * (Ch - 1)))
#define | XVPHY_RX_CONTROL_RXLPMEN_ALL_MASK
#define | XVPHY_INTR_TXRESETDONE_MASK 0x00000001
#define | XVPHY_INTR_RXRESETDONE_MASK 0x00000002
#define | XVPHY_INTR_CPLL_LOCK_MASK 0x00000004
#define | XVPHY_INTR_QPLL0_LOCK_MASK 0x00000008
#define | XVPHY_INTR_TXALIGNDONE_MASK 0x00000010
#define | XVPHY_INTR_QPLL1_LOCK_MASK 0x00000020
#define | XVPHY_INTR_TXCLKDETFREQCHANGE_MASK 0x00000040
#define | XVPHY_INTR_RXCLKDETFREQCHANGE_MASK 0x00000080
#define | XVPHY_INTR_TXMMCMUSRCLK_LOCK_MASK 0x00000200
#define | XVPHY_INTR_RXMMCMUSRCLK_LOCK_MASK 0x00000400
#define | XVPHY_INTR_TXTMRTIMEOUT_MASK 0x40000000
#define | XVPHY_INTR_RXTMRTIMEOUT_MASK 0x80000000
#define | XVPHY_INTR_QPLL_LOCK_MASK XVPHY_INTR_QPLL0_LOCK_MASK
#define | XVPHY_MMCM_USRCLK_CTRL_CFG_NEW_MASK 0x01
#define | XVPHY_MMCM_USRCLK_CTRL_RST_MASK 0x02
#define | XVPHY_MMCM_USRCLK_CTRL_CFG_SUCCESS_MASK 0x10
#define | XVPHY_MMCM_USRCLK_CTRL_LOCKED_MASK 0x200
#define | XVPHY_MMCM_USRCLK_CTRL_PWRDWN_MASK 0x400
#define | XVPHY_MMCM_USRCLK_CTRL_LOCKED_MASK_MASK 0x800
#define | XVPHY_MMCM_USRCLK_CTRL_CLKINSEL_MASK 0x1000
#define | XVPHY_MMCM_USRCLK_REG1_DIVCLK_MASK 0x00000FF
#define | XVPHY_MMCM_USRCLK_REG1_CLKFBOUT_MULT_MASK 0x000FF00
#define | XVPHY_MMCM_USRCLK_REG1_CLKFBOUT_MULT_SHIFT 8
#define | XVPHY_MMCM_USRCLK_REG1_CLKFBOUT_FRAC_MASK 0x3FF0000
#define | XVPHY_MMCM_USRCLK_REG1_CLKFBOUT_FRAC_SHIFT 16
#define | XVPHY_MMCM_USRCLK_REG2_DIVCLK_MASK 0x00000FF
#define | XVPHY_MMCM_USRCLK_REG2_CLKOUT0_FRAC_MASK 0x3FF0000
#define | XVPHY_MMCM_USRCLK_REG2_CLKOUT0_FRAC_SHIFT 16
#define | XVPHY_MMCM_USRCLK_REG34_DIVCLK_MASK 0x00000FF
#define | XVPHY_BUFGGT_XXUSRCLK_CLR_MASK 0x1
#define | XVPHY_BUFGGT_XXUSRCLK_DIV_MASK 0xE
#define | XVPHY_BUFGGT_XXUSRCLK_DIV_SHIFT 1
#define | XVPHY_MISC_XXUSRCLK_CKOUT1_OEN_MASK 0x1
#define | XVPHY_MISC_XXUSRCLK_REFCLK_CEB_MASK 0x2
#define | XVPHY_CLKDET_CTRL_RUN_MASK 0x1
#define | XVPHY_CLKDET_CTRL_TX_TMR_CLR_MASK 0x2
#define | XVPHY_CLKDET_CTRL_RX_TMR_CLR_MASK 0x4
#define | XVPHY_CLKDET_CTRL_TX_FREQ_RST_MASK 0x8
#define | XVPHY_CLKDET_CTRL_RX_FREQ_RST_MASK 0x10
#define | XVPHY_CLKDET_CTRL_FREQ_LOCK_THRESH_MASK 0x1FE0
#define | XVPHY_CLKDET_CTRL_FREQ_LOCK_THRESH_SHIFT 5
#define | XVPHY_CLKDET_STAT_TX_FREQ_ZERO_MASK 0x1
#define | XVPHY_CLKDET_STAT_RX_FREQ_ZERO_MASK 0x2
#define | XVPHY_CLKDET_STAT_TX_REFCLK_LOCK_MASK 0x3
#define | XVPHY_CLKDET_STAT_TX_REFCLK_LOCK_CAP_MASK 0x4
#define | XVPHY_DRU_CTRL_RST_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XVPHY_DRU_CTRL_EN_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XVPHY_DRU_STAT_ACTIVE_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XVPHY_DRU_STAT_VERSION_MASK 0xFF000000
#define | XVPHY_DRU_STAT_VERSION_SHIFT 24
#define | XVPHY_DRU_CFREQ_H_MASK 0x1F
#define | XVPHY_DRU_GAIN_G1_MASK 0x00001F
#define | XVPHY_DRU_GAIN_G1_SHIFT 0
#define | XVPHY_DRU_GAIN_G1_P_MASK 0x001F00
#define | XVPHY_DRU_GAIN_G1_P_SHIFT 8
#define | XVPHY_DRU_GAIN_G2_MASK 0x1F0000
#define | XVPHY_DRU_GAIN_G2_SHIFT 16
#define | XVPHY_PATGEN_CTRL_RATIO_MASK 0x7
#define | XVPHY_PATGEN_CTRL_RATIO_SHIFT 0

## Register access macro definitions.
#define | XVphy_In32 Xil_In32
#define | XVphy_Out32 Xil_Out32

## Macro Definition Documentation

#define XVphy_ReadReg | ( |  | BaseAddress,
|  |  | RegOffset
| ) |  | XVphy_In32((BaseAddress) + (RegOffset))

This is a low-level function that reads from the specified register.

Parameters

  BaseAddress | is the base address of the device.
  RegOffset | is the register offset to be read from.

Returns
  The 32-bit value of the specified register.

Note
  C-style signature: u32 XVphy_ReadReg(u32 BaseAddress, u32 RegOffset)

Referenced by XVphy_CfgErrIntr(), XVphy_Clkout1OBufTdsEnable(), XVphy_GetSysClkDataSel(), XVphy_GetSysClkOutSel(), XVphy_GetVersion(), XVphy_GtUserRdyEnable(), XVphy_IBufDsEnable(), XVphy_InterruptHandler(), XVphy_IntrDisable(), XVphy_IntrEnable(), XVphy_IsPllLocked(), XVphy_MmcmLocked(), XVphy_MmcmLockedMaskEnable(), XVphy_MmcmPowerDown(), XVphy_MmcmReset(), XVphy_PowerDownGtPll(), XVphy_RegisterDebug(), XVphy_ResetGtPll(), XVphy_ResetGtTxRx(), XVphy_SelfTest(), XVphy_SetBufgGtDiv(), XVphy_SetPolarity(), XVphy_SetPrbsSel(), XVphy_SetRxLpm(), XVphy_SetTxPostCursor(), XVphy_SetTxPreEmphasis(), XVphy_SetTxVoltageSwing(), and XVphy_TxPrbsForceError().

#define XVPHY_VERSION_CORE_PATCH_MASK 0x00000F00

Core patch details.

#define XVPHY_VERSION_CORE_PATCH_SHIFT 8

Shift bits for core patch details.

#define XVPHY_VERSION_CORE_VER_MJR_MASK 0xFF000000

Core major version.

#define XVPHY_VERSION_CORE_VER_MJR_SHIFT 24

Shift bits for core major version.

#define XVPHY_VERSION_CORE_VER_MNR_MASK 0x00FF0000

Core minor version.

#define XVPHY_VERSION_CORE_VER_MNR_SHIFT 16

Shift bits for core minor version.

#define XVPHY_VERSION_CORE_VER_REV_MASK 0x0000F000

Core version revision.

#define XVPHY_VERSION_CORE_VER_REV_SHIFT 12

Shift bits for core version revision.

#define XVPHY_VERSION_INTER_REV_MASK 0x000000FF

Internal revision.

#define XVphy_WriteReg | ( |  | BaseAddress,
|  |  | RegOffset,
|  |  | Data
| ) |  | XVphy_Out32((BaseAddress) + (RegOffset), (Data))

This is a low-level function that writes to the specified register.

Parameters

  BaseAddress | is the base address of the device.
  RegOffset | is the register offset to write to.
  Data | is the 32-bit data to write to the specified register.

Returns
  None.

Note
  C-style signature: void XVphy_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XVphy_CfgErrIntr(), XVphy_Clkout1OBufTdsEnable(), XVphy_GtUserRdyEnable(), XVphy_IBufDsEnable(), XVphy_IntrDisable(), XVphy_IntrEnable(), XVphy_MmcmLockedMaskEnable(), XVphy_MmcmPowerDown(), XVphy_MmcmReset(), XVphy_PowerDownGtPll(), XVphy_ResetGtPll(), XVphy_ResetGtTxRx(), XVphy_SetBufgGtDiv(), XVphy_SetPolarity(), XVphy_SetPrbsSel(), XVphy_SetRxLpm(), XVphy_SetTxPostCursor(), XVphy_SetTxPreEmphasis(), XVphy_SetTxVoltageSwing(), XVphy_TxPrbsForceError(), and XVphy_WriteCfgRefClkSelReg().

## Typedef Documentation

typedef void(* XVphy_Callback)(void *CallbackRef)

Generic callback type.

Parameters

  CallbackRef | is a pointer to the callback reference.

Note
  None.

typedef void(* XVphy_ErrorCallback)(void *CallbackRef)

Error callback type.

Parameters

  CallbackRef | is a pointer to the callback reference.

Note
  None.

typedef void(* XVphy_IntrHandler)(void *InstancePtr)

Callback type which represents the handler for interrupts.

Parameters

  InstancePtr | is a pointer to the XVphy instance.

Note
  None.

typedef void(* XVphy_TimerHandler)(void *InstancePtr, u32 MicroSeconds)

Callback type which represents a custom timer wait handler.

This is only used for Microblaze since it doesn't have a native sleep function. To avoid dependency on a hardware timer, the default wait functionality is implemented using loop iterations; this isn't too accurate. If a custom timer handler is used, the user may implement their own wait implementation using a hardware timer (see example/) for better accuracy.

Parameters

  InstancePtr | is a pointer to the XVphy instance.
  MicroSeconds | is the number of microseconds to be passed to the timer function.

Note
  None.

## Enumeration Type Documentation

enum XVphy_ChannelId

This typedef enumerates the available channels.

enum XVphy_ErrType

Enumerator
XVPHY_ERR_QPLL_CFG | QPLL CFG not found.
XVPHY_ERR_CPLL_CFG | CPLL CFG not found.
XVPHY_ERR_NO_DRU | No DRU in design.
XVPHY_ERR_VD_NOT_SPRTD | Video Not Supported.
XVPHY_ERR_MMCM_CFG | MMCM CFG not found.
XVPHY_ERR_PLL_LAYOUT | PLL Error.
XVPHY_ERR_BONDED_DRU | DRU and Bonded Mode Error.
XVPHY_ERR_NO_QPLL | No QPLL Error.
XVPHY_ERR_DRU_CLK | Wrong DRU clk freq Error.
XVPHY_ERR_USRCLK | USRCLK Error.

enum XVphy_GtState

Enumerator
XVPHY_GT_STATE_IDLE | Idle state.
XVPHY_GT_STATE_LOCK | Lock state.
XVPHY_GT_STATE_RESET | Reset state.
XVPHY_GT_STATE_ALIGN | Align state.
XVPHY_GT_STATE_READY | Ready state.

enum XVphy_HdmiHandlerType

This typedef enumerates the list of available hdmi handler types.

The values are used as parameters to the XVphy_SetHdmiCallback function.

Enumerator
XVPHY_HDMI_HANDLER_TXINIT | TX init handler.
XVPHY_HDMI_HANDLER_TXREADY | TX ready handler.
XVPHY_HDMI_HANDLER_RXINIT | RX init handler.
XVPHY_HDMI_HANDLER_RXREADY | RX ready handler.

enum XVphy_HdmiTx_Patgen

Enumerator
XVPHY_Patgen_Ratio_10 | LR:Clock Ratio = 10.
XVPHY_Patgen_Ratio_20 | LR:Clock Ratio = 20.
XVPHY_Patgen_Ratio_30 | LR:Clock Ratio = 30.
XVPHY_Patgen_Ratio_40 | LR:Clock Ratio = 40.
XVPHY_Patgen_Ratio_50 | LR:Clock Ratio = 50.

enum XVphy_IntrHandlerType

This typedef enumerates the list of available interrupt handler types.

The values are used as parameters to the XVphy_SetIntrHandler function.

enum XVphy_LogEvent

Enumerator
XVPHY_LOG_EVT_NONE | Log event none.
XVPHY_LOG_EVT_QPLL_EN | Log event QPLL enable.
XVPHY_LOG_EVT_QPLL_RST | Log event QPLL reset.
XVPHY_LOG_EVT_QPLL_LOCK | Log event QPLL lock.
XVPHY_LOG_EVT_QPLL_RECONFIG | Log event QPLL reconfig.
XVPHY_LOG_EVT_QPLL0_EN | Log event QPLL0 enable.
XVPHY_LOG_EVT_QPLL0_RST | Log event QPLL0 reset.
XVPHY_LOG_EVT_QPLL0_LOCK | Log event QPLL0 lock.
XVPHY_LOG_EVT_QPLL0_RECONFIG | Log event QPLL0 reconfig.
XVPHY_LOG_EVT_QPLL1_EN | Log event QPLL1 enable.
XVPHY_LOG_EVT_QPLL1_RST | Log event QPLL1 reset.
XVPHY_LOG_EVT_QPLL1_LOCK | Log event QPLL1 lock.
XVPHY_LOG_EVT_QPLL1_RECONFIG | Log event QPLL1 reconfig.
XVPHY_LOG_EVT_PLL0_EN | Log event PLL0 reset.
XVPHY_LOG_EVT_PLL0_RST | Log event PLL0 reset.
XVPHY_LOG_EVT_PLL0_LOCK | Log event PLL0 lock.
XVPHY_LOG_EVT_PLL0_RECONFIG | Log event PLL0 reconfig.
XVPHY_LOG_EVT_PLL1_EN | Log event PLL1 reset.
XVPHY_LOG_EVT_PLL1_RST | Log event PLL1 reset.
XVPHY_LOG_EVT_PLL1_LOCK | Log event PLL1 lock.
XVPHY_LOG_EVT_PLL1_RECONFIG | Log event PLL1 reconfig.
XVPHY_LOG_EVT_CPLL_EN | Log event CPLL reset.
XVPHY_LOG_EVT_CPLL_RST | Log event CPLL reset.
XVPHY_LOG_EVT_CPLL_LOCK | Log event CPLL lock.
XVPHY_LOG_EVT_CPLL_RECONFIG | Log event CPLL reconfig.
XVPHY_LOG_EVT_TXPLL_EN | Log event TXPLL enable.
XVPHY_LOG_EVT_TXPLL_RST | Log event TXPLL reset.
XVPHY_LOG_EVT_RXPLL_EN | Log event RXPLL enable.
XVPHY_LOG_EVT_RXPLL_RST | Log event RXPLL reset.
XVPHY_LOG_EVT_GTRX_RST | Log event GT RX reset.
XVPHY_LOG_EVT_GTTX_RST | Log event GT TX reset.
XVPHY_LOG_EVT_VID_TX_RST | Log event Vid TX reset.
XVPHY_LOG_EVT_VID_RX_RST | Log event Vid RX reset.
XVPHY_LOG_EVT_TX_ALIGN | Log event TX align.
XVPHY_LOG_EVT_TX_ALIGN_TMOUT | Log event TX align Timeout.
XVPHY_LOG_EVT_TX_TMR | Log event TX timer.
XVPHY_LOG_EVT_RX_TMR | Log event RX timer.
XVPHY_LOG_EVT_GT_RECONFIG | Log event GT reconfig.
XVPHY_LOG_EVT_GT_TX_RECONFIG | Log event GT reconfig.
XVPHY_LOG_EVT_GT_RX_RECONFIG | Log event GT reconfig.
XVPHY_LOG_EVT_INIT | Log event init.
XVPHY_LOG_EVT_TXPLL_RECONFIG | Log event TXPLL reconfig.
XVPHY_LOG_EVT_RXPLL_RECONFIG | Log event RXPLL reconfig.
XVPHY_LOG_EVT_RXPLL_LOCK | Log event RXPLL lock.
XVPHY_LOG_EVT_TXPLL_LOCK | Log event TXPLL lock.
XVPHY_LOG_EVT_TX_RST_DONE | Log event TX reset done.
XVPHY_LOG_EVT_RX_RST_DONE | Log event RX reset done.
XVPHY_LOG_EVT_TX_FREQ | Log event TX frequency.
XVPHY_LOG_EVT_RX_FREQ | Log event RX frequency.
XVPHY_LOG_EVT_DRU_EN | Log event DRU enable/disable.
XVPHY_LOG_EVT_GT_PLL_LAYOUT | Log event GT PLL Layout Change.
XVPHY_LOG_EVT_GT_UNBONDED | Log event GT Unbonded Change.
XVPHY_LOG_EVT_1PPC_ERR | Log event 1 PPC Error.
XVPHY_LOG_EVT_PPC_MSMTCH_ERR | Log event PPC MismatchError.
XVPHY_LOG_EVT_VDCLK_HIGH_ERR | Log event VidClk more than 148.5 MHz.
XVPHY_LOG_EVT_NO_DRU | Log event Vid not supported no DRU.
XVPHY_LOG_EVT_GT_QPLL_CFG_ERR | Log event QPLL Config not found.
XVPHY_LOG_EVT_GT_CPLL_CFG_ERR | Log event QPLL Config not found.
XVPHY_LOG_EVT_VD_NOT_SPRTD_ERR | Log event Vid format not supported.
XVPHY_LOG_EVT_MMCM_ERR | Log event MMCM Config not found.
XVPHY_LOG_EVT_HDMI20_ERR | Log event HDMI2.0 not supported.
XVPHY_LOG_EVT_NO_QPLL_ERR | Log event QPLL not present.
XVPHY_LOG_EVT_DRU_CLK_ERR | Log event DRU clk wrong freq.
XVPHY_LOG_EVT_USRCLK_ERR | Log event usrclk more than 297 MHz.
XVPHY_LOG_EVT_DUMMY | Dummy Event should be last.

enum XVphy_OutClkSelType

This typedef enumerates the available clocks that are used as multiplexer input selections for the RX/TX output clock.

enum XVphy_PllRefClkSelType

This typedef enumerates the available reference clocks for the PLL clock selection multiplexer.

enum XVphy_PllType

This typedef enumerates the different PLL types for a given GT channel.

enum XVphy_PrbsPattern

This typedef enumerates the available PRBS patterns available from the.

Enumerator
XVPHY_PRBSSEL_STD_MODE | Pattern gen/mon OFF.
XVPHY_PRBSSEL_PRBS7 | PRBS-7.
XVPHY_PRBSSEL_PRBS15 | PRBS-15.
XVPHY_PRBSSEL_PRBS23 | PRBS-23.
XVPHY_PRBSSEL_PRBS31 | PRBS-31.

enum XVphy_ProtocolType

This typedef enumerates the various protocols handled by the Video PHY controller (VPHY).

enum XVphy_SysClkDataSelType

This typedef enumerates the available reference clocks used to drive the RX/TX datapaths.

enum XVphy_SysClkOutSelType

This typedef enumerates the available reference clocks used to drive the RX/TX output clocks.

## Function Documentation

XVphy_SysClkDataSelType Pll2SysClkData | ( | XVphy_PllType | PllSelect | ) |

This function will translate from XVphy_PllType to XVphy_SysClkDataSelType.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.

Returns
  The reference clock type based on the PLL selection.

Note
  None.

Referenced by XVphy_PllInitialize().

XVphy_SysClkOutSelType Pll2SysClkOut | ( | XVphy_PllType | PllSelect | ) |

This function will translate from XVphy_PllType to XVphy_SysClkOutSelType.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.

Returns
  The reference clock type based on the PLL selection.

Note
  None.

Referenced by XVphy_PllInitialize().

void XVphy_CfgErrIntr | ( | XVphy * | InstancePtr,
|  | XVphy_ErrType | ErrIrq,
|  | u8 | Set
| ) |  |

This function configures the error IRQ register based on the condition to generate an ERR_IRQ event.

Parameters

  InstancePtr | is a pointer to the XVphy instance. ErrIrq is the IRQ type as define in XVphy_ErrType Set is the flag to set or clear the ErrIrq param

Returns
  None.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_ClkReconfig().

void XVphy_CfgInitialize | ( | XVphy * | InstancePtr,
|  | XVphy_Config * | ConfigPtr,
|  | UINTPTR | EffectiveAddr
| ) |  |

This function retrieves the configuration for this Video PHY instance and fills in the InstancePtr->Config structure.

Parameters

  InstancePtr | is a pointer to the XVphy instance.
  ConfigPtr | is a pointer to the configuration structure that will be used to copy the settings from.
  EffectiveAddr | is the device base address in the virtual memory space. If the address translation is not used, then the physical address is passed.

Returns
  None.

Note
  Unexpected errors may occur if the address mapping is changed after this function is invoked.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_Config::DruRefClkSel, XVphy::IsReady, XVphy_Config::RxRefClkSel, XVphy_Config::RxSysPllClkSel, XVphy_Config::TxRefClkSel, XVphy_Config::TxSysPllClkSel, and XVphy_Config::XcvrType.

u32 XVphy_CfgLineRate | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | u64 | LineRateHz
| ) |  |

Configure the channel's line rate.

This is a software only configuration and this value is used in the PLL calculator.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID to operate on.
  LineRate | is the line rate to configure software.

Returns
  - XST_SUCCESS if the reference clock type is valid.
  - XST_FAILURE otherwise.

Note
  None.

References XVphy_Channel::LineRateHz, XVphy::Quads, and XVphy_Ch2Ids().

void XVphy_CfgPllRefClkSel | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | XVphy_PllRefClkSelType | RefClkSel
| ) |  |

Configure the PLL reference clock selection for the specified channel(s).

This is applied to both direction to the software configuration only.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID to operate on.
  SysClkDataSel | is the reference clock selection to configure.

Returns
  None.

Note
  None.

References XVphy::Quads, and XVphy_Ch2Ids().

Referenced by XVphy_PllInitialize().

void XVphy_CfgSysClkDataSel | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_DirectionType | Dir,
|  | XVphy_SysClkDataSelType | SysClkDataSel
| ) |  |

Configure the SYSCLKDATA reference clock selection for the direction.

Same configuration applies to all channels in the quad. This is applied to the software configuration only.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  Dir | is an indicator for TX or RX.
  SysClkDataSel | is the reference clock selection to configure.

Returns
  None.

Note
  None.

References XVphy::Quads, and XVphy_Ch2Ids().

Referenced by XVphy_PllInitialize().

void XVphy_CfgSysClkOutSel | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_DirectionType | Dir,
|  | XVphy_SysClkOutSelType | SysClkOutSel
| ) |  |

Configure the SYSCLKOUT reference clock selection for the direction.

Same configuration applies to all channels in the quad. This is applied to the software configuration only.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  Dir | is an indicator for TX or RX.
  SysClkOutSel | is the reference clock selection to configure.

Returns
  None.

Note
  None.

References XVphy::Quads, and XVphy_Ch2Ids().

Referenced by XVphy_PllInitialize().

void XVphy_Ch2Ids | ( | XVphy * | InstancePtr,
|  | XVphy_ChannelId | ChId,
|  | u8 * | Id0,
|  | u8 * | Id1
| ) |  |

This function will set the channel IDs to correspond with the supplied channel ID based on the protocol.

HDMI uses 3 channels; DP uses 4. This ID translation is done to allow other functions to operate iteratively over multiple channels.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  ChId | is the channel ID used to determine the indices.
  Id0 | is a pointer to the start channel ID to set.
  Id1 | is a pointer to the end channel ID to set.

Returns
  None.

Note
  The contents of Id0 and Id1 will be set according to ChId.

References XVphy::Config, XVphy_Config::RxChannels, XVphy_Config::TxChannels, XVphy_Config::UseGtAsTxTmdsClk, XVphy_Config::XcvrType, and XVphy_IsHDMI().

Referenced by XVphy_CfgLineRate(), XVphy_CfgPllRefClkSel(), XVphy_CfgSysClkDataSel(), XVphy_CfgSysClkOutSel(), XVphy_ClkCalcParams(), XVphy_ClkReconfig(), XVphy_DirReconfig(), XVphy_OutDivReconfig(), XVphy_PllCalculator(), XVphy_PowerDownGtPll(), and XVphy_SetPrbsSel().

u32 XVphy_ClkCalcParams | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | XVphy_DirectionType | Dir,
|  | u32 | PllClkInFreqHz
| ) |  |

This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency.

This will be done for all channels specified by ChId. This function is a wrapper for XVphy_PllCalculator.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to calculate the PLL values for.
  ChId | is the channel ID to calculate the PLL values for.
  Dir | is an indicator for TX or RX.
  PllClkInFreqHz | is the PLL input frequency on which to base the calculations on. A value of 0 indicates to use the currently configured quad PLL reference clock. A non-zero value indicates to ignore what is currently configured in SW, and use a custom frequency instead.

Returns
  - XST_SUCCESS if valid PLL values were found to satisfy the constraints.
  - XST_FAILURE otherwise.

Note
  If successful, the channel's PllParams structure will be modified with the valid PLL parameters.

References XVphy_Ch2Ids(), and XVphy_PllCalculator().

void XVphy_Clkout1OBufTdsEnable | ( | XVphy * | InstancePtr,
|  | XVphy_DirectionType | Dir,
|  | u8 | Enable
| ) |  |

This function enables the TX or RX CLKOUT1 OBUFTDS peripheral.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  Dir | is an indicator for TX or RX.
  Enable | specifies TRUE/FALSE value to either enable or disable the OBUFTDS, respectively.

Returns
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

u32 XVphy_ClkReconfig | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId
| ) |  |

This function will set the current clocking settings for each channel to hardware based on the configuration stored in the driver's instance.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID for which to write the settings for.

Returns
  - XST_SUCCESS if the configuration was successful.
  - XST_FAILURE otherwise.

Note
  None.

References XVphy::Config, XVphy::HdmiIsQpllPresent, XVphy_Config::XcvrType, XVphy_CfgErrIntr(), XVphy_Ch2Ids(), XVPHY_ERR_NO_QPLL, XVphy_ErrorHandler(), XVphy_IsHDMI(), XVPHY_LOG_EVT_CPLL_RECONFIG, XVPHY_LOG_EVT_NO_QPLL_ERR, XVPHY_LOG_EVT_PLL0_RECONFIG, XVPHY_LOG_EVT_PLL1_RECONFIG, XVPHY_LOG_EVT_QPLL_RECONFIG, and XVphy_LogWrite().

u32 XVphy_DirReconfig | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | XVphy_DirectionType | Dir
| ) |  |

This function will set the current RX/TX configuration over DRP.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID for which to write the settings for.
  Dir | is an indicator for RX or TX.

Returns
  - XST_SUCCESS if the configuration was successful.
  - XST_FAILURE otherwise.

Note
  None.

References XVphy::Config, XVphy_Config::RxProtocol, XVphy_Config::TxProtocol, XVphy_Config::XcvrType, XVphy_Ch2Ids(), XVPHY_LOG_EVT_GT_RX_RECONFIG, XVPHY_LOG_EVT_GT_TX_RECONFIG, and XVphy_LogWrite().

u16 XVphy_DrpRd | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | u16 | Addr,
|  | u16 * | RetVal
| ) |  |

This function will initiate a read DRP transaction.

It is a wrapper around XVphy_DrpAccess.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID on which to direct the DRP access.
  Addr | is the DRP address to issue the DRP access to.
  RetVal | is the DRP read_value returned implicitly.

Returns
  - XST_SUCCESS if the DRP access was successful.
  - XST_FAILURE otherwise, if the busy bit did not go low, or if the ready bit did not go high.

Note
  None.

Referenced by XVphy_RegisterDebug().

u32 XVphy_DrpWr | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | u16 | Addr,
|  | u16 | Val
| ) |  |

This function will initiate a write DRP transaction.

It is a wrapper around XVphy_DrpAccess.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID on which to direct the DRP access.
  Addr | is the DRP address to issue the DRP access to.
  Val | is the value to write to the DRP address.

Returns
  - XST_SUCCESS if the DRP access was successful.
  - XST_FAILURE otherwise, if the busy bit did not go low, or if the ready bit did not go high.

Note
  None.

Referenced by XVphy_MmcmWriteParameters().

void XVphy_ErrorHandler | ( | XVphy * | InstancePtr | ) |

This function is the error condition handler.

Parameters

  InstancePtr | is a pointer to the VPHY instance.
  ErrIrqType | is the error type

Returns
  None.

Note
  None.

References XVphy::ErrorCallback, and XVphy::ErrorRef.

Referenced by XVphy_ClkReconfig().

u64 XVphy_GetLineRateHz | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId
| ) |  |

This function will return the line rate in Hz for a given channel / quad.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to check.
  ChId | is the channel ID for which to retrieve the line rate.

Returns
  The line rate in Hz.

Note
  None.

References XVphy_Channel::LineRateHz, and XVphy::Quads.

XVphy_PllType XVphy_GetPllType | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_DirectionType | Dir,
|  | XVphy_ChannelId | ChId
| ) |  |

Obtain the channel's PLL reference clock selection.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  Dir | is an indicator for TX or RX.
  ChId | is the channel ID which to operate on.

Returns
  The PLL type being used by the channel.

Note
  None.

References XVphy::Config, XVphy_Config::XcvrType, XVphy_GetSysClkDataSel(), and XVphy_GetSysClkOutSel().

Referenced by XVphy_IsPllLocked().

u64 XVphy_GetPllVcoFreqHz | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | XVphy_DirectionType | Dir
| ) |  |

This function calculates the PLL VCO operating frequency.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  Dir | is an indicator for TX or RX.

Returns
  PLL VCO frequency in Hz

Note
  None.

References XVphy::HdmiRxDruIsEnabled, XVphy::HdmiRxRefClkHz, XVphy::HdmiTxRefClkHz, XVphy::Quads, XVphy_GetQuadRefClkFreq(), and XVphy_IsHDMI().

u32 XVphy_GetQuadRefClkFreq | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_PllRefClkSelType | RefClkType
| ) |  |

Obtain the current reference clock frequency for the quad based on the reference clock type.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  RefClkType | is the type to obtain the clock selection for.

Returns
  The current reference clock frequency for the quad for the specified type selection.

Note
  None.

References XVphy::Quads.

Referenced by XVphy_GetPllVcoFreqHz(), and XVphy_PllCalculator().

XVphy_ChannelId XVphy_GetRcfgChId | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_DirectionType | Dir,
|  | XVphy_PllType | PllType
| ) |  |

Obtain the reconfiguration channel ID for given PLL type.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  Dir | is an indicator for TX or RX.
  PllType | is the PLL type being used by the channel.

Returns
  The Channel ID to be used for reconfiguration

Note
  None.

u8 XVphy_GetRefClkSourcesCount | ( | XVphy * | InstancePtr | ) |

This function returns the number of active reference clock sources based in the CFG.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.

Returns
  No of active REFCLK sources

Note
  None.

References XVphy::Config, XVphy_Config::DruIsPresent, XVphy_Config::DruRefClkSel, XVphy_Config::RxProtocol, XVphy_Config::RxRefClkSel, XVphy_Config::TxProtocol, and XVphy_Config::TxRefClkSel.

XVphy_SysClkDataSelType XVphy_GetSysClkDataSel | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_DirectionType | Dir,
|  | XVphy_ChannelId | ChId
| ) |  |

Obtain the current [RT]XSYSCLKSEL[0] configuration.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  Dir | is an indicator for TX or RX.
  ChId | is the channel ID which to operate on.

Returns
  The current [RT]XSYSCLKSEL[0] selection.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_Config::XcvrType, and XVphy_ReadReg.

Referenced by XVphy_GetPllType(), and XVphy_IsBonded().

XVphy_SysClkOutSelType XVphy_GetSysClkOutSel | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_DirectionType | Dir,
|  | XVphy_ChannelId | ChId
| ) |  |

Obtain the current [RT]XSYSCLKSEL[1] configuration.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  Dir | is an indicator for TX or RX.
  ChId | is the channel ID which to operate on.

Returns
  The current [RT]XSYSCLKSEL[1] selection.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_Config::XcvrType, and XVphy_ReadReg.

Referenced by XVphy_GetPllType(), and XVphy_IsBonded().

u32 XVphy_GetVersion | ( | XVphy * | InstancePtr | ) |

This function will obtian the IP version.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.

Returns
  The IP version of the Video PHY core.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, and XVphy_ReadReg.

u32 XVphy_GtUserRdyEnable | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | XVphy_DirectionType | Dir,
|  | u8 | Hold
| ) |  |

This function will reset and enable the Video PHY's user core logic.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID which to operate on.
  Dir | is an indicator for TX or RX.
  Hold | is an indicator whether to "hold" the reset if set to 1. If set to 0: reset, then enable.

Returns
  - XST_SUCCESS.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

void XVphy_IBufDsEnable | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_DirectionType | Dir,
|  | u8 | Enable
| ) |  |

This function enables the TX or RX IBUFDS peripheral.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  Dir | is an indicator for TX or RX.
  Enable | specifies TRUE/FALSE value to either enable or disable the IBUFDS, respectively.

Returns
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_Config::DruIsPresent, XVphy_Config::DruRefClkSel, XVphy_Config::RxRefClkSel, XVphy_Config::TxRefClkSel, XVphy_ReadReg, and XVphy_WriteReg.

void XVphy_InterruptHandler | ( | XVphy * | InstancePtr | ) |

This function is the interrupt handler for the XVphy driver.

It will detect what kind of interrupt has happened, and will invoke the appropriate callback function.

Parameters

  InstancePtr | is a pointer to the XVphy instance.

Returns
  None.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy::IntrCpllLockCallbackRef, XVphy::IntrCpllLockHandler, XVphy::IntrQpll1LockCallbackRef, XVphy::IntrQpll1LockHandler, XVphy::IntrQpllLockCallbackRef, XVphy::IntrQpllLockHandler, XVphy::IntrRxClkDetFreqChangeCallbackRef, XVphy::IntrRxClkDetFreqChangeHandler, XVphy::IntrRxMmcmLockCallbackRef, XVphy::IntrRxMmcmLockHandler, XVphy::IntrRxResetDoneCallbackRef, XVphy::IntrRxResetDoneHandler, XVphy::IntrRxTmrTimeoutCallbackRef, XVphy::IntrRxTmrTimeoutHandler, XVphy::IntrTxAlignDoneCallbackRef, XVphy::IntrTxAlignDoneHandler, XVphy::IntrTxClkDetFreqChangeCallbackRef, XVphy::IntrTxClkDetFreqChangeHandler, XVphy::IntrTxMmcmLockCallbackRef, XVphy::IntrTxMmcmLockHandler, XVphy::IntrTxResetDoneCallbackRef, XVphy::IntrTxResetDoneHandler, XVphy::IntrTxTmrTimeoutCallbackRef, XVphy::IntrTxTmrTimeoutHandler, XVphy::IsReady, and XVphy_ReadReg.

void XVphy_IntrDisable | ( | XVphy * | InstancePtr,
|  | XVphy_IntrHandlerType | Intr
| ) |  |

This function disabled interrupts associated with the specified interrupt type.

Parameters

  InstancePtr | is a pointer to the XVphy instance.
  Intr | is the interrupt type/mask to disable.

Returns
  None.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

void XVphy_IntrEnable | ( | XVphy * | InstancePtr,
|  | XVphy_IntrHandlerType | Intr
| ) |  |

This function enables interrupts associated with the specified interrupt type.

Parameters

  InstancePtr | is a pointer to the XVphy instance.
  Intr | is the interrupt type/mask to enable.

Returns
  None.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

u32 XVphy_IsBonded | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId
| ) |  |

This function returns true when the RX and TX are bonded and are running from the same (RX) reference clock.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.

Returns
  TRUE if the RX and TX are using the same PLL, FALSE otherwise.

Note
  None.

References XVphy_GetSysClkDataSel(), and XVphy_GetSysClkOutSel().

u8 XVphy_IsHDMI | ( | XVphy * | InstancePtr,
|  | XVphy_DirectionType | Dir
| ) |  |

This function checks if Instance is HDMI 2.0 or HDMI 2.1.

Parameters

  InstancePtr | is a pointer to the VPHY instance.
  Dir | is an indicator for RX or TX.

Returns
  TRUE if HDMI 2.0 or 2.1 else FALSE.

Note
  None.

References XVphy::Config, XVphy_Config::RxProtocol, and XVphy_Config::TxProtocol.

Referenced by XVphy_Ch2Ids(), XVphy_ClkReconfig(), XVphy_GetPllVcoFreqHz(), XVphy_IsPllLocked(), XVphy_MmcmStart(), and XVphy_MmcmWriteParameters().

u32 XVphy_IsPllLocked | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId
| ) |  |

This function will check the status of a PLL lock on the specified channel.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID which to operate on.

Returns
  - XST_SUCCESS if the specified PLL is locked.
  - XST_FAILURE otherwise.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_GetPllType(), XVphy_IsHDMI(), and XVphy_ReadReg.

void XVphy_LogDisplay | ( | XVphy * | InstancePtr | ) |

This function will print the entire log.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.

Returns
  None.

Note
  None.

References XVPHY_LOG_EVT_1PPC_ERR, XVPHY_LOG_EVT_CPLL_EN, XVPHY_LOG_EVT_CPLL_LOCK, XVPHY_LOG_EVT_CPLL_RECONFIG, XVPHY_LOG_EVT_CPLL_RST, XVPHY_LOG_EVT_DRU_CLK_ERR, XVPHY_LOG_EVT_DRU_EN, XVPHY_LOG_EVT_GT_CPLL_CFG_ERR, XVPHY_LOG_EVT_GT_PLL_LAYOUT, XVPHY_LOG_EVT_GT_QPLL_CFG_ERR, XVPHY_LOG_EVT_GT_RECONFIG, XVPHY_LOG_EVT_GT_RX_RECONFIG, XVPHY_LOG_EVT_GT_TX_RECONFIG, XVPHY_LOG_EVT_GT_UNBONDED, XVPHY_LOG_EVT_GTRX_RST, XVPHY_LOG_EVT_GTTX_RST, XVPHY_LOG_EVT_HDMI20_ERR, XVPHY_LOG_EVT_INIT, XVPHY_LOG_EVT_MMCM_ERR, XVPHY_LOG_EVT_NO_DRU, XVPHY_LOG_EVT_NO_QPLL_ERR, XVPHY_LOG_EVT_NONE, XVPHY_LOG_EVT_PLL0_LOCK, XVPHY_LOG_EVT_PLL0_RECONFIG, XVPHY_LOG_EVT_PLL1_LOCK, XVPHY_LOG_EVT_PLL1_RECONFIG, XVPHY_LOG_EVT_PPC_MSMTCH_ERR, XVPHY_LOG_EVT_QPLL_EN, XVPHY_LOG_EVT_QPLL_LOCK, XVPHY_LOG_EVT_QPLL_RECONFIG, XVPHY_LOG_EVT_QPLL_RST, XVPHY_LOG_EVT_RX_FREQ, XVPHY_LOG_EVT_RX_RST_DONE, XVPHY_LOG_EVT_RX_TMR, XVPHY_LOG_EVT_RXPLL_EN, XVPHY_LOG_EVT_RXPLL_LOCK, XVPHY_LOG_EVT_RXPLL_RECONFIG, XVPHY_LOG_EVT_RXPLL_RST, XVPHY_LOG_EVT_TX_ALIGN, XVPHY_LOG_EVT_TX_ALIGN_TMOUT, XVPHY_LOG_EVT_TX_FREQ, XVPHY_LOG_EVT_TX_RST_DONE, XVPHY_LOG_EVT_TX_TMR, XVPHY_LOG_EVT_TXPLL_EN, XVPHY_LOG_EVT_TXPLL_LOCK, XVPHY_LOG_EVT_TXPLL_RECONFIG, XVPHY_LOG_EVT_TXPLL_RST, XVPHY_LOG_EVT_USRCLK_ERR, XVPHY_LOG_EVT_VD_NOT_SPRTD_ERR, XVPHY_LOG_EVT_VDCLK_HIGH_ERR, XVPHY_LOG_EVT_VID_RX_RST, XVPHY_LOG_EVT_VID_TX_RST, and XVphy_LogRead().

u16 XVphy_LogRead | ( | XVphy * | InstancePtr | ) |

This function will read the last event from the log.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.

Returns
  The log data.

Note
  None.

References XVphy_Log::DataBuffer, XVphy_Log::HeadIndex, XVphy::Log, and XVphy_Log::TailIndex.

Referenced by XVphy_LogDisplay().

void XVphy_LogReset | ( | XVphy * | InstancePtr | ) |

This function will reset the driver's logginc mechanism.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.

Returns
  None.

Note
  None.

References XVphy_Log::HeadIndex, XVphy::Log, and XVphy_Log::TailIndex.

void XVphy_LogWrite | ( | XVphy * | InstancePtr,
|  | XVphy_LogEvent | Evt,
|  | u8 | Data
| ) |  |

This function will insert an event in the driver's logginc mechanism.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  Evt | is the event type to log.
  Data | is the associated data for the event.

Returns
  None.

Note
  None.

References XVphy_Log::DataBuffer, XVphy_Log::HeadIndex, XVphy::Log, XVphy_Log::TailIndex, and XVPHY_LOG_EVT_DUMMY.

Referenced by XVphy_ClkReconfig(), XVphy_DirReconfig(), XVphy_MmcmStart(), and XVphy_OutDivReconfig().

XVphy_Config* XVphy_LookupConfig | ( | u16 | DeviceId | ) |

This function looks for the device configuration based on the unique device ID.

The table XVphy_ConfigTable[] contains the configuration information for each device in the system.

Parameters

  DeviceId | is the unique device ID of the device being looked up.

Returns
  A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.

Note
  None.

u8 XVphy_MmcmLocked | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_DirectionType | Dir
| ) |  |

This function will get the lock status of the mixed-mode clock manager (MMCM) core.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  Dir | is an indicator for TX or RX.

Returns
  TRUE if Locked else FALSE.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, and XVphy_ReadReg.

void XVphy_MmcmLockedMaskEnable | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_DirectionType | Dir,
|  | u8 | Enable
| ) |  |

This function will reset the mixed-mode clock manager (MMCM) core.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  Dir | is an indicator for TX or RX.
  Enable | is an indicator whether to "Enable" the locked mask if set to 1. If set to 0: reset, then disable.

Returns
  None.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_MmcmStart().

void XVphy_MmcmPowerDown | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_DirectionType | Dir,
|  | u8 | Hold
| ) |  |

This function will power down the mixed-mode clock manager (MMCM) core.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  Dir | is an indicator for TX or RX.
  Hold | is an indicator whether to "hold" the power down if set to 1. If set to 0: power down, then power back up.

Returns
  - XST_SUCCESS.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_MmcmStart().

void XVphy_MmcmReset | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_DirectionType | Dir,
|  | u8 | Hold
| ) |  |

This function will reset the mixed-mode clock manager (MMCM) core.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  Dir | is an indicator for TX or RX.
  Hold | is an indicator whether to "hold" the reset if set to 1. If set to 0: reset, then enable.

Returns
  - XST_SUCCESS.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

Referenced by XVphy_MmcmStart().

void XVphy_MmcmStart | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_DirectionType | Dir
| ) |  |

This function will start the mixed-mode clock manager (MMCM) core.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  Dir | is an indicator for TX or RX.

Returns
  None.

Note
  None.

References XVphy::Config, XVphy::Quads, XVphy_Quad::RxMmcm, XVphy_Config::RxProtocol, XVphy_Quad::TxMmcm, XVphy_Config::TxProtocol, XVphy_IsHDMI(), XVPHY_LOG_EVT_RXPLL_RECONFIG, XVPHY_LOG_EVT_TXPLL_RECONFIG, XVphy_LogWrite(), XVphy_MmcmLockedMaskEnable(), XVphy_MmcmPowerDown(), XVphy_MmcmReset(), XVphy_MmcmWriteParameters(), and XVphy_WaitUs().

u32 XVphy_MmcmWriteParameters | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_DirectionType | Dir
| ) |  |

This function will write the mixed-mode clock manager (MMCM) values currently stored in the driver's instance structure to hardware .

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  Dir | is an indicator for TX or RX.

Returns
  - XST_SUCCESS if the MMCM write was successful.
  - XST_FAILURE otherwise, if the configuration success bit did not go low.

Note
  None.

References XVphy_Quad::Mmcm, XVphy::Quads, XVphy_DrpWr(), and XVphy_IsHDMI().

Referenced by XVphy_MmcmStart().

u32 XVphy_OutDivReconfig | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | XVphy_DirectionType | Dir
| ) |  |

This function will set the current output divider configuration over DRP.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID for which to write the settings for.
  Dir | is an indicator for RX or TX.

Returns
  - XST_SUCCESS if the configuration was successful.
  - XST_FAILURE otherwise.

Note
  None.

References XVphy_Ch2Ids(), XVPHY_LOG_EVT_GT_RX_RECONFIG, XVPHY_LOG_EVT_GT_TX_RECONFIG, and XVphy_LogWrite().

u32 XVphy_PllCalculator | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | XVphy_DirectionType | Dir,
|  | u32 | PllClkInFreqHz
| ) |  |

This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to calculate the PLL values for.
  ChId | is the channel ID to calculate the PLL values for.
  Dir | is an indicator for TX or RX.
  PllClkInFreqHz | is the PLL input frequency on which to base the calculations on. A value of 0 indicates to use the currently configured quad PLL reference clock. A non-zero value indicates to ignore what is currently configured in SW, and use a custom frequency instead.

Returns
  - XST_SUCCESS if valid PLL values were found to satisfy the constraints.
  - XST_FAILURE otherwise.

Note
  If successful, the channel's PllParams structure will be modified with the valid PLL parameters.

References XVphy::Config, XVphy_Channel::LineRateHz, XVphy::Quads, XVphy_Config::XcvrType, XVphy_Ch2Ids(), and XVphy_GetQuadRefClkFreq().

Referenced by XVphy_ClkCalcParams().

u32 XVphy_PllInitialize | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | XVphy_PllRefClkSelType | QpllRefClkSel,
|  | XVphy_PllRefClkSelType | CpllRefClkSel,
|  | XVphy_PllType | TxPllSelect,
|  | XVphy_PllType | RxPllSelect
| ) |  |

This function will initialize the PLL selection for a given channel.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID to operate on.
  QpllRefClkSel | is the QPLL reference clock selection for the quad. In GTP, this is used to hold PLL0 refclk selection.
  CpllRefClkSel | is the CPLL reference clock selection for the quad. In GTP, this is used to hold PLL1 refclk selection.
  TxPllSelect | is the reference clock selection for the quad's TX PLL dividers.
  RxPllSelect | is the reference clock selection for the quad's RX PLL dividers.

Returns
  - XST_SUCCESS.

Note
  None.

References XVphy::Config, Pll2SysClkData(), Pll2SysClkOut(), XVphy_Config::XcvrType, XVphy_CfgPllRefClkSel(), XVphy_CfgSysClkDataSel(), XVphy_CfgSysClkOutSel(), and XVphy_WriteCfgRefClkSelReg().

u32 XVphy_PowerDownGtPll | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | u8 | Hold
| ) |  |

This function will power down the specified GT PLL.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID to power down the PLL for.
  Dir | is an indicator for TX or RX.
  Hold | is an indicator whether to "hold" the power down if set to 1. If set to 0: power down, then power back up.

Returns
  - XST_SUCCESS.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_Ch2Ids(), XVphy_ReadReg, and XVphy_WriteReg.

void XVphy_RegisterDebug | ( | XVphy * | InstancePtr | ) |

This function prints out Video PHY register and GT Channel and Common DRP register contents.

Parameters

  InstancePtr | is a pointer to the Vphy core instance.

Returns
  None.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy::HdmiIsQpllPresent, XVphy_Config::RxChannels, XVphy_Config::RxProtocol, XVphy_Config::TxChannels, XVphy_Config::TxProtocol, XVphy_DrpRd(), and XVphy_ReadReg.

u32 XVphy_ResetGtPll | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | XVphy_DirectionType | Dir,
|  | u8 | Hold
| ) |  |

This function will reset the GT's PLL logic.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID which to operate on.
  Dir | is an indicator for TX or RX.
  Hold | is an indicator whether to "hold" the reset if set to 1. If set to 0: reset, then enable.

Returns
  - XST_SUCCESS.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

u32 XVphy_ResetGtTxRx | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | XVphy_DirectionType | Dir,
|  | u8 | Hold
| ) |  |

This function will reset the GT's TX/RX logic.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID which to operate on.
  Dir | is an indicator for TX or RX.
  Hold | is an indicator whether to "hold" the reset if set to 1. If set to 0: reset, then enable.

Returns
  - XST_SUCCESS.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

u32 XVphy_SelfTest | ( | XVphy * | InstancePtr | ) |

This function runs a self-test on the XVphy driver/device.

The sanity test checks whether or not all tested registers hold their default reset values.

Parameters

  InstancePtr | is a pointer to the XVphy instance.

Returns
  - XST_SUCCESS if the self-test passed - all tested registers hold their default reset values.
  - XST_FAILURE otherwise.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, and XVphy_ReadReg.

void XVphy_SetBufgGtDiv | ( | XVphy * | InstancePtr,
|  | XVphy_DirectionType | Dir,
|  | u8 | Div
| ) |  |

This function obtains the divider value of the BUFG_GT peripheral.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  Dir | is an indicator for TX or RX
  Div | 3-bit divider value

Returns
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

void XVphy_SetErrorCallback | ( | XVphy * | InstancePtr,
|  | void * | CallbackFunc,
|  | void * | CallbackRef
| ) |  |

This function installs a callback function for the VPHY error conditions.

Parameters

  InstancePtr | is a pointer to the XVPhy instance.
  CallbackFunc | is the address to the callback function.
  CallbackRef | is the user data item that will be passed to the callback function when it is invoked.

Returns
  None.

Note
  The XVphy_ErrorHandler API calls the registered function in ErrorCallback and passes two arguments: 1) CallbackRef 2) Error Type as defined by XVphy_ErrType.

Sample Function Call: CallbackFunc(CallbackRef, XVphy_ErrType);

References XVphy::ErrorCallback, and XVphy::ErrorRef.

void XVphy_SetIntrHandler | ( | XVphy * | InstancePtr,
|  | XVphy_IntrHandlerType | HandlerType,
|  | XVphy_IntrHandler | CallbackFunc,
|  | void * | CallbackRef
| ) |  |

This function installs a callback function for the specified handler type.

Parameters

  InstancePtr | is a pointer to the XVPhy instance.
  HandlerType | is the interrupt handler type which specifies which interrupt event to attach the callback for.
  CallbackFunc | is the address to the callback function.
  CallbackRef | is the user data item that will be passed to the callback function when it is invoked.

Returns
  None.

Note
  None.

References XVphy::IntrCpllLockCallbackRef, XVphy::IntrCpllLockHandler, XVphy::IntrQpll1LockCallbackRef, XVphy::IntrQpll1LockHandler, XVphy::IntrQpllLockCallbackRef, XVphy::IntrQpllLockHandler, XVphy::IntrRxClkDetFreqChangeCallbackRef, XVphy::IntrRxClkDetFreqChangeHandler, XVphy::IntrRxMmcmLockCallbackRef, XVphy::IntrRxMmcmLockHandler, XVphy::IntrRxResetDoneCallbackRef, XVphy::IntrRxResetDoneHandler, XVphy::IntrRxTmrTimeoutCallbackRef, XVphy::IntrRxTmrTimeoutHandler, XVphy::IntrTxAlignDoneCallbackRef, XVphy::IntrTxAlignDoneHandler, XVphy::IntrTxClkDetFreqChangeCallbackRef, XVphy::IntrTxClkDetFreqChangeHandler, XVphy::IntrTxMmcmLockCallbackRef, XVphy::IntrTxMmcmLockHandler, XVphy::IntrTxResetDoneCallbackRef, XVphy::IntrTxResetDoneHandler, XVphy::IntrTxTmrTimeoutCallbackRef, and XVphy::IntrTxTmrTimeoutHandler.

u32 XVphy_SetPolarity | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | XVphy_DirectionType | Dir,
|  | u8 | Polarity
| ) |  |

This function will set/clear the TX/RX polarity bit.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID which to operate on.
  Dir | is an indicator for TX or RX.
  Polarity | 0-Not inverted 1-Inverted

Returns
  - XST_SUCCESS.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

u32 XVphy_SetPrbsSel | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | XVphy_DirectionType | Dir,
|  | XVphy_PrbsPattern | Pattern
| ) |  |

This function will set the TX/RXPRBSEL of the GT.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID which to operate on.
  Dir | is an indicator for TX or RX.
  Pattern | is the pattern XVphy_PrbsPattern

Returns
  - XST_SUCCESS.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_Ch2Ids(), XVphy_ReadReg, and XVphy_WriteReg.

void XVphy_SetRxLpm | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | XVphy_DirectionType | Dir,
|  | u8 | Enable
| ) |  |

This function will enable or disable the LPM logic in the Video PHY core.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID to operate on.
  Dir | is an indicator for TX or RX.
  Enable | will enable (if 1) or disable (if 0) the LPM logic.

Returns
  None.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

void XVphy_SetTxPostCursor | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | u8 | Pc
| ) |  |

This function will set the TX post-curosr value for a given channel.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID to operate on.
  Pe | is the pre-emphasis value to write.

Returns
  None.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

void XVphy_SetTxPreEmphasis | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | u8 | Pe
| ) |  |

This function will set the TX pre-emphasis value for a given channel.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID to operate on.
  Pe | is the pre-emphasis value to write.

Returns
  None.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

void XVphy_SetTxVoltageSwing | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | u8 | Vs
| ) |  |

This function will set the TX voltage swing value for a given channel.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID to operate on.
  Vs | is the voltage swing value to write.

Returns
  None.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

u32 XVphy_TxPrbsForceError | ( | XVphy * | InstancePtr,
|  | u8 | QuadId,
|  | XVphy_ChannelId | ChId,
|  | u8 | ForceErr
| ) |  |

This function will set the TX/RXPRBSEL of the GT.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.
  ChId | is the channel ID which to operate on.
  Dir | is an indicator for TX or RX.
  ForceErr | 0-No Error 1-Force Error

Returns
  - XST_SUCCESS.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_ReadReg, and XVphy_WriteReg.

void XVphy_WaitUs | ( | XVphy * | InstancePtr,
|  | u32 | MicroSeconds
| ) |  |

This function is the delay/sleep function for the XVphy driver.

For the Zynq family, there exists native sleep functionality. For MicroBlaze however, there does not exist such functionality. In the MicroBlaze case, the default method for delaying is to use a predetermined amount of loop iterations. This method is prone to inaccuracy and dependent on system configuration; for greater accuracy, the user may supply their own delay/sleep handler, pointed to by InstancePtr->UserTimerWaitUs, which may have better accuracy if a hardware timer is used.

Parameters

  InstancePtr | is a pointer to the XVphy instance.
  MicroSeconds | is the number of microseconds to delay/sleep for.

Returns
  None.

Note
  None.

References XVphy::IsReady, and XVphy::UserTimerWaitUs.

Referenced by XVphy_MmcmStart().

u32 XVphy_WriteCfgRefClkSelReg | ( | XVphy * | InstancePtr,
|  | u8 | QuadId
| ) |  |

This function writes the current software configuration for the reference clock selections to hardware for the specified quad on all channels.

Parameters

  InstancePtr | is a pointer to the XVphy core instance.
  QuadId | is the GT quad ID to operate on.

Returns
  - XST_SUCCESS.

Note
  None.

References XVphy_Config::BaseAddr, XVphy::Config, XVphy_Channel::CpllRefClkSel, XVphy::Quads, XVphy_Channel::RxDataRefClkSel, XVphy_Channel::RxOutRefClkSel, XVphy_Channel::TxDataRefClkSel, XVphy_Channel::TxOutRefClkSel, XVphy_Config::XcvrType, and XVphy_WriteReg.

Referenced by XVphy_PllInitialize().