usbps: Usbps_v2_4

| usbps Xilinx SDK Drivers API Documentation

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Macros | Functions | Variables
Usbps_v2_4

## Macros
#define | XUSBPS_MAX_PACKET_SIZE 1024
| Maximum value can be put into the queue head. More...
#define | XUSBPS_dTDNLP 0x00
| Endpoint Device Transfer Descriptor. More...
#define | XUSBPS_dTDTOKEN 0x04
| Descriptor Token. More...
#define | XUSBPS_dTDBPTR0 0x08
| Buffer Pointer 0. More...
#define | XUSBPS_dTDBPTR1 0x0C
| Buffer Pointer 1. More...
#define | XUSBPS_dTDBPTR2 0x10
| Buffer Pointer 2. More...
#define | XUSBPS_dTDBPTR3 0x14
| Buffer Pointer 3. More...
#define | XUSBPS_dTDBPTR4 0x18
| Buffer Pointer 4. More...
#define | XUSBPS_dTDRSRVD 0x1C
| Reserved field. More...
#define | XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD
| Reserved field. More...
#define | XUsbPs_dTDInvalidateCache(dTDPtr) Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
| # IMPORTANT NOTE: More...
#define | XUsbPs_dTDSetTransferLen(dTDPtr, Len)
| This macro sets the Transfer Length for the given Transfer Descriptor. More...
#define | XUsbPs_dTDGetNLP(dTDPtr)
| This macro gets the Next Link pointer of the given Transfer Descriptor. More...
#define | XUsbPs_dTDSetNLP(dTDPtr, NLP)
| This macro sets the Next Link pointer of the given Transfer Descriptor. More...
#define | XUsbPs_dTDGetTransferLen(dTDPtr)
| This macro gets the Transfer Length for the given Transfer Descriptor. More...
#define | XUsbPs_dTDSetIOC(dTDPtr)
| This macro sets the Interrupt On Complete (IOC) bit for the given Transfer Descriptor. More...
#define | XUsbPs_dTDSetTerminate(dTDPtr)
| This macro sets the Terminate bit for the given Transfer Descriptor. More...
#define | XUsbPs_dTDClrTerminate(dTDPtr)
| This macro clears the Terminate bit for the given Transfer Descriptor. More...
#define | XUsbPs_dTDIsActive(dTDPtr)
| This macro checks if the given descriptor is active. More...
#define | XUsbPs_dTDSetActive(dTDPtr)
| This macro sets the Active bit for the given Transfer Descriptor. More...
#define | XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
| This macro reads the content of a field in a Transfer Descriptor. More...
#define | XUsbPs_WritedTD(dTDPtr, Id, Val) (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
| This macro writes a value to a field in a Transfer Descriptor. More...
#define | XUSBPS_dQHCFG 0x00
| Endpoint Device Queue Head. More...
#define | XUSBPS_dQHCPTR 0x04
| dQH Current dTD Pointer More...
#define | XUSBPS_dQHdTDNLP 0x08
| dTD Next Link Ptr in dQH overlay More...
#define | XUSBPS_dQHdTDTOKEN 0x0C
| dTD Token in dQH overlay More...
#define | XUSBPS_dQHSUB0 0x28
| USB dQH Setup Buffer 0. More...
#define | XUSBPS_dQHSUB1 0x2C
| USB dQH Setup Buffer 1. More...
#define | XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len)
| This macro sets the Maximum Packet Length field of the give Queue Head. More...
#define | XUsbPs_dQHSetIOS(dQHPtr)
| This macro sets the Interrupt On Setup (IOS) bit for an endpoint. More...
#define | XUsbPs_dQHClrIOS(dQHPtr)
| This macro clears the Interrupt On Setup (IOS) bit for an endpoint. More...
#define | XUsbPs_dQHEnableZLT(dQHPtr)
| This macro enables Zero Length Termination for the endpoint. More...
#define | XUsbPs_dQHDisableZLT(dQHPtr)
| This macro disables Zero Length Termination for the endpoint. More...
#define | XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
| This macro reads the content of a field in a Queue Head. More...
#define | XUsbPs_WritedQH(dQHPtr, Id, Val) (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
| This macro writes a value to a field in a Queue Head. More...
#define | XUSBPS_dQH_BASE_ALIGN 2048
| Mask for All IRQ Enable masks. More...
#define | XUSBPS_dQH_ALIGN 64
| Alignment of a Device Transfer Descriptor structure. More...
#define | XUSBPS_dTD_ALIGN 32
| Size of one RX buffer for a OUT Transfer Descriptor. More...
#define | XUSBPS_dTD_BUF_SIZE 4096
| Maximum size of one RX/TX buffer. More...
#define | XUSBPS_dTD_BUF_MAX_SIZE 16*1024
| Alignment requirement for Transfer Descriptor buffers. More...
#define | XUsbPs_ReadReg(BaseAddress, RegOffset) Xil_In32(BaseAddress + (RegOffset))
| This macro reads the given register. More...
#define | XUsbPs_WriteReg(BaseAddress, RegOffset, Data) Xil_Out32(BaseAddress + (RegOffset), (Data))
| This macro writes the given register. More...

## Functions
int | XUsbPs_CfgInitialize (XUsbPs *InstancePtr, const XUsbPs_Config *ConfigPtr, u32 VirtBaseAddress)
| This function initializes a XUsbPs instance/driver. More...
void | XUsbPs_DeviceReset (XUsbPs *InstancePtr)
| This function performs device reset, device is stopped at the end. More...
int | XUsbPs_Reset (XUsbPs *InstancePtr)
| This function resets the USB device. More...
int | XUsbPs_Suspend (const XUsbPs *InstancePtr)
| USB Suspend. More...
int | XUsbPs_Resume (const XUsbPs *InstancePtr)
| USB Resume. More...
int | XUsbPs_RequestHostResume (const XUsbPs *InstancePtr)
| USB Assert Resume. More...
int | XUsbPs_SetDeviceAddress (XUsbPs *InstancePtr, u8 Address)
| This functions sets the controller's DEVICE address. More...
int | XUsbPs_ConfigureDevice (XUsbPs *InstancePtr, const XUsbPs_DeviceConfig *CfgPtr)
| This function configures the DEVICE side of the controller. More...
int | XUsbPs_EpBufferSend (XUsbPs *InstancePtr, u8 EpNum, const u8 *BufferPtr, u32 BufferLen)
| This function sends a given data buffer. More...
int | XUsbPs_EpBufferSendWithZLT (XUsbPs *InstancePtr, u8 EpNum, const u8 *BufferPtr, u32 BufferLen)
| This function sends a given data buffer and also zero length packet if the Bufferlen is in multiples of endpoint max packet size. More...
int | XUsbPs_EpBufferReceive (XUsbPs *InstancePtr, u8 EpNum, u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle)
| This function receives a data buffer from the endpoint of the given endpoint number. More...
void | XUsbPs_EpBufferRelease (u32 Handle)
| This function returns a previously received data buffer to the driver. More...
int | XUsbPs_EpSetHandler (XUsbPs *InstancePtr, u8 EpNum, u8 Direction, XUsbPs_EpHandlerFunc CallBackFunc, void *CallBackRef)
| This function sets the handler for endpoint events. More...
int | XUsbPs_EpPrime (XUsbPs *InstancePtr, u8 EpNum, u8 Direction)
| This function primes an endpoint. More...
int | XUsbPs_EpGetSetupData (XUsbPs *InstancePtr, int EpNum, XUsbPs_SetupData *SetupDataPtr)
| This function extracts the Setup Data from a given endpoint. More...
int | XUsbPs_ReconfigureEp (XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, int EpNum, unsigned short NewDirection, int DirectionChanged)
| This function reconfigures one Ep corresponding to host's request of setting alternate interface. More...
void | XUsbPs_ResetHw (u32 BaseAddress)
| This function perform the reset sequence to the given usbps interface by configuring the appropriate control bits in the usbps specific registers. More...
void | XUsbPs_IntrHandler (void *HandlerRef)
| This function is the first-level interrupt handler for the USB core. More...
int | XUsbPs_IntrSetHandler (XUsbPs *InstancePtr, XUsbPs_IntrHandlerFunc CallBackFunc, void *CallBackRef, u32 Mask)
| This function registers the user callback handler for controller (non-endpoint) interrupts. More...
XUsbPs_Config * | XUsbPs_LookupConfig (u16 DeviceID)
| Looks up the controller configuration based on the unique controller ID. More...

## Variables
XUsbPs_Config | XUsbPs_ConfigTable []
| Each XUsbPs device in the system has an entry in this table. More...
XUsbPs_Config | XUsbPs_ConfigTable []
| Each XUsbPs device in the system has an entry in this table. More...

## System hang prevention Timeout counter value.
This value is used throughout the code to initialize a Timeout counter that is used when hard polling a register. The ides is to initialize the Timeout counter to a value that is longer than any expected Timeout but short enough so the system will continue to work and report an error while the user is still paying attention. A reasonable Timeout time would be about 10 seconds. The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would run about 10 seconds before a Timeout is detected. For example:
        int Timeout = XUSBPS_TIMEOUT_COUNTER;
     while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
                        XUSBPS_CMD_OFFSET) &
                        XUSBPS_CMD_RST_MASK) && --Timeout) {
        ;
     }
     if (0 == Timeout) {
        return XST_FAILURE;
#define | XUSBPS_TIMEOUT_COUNTER 1000000

## Endpoint Direction (bitmask)
Definitions to be used with Endpoint related function that require a 'Direction' parameter. NOTE: The direction is always defined from the perspective of the HOST! This means that an IN endpoint on the controller is used for sending data while the OUT endpoint on the controller is used for receiving data.
#define | XUSBPS_EP_DIRECTION_IN 0x01
| Endpoint direction IN. More...
#define | XUSBPS_EP_DIRECTION_OUT 0x02
| Endpoint direction OUT. More...

## Endpoint Type
Definitions to be used with Endpoint related functions that require a 'Type' parameter.
#define | XUSBPS_EP_TYPE_NONE 0
| Endpoint is not used. More...
#define | XUSBPS_EP_TYPE_CONTROL 1
| Endpoint for Control Transfers. More...
#define | XUSBPS_EP_TYPE_ISOCHRONOUS 2
| Endpoint for isochronous data. More...
#define | XUSBPS_EP_TYPE_BULK 3
| Endpoint for BULK Transfers. More...
#define | XUSBPS_EP_TYPE_INTERRUPT 4
| Endpoint for interrupt Transfers. More...
#define | ENDPOINT_MAXP_LENGTH 0x400
| Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6. More...

## Field names for status retrieval
Definitions for the XUsbPs_GetStatus() function call 'StatusType' parameter.
#define | XUSBPS_EP_STS_ADDRESS 1
| Address of controller. More...
#define | XUSBPS_EP_STS_CONTROLLER_STATE 2
| Current controller state. More...

## USB Default alternate setting
#define | XUSBPS_DEFAULT_ALT_SETTING 0
| The default alternate setting is 0. More...

## Endpoint event types
Definitions that are used to identify events that occur on endpoints. Passed to the endpoint event handler functions registered with XUsbPs_EpSetHandler().
#define | XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01
| Setup data has been received on the endpoint. More...
#define | XUSBPS_EP_EVENT_DATA_RX 0x02
| Data frame has been received on the endpoint. More...
#define | XUSBPS_EP_EVENT_DATA_TX 0x03
| Data frame has been sent on the endpoint. More...

## dTD Next Link Pointer (dTDNLP) bit positions.
#define | XUSBPS_dTDNLP_T_MASK 0x00000001
| USB dTD Next Link Pointer Terminate Bit. More...
#define | XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0
| USB dTD Next Link Pointer Address [31:5]. More...

## dTD Token (dTDTOKEN) bit positions.
#define | XUSBPS_dTDTOKEN_XERR_MASK 0x00000008
| dTD Transaction Error More...
#define | XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020
| dTD Data Buffer Error More...
#define | XUSBPS_dTDTOKEN_HALT_MASK 0x00000040
| dTD Halted Flag More...
#define | XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080
| dTD Active Bit More...
#define | XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00
| Multiplier Override Field [1:0]. More...
#define | XUSBPS_dTDTOKEN_IOC_MASK 0x00008000
| Interrupt on Complete Bit. More...
#define | XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000
| Transfer Length Field. More...

## dQH Configuration (dQHCFG) bit positions.
#define | XUSBPS_dQHCFG_IOS_MASK 0x00008000
| USB dQH Interrupt on Setup Bit. More...
#define | XUSBPS_dQHCFG_MPL_MASK 0x07FF0000
| USB dQH Maximum Packet Length Field [10:0]. More...
#define | XUSBPS_dQHCFG_MPL_SHIFT 16
#define | XUSBPS_dQHCFG_ZLT_MASK 0x20000000
| USB dQH Zero Length Termination Select Bit. More...
#define | XUSBPS_dQHCFG_MULT_MASK 0xC0000000
#define | XUSBPS_dQHCFG_MULT_SHIFT 30

## Timer 0 Register offsets
#define | XUSBPS_TIMER0_LD_OFFSET 0x00000080
#define | XUSBPS_TIMER0_CTL_OFFSET 0x00000084

## Timer Control Register bit mask
#define | XUSBPS_TIMER_RUN_MASK 0x80000000
#define | XUSBPS_TIMER_STOP_MASK 0x80000000
#define | XUSBPS_TIMER_RESET_MASK 0x40000000
#define | XUSBPS_TIMER_REPEAT_MASK 0x01000000
#define | XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF

## Device Hardware Parameters
#define | XUSBPS_HWDEVICE_OFFSET 0x0000000C
#define | XUSBPS_EP_NUM_MASK 0x3E
#define | XUSBPS_EP_NUM_SHIFT 1

## Capability Register offsets
#define | XUSBPS_HCSPARAMS_OFFSET 0x00000104

## Operational Register offsets.
Register comments are tagged with "H:" and "D:" for Host and Device modes, respectively. Tags are only present for registers that have a different meaning DEVICE and HOST modes. Most registers are only valid for either DEVICE or HOST mode. Those registers don't have tags.
#define | XUSBPS_CMD_OFFSET 0x00000140
| Configuration. More...
#define | XUSBPS_ISR_OFFSET 0x00000144
| Interrupt Status. More...
#define | XUSBPS_IER_OFFSET 0x00000148
| Interrupt Enable. More...
#define | XUSBPS_FRAME_OFFSET 0x0000014C
| USB Frame Index. More...
#define | XUSBPS_LISTBASE_OFFSET 0x00000154
| H: Periodic List Base Address. More...
#define | XUSBPS_DEVICEADDR_OFFSET 0x00000154
| D: Device Address. More...
#define | XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158
| H: Async List Address. More...
#define | XUSBPS_EPLISTADDR_OFFSET 0x00000158
| D: Endpoint List Addr. More...
#define | XUSBPS_TTCTRL_OFFSET 0x0000015C
| TT Control. More...
#define | XUSBPS_BURSTSIZE_OFFSET 0x00000160
| Burst Size. More...
#define | XUSBPS_TXFILL_OFFSET 0x00000164
| Tx Fill Tuning. More...
#define | XUSBPS_ULPIVIEW_OFFSET 0x00000170
| ULPI Viewport. More...
#define | XUSBPS_EPNAKISR_OFFSET 0x00000178
| Endpoint NAK IRQ Status. More...
#define | XUSBPS_EPNAKIER_OFFSET 0x0000017C
| Endpoint NAK IRQ Enable. More...
#define | XUSBPS_PORTSCR1_OFFSET 0x00000184
| Port Control/Status 1. More...
#define | XUSBPS_PORTSCRn_OFFSET(n) (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
#define | XUSBPS_OTGCSR_OFFSET 0x000001A4
| OTG Status and Control. More...
#define | XUSBPS_MODE_OFFSET 0x000001A8
| USB Mode. More...
#define | XUSBPS_EPSTAT_OFFSET 0x000001AC
| Endpoint Setup Status. More...
#define | XUSBPS_EPPRIME_OFFSET 0x000001B0
| Endpoint Prime. More...
#define | XUSBPS_EPFLUSH_OFFSET 0x000001B4
| Endpoint Flush. More...
#define | XUSBPS_EPRDY_OFFSET 0x000001B8
| Endpoint Ready. More...
#define | XUSBPS_EPCOMPL_OFFSET 0x000001BC
| Endpoint Complete. More...
#define | XUSBPS_EPCR0_OFFSET 0x000001C0
| Endpoint Control 0. More...
#define | XUSBPS_EPCR1_OFFSET 0x000001C4
| Endpoint Control 1. More...
#define | XUSBPS_EPCR2_OFFSET 0x000001C8
| Endpoint Control 2. More...
#define | XUSBPS_EPCR3_OFFSET 0x000001CC
| Endpoint Control 3. More...
#define | XUSBPS_EPCR4_OFFSET 0x000001D0
| Endpoint Control 4. More...
#define | XUSBPS_MAX_ENDPOINTS 12
| Number of supported Endpoints in this core. More...
#define | XUSBPS_EP_OUT_MASK 0x00000FFF
| OUR (RX) endpoint mask. More...
#define | XUSBPS_EP_IN_MASK 0x0FFF0000
| IN (TX) endpoint mask. More...
#define | XUSBPS_EP_ALL_MASK 0x0FFF0FFF
| Mask used for endpoint control registers. More...
#define | XUSBPS_EPCRn_OFFSET(n) (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
#define | XUSBPS_EPFLUSH_RX_SHIFT 0
#define | XUSBPS_EPFLUSH_TX_SHIFT 16

## Endpoint Control Register (EPCR) bit positions.
#define | XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000
| Control Endpoint - TX. More...
#define | XUSBPS_EPCR_TXT_ISO_MASK 0x00040000
| Isochronous. More...
#define | XUSBPS_EPCR_TXT_BULK_MASK 0x00080000
| Bulk Endpoint - TX. More...
#define | XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000
| Interrupt Endpoint. More...
#define | XUSBPS_EPCR_TXS_MASK 0x00010000
| Stall TX endpoint. More...
#define | XUSBPS_EPCR_TXE_MASK 0x00800000
| Transmit enable - TX. More...
#define | XUSBPS_EPCR_TXR_MASK 0x00400000
| Data Toggle Reset Bit. More...
#define | XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000
| Control Endpoint - RX. More...
#define | XUSBPS_EPCR_RXT_ISO_MASK 0x00000004
| Isochronous Endpoint. More...
#define | XUSBPS_EPCR_RXT_BULK_MASK 0x00000008
| Bulk Endpoint - RX. More...
#define | XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C
| Interrupt Endpoint. More...
#define | XUSBPS_EPCR_RXS_MASK 0x00000001
| Stall RX endpoint. More...
#define | XUSBPS_EPCR_RXE_MASK 0x00000080
| Transmit enable. More...
#define | XUSBPS_EPCR_RXR_MASK 0x00000040
| Data Toggle Reset Bit. More...

## USB Command Register (CR) bit positions.
#define | XUSBPS_CMD_RS_MASK 0x00000001
| Run/Stop. More...
#define | XUSBPS_CMD_RST_MASK 0x00000002
| Controller RESET. More...
#define | XUSBPS_CMD_FS01_MASK 0x0000000C
| Frame List Size bit 0,1. More...
#define | XUSBPS_CMD_PSE_MASK 0x00000010
| Periodic Sched Enable. More...
#define | XUSBPS_CMD_ASE_MASK 0x00000020
| Async Sched Enable. More...
#define | XUSBPS_CMD_IAA_MASK 0x00000040
| IRQ Async Advance Doorbell. More...
#define | XUSBPS_CMD_ASP_MASK 0x00000300
| Async Sched Park Mode Cnt. More...
#define | XUSBPS_CMD_ASPE_MASK 0x00000800
| Async Sched Park Mode Enbl. More...
#define | XUSBPS_CMD_SUTW_MASK 0x00002000
| Setup TripWire. More...
#define | XUSBPS_CMD_ATDTW_MASK 0x00004000
| Add dTD TripWire. More...
#define | XUSBPS_CMD_FS2_MASK 0x00008000
| Frame List Size bit 2. More...
#define | XUSBPS_CMD_ITC_MASK 0x00FF0000
| IRQ Threshold Control. More...

## Interrupt Threshold
These definitions are used by software to set the maximum rate at which the USB controller will generate interrupt requests. The interrupt interval is given in number of micro-frames. USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF) packet each and every 1ms. USB also defines a high-speed micro-frame with a 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is generated. Data is sent in between the SOF packets. The interrupt threshold defines how many micro-frames the controller waits before issuing an interrupt after data has been received. For a threshold of 0 the controller will issue an interrupt immediately after the last byte of the data has been received. For a threshold n>0 the controller will wait for n micro-frames before issuing an interrupt. Therefore, a setting of 8 micro-frames (default) means that the controller will issue at most 1 interrupt per millisecond.
#define | XUSBPS_CMD_ITHRESHOLD_0 0x00
| Immediate interrupt. More...
#define | XUSBPS_CMD_ITHRESHOLD_1 0x01
| 1 micro-frame More...
#define | XUSBPS_CMD_ITHRESHOLD_2 0x02
| 2 micro-frames More...
#define | XUSBPS_CMD_ITHRESHOLD_4 0x04
| 4 micro-frames More...
#define | XUSBPS_CMD_ITHRESHOLD_8 0x08
| 8 micro-frames More...
#define | XUSBPS_CMD_ITHRESHOLD_16 0x10
| 16 micro-frames More...
#define | XUSBPS_CMD_ITHRESHOLD_32 0x20
| 32 micro-frames More...
#define | XUSBPS_CMD_ITHRESHOLD_64 0x40
| 64 micro-frames More...
#define | XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64
#define | XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8

## USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
bit positions.
#define | XUSBPS_IXR_UI_MASK 0x00000001
| USB Transaction Complete. More...
#define | XUSBPS_IXR_UE_MASK 0x00000002
| Transaction Error. More...
#define | XUSBPS_IXR_PC_MASK 0x00000004
| Port Change Detect. More...
#define | XUSBPS_IXR_FRE_MASK 0x00000008
| Frame List Rollover. More...
#define | XUSBPS_IXR_AA_MASK 0x00000020
| Async Advance. More...
#define | XUSBPS_IXR_UR_MASK 0x00000040
| RESET Received. More...
#define | XUSBPS_IXR_SR_MASK 0x00000080
| Start of Frame. More...
#define | XUSBPS_IXR_SLE_MASK 0x00000100
| Device Controller Suspend. More...
#define | XUSBPS_IXR_ULPI_MASK 0x00000400
| ULPI IRQ. More...
#define | XUSBPS_IXR_HCH_MASK 0x00001000
| Host Controller Halted Read Only. More...
#define | XUSBPS_IXR_RCL_MASK 0x00002000
| USB Reclamation Read Only. More...
#define | XUSBPS_IXR_PS_MASK 0x00004000
| Periodic Sched Status Read Only. More...
#define | XUSBPS_IXR_AS_MASK 0x00008000
| Async Sched Status Read only. More...
#define | XUSBPS_IXR_NAK_MASK 0x00010000
| NAK IRQ. More...
#define | XUSBPS_IXR_UA_MASK 0x00040000
| USB Host Async IRQ. More...
#define | XUSBPS_IXR_UP_MASK 0x00080000
| USB Host Periodic IRQ. More...
#define | XUSBPS_IXR_TI0_MASK 0x01000000
| Timer 0 Interrupt. More...
#define | XUSBPS_IXR_TI1_MASK 0x02000000
| Timer 1 Interrupt. More...
#define | XUSBPS_IXR_ALL
| Mask for ALL IRQ types. More...

## USB Mode Register (MODE) bit positions.
#define | XUSBPS_MODE_CM_MASK 0x00000003
| Controller Mode Select. More...
#define | XUSBPS_MODE_CM_IDLE_MASK 0x00000000
#define | XUSBPS_MODE_CM_DEVICE_MASK 0x00000002
#define | XUSBPS_MODE_CM_HOST_MASK 0x00000003
#define | XUSBPS_MODE_ES_MASK 0x00000004
| USB Endian Select. More...
#define | XUSBPS_MODE_SLOM_MASK 0x00000008
| USB Setup Lockout Mode Disable. More...
#define | XUSBPS_MODE_SDIS_MASK 0x00000010
#define | XUSBPS_MODE_VALID_MASK 0x0000001F

## USB Device Address Register (DEVICEADDR) bit positions.
#define | XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
| Device Addr Auto Advance. More...
#define | XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
| Device Address. More...
#define | XUSBPS_DEVICEADDR_ADDR_SHIFT 25
| Address shift. More...
#define | XUSBPS_DEVICEADDR_MAX 127
| Biggest allowed address. More...

## USB TT Control Register (TTCTRL) bit positions.
#define | XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000
| TT Hub Address. More...

## USB Burst Size Register (BURSTSIZE) bit posisions.
#define | XUSBPS_BURSTSIZE_RX_MASK 0x000000FF
| RX Burst Length. More...
#define | XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00
| TX Burst Length. More...

## USB Tx Fill Tuning Register (TXFILL) bit positions.
#define | XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
| Scheduler Overhead. More...
#define | XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
| Scheduler Health Cntr. More...
#define | XUSBPS_TXFILL_BURST_MASK 0x003F0000
| FIFO Burst Threshold. More...

## USB ULPI Viewport Register (ULPIVIEW) bit positions.
#define | XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF
| ULPI Data Write. More...
#define | XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00
| ULPI Data Read. More...
#define | XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000
| ULPI Data Address. More...
#define | XUSBPS_ULPIVIEW_PORT_MASK 0x07000000
| ULPI Port Number. More...
#define | XUSBPS_ULPIVIEW_SS_MASK 0x08000000
| ULPI Synchronous State. More...
#define | XUSBPS_ULPIVIEW_RW_MASK 0x20000000
| ULPI Read/Write Control. More...
#define | XUSBPS_ULPIVIEW_RUN_MASK 0x40000000
| ULPI Run. More...
#define | XUSBPS_ULPIVIEW_WU_MASK 0x80000000
| ULPI Wakeup. More...

## Port Status Control Register bit positions.
#define | XUSBPS_PORTSCR_CCS_MASK 0x00000001
| Current Connect Status. More...
#define | XUSBPS_PORTSCR_CSC_MASK 0x00000002
| Connect Status Change. More...
#define | XUSBPS_PORTSCR_PE_MASK 0x00000004
| Port Enable/Disable. More...
#define | XUSBPS_PORTSCR_PEC_MASK 0x00000008
| Port Enable/Disable Change. More...
#define | XUSBPS_PORTSCR_OCA_MASK 0x00000010
| Over-current Active. More...
#define | XUSBPS_PORTSCR_OCC_MASK 0x00000020
| Over-current Change. More...
#define | XUSBPS_PORTSCR_FPR_MASK 0x00000040
| Force Port Resume. More...
#define | XUSBPS_PORTSCR_SUSP_MASK 0x00000080
| Suspend. More...
#define | XUSBPS_PORTSCR_PR_MASK 0x00000100
| Port Reset. More...
#define | XUSBPS_PORTSCR_HSP_MASK 0x00000200
| High Speed Port. More...
#define | XUSBPS_PORTSCR_LS_MASK 0x00000C00
| Line Status. More...
#define | XUSBPS_PORTSCR_PP_MASK 0x00001000
| Port Power. More...
#define | XUSBPS_PORTSCR_PO_MASK 0x00002000
| Port Owner. More...
#define | XUSBPS_PORTSCR_PIC_MASK 0x0000C000
| Port Indicator Control. More...
#define | XUSBPS_PORTSCR_PTC_MASK 0x000F0000
| Port Test Control. More...
#define | XUSBPS_PORTSCR_WKCN_MASK 0x00100000
| Wake on Connect Enable. More...
#define | XUSBPS_PORTSCR_WKDS_MASK 0x00200000
| Wake on Disconnect Enable. More...
#define | XUSBPS_PORTSCR_WKOC_MASK 0x00400000
| Wake on Over-current Enable. More...
#define | XUSBPS_PORTSCR_PHCD_MASK 0x00800000
| PHY Low Power Suspend - Clock Disable. More...
#define | XUSBPS_PORTSCR_PFSC_MASK 0x01000000
| Port Force Full Speed Connect. More...
#define | XUSBPS_PORTSCR_PSPD_MASK 0x0C000000
| Port Speed. More...

## On-The-Go Status Control Register (OTGCSR) bit positions.
#define | XUSBPS_OTGSC_VD_MASK 0x00000001
| VBus Discharge Bit. More...
#define | XUSBPS_OTGSC_VC_MASK 0x00000002
| VBus Charge Bit. More...
#define | XUSBPS_OTGSC_HAAR_MASK 0x00000004
| HW Assist Auto Reset Enable Bit. More...
#define | XUSBPS_OTGSC_OT_MASK 0x00000008
| OTG Termination Bit. More...
#define | XUSBPS_OTGSC_DP_MASK 0x00000010
| Data Pulsing Pull-up Enable Bit. More...
#define | XUSBPS_OTGSC_IDPU_MASK 0x00000020
| ID Pull-up Enable Bit. More...
#define | XUSBPS_OTGSC_HADP_MASK 0x00000040
| HW Assist Data Pulse Enable Bit. More...
#define | XUSBPS_OTGSC_HABA_MASK 0x00000080
| USB Hardware Assist B Disconnect to A Connect Enable Bit. More...
#define | XUSBPS_OTGSC_ID_MASK 0x00000100
| ID Status Flag. More...
#define | XUSBPS_OTGSC_AVV_MASK 0x00000200
| USB A VBus Valid Interrupt Status Flag. More...
#define | XUSBPS_OTGSC_ASV_MASK 0x00000400
| USB A Session Valid Interrupt Status Flag. More...
#define | XUSBPS_OTGSC_BSV_MASK 0x00000800
| USB B Session Valid Status Flag. More...
#define | XUSBPS_OTGSC_BSE_MASK 0x00001000
| USB B Session End Status Flag. More...
#define | XUSBPS_OTGSC_1MST_MASK 0x00002000
| USB 1 Millisecond Timer Status Flag. More...
#define | XUSBPS_OTGSC_DPS_MASK 0x00004000
| Data Pulse Status Flag. More...
#define | XUSBPS_OTGSC_IDIS_MASK 0x00010000
| USB ID Interrupt Status Flag. More...
#define | XUSBPS_OTGSC_AVVIS_MASK 0x00020000
| USB A VBus Valid Interrupt Status Flag. More...
#define | XUSBPS_OTGSC_ASVIS_MASK 0x00040000
| USB A Session Valid Interrupt Status Flag. More...
#define | XUSBPS_OTGSC_BSVIS_MASK 0x00080000
| USB B Session Valid Interrupt Status Flag. More...
#define | XUSBPS_OTGSC_BSEIS_MASK 0x00100000
| USB B Session End Interrupt Status Flag. More...
#define | XUSBPS_OTGSC_1MSS_MASK 0x00200000
| 1 Millisecond Timer Interrupt Status Flag More...
#define | XUSBPS_OTGSC_DPIS_MASK 0x00400000
| Data Pulse Interrupt Status Flag. More...
#define | XUSBPS_OTGSC_IDIE_MASK 0x01000000
| ID Interrupt Enable Bit. More...
#define | XUSBPS_OTGSC_AVVIE_MASK 0x02000000
| USB A VBus Valid Interrupt Enable Bit. More...
#define | XUSBPS_OTGSC_ASVIE_MASK 0x04000000
| USB A Session Valid Interrupt Enable Bit. More...
#define | XUSBPS_OTGSC_BSVIE_MASK 0x08000000
| USB B Session Valid Interrupt Enable Bit. More...
#define | XUSBPS_OTGSC_BSEE_MASK 0x10000000
| USB B Session End Interrupt Enable Bit. More...
#define | XUSBPS_OTGSC_1MSE_MASK 0x20000000
| 1 Millisecond Timer Interrupt Enable Bit More...
#define | XUSBPS_OTGSC_DPIE_MASK 0x40000000
| Data Pulse Interrupt Enable Bit. More...
#define | XUSBPS_OTG_ISB_ALL
#define | XUSBPS_OTG_IEB_ALL
| Mask for All IRQ status masks. More...

## Macro Definition Documentation

#define ENDPOINT_MAXP_LENGTH 0x400

Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.

#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158

H: Async List Address.

Referenced by XUsbPs_ResetHw().

#define XUSBPS_BURSTSIZE_OFFSET 0x00000160

Burst Size.

#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF

RX Burst Length.

#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00

TX Burst Length.

#define XUSBPS_CMD_ASE_MASK 0x00000020

Async Sched Enable.

#define XUSBPS_CMD_ASP_MASK 0x00000300

Async Sched Park Mode Cnt.

#define XUSBPS_CMD_ASPE_MASK 0x00000800

Async Sched Park Mode Enbl.

#define XUSBPS_CMD_ATDTW_MASK 0x00004000

Add dTD TripWire.

#define XUSBPS_CMD_FS01_MASK 0x0000000C

Frame List Size bit 0,1.

#define XUSBPS_CMD_FS2_MASK 0x00008000

Frame List Size bit 2.

#define XUSBPS_CMD_IAA_MASK 0x00000040

IRQ Async Advance Doorbell.

#define XUSBPS_CMD_ITC_MASK 0x00FF0000

IRQ Threshold Control.

#define XUSBPS_CMD_ITHRESHOLD_0 0x00

Immediate interrupt.

#define XUSBPS_CMD_ITHRESHOLD_1 0x01

1 micro-frame

#define XUSBPS_CMD_ITHRESHOLD_16 0x10

16 micro-frames

#define XUSBPS_CMD_ITHRESHOLD_2 0x02

2 micro-frames

#define XUSBPS_CMD_ITHRESHOLD_32 0x20

32 micro-frames

#define XUSBPS_CMD_ITHRESHOLD_4 0x04

4 micro-frames

#define XUSBPS_CMD_ITHRESHOLD_64 0x40

64 micro-frames

#define XUSBPS_CMD_ITHRESHOLD_8 0x08

8 micro-frames

#define XUSBPS_CMD_OFFSET 0x00000140

Configuration.

Referenced by XUsbPs_DeviceReset(), XUsbPs_Reset(), and XUsbPs_ResetHw().

#define XUSBPS_CMD_PSE_MASK 0x00000010

Periodic Sched Enable.

#define XUSBPS_CMD_RS_MASK 0x00000001

Run/Stop.

#define XUSBPS_CMD_RST_MASK 0x00000002

Controller RESET.

Referenced by XUsbPs_DeviceReset(), XUsbPs_Reset(), and XUsbPs_ResetHw().

#define XUSBPS_CMD_SUTW_MASK 0x00002000

Setup TripWire.

#define XUSBPS_DEFAULT_ALT_SETTING 0

The default alternate setting is 0.

Referenced by XUsbPs_CfgInitialize().

#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000

Device Address.

#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25

Address shift.

Referenced by XUsbPs_SetDeviceAddress().

#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000

Device Addr Auto Advance.

Referenced by XUsbPs_SetDeviceAddress().

#define XUSBPS_DEVICEADDR_MAX 127

Biggest allowed address.

Referenced by XUsbPs_SetDeviceAddress().

#define XUSBPS_DEVICEADDR_OFFSET 0x00000154

D: Device Address.

Referenced by XUsbPs_SetDeviceAddress().

#define XUSBPS_dQH_ALIGN 64

Alignment of a Device Transfer Descriptor structure.

#define XUSBPS_dQH_BASE_ALIGN 2048

Mask for All IRQ Enable masks.

< Alignment of the Device Queue Head List BASE. Alignment of a Device Queue Head structure.

Referenced by XUsbPs_ConfigureDevice().

#define XUSBPS_dQHCFG 0x00

Endpoint Device Queue Head.

Device queue heads are arranged in an array in a continuous area of memory pointed to by the ENDPOINTLISTADDR pointer. The device controller will index into this array based upon the endpoint number received from the USB bus. All information necessary to respond to transactions for all primed transfers is contained in this list so the Device Controller can readily respond to incoming requests without having to traverse a linked list.

The device Endpoint Queue Head (dQH) is where all transfers are managed. The dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary. During priming of an endpoint, the dTD (device transfer descriptor) is copied into the overlay area of the dQH, which starts at the nextTD pointer DWord and continues through the end of the buffer pointers DWords. After a transfer is complete, the dTD status DWord is updated in the dTD pointed to by the currentTD pointer. While a packet is in progress, the overlay area of the dQH is used as a staging area for the dTD so that the Device Controller can access needed information with little minimal latency.

Note
  Software must ensure that no interface data structure reachable by the Device Controller spans a 4K-page boundary. The first element of the Endpoint Queue Head List must be aligned on a 4K boundary.dQH Configuration

#define XUSBPS_dQHCFG_IOS_MASK 0x00008000

USB dQH Interrupt on Setup Bit.

#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000

USB dQH Maximum Packet Length Field [10:0].

#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000

USB dQH Zero Length Termination Select Bit.

#define XUsbPs_dQHClrIOS | ( |  | dQHPtr | ) |

Value:
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
~XUSBPS_dQHCFG_IOS_MASK)
XUSBPS_dQHCFG
#define XUSBPS_dQHCFG
Endpoint Device Queue Head.
Definition: xusbps_endpoint.h:360
XUsbPs_ReaddQH
#define XUsbPs_ReaddQH(dQHPtr, Id)
This macro reads the content of a field in a Queue Head.
Definition: xusbps_endpoint.h:485
XUSBPS_dQHCFG_IOS_MASK
#define XUSBPS_dQHCFG_IOS_MASK
USB dQH Interrupt on Setup Bit.
Definition: xusbps_endpoint.h:373
XUsbPs_WritedQH
#define XUsbPs_WritedQH(dQHPtr, Id, Val)
This macro writes a value to a field in a Queue Head.
Definition: xusbps_endpoint.h:500

This macro clears the Interrupt On Setup (IOS) bit for an endpoint.

Parameters

  dQHPtr | is a pointer to the dQH element.

Note
  C-style signature: void XUsbPs_dQHClrIOS(u32 dQHPtr)

#define XUSBPS_dQHCPTR 0x04

dQH Current dTD Pointer

#define XUsbPs_dQHDisableZLT | ( |  | dQHPtr | ) |

Value:
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
XUSBPS_dQHCFG_ZLT_MASK)
XUSBPS_dQHCFG
#define XUSBPS_dQHCFG
Endpoint Device Queue Head.
Definition: xusbps_endpoint.h:360
XUsbPs_ReaddQH
#define XUsbPs_ReaddQH(dQHPtr, Id)
This macro reads the content of a field in a Queue Head.
Definition: xusbps_endpoint.h:485
XUSBPS_dQHCFG_ZLT_MASK
#define XUSBPS_dQHCFG_ZLT_MASK
USB dQH Zero Length Termination Select Bit.
Definition: xusbps_endpoint.h:379
XUsbPs_WritedQH
#define XUsbPs_WritedQH(dQHPtr, Id, Val)
This macro writes a value to a field in a Queue Head.
Definition: xusbps_endpoint.h:500

This macro disables Zero Length Termination for the endpoint.

Parameters

  dQHPtr | is a pointer to the dQH element.

Note
  C-style signature: void XUsbPs_dQHDisableZLT(u32 dQHPtr)

#define XUSBPS_dQHdTDNLP 0x08

dTD Next Link Ptr in dQH overlay

#define XUSBPS_dQHdTDTOKEN 0x0C

dTD Token in dQH overlay

#define XUsbPs_dQHEnableZLT | ( |  | dQHPtr | ) |

Value:
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
~XUSBPS_dQHCFG_ZLT_MASK)
XUSBPS_dQHCFG
#define XUSBPS_dQHCFG
Endpoint Device Queue Head.
Definition: xusbps_endpoint.h:360
XUsbPs_ReaddQH
#define XUsbPs_ReaddQH(dQHPtr, Id)
This macro reads the content of a field in a Queue Head.
Definition: xusbps_endpoint.h:485
XUSBPS_dQHCFG_ZLT_MASK
#define XUSBPS_dQHCFG_ZLT_MASK
USB dQH Zero Length Termination Select Bit.
Definition: xusbps_endpoint.h:379
XUsbPs_WritedQH
#define XUsbPs_WritedQH(dQHPtr, Id, Val)
This macro writes a value to a field in a Queue Head.
Definition: xusbps_endpoint.h:500

This macro enables Zero Length Termination for the endpoint.

Parameters

  dQHPtr | is a pointer to the dQH element.

Note
  C-style signature: void XUsbPs_dQHEnableZLT(u32 dQHPtr)

#define XUsbPs_dQHSetIOS | ( |  | dQHPtr | ) |

Value:
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
XUSBPS_dQHCFG_IOS_MASK)
XUSBPS_dQHCFG
#define XUSBPS_dQHCFG
Endpoint Device Queue Head.
Definition: xusbps_endpoint.h:360
XUsbPs_ReaddQH
#define XUsbPs_ReaddQH(dQHPtr, Id)
This macro reads the content of a field in a Queue Head.
Definition: xusbps_endpoint.h:485
XUSBPS_dQHCFG_IOS_MASK
#define XUSBPS_dQHCFG_IOS_MASK
USB dQH Interrupt on Setup Bit.
Definition: xusbps_endpoint.h:373
XUsbPs_WritedQH
#define XUsbPs_WritedQH(dQHPtr, Id, Val)
This macro writes a value to a field in a Queue Head.
Definition: xusbps_endpoint.h:500

This macro sets the Interrupt On Setup (IOS) bit for an endpoint.

Parameters

  dQHPtr | is a pointer to the dQH element.

Note
  C-style signature: void XUsbPs_dQHSetIOS(u32 dQHPtr)

#define XUsbPs_dQHSetMaxPacketLen | ( |  | dQHPtr,
|  |  | Len
| ) |  |

Value:
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
(XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
XUSBPS_dQHCFG
#define XUSBPS_dQHCFG
Endpoint Device Queue Head.
Definition: xusbps_endpoint.h:360
XUSBPS_dQHCFG_MPL_MASK
#define XUSBPS_dQHCFG_MPL_MASK
USB dQH Maximum Packet Length Field [10:0].
Definition: xusbps_endpoint.h:375
XUsbPs_ReaddQH
#define XUsbPs_ReaddQH(dQHPtr, Id)
This macro reads the content of a field in a Queue Head.
Definition: xusbps_endpoint.h:485
XUsbPs_WritedQH
#define XUsbPs_WritedQH(dQHPtr, Id, Val)
This macro writes a value to a field in a Queue Head.
Definition: xusbps_endpoint.h:500

This macro sets the Maximum Packet Length field of the give Queue Head.

Parameters

  dQHPtr | is a pointer to the dQH element.
  Len | is the length to be set.

Note
  C-style signature: void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)

#define XUSBPS_dQHSUB0 0x28

USB dQH Setup Buffer 0.

Referenced by XUsbPs_EpGetSetupData().

#define XUSBPS_dQHSUB1 0x2C

USB dQH Setup Buffer 1.

Referenced by XUsbPs_EpGetSetupData().

#define XUSBPS_dTD_ALIGN 32

Size of one RX buffer for a OUT Transfer Descriptor.

Referenced by XUsbPs_EpBufferRelease(), and XUsbPs_ReconfigureEp().

#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024

Alignment requirement for Transfer Descriptor buffers.

#define XUSBPS_dTD_BUF_SIZE 4096

Maximum size of one RX/TX buffer.

#define XUSBPS_dTDBPTR0 0x08

Buffer Pointer 0.

Referenced by XUsbPs_EpBufferReceive().

#define XUSBPS_dTDBPTR1 0x0C

Buffer Pointer 1.

#define XUSBPS_dTDBPTR2 0x10

Buffer Pointer 2.

#define XUSBPS_dTDBPTR3 0x14

Buffer Pointer 3.

#define XUSBPS_dTDBPTR4 0x18

Buffer Pointer 4.

#define XUsbPs_dTDClrTerminate | ( |  | dTDPtr | ) |

Value:
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
~XUSBPS_dTDNLP_T_MASK)
XUsbPs_WritedTD
#define XUsbPs_WritedTD(dTDPtr, Id, Val)
This macro writes a value to a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:330
XUsbPs_ReaddTD
#define XUsbPs_ReaddTD(dTDPtr, Id)
This macro reads the content of a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:315
XUSBPS_dTDNLP
#define XUSBPS_dTDNLP
Endpoint Device Transfer Descriptor.
Definition: xusbps_endpoint.h:71
XUSBPS_dTDNLP_T_MASK
#define XUSBPS_dTDNLP_T_MASK
USB dTD Next Link Pointer Terminate Bit.
Definition: xusbps_endpoint.h:88

This macro clears the Terminate bit for the given Transfer Descriptor.

Parameters

  dTDPtr | is a pointer to the dTD element.

Note
  C-style signature: void XUsbPs_dTDClrTerminate(u32 dTDPtr)

Referenced by XUsbPs_EpBufferRelease().

#define XUsbPs_dTDGetNLP | ( |  | dTDPtr | ) |

Value:
(XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
& XUSBPS_dTDNLP_ADDR_MASK))
XUsbPs_ReaddTD
#define XUsbPs_ReaddTD(dTDPtr, Id)
This macro reads the content of a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:315
XUSBPS_dTDNLP
#define XUSBPS_dTDNLP
Endpoint Device Transfer Descriptor.
Definition: xusbps_endpoint.h:71
XUSBPS_dTDNLP_ADDR_MASK
#define XUSBPS_dTDNLP_ADDR_MASK
USB dTD Next Link Pointer Address [31:5].
Definition: xusbps_endpoint.h:90

This macro gets the Next Link pointer of the given Transfer Descriptor.

Parameters

  dTDPtr | is pointer to the dTD element.

Returns
  TransferLength field of the descriptor.

Note
  C-style signature: u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)

#define XUsbPs_dTDGetTransferLen | ( |  | dTDPtr | ) |

Value:
(u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
& XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
XUsbPs_ReaddTD
#define XUsbPs_ReaddTD(dTDPtr, Id)
This macro reads the content of a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:315
XUSBPS_dTDTOKEN_LEN_MASK
#define XUSBPS_dTDTOKEN_LEN_MASK
Transfer Length Field.
Definition: xusbps_endpoint.h:104
XUSBPS_dTDTOKEN
#define XUSBPS_dTDTOKEN
Descriptor Token.
Definition: xusbps_endpoint.h:72

This macro gets the Transfer Length for the given Transfer Descriptor.

Parameters

  dTDPtr | is a pointer to the dTD element.

Returns
  TransferLength field of the descriptor.

Note
  C-style signature: u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)

Referenced by XUsbPs_EpBufferReceive().

#define XUsbPs_dTDInvalidateCache | ( |  | dTDPtr | ) | Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))

# IMPORTANT NOTE:

Many of the following macros modify Device Queue Head (dQH) data structures and Device Transfer Descriptor (dTD) data structures. Those structures can potentially reside in CACHED memory. Therefore, it's the callers responsibility to ensure cache coherency by using provided

        XUsbPs_dQHInvalidateCache()
        XUsbPs_dQHFlushCache()
        XUsbPs_dTDInvalidateCache()
        XUsbPs_dTDFlushCache()

function calls.

Referenced by XUsbPs_EpBufferReceive(), and XUsbPs_EpBufferRelease().

#define XUsbPs_dTDIsActive | ( |  | dTDPtr | ) |

Value:
((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
XUsbPs_ReaddTD
#define XUsbPs_ReaddTD(dTDPtr, Id)
This macro reads the content of a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:315
XUSBPS_dTDTOKEN_ACTIVE_MASK
#define XUSBPS_dTDTOKEN_ACTIVE_MASK
dTD Active Bit
Definition: xusbps_endpoint.h:101
XUSBPS_dTDTOKEN
#define XUSBPS_dTDTOKEN
Descriptor Token.
Definition: xusbps_endpoint.h:72

This macro checks if the given descriptor is active.

Parameters

  dTDPtr | is a pointer to the dTD element.

Returns
  - TRUE: The buffer is active.
  - FALSE: The buffer is not active.

Note
  C-style signature: int XUsbPs_dTDIsActive(u32 dTDPtr)

Referenced by XUsbPs_EpBufferReceive().

#define XUSBPS_dTDNLP 0x00

Endpoint Device Transfer Descriptor.

The dTD describes to the device controller the location and quantity of data to be sent/received for given transfer. The driver does not attempt to modify any field in an active dTD except the Next Link Pointer.Pointer to the next descriptor

#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0

USB dTD Next Link Pointer Address [31:5].

#define XUSBPS_dTDNLP_T_MASK 0x00000001

USB dTD Next Link Pointer Terminate Bit.

#define XUSBPS_dTDRSRVD 0x1C

Reserved field.

#define XUsbPs_dTDSetActive | ( |  | dTDPtr | ) |

Value:
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
XUSBPS_dTDTOKEN_ACTIVE_MASK)
XUsbPs_WritedTD
#define XUsbPs_WritedTD(dTDPtr, Id, Val)
This macro writes a value to a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:330
XUsbPs_ReaddTD
#define XUsbPs_ReaddTD(dTDPtr, Id)
This macro reads the content of a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:315
XUSBPS_dTDTOKEN_ACTIVE_MASK
#define XUSBPS_dTDTOKEN_ACTIVE_MASK
dTD Active Bit
Definition: xusbps_endpoint.h:101
XUSBPS_dTDTOKEN
#define XUSBPS_dTDTOKEN
Descriptor Token.
Definition: xusbps_endpoint.h:72

This macro sets the Active bit for the given Transfer Descriptor.

Parameters

  dTDPtr | is a pointer to the dTD element.

Note
  C-style signature: void XUsbPs_dTDSetActive(u32 dTDPtr)

Referenced by XUsbPs_EpBufferRelease().

#define XUsbPs_dTDSetIOC | ( |  | dTDPtr | ) |

Value:
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
XUSBPS_dTDTOKEN_IOC_MASK)
XUsbPs_WritedTD
#define XUsbPs_WritedTD(dTDPtr, Id, Val)
This macro writes a value to a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:330
XUsbPs_ReaddTD
#define XUsbPs_ReaddTD(dTDPtr, Id)
This macro reads the content of a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:315
XUSBPS_dTDTOKEN_IOC_MASK
#define XUSBPS_dTDTOKEN_IOC_MASK
Interrupt on Complete Bit.
Definition: xusbps_endpoint.h:103
XUSBPS_dTDTOKEN
#define XUSBPS_dTDTOKEN
Descriptor Token.
Definition: xusbps_endpoint.h:72

This macro sets the Interrupt On Complete (IOC) bit for the given Transfer Descriptor.

Parameters

  dTDPtr | is a pointer to the dTD element.

Note
  C-style signature: void XUsbPs_dTDSetIOC(u32 dTDPtr)

Referenced by XUsbPs_EpBufferRelease().

#define XUsbPs_dTDSetNLP | ( |  | dTDPtr,
|  |  | NLP
| ) |  |

Value:
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
(XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
~XUSBPS_dTDNLP_ADDR_MASK) | \
((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
XUsbPs_WritedTD
#define XUsbPs_WritedTD(dTDPtr, Id, Val)
This macro writes a value to a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:330
XUsbPs_ReaddTD
#define XUsbPs_ReaddTD(dTDPtr, Id)
This macro reads the content of a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:315
XUSBPS_dTDNLP
#define XUSBPS_dTDNLP
Endpoint Device Transfer Descriptor.
Definition: xusbps_endpoint.h:71
XUSBPS_dTDNLP_ADDR_MASK
#define XUSBPS_dTDNLP_ADDR_MASK
USB dTD Next Link Pointer Address [31:5].
Definition: xusbps_endpoint.h:90

This macro sets the Next Link pointer of the given Transfer Descriptor.

Parameters

  dTDPtr | is a pointer to the dTD element.
  NLP | is the Next Link Pointer

Note
  C-style signature: void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)

#define XUsbPs_dTDSetTerminate | ( |  | dTDPtr | ) |

Value:
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \
XUSBPS_dTDNLP_T_MASK)
XUsbPs_WritedTD
#define XUsbPs_WritedTD(dTDPtr, Id, Val)
This macro writes a value to a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:330
XUsbPs_ReaddTD
#define XUsbPs_ReaddTD(dTDPtr, Id)
This macro reads the content of a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:315
XUSBPS_dTDNLP
#define XUSBPS_dTDNLP
Endpoint Device Transfer Descriptor.
Definition: xusbps_endpoint.h:71
XUSBPS_dTDNLP_T_MASK
#define XUSBPS_dTDNLP_T_MASK
USB dTD Next Link Pointer Terminate Bit.
Definition: xusbps_endpoint.h:88

This macro sets the Terminate bit for the given Transfer Descriptor.

Parameters

  dTDPtr | is a pointer to the dTD element.

Note
  C-style signature: void XUsbPs_dTDSetTerminate(u32 dTDPtr)

#define XUsbPs_dTDSetTransferLen | ( |  | dTDPtr,
|  |  | Len
| ) |  |

Value:
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
(XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
XUsbPs_WritedTD
#define XUsbPs_WritedTD(dTDPtr, Id, Val)
This macro writes a value to a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:330
XUsbPs_ReaddTD
#define XUsbPs_ReaddTD(dTDPtr, Id)
This macro reads the content of a field in a Transfer Descriptor.
Definition: xusbps_endpoint.h:315
XUSBPS_dTDTOKEN_LEN_MASK
#define XUSBPS_dTDTOKEN_LEN_MASK
Transfer Length Field.
Definition: xusbps_endpoint.h:104
XUSBPS_dTDTOKEN
#define XUSBPS_dTDTOKEN
Descriptor Token.
Definition: xusbps_endpoint.h:72

This macro sets the Transfer Length for the given Transfer Descriptor.

Parameters

  dTDPtr | is pointer to the dTD element.
  Len | is the length to be set. Range: 0..16384

Note
  C-style signature: void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)

Referenced by XUsbPs_EpBufferReceive().

#define XUSBPS_dTDTOKEN 0x04

Descriptor Token.

#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080

dTD Active Bit

#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020

dTD Data Buffer Error

#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040

dTD Halted Flag

#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000

Interrupt on Complete Bit.

#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000

Transfer Length Field.

#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00

Multiplier Override Field [1:0].

#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008

dTD Transaction Error

#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD

Reserved field.

Referenced by XUsbPs_EpBufferReceive().

#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF

Mask used for endpoint control registers.

Referenced by XUsbPs_DeviceReset().

#define XUSBPS_EP_DIRECTION_IN 0x01

Endpoint direction IN.

Referenced by XUsbPs_Ch9HandleSetupPacket(), XUsbPs_ClassReq(), XUsbPs_EpPrime(), XUsbPs_EpSetHandler(), XUsbPs_ReconfigureEp(), and XUsbPs_SetConfiguration().

#define XUSBPS_EP_DIRECTION_OUT 0x02

Endpoint direction OUT.

Referenced by XUsbPs_Ch9HandleSetupPacket(), XUsbPs_EpPrime(), XUsbPs_EpSetHandler(), XUsbPs_IntrHandler(), XUsbPs_ReconfigureEp(), and XUsbPs_SetConfiguration().

#define XUSBPS_EP_EVENT_DATA_RX 0x02

Data frame has been received on the endpoint.

#define XUSBPS_EP_EVENT_DATA_TX 0x03

Data frame has been sent on the endpoint.

#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01

Setup data has been received on the endpoint.

#define XUSBPS_EP_IN_MASK 0x0FFF0000

IN (TX) endpoint mask.

Referenced by XUsbPs_IntrHandler().

#define XUSBPS_EP_OUT_MASK 0x00000FFF

OUR (RX) endpoint mask.

Referenced by XUsbPs_IntrHandler().

#define XUSBPS_EP_STS_ADDRESS 1

Address of controller.

#define XUSBPS_EP_STS_CONTROLLER_STATE 2

Current controller state.

#define XUSBPS_EP_TYPE_BULK 3

Endpoint for BULK Transfers.

#define XUSBPS_EP_TYPE_CONTROL 1

Endpoint for Control Transfers.

#define XUSBPS_EP_TYPE_INTERRUPT 4

Endpoint for interrupt Transfers.

#define XUSBPS_EP_TYPE_ISOCHRONOUS 2

Endpoint for isochronous data.

#define XUSBPS_EP_TYPE_NONE 0

Endpoint is not used.

#define XUSBPS_EPCOMPL_OFFSET 0x000001BC

Endpoint Complete.

Referenced by XUsbPs_DeviceReset(), and XUsbPs_IntrHandler().

#define XUSBPS_EPCR0_OFFSET 0x000001C0

Endpoint Control 0.

#define XUSBPS_EPCR1_OFFSET 0x000001C4

Endpoint Control 1.

Referenced by XUsbPs_SetConfiguration().

#define XUSBPS_EPCR2_OFFSET 0x000001C8

Endpoint Control 2.

#define XUSBPS_EPCR3_OFFSET 0x000001CC

Endpoint Control 3.

#define XUSBPS_EPCR4_OFFSET 0x000001D0

Endpoint Control 4.

#define XUSBPS_EPCR_RXE_MASK 0x00000080

Transmit enable.

- RX

#define XUSBPS_EPCR_RXR_MASK 0x00000040

Data Toggle Reset Bit.

Referenced by XUsbPs_SetConfiguration().

#define XUSBPS_EPCR_RXS_MASK 0x00000001

Stall RX endpoint.

#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008

Bulk Endpoint - RX.

Referenced by XUsbPs_SetConfiguration().

#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000

Control Endpoint - RX.

#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C

Interrupt Endpoint.

#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004

Isochronous Endpoint.

#define XUSBPS_EPCR_TXE_MASK 0x00800000

Transmit enable - TX.

#define XUSBPS_EPCR_TXR_MASK 0x00400000

Data Toggle Reset Bit.

Referenced by XUsbPs_SetConfiguration().

#define XUSBPS_EPCR_TXS_MASK 0x00010000

Stall TX endpoint.

#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000

Bulk Endpoint - TX.

Referenced by XUsbPs_SetConfiguration().

#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000

Control Endpoint - TX.

#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000

Interrupt Endpoint.

#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000

Isochronous.

Endpoint

#define XUSBPS_EPFLUSH_OFFSET 0x000001B4

Endpoint Flush.

Referenced by XUsbPs_DeviceReset().

#define XUSBPS_EPLISTADDR_OFFSET 0x00000158

D: Endpoint List Addr.

Referenced by XUsbPs_ConfigureDevice().

#define XUSBPS_EPNAKIER_OFFSET 0x0000017C

Endpoint NAK IRQ Enable.

#define XUSBPS_EPNAKISR_OFFSET 0x00000178

Endpoint NAK IRQ Status.

Referenced by XUsbPs_IntrHandler().

#define XUSBPS_EPPRIME_OFFSET 0x000001B0

Endpoint Prime.

Referenced by XUsbPs_DeviceReset(), and XUsbPs_EpPrime().

#define XUSBPS_EPRDY_OFFSET 0x000001B8

Endpoint Ready.

#define XUSBPS_EPSTAT_OFFSET 0x000001AC

Endpoint Setup Status.

Referenced by XUsbPs_DeviceReset(), XUsbPs_EpGetSetupData(), and XUsbPs_IntrHandler().

#define XUSBPS_FRAME_OFFSET 0x0000014C

USB Frame Index.

#define XUSBPS_IER_OFFSET 0x00000148

Interrupt Enable.

Referenced by XUsbPs_ResetHw().

#define XUSBPS_ISR_OFFSET 0x00000144

Interrupt Status.

Referenced by XUsbPs_IntrHandler(), and XUsbPs_ResetHw().

#define XUSBPS_IXR_AA_MASK 0x00000020

Async Advance.

#define XUSBPS_IXR_ALL

Value:
(XUSBPS_IXR_UI_MASK | \
XUSBPS_IXR_UE_MASK | \
XUSBPS_IXR_PC_MASK | \
XUSBPS_IXR_FRE_MASK | \
XUSBPS_IXR_AA_MASK | \
XUSBPS_IXR_UR_MASK | \
XUSBPS_IXR_SR_MASK | \
XUSBPS_IXR_SLE_MASK | \
XUSBPS_IXR_ULPI_MASK | \
XUSBPS_IXR_HCH_MASK | \
XUSBPS_IXR_RCL_MASK | \
XUSBPS_IXR_PS_MASK | \
XUSBPS_IXR_AS_MASK | \
XUSBPS_IXR_NAK_MASK | \
XUSBPS_IXR_UA_MASK | \
XUSBPS_IXR_UP_MASK | \
XUSBPS_IXR_TI0_MASK | \
XUSBPS_IXR_TI1_MASK)
XUSBPS_IXR_SLE_MASK
#define XUSBPS_IXR_SLE_MASK
Device Controller Suspend.
Definition: xusbps_hw.h:256
XUSBPS_IXR_AS_MASK
#define XUSBPS_IXR_AS_MASK
Async Sched Status Read only.
Definition: xusbps_hw.h:265
XUSBPS_IXR_TI0_MASK
#define XUSBPS_IXR_TI0_MASK
Timer 0 Interrupt.
Definition: xusbps_hw.h:269
XUSBPS_IXR_SR_MASK
#define XUSBPS_IXR_SR_MASK
Start of Frame.
Definition: xusbps_hw.h:255
XUSBPS_IXR_PC_MASK
#define XUSBPS_IXR_PC_MASK
Port Change Detect.
Definition: xusbps_hw.h:251
XUSBPS_IXR_UE_MASK
#define XUSBPS_IXR_UE_MASK
Transaction Error.
Definition: xusbps_hw.h:250
XUSBPS_IXR_UA_MASK
#define XUSBPS_IXR_UA_MASK
USB Host Async IRQ.
Definition: xusbps_hw.h:267
XUSBPS_IXR_PS_MASK
#define XUSBPS_IXR_PS_MASK
Periodic Sched Status Read Only.
Definition: xusbps_hw.h:262
XUSBPS_IXR_NAK_MASK
#define XUSBPS_IXR_NAK_MASK
NAK IRQ.
Definition: xusbps_hw.h:266
XUSBPS_IXR_UP_MASK
#define XUSBPS_IXR_UP_MASK
USB Host Periodic IRQ.
Definition: xusbps_hw.h:268
XUSBPS_IXR_FRE_MASK
#define XUSBPS_IXR_FRE_MASK
Frame List Rollover.
Definition: xusbps_hw.h:252
XUSBPS_IXR_TI1_MASK
#define XUSBPS_IXR_TI1_MASK
Timer 1 Interrupt.
Definition: xusbps_hw.h:270
XUSBPS_IXR_RCL_MASK
#define XUSBPS_IXR_RCL_MASK
USB Reclamation Read Only.
Definition: xusbps_hw.h:261
XUSBPS_IXR_UI_MASK
#define XUSBPS_IXR_UI_MASK
USB Transaction Complete.
Definition: xusbps_hw.h:249
XUSBPS_IXR_ULPI_MASK
#define XUSBPS_IXR_ULPI_MASK
ULPI IRQ.
Definition: xusbps_hw.h:257
XUSBPS_IXR_AA_MASK
#define XUSBPS_IXR_AA_MASK
Async Advance.
Definition: xusbps_hw.h:253
XUSBPS_IXR_UR_MASK
#define XUSBPS_IXR_UR_MASK
RESET Received.
Definition: xusbps_hw.h:254
XUSBPS_IXR_HCH_MASK
#define XUSBPS_IXR_HCH_MASK
Host Controller Halted Read Only.
Definition: xusbps_hw.h:258

Mask for ALL IRQ types.

#define XUSBPS_IXR_AS_MASK 0x00008000

Async Sched Status Read only.

#define XUSBPS_IXR_FRE_MASK 0x00000008

Frame List Rollover.

#define XUSBPS_IXR_HCH_MASK 0x00001000

Host Controller Halted Read Only.

#define XUSBPS_IXR_NAK_MASK 0x00010000

NAK IRQ.

Referenced by XUsbPs_IntrHandler().

#define XUSBPS_IXR_PC_MASK 0x00000004

Port Change Detect.

#define XUSBPS_IXR_PS_MASK 0x00004000

Periodic Sched Status Read Only.

#define XUSBPS_IXR_RCL_MASK 0x00002000

USB Reclamation Read Only.

#define XUSBPS_IXR_SLE_MASK 0x00000100

Device Controller Suspend.

#define XUSBPS_IXR_SR_MASK 0x00000080

Start of Frame.

#define XUSBPS_IXR_TI0_MASK 0x01000000

Timer 0 Interrupt.

#define XUSBPS_IXR_TI1_MASK 0x02000000

Timer 1 Interrupt.

#define XUSBPS_IXR_UA_MASK 0x00040000

USB Host Async IRQ.

#define XUSBPS_IXR_UE_MASK 0x00000002

Transaction Error.

#define XUSBPS_IXR_UI_MASK 0x00000001

USB Transaction Complete.

Referenced by XUsbPs_IntrHandler().

#define XUSBPS_IXR_ULPI_MASK 0x00000400

ULPI IRQ.

#define XUSBPS_IXR_UP_MASK 0x00080000

USB Host Periodic IRQ.

#define XUSBPS_IXR_UR_MASK 0x00000040

RESET Received.

Referenced by XUsbPs_IntrHandler().

#define XUSBPS_LISTBASE_OFFSET 0x00000154

H: Periodic List Base Address.

Referenced by XUsbPs_ResetHw().

#define XUSBPS_MAX_ENDPOINTS 12

Number of supported Endpoints in this core.

#define XUSBPS_MAX_PACKET_SIZE 1024

Maximum value can be put into the queue head.

#define XUSBPS_MODE_CM_MASK 0x00000003

Controller Mode Select.

#define XUSBPS_MODE_ES_MASK 0x00000004

USB Endian Select.

#define XUSBPS_MODE_OFFSET 0x000001A8

USB Mode.

Referenced by XUsbPs_ConfigureDevice().

#define XUSBPS_MODE_SLOM_MASK 0x00000008

USB Setup Lockout Mode Disable.

Referenced by XUsbPs_ConfigureDevice().

#define XUSBPS_OTG_IEB_ALL

Value:
(XUSBPS_OTGSC_IDIE_MASK |\
XUSBPS_OTGSC_AVVIE_MASK | \
XUSBPS_OTGSC_ASVIE_MASK | \
XUSBPS_OTGSC_BSVIE_MASK | \
XUSBPS_OTGSC_BSEE_IEB_MASK | \
XUSBPS_OTGSC_1MSE_MASK | \
XUSBPS_OTGSC_DPIE_MASK)
XUSBPS_OTGSC_DPIE_MASK
#define XUSBPS_OTGSC_DPIE_MASK
Data Pulse Interrupt Enable Bit.
Definition: xusbps_hw.h:437
XUSBPS_OTGSC_BSVIE_MASK
#define XUSBPS_OTGSC_BSVIE_MASK
USB B Session Valid Interrupt Enable Bit.
Definition: xusbps_hw.h:432
XUSBPS_OTGSC_IDIE_MASK
#define XUSBPS_OTGSC_IDIE_MASK
ID Interrupt Enable Bit.
Definition: xusbps_hw.h:429
XUSBPS_OTGSC_AVVIE_MASK
#define XUSBPS_OTGSC_AVVIE_MASK
USB A VBus Valid Interrupt Enable Bit.
Definition: xusbps_hw.h:430
XUSBPS_OTGSC_ASVIE_MASK
#define XUSBPS_OTGSC_ASVIE_MASK
USB A Session Valid Interrupt Enable Bit.
Definition: xusbps_hw.h:431
XUSBPS_OTGSC_1MSE_MASK
#define XUSBPS_OTGSC_1MSE_MASK
1 Millisecond Timer Interrupt Enable Bit
Definition: xusbps_hw.h:434

Mask for All IRQ status masks.

#define XUSBPS_OTGCSR_OFFSET 0x000001A4

OTG Status and Control.

Referenced by XUsbPs_ConfigureDevice().

#define XUSBPS_OTGSC_1MSE_MASK 0x20000000

1 Millisecond Timer Interrupt Enable Bit

#define XUSBPS_OTGSC_1MSS_MASK 0x00200000

1 Millisecond Timer Interrupt Status Flag

#define XUSBPS_OTGSC_1MST_MASK 0x00002000

USB 1 Millisecond Timer Status Flag.

#define XUSBPS_OTGSC_ASV_MASK 0x00000400

USB A Session Valid Interrupt Status Flag.

#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000

USB A Session Valid Interrupt Enable Bit.

#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000

USB A Session Valid Interrupt Status Flag.

#define XUSBPS_OTGSC_AVV_MASK 0x00000200

USB A VBus Valid Interrupt Status Flag.

#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000

USB A VBus Valid Interrupt Enable Bit.

#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000

USB A VBus Valid Interrupt Status Flag.

#define XUSBPS_OTGSC_BSE_MASK 0x00001000

USB B Session End Status Flag.

#define XUSBPS_OTGSC_BSEE_MASK 0x10000000

USB B Session End Interrupt Enable Bit.

#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000

USB B Session End Interrupt Status Flag.

#define XUSBPS_OTGSC_BSV_MASK 0x00000800

USB B Session Valid Status Flag.

#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000

USB B Session Valid Interrupt Enable Bit.

#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000

USB B Session Valid Interrupt Status Flag.

#define XUSBPS_OTGSC_DP_MASK 0x00000010

Data Pulsing Pull-up Enable Bit.

#define XUSBPS_OTGSC_DPIE_MASK 0x40000000

Data Pulse Interrupt Enable Bit.

#define XUSBPS_OTGSC_DPIS_MASK 0x00400000

Data Pulse Interrupt Status Flag.

#define XUSBPS_OTGSC_DPS_MASK 0x00004000

Data Pulse Status Flag.

#define XUSBPS_OTGSC_HAAR_MASK 0x00000004

HW Assist Auto Reset Enable Bit.

#define XUSBPS_OTGSC_HABA_MASK 0x00000080

USB Hardware Assist B Disconnect to A Connect Enable Bit.

#define XUSBPS_OTGSC_HADP_MASK 0x00000040

HW Assist Data Pulse Enable Bit.

#define XUSBPS_OTGSC_ID_MASK 0x00000100

ID Status Flag.

#define XUSBPS_OTGSC_IDIE_MASK 0x01000000

ID Interrupt Enable Bit.

#define XUSBPS_OTGSC_IDIS_MASK 0x00010000

USB ID Interrupt Status Flag.

#define XUSBPS_OTGSC_IDPU_MASK 0x00000020

ID Pull-up Enable Bit.

#define XUSBPS_OTGSC_OT_MASK 0x00000008

OTG Termination Bit.

Referenced by XUsbPs_ConfigureDevice().

#define XUSBPS_OTGSC_VC_MASK 0x00000002

VBus Charge Bit.

#define XUSBPS_OTGSC_VD_MASK 0x00000001

VBus Discharge Bit.

#define XUSBPS_PORTSCR1_OFFSET 0x00000184

Port Control/Status 1.

#define XUSBPS_PORTSCR_CCS_MASK 0x00000001

Current Connect Status.

#define XUSBPS_PORTSCR_CSC_MASK 0x00000002

Connect Status Change.

#define XUSBPS_PORTSCR_FPR_MASK 0x00000040

Force Port Resume.

#define XUSBPS_PORTSCR_HSP_MASK 0x00000200

High Speed Port.

#define XUSBPS_PORTSCR_LS_MASK 0x00000C00

Line Status.

#define XUSBPS_PORTSCR_OCA_MASK 0x00000010

Over-current Active.

#define XUSBPS_PORTSCR_OCC_MASK 0x00000020

Over-current Change.

#define XUSBPS_PORTSCR_PE_MASK 0x00000004

Port Enable/Disable.

#define XUSBPS_PORTSCR_PEC_MASK 0x00000008

Port Enable/Disable Change.

#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000

Port Force Full Speed Connect.

#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000

PHY Low Power Suspend - Clock Disable.

#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000

Port Indicator Control.

#define XUSBPS_PORTSCR_PO_MASK 0x00002000

Port Owner.

#define XUSBPS_PORTSCR_PP_MASK 0x00001000

Port Power.

#define XUSBPS_PORTSCR_PR_MASK 0x00000100

Port Reset.

#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000

Port Speed.

#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000

Port Test Control.

#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080

Suspend.

#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000

Wake on Connect Enable.

#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000

Wake on Disconnect Enable.

#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000

Wake on Over-current Enable.

#define XUsbPs_ReaddQH | ( |  | dQHPtr,
|  |  | Id
| ) |  | (*(u32 *)((u32)(dQHPtr) + (u32) (Id)))

This macro reads the content of a field in a Queue Head.

Parameters

  dQHPtr | is a pointer to the dQH element.
  Id | is the Field ID inside the dQH element to read.

Note
  C-style signature: u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)

Referenced by XUsbPs_EpGetSetupData().

#define XUsbPs_ReaddTD | ( |  | dTDPtr,
|  |  | Id
| ) |  | (*(u32 *)((u32)(dTDPtr) + (u32)(Id)))

This macro reads the content of a field in a Transfer Descriptor.

Parameters

  dTDPtr | is a pointer to the dTD element.
  Id | is the field ID inside the dTD element to read.

Note
  C-style signature: u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)

Referenced by XUsbPs_EpBufferReceive().

#define XUsbPs_ReadReg | ( |  | BaseAddress,
|  |  | RegOffset
| ) |  | Xil_In32(BaseAddress + (RegOffset))

This macro reads the given register.

Parameters

  BaseAddress | is the base address for the USB registers.
  RegOffset | is the register offset to be read.

Returns
  The 32-bit value of the register.

Note
  C-style signature: u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)

Referenced by XUsbPs_DeviceReset(), XUsbPs_EpGetSetupData(), XUsbPs_IntrHandler(), XUsbPs_Reset(), and XUsbPs_ResetHw().

#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000

TT Hub Address.

#define XUSBPS_TTCTRL_OFFSET 0x0000015C

TT Control.

#define XUSBPS_TXFILL_BURST_MASK 0x003F0000

FIFO Burst Threshold.

#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00

Scheduler Health Cntr.

#define XUSBPS_TXFILL_OFFSET 0x00000164

Tx Fill Tuning.

#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF

Scheduler Overhead.

#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000

ULPI Data Address.

#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00

ULPI Data Read.

#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF

ULPI Data Write.

#define XUSBPS_ULPIVIEW_OFFSET 0x00000170

ULPI Viewport.

#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000

ULPI Port Number.

#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000

ULPI Run.

#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000

ULPI Read/Write Control.

#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000

ULPI Synchronous State.

#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000

ULPI Wakeup.

#define XUsbPs_WritedQH | ( |  | dQHPtr,
|  |  | Id,
|  |  | Val
| ) |  | (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))

This macro writes a value to a field in a Queue Head.

Parameters

  dQHPtr | is a pointer to the dQH element.
  Id | is the Field ID inside the dQH element to read.
  Val | is the Value to write to the field.

Note
  C-style signature: u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)

#define XUsbPs_WritedTD | ( |  | dTDPtr,
|  |  | Id,
|  |  | Val
| ) |  | (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))

This macro writes a value to a field in a Transfer Descriptor.

Parameters

  dTDPtr | is pointer to the dTD element.
  Id | is the field ID inside the dTD element to read.
  Val | is the value to write to the field.

Note
  C-style signature: u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)

Referenced by XUsbPs_EpBufferReceive().

#define XUsbPs_WriteReg | ( |  | BaseAddress,
|  |  | RegOffset,
|  |  | Data
| ) |  | Xil_Out32(BaseAddress + (RegOffset), (Data))

This macro writes the given register.

Parameters

  BaseAddress | is the the base address for the USB registers.
  RegOffset | is the register offset to be written.
  Data | is the the 32-bit value to write to the register.

Returns
  None.

Note
  C-style signature: void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XUsbPs_ConfigureDevice(), XUsbPs_DeviceReset(), XUsbPs_EpGetSetupData(), XUsbPs_EpPrime(), XUsbPs_IntrHandler(), XUsbPs_Reset(), XUsbPs_ResetHw(), and XUsbPs_SetDeviceAddress().

## Function Documentation

int XUsbPs_CfgInitialize | ( | XUsbPs * | InstancePtr,
|  | const XUsbPs_Config * | ConfigPtr,
|  | u32 | VirtBaseAddress
| ) |  |

This function initializes a XUsbPs instance/driver.

Setup / Initialize functions.

The initialization entails:

- Initialize all members of the XUsbPs structure.

Parameters

  InstancePtr | is a pointer to XUsbPs instance of the controller.
  ConfigPtr | is a pointer to a XUsbPs_Config configuration structure. This structure will contain the requested configuration for the device. Typically, this is a local structure and the content of which will be copied into the configuration structure within XUsbPs.
  VirtBaseAddress | is the base address of the device. For systems with virtual memory, this address must be the virtual address of the device. For systems that do not support virtual memory this address should be the physical address of the device. For backwards compatibility NULL may be passed in systems that do not support virtual memory (deprecated).

Returns
  - XST_SUCCESS no errors occurred.
  - XST_FAILURE an error occurred during initialization.

Note
  After calling XUsbPs_CfgInitialize() the controller IS NOT READY for use. Before the controller can be used its DEVICE parameters must be configured. See xusbps.h for details.

References XUsbPs_Config::BaseAddress, XUsbPs::Config, XUsbPs::CurrentAltSetting, XUsbPs::HandlerFunc, and XUSBPS_DEFAULT_ALT_SETTING.

int XUsbPs_ConfigureDevice | ( | XUsbPs * | InstancePtr,
|  | const XUsbPs_DeviceConfig * | CfgPtr
| ) |  |

This function configures the DEVICE side of the controller.

The caller needs to pass in the desired configuration (e.g. number of endpoints) and a DMAable buffer that will hold the Queue Head List and the Transfer Descriptors. The required size for this buffer can be obtained by the caller using the: XUsbPs_DeviceMemRequired() macro.

Parameters

  InstancePtr | is a pointer to the XUsbPs instance of the controller.
  CfgPtr | is a pointer to the configuration structure that contains the desired DEVICE side configuration.

Returns
  - XST_SUCCESS: The operation completed successfully.
  - XST_FAILURE: An error occurred.

Note
  The caller may configure the controller for both, DEVICE and HOST side.

References XUsbPs_Config::BaseAddress, XUsbPs::Config, XUsbPs::DeviceConfig, XUsbPs_DeviceConfig::DMAMemPhys, XUsbPs_DeviceConfig::PhysAligned, XUSBPS_dQH_BASE_ALIGN, XUSBPS_EPLISTADDR_OFFSET, XUSBPS_MODE_OFFSET, XUSBPS_MODE_SLOM_MASK, XUSBPS_OTGCSR_OFFSET, XUSBPS_OTGSC_OT_MASK, XUsbPs_Reset(), XUsbPs_SetBits, and XUsbPs_WriteReg.

void XUsbPs_DeviceReset | ( | XUsbPs * | InstancePtr | ) |

This function performs device reset, device is stopped at the end.

Parameters

  InstancePtr | is a pointer to XUsbPs instance of the controller.

Returns
  None.

Note
  None.

References XUsbPs_Config::BaseAddress, XUsbPs::Config, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK, XUSBPS_EP_ALL_MASK, XUSBPS_EPCOMPL_OFFSET, XUSBPS_EPFLUSH_OFFSET, XUSBPS_EPPRIME_OFFSET, XUSBPS_EPSTAT_OFFSET, XUsbPs_ReadReg, XUsbPs_Stop, and XUsbPs_WriteReg.

int XUsbPs_EpBufferReceive | ( | XUsbPs * | InstancePtr,
|  | u8 | EpNum,
|  | u8 ** | BufferPtr,
|  | u32 * | BufferLenPtr,
|  | u32 * | Handle
| ) |  |

This function receives a data buffer from the endpoint of the given endpoint number.

Parameters

  InstancePtr | is a pointer to the XUsbPs instance of the controller.
  EpNum | is the number of the endpoint to receive data from.
  BufferPtr | (OUT param) is a pointer to the buffer pointer to hold the reference of the data buffer.
  BufferLenPtr | (OUT param) is a pointer to the integer that will hold the buffer length.
  Handle | is the opaque handle to be used when the buffer is released.

Returns
  - XST_SUCCESS: The operation completed successfully.
  - XST_FAILURE: An error occurred.
  - XST_USB_NO_BUF: No buffer available.

Note
  After handling the data in the buffer, the user MUST release the buffer using the Handle by calling the XUsbPs_EpBufferRelease() function.

References XUsbPs_EpSetup::BufSize, XUsbPs::DeviceConfig, XUsbPs_EpOut::dTDCurr, XUsbPs_DeviceConfig::Ep, XUsbPs_DeviceConfig::EpCfg, XUsbPs_Endpoint::Out, XUsbPs_EpConfig::Out, XUSBPS_dTDBPTR0, XUsbPs_dTDGetTransferLen, XUsbPs_dTDInvalidateCache, XUsbPs_dTDIsActive, XUsbPs_dTDSetTransferLen, XUSBPS_dTDUSERDATA, XUsbPs_ReaddTD, and XUsbPs_WritedTD.

void XUsbPs_EpBufferRelease | ( | u32 | Handle | ) |

This function returns a previously received data buffer to the driver.

Parameters

  Handle | is a pointer to the buffer that is returned.

Returns
  None.

References XUSBPS_dTD_ALIGN, XUsbPs_dTDClrTerminate, XUsbPs_dTDInvalidateCache, XUsbPs_dTDSetActive, and XUsbPs_dTDSetIOC.

int XUsbPs_EpBufferSend | ( | XUsbPs * | InstancePtr,
|  | u8 | EpNum,
|  | const u8 * | BufferPtr,
|  | u32 | BufferLen
| ) |  |

This function sends a given data buffer.

Parameters

  InstancePtr | is a pointer to XUsbPs instance of the controller.
  EpNum | is the number of the endpoint to receive data from.
  BufferPtr | is a pointer to the buffer to send.
  BufferLen | is the Buffer length.

Returns
  - XST_SUCCESS: The operation completed successfully.
  - XST_FAILURE: An error occurred.
  - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
  - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.

Referenced by XUsbPs_ClassReq(), and XUsbPs_HandleStorageReq().

int XUsbPs_EpBufferSendWithZLT | ( | XUsbPs * | InstancePtr,
|  | u8 | EpNum,
|  | const u8 * | BufferPtr,
|  | u32 | BufferLen
| ) |  |

This function sends a given data buffer and also zero length packet if the Bufferlen is in multiples of endpoint max packet size.

Parameters

  InstancePtr | is a pointer to XUsbPs instance of the controller.
  EpNum | is the number of the endpoint to receive data from.
  BufferPtr | is a pointer to the buffer to send.
  BufferLen | is the Buffer length.

Returns
  - XST_SUCCESS: The operation completed successfully.
  - XST_FAILURE: An error occurred.
  - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
  - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.

References XUsbPs::DeviceConfig, XUsbPs_DeviceConfig::EpCfg, XUsbPs_EpConfig::In, and XUsbPs_EpSetup::MaxPacketSize.

int XUsbPs_EpGetSetupData | ( | XUsbPs * | InstancePtr,
|  | int | EpNum,
|  | XUsbPs_SetupData * | SetupDataPtr
| ) |  |

This function extracts the Setup Data from a given endpoint.

Parameters

  InstancePtr | is a pointer to the XUsbPs instance of the controller.
  EpNum | is the number of the endpoint to receive data from.
  SetupDataPtr | is a pointer to the setup data structure to be filled.

Returns
  - XST_SUCCESS: The operation completed successfully.
  - XST_FAILURE: An error occurred.

Note
  None.

References XUsbPs_Config::BaseAddress, XUsbPs_SetupData::bmRequestType, XUsbPs_SetupData::bRequest, XUsbPs::Config, XUsbPs::DeviceConfig, XUsbPs_EpOut::dQH, XUsbPs_DeviceConfig::Ep, XUsbPs_Endpoint::Out, XUsbPs_SetupData::wIndex, XUsbPs_SetupData::wLength, XUsbPs_SetupData::wValue, XUsbPs_ClrSetupTripwire, XUSBPS_dQHSUB0, XUSBPS_dQHSUB1, XUSBPS_EPSTAT_OFFSET, XUsbPs_ReaddQH, XUsbPs_ReadReg, XUsbPs_SetSetupTripwire, XUsbPs_SetupTripwireIsSet, and XUsbPs_WriteReg.

int XUsbPs_EpPrime | ( | XUsbPs * | InstancePtr,
|  | u8 | EpNum,
|  | u8 | Direction
| ) |  |

This function primes an endpoint.

Parameters

  InstancePtr | is pointer to the XUsbPs instance.
  EpNum | is the number of the endpoint to receive data from.
  Direction | is the direction of the endpoint (bitfield): XUSBPS_EP_DIRECTION_OUT XUSBPS_EP_DIRECTION_IN

Returns
  - XST_SUCCESS: The operation completed successfully.
  - XST_FAILURE: An error occurred.
  - XST_INVALID_PARAM: Invalid parameter passed.

Note
  None.

References XUsbPs_Config::BaseAddress, XUsbPs::Config, XUSBPS_EP_DIRECTION_IN, XUSBPS_EP_DIRECTION_OUT, XUSBPS_EPPRIME_OFFSET, and XUsbPs_WriteReg.

Referenced by XUsbPs_IntrHandler(), and XUsbPs_SetConfiguration().

int XUsbPs_EpSetHandler | ( | XUsbPs * | InstancePtr,
|  | u8 | EpNum,
|  | u8 | Direction,
|  | XUsbPs_EpHandlerFunc | CallBackFunc,
|  | void * | CallBackRef
| ) |  |

This function sets the handler for endpoint events.

Parameters

  InstancePtr | is a pointer to the XUsbPs instance of the controller.
  EpNum | is the number of the endpoint to receive data from.
  Direction | is the direction of the endpoint (bitfield): XUSBPS_EP_DIRECTION_OUT XUSBPS_EP_DIRECTION_IN
  CallBackFunc | is the Handler callback function. Can be NULL if the user wants to disable the handler entry.
  CallBackRef | is the user definable data pointer that will be passed back if the handler is called. May be NULL.

Returns
  - XST_SUCCESS: The operation completed successfully.
  - XST_FAILURE: An error occurred.
  - XST_INVALID_PARAM: Invalid parameter passed.

Note
  The user can disable a handler by setting the callback function pointer to NULL.

References XUsbPs::DeviceConfig, XUsbPs_DeviceConfig::Ep, XUsbPs_EpOut::HandlerFunc, XUsbPs_EpIn::HandlerFunc, XUsbPs_EpOut::HandlerRef, XUsbPs_EpIn::HandlerRef, XUsbPs_Endpoint::In, XUsbPs_Endpoint::Out, XUSBPS_EP_DIRECTION_IN, and XUSBPS_EP_DIRECTION_OUT.

void XUsbPs_IntrHandler | ( | void * | HandlerRef | ) |

This function is the first-level interrupt handler for the USB core.

All USB interrupts will be handled here. Depending on the type of the interrupt, second level interrupt handler may be called. Second level interrupt handlers will be registered by the user using the: XUsbPs_IntrSetHandler() and/or XUsbPs_EpSetHandler() functions.

Parameters

  HandlerRef | is a Reference passed to the interrupt register function. In our case this will be a pointer to the XUsbPs instance.

Returns
  None

Note
  None

References XUsbPs_Config::BaseAddress, XUsbPs::Config, XUsbPs::HandlerFunc, XUsbPs::HandlerMask, XUsbPs::HandlerRef, XUSBPS_EP_DIRECTION_OUT, XUSBPS_EP_IN_MASK, XUSBPS_EP_OUT_MASK, XUSBPS_EPCOMPL_OFFSET, XUSBPS_EPNAKISR_OFFSET, XUsbPs_EpPrime(), XUSBPS_EPSTAT_OFFSET, XUSBPS_ISR_OFFSET, XUSBPS_IXR_NAK_MASK, XUSBPS_IXR_UI_MASK, XUSBPS_IXR_UR_MASK, XUsbPs_ReadReg, and XUsbPs_WriteReg.

int XUsbPs_IntrSetHandler | ( | XUsbPs * | InstancePtr,
|  | XUsbPs_IntrHandlerFunc | CallBackFunc,
|  | void * | CallBackRef,
|  | u32 | Mask
| ) |  |

This function registers the user callback handler for controller (non-endpoint) interrupts.

Parameters

  InstancePtr | is a pointer to the XUsbPs instance of the controller.
  CallBackFunc | is the Callback function to register. CallBackFunc may be NULL to clear the entry.
  CallBackRef | is the user data reference passed to the callback function. CallBackRef may be NULL.
  Mask | is the User interrupt mask. Defines which interrupts will cause the callback to be called.

Returns
  - XST_SUCCESS: Callback registered successfully.
  - XST_FAILURE: Callback could not be registered.

Note
  None.

References XUsbPs::HandlerFunc, XUsbPs::HandlerMask, and XUsbPs::HandlerRef.

XUsbPs_Config* XUsbPs_LookupConfig | ( | u16 | DeviceID | ) |

Looks up the controller configuration based on the unique controller ID.

A table contains the configuration info for each controller in the system.

Parameters

  DeviceID | is the ID of the controller to look up the configuration for.

Returns
  A pointer to the configuration found or NULL if the specified controller ID was not found.

int XUsbPs_ReconfigureEp | ( | XUsbPs * | InstancePtr,
|  | XUsbPs_DeviceConfig * | CfgPtr,
|  | int | EpNum,
|  | unsigned short | NewDirection,
|  | int | DirectionChanged
| ) |  |

This function reconfigures one Ep corresponding to host's request of setting alternate interface.

The endpoint has been disabled before this call.

Both QH and dTDs are updated for the new configuration.

Parameters

  InstancePtr | is a pointer to the XUsbPs instance of the controller.
  CfgPtr | Pointer to the updated XUsbPs DEVICE configuration structure.
  EpNum | The endpoint to be reconfigured.
  NewDirection | The new transfer direction the endpoint.
  DirectionChanged | A boolean value indicate whether the transfer direction has changed.

Returns
  XST_SUCCESS upon success, XST_FAILURE otherwise.

References XUsbPs_EpOut::dTDBufs, XUsbPs_EpOut::dTDCurr, XUsbPs_EpIn::dTDHead, XUsbPs_EpOut::dTDs, XUsbPs_EpIn::dTDs, XUsbPs_EpIn::dTDTail, XUsbPs_DeviceConfig::Ep, XUsbPs_DeviceConfig::EpCfg, XUsbPs_Endpoint::In, XUsbPs_EpSetup::NumBufs, XUsbPs_Endpoint::Out, XUsbPs_EpConfig::Out, XUSBPS_dTD_ALIGN, XUSBPS_EP_DIRECTION_IN, and XUSBPS_EP_DIRECTION_OUT.

int XUsbPs_RequestHostResume | ( | const XUsbPs * | InstancePtr | ) |

USB Assert Resume.

Parameters

  InstancePtr | is a pointer to XUsbPs instance of the controller.

Returns
  - XST_SUCCESS if the USB device has Resumed successfully
  - XST_FAILURE on any error

Note
  None.

int XUsbPs_Reset | ( | XUsbPs * | InstancePtr | ) |

This function resets the USB device.

Common functions used for DEVICE/HOST mode.

All the configuration registers are reset to their default values. The function waits until the reset operation is complete or for a certain duration within which the reset operation is expected to be completed.

Parameters

  InstancePtr | is a pointer to XUsbPs instance of the controller.

Returns
  - XST_SUCCESS Reset operation completed successfully.
  - XST_FAILURE Reset operation timed out.

Note
  None.

References XUsbPs_Config::BaseAddress, XUsbPs::Config, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK, XUsbPs_ReadReg, and XUsbPs_WriteReg.

Referenced by XUsbPs_ConfigureDevice().

void XUsbPs_ResetHw | ( | u32 | BaseAddress | ) |

This function perform the reset sequence to the given usbps interface by configuring the appropriate control bits in the usbps specific registers.

the usbps reset sequence involves the below steps Disable the interrupts Clear the status registers Apply the reset command and wait for reset complete status Update the relevant control registers with reset values

Parameters

  BaseAddress | of the interface

Returns
  N/A.

Note
  None.

References XUSBPS_ASYNCLISTADDR_OFFSET, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK, XUSBPS_IER_OFFSET, XUSBPS_ISR_OFFSET, XUSBPS_LISTBASE_OFFSET, XUsbPs_ReadReg, and XUsbPs_WriteReg.

int XUsbPs_Resume | ( | const XUsbPs * | InstancePtr | ) |

USB Resume.

If the USB controller is suspended, its operation is resumed when any non-idle signaling is received on its upstream facing port.

Parameters

  InstancePtr | is a pointer to XUsbPs instance of the controller.

Returns
  - XST_SUCCESS if the USB device has Resumed successfully
  - XST_FAILURE on any error

Note
  None.

int XUsbPs_SetDeviceAddress | ( | XUsbPs * | InstancePtr,
|  | u8 | Address
| ) |  |

This functions sets the controller's DEVICE address.

It also sets the advance bit so the controller will wait for the next IN-ACK before the new address takes effect.

Parameters

  InstancePtr | is a pointer to XUsbPs instance of the controller.
  Address | is the Address of the device.

Returns
  - XST_SUCCESS: Address set successfully.
  - XST_FAILURE: An error occurred.
  - XST_INVALID_PARAM: Invalid parameter passed, e.g. address value too big.

Note
  None.

References XUsbPs_Config::BaseAddress, XUsbPs::Config, XUSBPS_DEVICEADDR_ADDR_SHIFT, XUSBPS_DEVICEADDR_DEVICEAADV_MASK, XUSBPS_DEVICEADDR_MAX, XUSBPS_DEVICEADDR_OFFSET, and XUsbPs_WriteReg.

int XUsbPs_Suspend | ( | const XUsbPs * | InstancePtr | ) |

USB Suspend.

Handling Suspend and Resume.

In order to conserve power, USB devices automatically enter the suspended state when the device has observed no bus traffic for a specified period. When suspended, the USB device maintains any internal status, including its address and configuration. Attached devices must be prepared to suspend at any time they are powered, regardless of if they have been assigned a non-default address, are configured, or neither. Bus activity may cease due to the host entering a suspend mode of its own. In addition, a USB device shall also enter the suspended state when the hub port it is attached to is disabled.

A USB device exits suspend mode when there is bus activity. A USB device may also request the host to exit suspend mode or selective suspend by using electrical signaling to indicate remote wakeup. The ability of a device to signal remote wakeup is optional. If the USB device is capable of remote wakeup signaling, the device must support the ability of the host to enable and disable this capability. When the device is reset, remote wakeup signaling must be disabled.

Parameters

  InstancePtr | is a pointer to XUsbPs instance of the controller.

Returns
  - XST_SUCCESS if the USB device has entered Suspend mode successfully
  - XST_FAILURE on any error

Note
  None.

## Variable Documentation

XUsbPs_Config XUsbPs_ConfigTable[]

Each XUsbPs device in the system has an entry in this table.

XUsbPs_Config XUsbPs_ConfigTable[]

Initial value:
= {
{
0,
XPAR_XUSBPS_0_BASEADDR
},
}

Each XUsbPs device in the system has an entry in this table.