axidma: xaxidma_example_sg_intr.c File Reference

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xaxidma_example_sg_intr.c File Reference

## Overview

This file demonstrates how to use the xaxidma driver on the Xilinx AXI DMA core (AXIDMA) to transfer packets in interrupt mode when the AXIDMA core is configured in Scatter Gather Mode.

We show how to do multiple packets transfers, as well as how to do multiple BDs per packet transfers.

This code assumes a loopback hardware widget is connected to the AXI DMA core for data packet loopback.

To see the debug print, you need a Uart16550 or uartlite in your system, and please set "-DDEBUG" in your compiler options. You need to rebuild your software executable.

Make sure that MEMORY_BASE is defined properly as per the HW system. The h/w system built in Area mode has a maximum DDR memory limit of 64MB. In throughput mode, it is 512MB. These limits are need to ensured for proper operation of this code.

    MODIFICATION HISTORY:

    Ver   Who  Date     Changes
    ----- ---- -------- -------------------------------------------------------
    1.00a jz   05/18/10 First release
    2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
                               updated tcl file, added xaxidma_porting_guide.h, removed
                               workaround for endianness
    4.00a rkv  02/22/11 Name of the file has been changed for naming consistency
                               Added interrupt support for Zynq.
    5.00a srt  03/05/12 Added Flushing and Invalidation of Caches to fix CRs
                               648103, 648701.
                               Added V7 DDR Base Address to fix CR 649405.
    6.00a srt  01/24/12 Changed API calls to support MCDMA driver.
    7.00a srt  06/18/12 API calls are reverted back for backward compatibility.
    7.01a srt  11/02/12 Buffer sizes (Tx and Rx) are modified to meet maximum
                   DDR memory limit of the h/w system built with Area mode
    7.02a srt  03/01/13 Updated DDR base address for IPI designs (CR 703656).
    9.1   adk  01/07/16 Updated DDR base address for Ultrascale (CR 799532) and
                   removed the defines for S6/V6.
    9.3   ms   01/23/17 Modified xil_printf statement in main function to
                        ensure that "Successfully ran" and "Failed" strings are
                        available in all examples. This is a fix for CR-965028.
          ms   04/05/17 Added tabspace for return statements in functions
                        for proper documentation while generating doxygen.
    9.6   rsp  02/14/18 Support data buffers above 4GB.Use UINTPTR for storing
                        and typecasting buffer address(CR-992638).
    9.9   rsp  01/21/19 Fix use of #elif check in deriving DDR_BASE_ADDR.
    9.10  rsp  09/17/19 Fix cache maintenance ops for source and dest buffer.

## Functions
int | main (void)
| Main function. More...

## Function Documentation

int main | ( | void |  | ) |

Main function.

This function is the main entry of the interrupt test. It does the following:

- Set up the output terminal if UART16550 is in the hardware build
- Initialize the DMA engine
- Set up Tx and Rx channels
- Set up the interrupt system for the Tx and Rx interrupts
- Submit a transfer
- Wait for the transfer to finish
- Check transfer status
- Disable Tx and Rx interrupts
- Print test status and exit

Parameters

  None |

Returns
  - XST_SUCCESS if tests pass
  - XST_FAILURE if fails.

Note
  None.

References XAxiDma_CfgInitialize(), XAxiDma_HasSg, and XAxiDma_LookupConfig().