axis_switch: Axis_switch_v1_2

| axis_switch Xilinx SDK Drivers API Documentation

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Data Structures | Macros | Functions
Axis_switch_v1_2

## Data Structures
struct | XAxis_Switch_Config
| This typedef contains configuration information for the AXI4-Stream Switch core. More...
struct | XAxis_Switch
| The AXI4-Stream Switch driver instance data. More...

## Macros
#define | XAXIS_SWITCH_H_
| Prevent circular inclusions by using protection macros. More...
#define | XAxisScr_RegUpdateEnable(InstancePtr)
| This macro enables register updates. More...
#define | XAxisScr_RegUpdateDisable(InstancePtr)
| This macro disables register updates. More...
#define | XAXIS_SWITCH_HW_H_
| Prevent circular inclusions by using protection macros. More...

## Functions
s32 | XAxisScr_CfgInitialize (XAxis_Switch *InstancePtr, XAxis_Switch_Config *CfgPtr, UINTPTR EffectiveAddr)
| This function initializes the AXI4-Stream Switch core. More...
void | XAxisScr_MiPortEnable (XAxis_Switch *InstancePtr, u8 MiIndex, u8 SiIndex)
| This function enables the MUX port specified by a MI index and links with desired SI, indicated by a SiIndex. More...
void | XAxisScr_MiPortDisable (XAxis_Switch *InstancePtr, u8 MiIndex)
| This function disables the MUX port specified by a MI index and un-link SI, set previously. More...
s32 | XAxisScr_IsMiPortEnabled (XAxis_Switch *InstancePtr, u8 MiIndex, u8 SiIndex)
| This function returns the status of whether MUX is sourced from desired SI. More...
s32 | XAxisScr_IsMiPortDisabled (XAxis_Switch *InstancePtr, u8 MiIndex)
| This function returns the status of whether MUX is disabled. More...
void | XAxisScr_MiPortDisableAll (XAxis_Switch *InstancePtr)
| This function disables all the MUX port, in turn removes association with desired SI. More...
XAxis_Switch_Config * | XAxisScr_LookupConfig (u16 DeviceId)
| This function returns a reference to an XAxis_Switch_Config structure based on the core id, DeviceId. More...
s32 | XAxisScr_SelfTest (XAxis_Switch *InstancePtr)
| This function performs self test on AXI4-Stream Switch core registers. More...

## MI MUX register offsets
#define | XAXIS_SCR_CTRL_OFFSET 0x000
| Control Register offset. More...
#define | XAXIS_SCR_MI_MUX_START_OFFSET 0x040
| Start of MI MUX Register offset. More...
#define | XAXIS_SCR_MI_MUX_END_OFFSET 0x07C
| End of MI MUX Register offset. More...

## MI MUX Control register mask
#define | XAXIS_SCR_CTRL_REG_UPDATE_MASK 0x02
| Register Update mask. More...

## MI MUX register mask
It is applicable for MI[0...15] registers.
#define | XAXIS_SCR_MI_X_MUX_MASK 0x0F
| MI MUX mask. More...
#define | XAXIS_SCR_MI_X_DISABLE_MASK 0x80000000
| MI Disable mask. More...
#define | XAXIS_SCR_MI_X_DISABLE_SHIFT 31
| MI Disable shift. More...

## Register access macro definition
#define | XAxisScr_In32 Xil_In32
| Input Operations. More...
#define | XAxisScr_Out32 Xil_Out32
| Output Operations. More...
#define | XAxisScr_ReadReg(BaseAddress, RegOffset) XAxisScr_In32((BaseAddress) + ((u32)RegOffset))
| This macro reads a value from a AXI4-Stream Switch register. More...
#define | XAxisScr_WriteReg(BaseAddress, RegOffset, Data) XAxisScr_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
| This macro writes a value to a AXI4-Stream Switch register. More...

## Macro Definition Documentation

#define XAXIS_SCR_CTRL_OFFSET 0x000

Control Register offset.

#define XAXIS_SCR_CTRL_REG_UPDATE_MASK 0x02

Register Update mask.

#define XAXIS_SCR_MI_MUX_END_OFFSET 0x07C

End of MI MUX Register offset.

#define XAXIS_SCR_MI_MUX_START_OFFSET 0x040

Start of MI MUX Register offset.

Referenced by XAxisScr_IsMiPortDisabled(), XAxisScr_IsMiPortEnabled(), XAxisScr_MiPortDisable(), XAxisScr_MiPortDisableAll(), and XAxisScr_MiPortEnable().

#define XAXIS_SCR_MI_X_DISABLE_MASK 0x80000000

MI Disable mask.

Referenced by XAxisScr_MiPortDisable(), and XAxisScr_MiPortDisableAll().

#define XAXIS_SCR_MI_X_DISABLE_SHIFT 31

MI Disable shift.

Referenced by XAxisScr_IsMiPortDisabled(), and XAxisScr_IsMiPortEnabled().

#define XAXIS_SCR_MI_X_MUX_MASK 0x0F

MI MUX mask.

Referenced by XAxisScr_IsMiPortEnabled().

#define XAXIS_SWITCH_H_

Prevent circular inclusions by using protection macros.

#define XAXIS_SWITCH_HW_H_

Prevent circular inclusions by using protection macros.

#define XAxisScr_In32 Xil_In32

Input Operations.

#define XAxisScr_Out32 Xil_Out32

Output Operations.

#define XAxisScr_ReadReg | ( |  | BaseAddress,
|  |  | RegOffset
| ) |  | XAxisScr_In32((BaseAddress) + ((u32)RegOffset))

This macro reads a value from a AXI4-Stream Switch register.

A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.

Parameters

  BaseAddress | is the base address of the XAxis_Switch core instance.
  RegOffset | is the register offset of the register (defined at the top of this file).

Returns
  The 32-bit value of the register.

Note
  C-style signature: u32 XAxisScr_ReadReg(u32 BaseAddress, u32 RegOffset)

Referenced by XAxisScr_IsMiPortDisabled(), and XAxisScr_IsMiPortEnabled().

#define XAxisScr_RegUpdateDisable | ( |  | InstancePtr | ) |

Value:
XAxisScr_WriteReg((InstancePtr)->Config.BaseAddress, \
XAXIS_SCR_CTRL_OFFSET, \
XAxisScr_ReadReg((InstancePtr)->Config.BaseAddress, \
XAXIS_SCR_CTRL_OFFSET) & \
(~XAXIS_SCR_CTRL_REG_UPDATE_MASK))
XAxisScr_WriteReg
#define XAxisScr_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a AXI4-Stream Switch register.
Definition: xaxis_switch_hw.h:150
XAxisScr_ReadReg
#define XAxisScr_ReadReg(BaseAddress, RegOffset)
This macro reads a value from a AXI4-Stream Switch register.
Definition: xaxis_switch_hw.h:127
XAXIS_SCR_CTRL_REG_UPDATE_MASK
#define XAXIS_SCR_CTRL_REG_UPDATE_MASK
Register Update mask.
Definition: xaxis_switch_hw.h:82
XAXIS_SCR_CTRL_OFFSET
#define XAXIS_SCR_CTRL_OFFSET
Control Register offset.
Definition: xaxis_switch_hw.h:69

This macro disables register updates.

Parameters

  InstancePtr | is a pointer to the XAxis_Switch core instance.

Returns
  None.

Note
  C-style signature: void XAxisScr_RegUpdateDisable(XAxis_Switch *InstancePtr)

Referenced by AxisSwitch_Example().

#define XAxisScr_RegUpdateEnable | ( |  | InstancePtr | ) |

Value:
XAxisScr_WriteReg((InstancePtr)->Config.BaseAddress, \
XAXIS_SCR_CTRL_OFFSET, \
XAxisScr_ReadReg((InstancePtr)->Config.BaseAddress, \
XAXIS_SCR_CTRL_OFFSET) | \
XAXIS_SCR_CTRL_REG_UPDATE_MASK)
XAxisScr_WriteReg
#define XAxisScr_WriteReg(BaseAddress, RegOffset, Data)
This macro writes a value to a AXI4-Stream Switch register.
Definition: xaxis_switch_hw.h:150
XAxisScr_ReadReg
#define XAxisScr_ReadReg(BaseAddress, RegOffset)
This macro reads a value from a AXI4-Stream Switch register.
Definition: xaxis_switch_hw.h:127
XAXIS_SCR_CTRL_REG_UPDATE_MASK
#define XAXIS_SCR_CTRL_REG_UPDATE_MASK
Register Update mask.
Definition: xaxis_switch_hw.h:82
XAXIS_SCR_CTRL_OFFSET
#define XAXIS_SCR_CTRL_OFFSET
Control Register offset.
Definition: xaxis_switch_hw.h:69

This macro enables register updates.

Parameters

  InstancePtr | is a pointer to the XAxis_Switch core instance.

Returns
  None.

Note
  C-style signature: void XAxisScr_RegUpdateEnable(XAxis_Switch *InstancePtr)

Referenced by AxisSwitch_Example().

#define XAxisScr_WriteReg | ( |  | BaseAddress,
|  |  | RegOffset,
|  |  | Data
| ) |  | XAxisScr_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))

This macro writes a value to a AXI4-Stream Switch register.

A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.

Parameters

  BaseAddress | is the base address of the XAxis_Switch core instance.
  RegOffset | is the register offset of the register (defined at the top of this file) to be written.
  Data | is the 32-bit value to write into the register.

Returns
  None.

Note
  C-style signature: void XAxisScr_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XAxisScr_MiPortDisable(), XAxisScr_MiPortDisableAll(), and XAxisScr_MiPortEnable().

## Function Documentation

s32 XAxisScr_CfgInitialize | ( | XAxis_Switch * | InstancePtr,
|  | XAxis_Switch_Config * | CfgPtr,
|  | UINTPTR | EffectiveAddr
| ) |  |

This function initializes the AXI4-Stream Switch core.

This function must be called prior to using the core. Initialization of the core includes setting up the instance data and ensuring the hardware is in a quiescent state.

Parameters

  InstancePtr | is a pointer to the XAxis_Switch core instance.
  CfgPtr | points to the configuration structure associated with the AXI4-Stream Switch core.
  EffectiveAddr | is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.

Returns
  - XST_SUCCESS if XAxisScr_CfgInitialize was successful.

Note
  Axis_Switch core connects up to 16 masters to 16 slaves.

References XAxis_Switch_Config::BaseAddress, XAxis_Switch::Config, XAxis_Switch::IsReady, and XAxisScr_MiPortDisableAll().

Referenced by AxisSwitch_Example().

s32 XAxisScr_IsMiPortDisabled | ( | XAxis_Switch * | InstancePtr,
|  | u8 | MiIndex
| ) |  |

This function returns the status of whether MUX is disabled.

Parameters

  InstancePtr | is a pointer to the XAxis_Switch core instance.
  MiIndex | specifies an index that will be used for addressing the MUX which is within the range [0 to 15].

Returns
  - TRUE, if MUX is disabled.
  - FALSE, if MUX is enabled.

Note
  Axis_Switch core connects up to 16 masters to 16 slaves.

References XAxis_Switch_Config::BaseAddress, XAxis_Switch::Config, XAXIS_SCR_MI_MUX_START_OFFSET, XAXIS_SCR_MI_X_DISABLE_SHIFT, and XAxisScr_ReadReg.

s32 XAxisScr_IsMiPortEnabled | ( | XAxis_Switch * | InstancePtr,
|  | u8 | MiIndex,
|  | u8 | SiIndex
| ) |  |

This function returns the status of whether MUX is sourced from desired SI.

Parameters

  InstancePtr | is a pointer to the XAxis_Switch core instance.
  MiIndex | specifies an index that will be used for addressing the MUX which is within the range [0 to 15].
  SiIndex | specifies an index that will be used to identify, whether it is sourced. The range is [0 to 15].

Returns
  - TRUE, if MUX is sourced from SI.
  - FALSE, if MUX is not sourced from SI.

Note
  Axis_Switch core connects up to 16 masters to 16 slaves.

References XAxis_Switch_Config::BaseAddress, XAxis_Switch::Config, XAXIS_SCR_MI_MUX_START_OFFSET, XAXIS_SCR_MI_X_DISABLE_SHIFT, XAXIS_SCR_MI_X_MUX_MASK, and XAxisScr_ReadReg.

Referenced by AxisSwitch_Example(), and XAxisScr_SelfTest().

XAxis_Switch_Config * XAxisScr_LookupConfig | ( | u16 | DeviceId | ) |

This function returns a reference to an XAxis_Switch_Config structure based on the core id, DeviceId.

The return value will refer to an entry in the device configuration table defined in the xaxis_switch_g.c file.

Parameters

  DeviceId | is the unique core ID of the XAxis_Switch core for the lookup operation.

Returns
  XAxisScr_LookupConfig returns a reference to a config record in the configuration table (in xaxis_switch_g.c) corresponding to DeviceId, or NULL if no match is found.

Note
  None.

Referenced by AxisSwitch_Example().

void XAxisScr_MiPortDisable | ( | XAxis_Switch * | InstancePtr,
|  | u8 | MiIndex
| ) |  |

This function disables the MUX port specified by a MI index and un-link SI, set previously.

Parameters

  InstancePtr | is a pointer to the XAxis_Switch core instance.
  MiIndex | specifies an index that will be used for disabling MUX which is within the range [0 to 15].

Returns
  None.

Note
  MUX[MiIndex] is removed for SI[SiIndex]. Axis_Switch core connects up to 16 masters to 16 slaves.

References XAxis_Switch_Config::BaseAddress, XAxis_Switch::Config, XAXIS_SCR_MI_MUX_START_OFFSET, XAXIS_SCR_MI_X_DISABLE_MASK, and XAxisScr_WriteReg.

Referenced by AxisSwitch_Example().

void XAxisScr_MiPortDisableAll | ( | XAxis_Switch * | InstancePtr | ) |

This function disables all the MUX port, in turn removes association with desired SI.

Parameters

  InstancePtr | is a pointer to the XAxis_Switch core instance.

Returns
  None.

Note
  Axis_Switch core connects up to 16 masters to 16 slaves.

References XAxis_Switch_Config::BaseAddress, XAxis_Switch::Config, XAxis_Switch_Config::MaxNumMI, XAXIS_SCR_MI_MUX_START_OFFSET, XAXIS_SCR_MI_X_DISABLE_MASK, and XAxisScr_WriteReg.

Referenced by AxisSwitch_Example(), XAxisScr_CfgInitialize(), and XAxisScr_SelfTest().

void XAxisScr_MiPortEnable | ( | XAxis_Switch * | InstancePtr,
|  | u8 | MiIndex,
|  | u8 | SiIndex
| ) |  |

This function enables the MUX port specified by a MI index and links with desired SI, indicated by a SiIndex.

Parameters

  InstancePtr | is a pointer to the XAxis_Switch core instance.
  MiIndex | specifies an index that will be used for enabling MUX which is within the range [0 to 15].
  SiIndex | specifies an index that will be used as a source to MUX. The range is [0 to 15].

Returns
  None.

Note
  MUX[MiIndex] is sourced from SI[SiIndex]. Axis_Switch core connects up to 16 masters to 16 slaves.

References XAxis_Switch_Config::BaseAddress, XAxis_Switch::Config, XAXIS_SCR_MI_MUX_START_OFFSET, and XAxisScr_WriteReg.

Referenced by AxisSwitch_Example(), and XAxisScr_SelfTest().

s32 XAxisScr_SelfTest | ( | XAxis_Switch * | InstancePtr | ) |

This function performs self test on AXI4-Stream Switch core registers.

Parameters

  InstancePtr | is a pointer to the XAxis_Switch core instance.

Returns
  - TRUE if self test passed.
  - FALSE if self test failed.

Note
  None.

References XAxisScr_IsMiPortEnabled(), XAxisScr_MiPortDisableAll(), and XAxisScr_MiPortEnable().