/**
 * (c) 2013 Xilinx Inc.
 * XREGDB v0.91
 * XREGCHDR v0.15
 *
 * Generated on: 2018-10-30
 *
 * @file: pmc_global.h
 *
 *
 * This file contains confidential and proprietary information
 * of Xilinx, Inc. and is protected under U.S. and
 * international copyright and other intellectual property
 * laws.
 *
 * DISCLAIMER
 * This disclaimer is not a license and does not grant any
 * rights to the materials distributed herewith. Except as
 * otherwise provided in a valid license issued to you by
 * Xilinx, and to the maximum extent permitted by applicable
 * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
 * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
 * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
 * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
 * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
 * (2) Xilinx shall not be liable (whether in contract or tort,
 * including negligence, or under any other theory of
 * liability) for any loss or damage of any kind or nature
 * related to, arising under or in connection with these
 * materials, including for any direct, or any indirect,
 * special, incidental, or consequential loss or damage
 * (including loss of data, profits, goodwill, or any type of
 * loss or damage suffered as a result of any action brought
 * by a third party) even if such damage or loss was
 * reasonably foreseeable or Xilinx had been advised of the
 * possibility of the same.
 *
 * CRITICAL APPLICATIONS
 * Xilinx products are not designed or intended to be fail-
 * safe, or for use in any application requiring fail-safe
 * performance, such as life-support or safety devices or
 * systems, Class III medical devices, nuclear facilities,
 * applications related to the deployment of airbags, or any
 * other applications that could lead to death, personal
 * injury, or severe property or environmental damage
 * (individually and collectively, "Critical
 * Applications"). Customer assumes the sole risk and
 * liability of any use of Xilinx products in Critical
 * Applications, subject only to applicable laws and
 * regulations governing limitations on product liability.
 *
 * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
 * PART OF THIS FILE AT ALL TIMES.
 *
 * Naming Convention: <MODULE>_<REGISTER>[_<FIELD>[_<DESC>]]
 *     <MODULE>       Module name (e.g. can or usb)
 *     <REGISTER>     Register within the current module
 *     [_<FIELD>]     Bit field within a register
 *     [_<DESC>]      Type of bit field define:
 *         SHIFT:     Least significant bit for the field
 *         WIDTH:     Size of field in bites
 *         MASK:      A masking over a range of bits or a bit to
 *                    be used for setting or clearing
 *
 */

#ifndef _PMC_GLOBAL_H_
#define _PMC_GLOBAL_H_

#ifdef __cplusplus
extern "C" {
#endif

/**
 * PMC_GLOBAL Base Address
 */
#define PMC_GLOBAL_BASEADDR      0XF1110000

/**
 * Register: PMC_GLOBAL_GLOBAL_CNTRL
 */
#define PMC_GLOBAL_GLOBAL_CNTRL    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000000 )

#define PMC_GLOBAL_GLOBAL_CNTRL_MB_CLK_EN_FORCE_SHIFT   18
#define PMC_GLOBAL_GLOBAL_CNTRL_MB_CLK_EN_FORCE_WIDTH   1
#define PMC_GLOBAL_GLOBAL_CNTRL_MB_CLK_EN_FORCE_MASK    0X00040000

#define PMC_GLOBAL_GLOBAL_CNTRL_MB_DBG_WAKE_SHIFT   17
#define PMC_GLOBAL_GLOBAL_CNTRL_MB_DBG_WAKE_WIDTH   1
#define PMC_GLOBAL_GLOBAL_CNTRL_MB_DBG_WAKE_MASK    0X00020000

#define PMC_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_SHIFT   16
#define PMC_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_WIDTH   1
#define PMC_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_MASK    0X00010000

#define PMC_GLOBAL_GLOBAL_CNTRL_WRITE_QOS_SHIFT   12
#define PMC_GLOBAL_GLOBAL_CNTRL_WRITE_QOS_WIDTH   4
#define PMC_GLOBAL_GLOBAL_CNTRL_WRITE_QOS_MASK    0X0000F000

#define PMC_GLOBAL_GLOBAL_CNTRL_READ_QOS_SHIFT   8
#define PMC_GLOBAL_GLOBAL_CNTRL_READ_QOS_WIDTH   4
#define PMC_GLOBAL_GLOBAL_CNTRL_READ_QOS_MASK    0X00000F00

#define PMC_GLOBAL_GLOBAL_CNTRL_FW_IS_PRESENT_SHIFT   4
#define PMC_GLOBAL_GLOBAL_CNTRL_FW_IS_PRESENT_WIDTH   1
#define PMC_GLOBAL_GLOBAL_CNTRL_FW_IS_PRESENT_MASK    0X00000010

#define PMC_GLOBAL_GLOBAL_CNTRL_COHERENT_SHIFT   2
#define PMC_GLOBAL_GLOBAL_CNTRL_COHERENT_WIDTH   1
#define PMC_GLOBAL_GLOBAL_CNTRL_COHERENT_MASK    0X00000004

#define PMC_GLOBAL_GLOBAL_CNTRL_SLVERR_ENABLE_SHIFT   1
#define PMC_GLOBAL_GLOBAL_CNTRL_SLVERR_ENABLE_WIDTH   1
#define PMC_GLOBAL_GLOBAL_CNTRL_SLVERR_ENABLE_MASK    0X00000002

#define PMC_GLOBAL_GLOBAL_CNTRL_DONT_SLEEP_SHIFT   0
#define PMC_GLOBAL_GLOBAL_CNTRL_DONT_SLEEP_WIDTH   1
#define PMC_GLOBAL_GLOBAL_CNTRL_DONT_SLEEP_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_MULTI_BOOT
 */
#define PMC_GLOBAL_PMC_MULTI_BOOT    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000004 )

#define PMC_GLOBAL_PMC_MULTI_BOOT_VALUE_SHIFT   0
#define PMC_GLOBAL_PMC_MULTI_BOOT_VALUE_WIDTH   32
#define PMC_GLOBAL_PMC_MULTI_BOOT_VALUE_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PPU1_TRM_CTRL
 */
#define PMC_GLOBAL_PPU1_TRM_CTRL    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000008 )

#define PMC_GLOBAL_PPU1_TRM_CTRL_EN_LMB_UE_FATAL_SHIFT   0
#define PMC_GLOBAL_PPU1_TRM_CTRL_EN_LMB_UE_FATAL_WIDTH   1
#define PMC_GLOBAL_PPU1_TRM_CTRL_EN_LMB_UE_FATAL_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_MEM_CNTRL
 */
#define PMC_GLOBAL_MEM_CNTRL    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000000C )

#define PMC_GLOBAL_MEM_CNTRL_PPU0_ROM_KEN_SHIFT   21
#define PMC_GLOBAL_MEM_CNTRL_PPU0_ROM_KEN_WIDTH   1
#define PMC_GLOBAL_MEM_CNTRL_PPU0_ROM_KEN_MASK    0X00200000

#define PMC_GLOBAL_MEM_CNTRL_PPU0_ROM_EMA_SHIFT   18
#define PMC_GLOBAL_MEM_CNTRL_PPU0_ROM_EMA_WIDTH   3
#define PMC_GLOBAL_MEM_CNTRL_PPU0_ROM_EMA_MASK    0X001C0000

#define PMC_GLOBAL_MEM_CNTRL_PPU1_ECC_RAM_EMAS_SHIFT   17
#define PMC_GLOBAL_MEM_CNTRL_PPU1_ECC_RAM_EMAS_WIDTH   1
#define PMC_GLOBAL_MEM_CNTRL_PPU1_ECC_RAM_EMAS_MASK    0X00020000

#define PMC_GLOBAL_MEM_CNTRL_PPU1_ECC_RAM_EMAW_SHIFT   15
#define PMC_GLOBAL_MEM_CNTRL_PPU1_ECC_RAM_EMAW_WIDTH   2
#define PMC_GLOBAL_MEM_CNTRL_PPU1_ECC_RAM_EMAW_MASK    0X00018000

#define PMC_GLOBAL_MEM_CNTRL_PPU1_ECC_RAM_EMA_SHIFT   12
#define PMC_GLOBAL_MEM_CNTRL_PPU1_ECC_RAM_EMA_WIDTH   3
#define PMC_GLOBAL_MEM_CNTRL_PPU1_ECC_RAM_EMA_MASK    0X00007000

#define PMC_GLOBAL_MEM_CNTRL_PPU1_DATA_RAM_EMAS_SHIFT   11
#define PMC_GLOBAL_MEM_CNTRL_PPU1_DATA_RAM_EMAS_WIDTH   1
#define PMC_GLOBAL_MEM_CNTRL_PPU1_DATA_RAM_EMAS_MASK    0X00000800

#define PMC_GLOBAL_MEM_CNTRL_PPU1_DATA_RAM_EMAW_SHIFT   9
#define PMC_GLOBAL_MEM_CNTRL_PPU1_DATA_RAM_EMAW_WIDTH   2
#define PMC_GLOBAL_MEM_CNTRL_PPU1_DATA_RAM_EMAW_MASK    0X00000600

#define PMC_GLOBAL_MEM_CNTRL_PPU1_DATA_RAM_EMA_SHIFT   6
#define PMC_GLOBAL_MEM_CNTRL_PPU1_DATA_RAM_EMA_WIDTH   3
#define PMC_GLOBAL_MEM_CNTRL_PPU1_DATA_RAM_EMA_MASK    0X000001C0

#define PMC_GLOBAL_MEM_CNTRL_PPU0_RAM_EMAS_SHIFT   5
#define PMC_GLOBAL_MEM_CNTRL_PPU0_RAM_EMAS_WIDTH   1
#define PMC_GLOBAL_MEM_CNTRL_PPU0_RAM_EMAS_MASK    0X00000020

#define PMC_GLOBAL_MEM_CNTRL_PPU0_RAM_EMAW_SHIFT   3
#define PMC_GLOBAL_MEM_CNTRL_PPU0_RAM_EMAW_WIDTH   2
#define PMC_GLOBAL_MEM_CNTRL_PPU0_RAM_EMAW_MASK    0X00000018

#define PMC_GLOBAL_MEM_CNTRL_PPU0_RAM_EMA_SHIFT   0
#define PMC_GLOBAL_MEM_CNTRL_PPU0_RAM_EMA_WIDTH   3
#define PMC_GLOBAL_MEM_CNTRL_PPU0_RAM_EMA_MASK    0X00000007

/**
 * Register: PMC_GLOBAL_PMC_GLOBAL_ISR
 */
#define PMC_GLOBAL_PMC_GLOBAL_ISR    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000010 )

#define PMC_GLOBAL_PMC_GLOBAL_ISR_TAMPER_INT_SHIFT   3
#define PMC_GLOBAL_PMC_GLOBAL_ISR_TAMPER_INT_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_ISR_TAMPER_INT_MASK    0X00000008

#define PMC_GLOBAL_PMC_GLOBAL_ISR_PUF_ACC_ERROR_SHIFT   2
#define PMC_GLOBAL_PMC_GLOBAL_ISR_PUF_ACC_ERROR_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_ISR_PUF_ACC_ERROR_MASK    0X00000004

#define PMC_GLOBAL_PMC_GLOBAL_ISR_SSS_CFG_ERR_SHIFT   1
#define PMC_GLOBAL_PMC_GLOBAL_ISR_SSS_CFG_ERR_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_ISR_SSS_CFG_ERR_MASK    0X00000002

#define PMC_GLOBAL_PMC_GLOBAL_ISR_ADDR_ERR_SHIFT   0
#define PMC_GLOBAL_PMC_GLOBAL_ISR_ADDR_ERR_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_ISR_ADDR_ERR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_GLOBAL_IMR
 */
#define PMC_GLOBAL_PMC_GLOBAL_IMR    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000014 )

#define PMC_GLOBAL_PMC_GLOBAL_IMR_TAMPER_INT_SHIFT   3
#define PMC_GLOBAL_PMC_GLOBAL_IMR_TAMPER_INT_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_IMR_TAMPER_INT_MASK    0X00000008

#define PMC_GLOBAL_PMC_GLOBAL_IMR_PUF_ACC_ERROR_SHIFT   2
#define PMC_GLOBAL_PMC_GLOBAL_IMR_PUF_ACC_ERROR_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_IMR_PUF_ACC_ERROR_MASK    0X00000004

#define PMC_GLOBAL_PMC_GLOBAL_IMR_SSS_CFG_ERR_SHIFT   1
#define PMC_GLOBAL_PMC_GLOBAL_IMR_SSS_CFG_ERR_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_IMR_SSS_CFG_ERR_MASK    0X00000002

#define PMC_GLOBAL_PMC_GLOBAL_IMR_ADDR_ERR_SHIFT   0
#define PMC_GLOBAL_PMC_GLOBAL_IMR_ADDR_ERR_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_IMR_ADDR_ERR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_GLOBAL_IER
 */
#define PMC_GLOBAL_PMC_GLOBAL_IER    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000018 )

#define PMC_GLOBAL_PMC_GLOBAL_IER_TAMPER_INT_SHIFT   3
#define PMC_GLOBAL_PMC_GLOBAL_IER_TAMPER_INT_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_IER_TAMPER_INT_MASK    0X00000008

#define PMC_GLOBAL_PMC_GLOBAL_IER_PUF_ACC_ERROR_SHIFT   2
#define PMC_GLOBAL_PMC_GLOBAL_IER_PUF_ACC_ERROR_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_IER_PUF_ACC_ERROR_MASK    0X00000004

#define PMC_GLOBAL_PMC_GLOBAL_IER_SSS_CFG_ERR_SHIFT   1
#define PMC_GLOBAL_PMC_GLOBAL_IER_SSS_CFG_ERR_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_IER_SSS_CFG_ERR_MASK    0X00000002

#define PMC_GLOBAL_PMC_GLOBAL_IER_ADDR_ERR_SHIFT   0
#define PMC_GLOBAL_PMC_GLOBAL_IER_ADDR_ERR_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_IER_ADDR_ERR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_GLOBAL_IDR
 */
#define PMC_GLOBAL_PMC_GLOBAL_IDR    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000001C )

#define PMC_GLOBAL_PMC_GLOBAL_IDR_TAMPER_INT_SHIFT   3
#define PMC_GLOBAL_PMC_GLOBAL_IDR_TAMPER_INT_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_IDR_TAMPER_INT_MASK    0X00000008

#define PMC_GLOBAL_PMC_GLOBAL_IDR_PUF_ACC_ERROR_SHIFT   2
#define PMC_GLOBAL_PMC_GLOBAL_IDR_PUF_ACC_ERROR_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_IDR_PUF_ACC_ERROR_MASK    0X00000004

#define PMC_GLOBAL_PMC_GLOBAL_IDR_SSS_CFG_ERR_SHIFT   1
#define PMC_GLOBAL_PMC_GLOBAL_IDR_SSS_CFG_ERR_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_IDR_SSS_CFG_ERR_MASK    0X00000002

#define PMC_GLOBAL_PMC_GLOBAL_IDR_ADDR_ERR_DIS_SHIFT   0
#define PMC_GLOBAL_PMC_GLOBAL_IDR_ADDR_ERR_DIS_WIDTH   1
#define PMC_GLOBAL_PMC_GLOBAL_IDR_ADDR_ERR_DIS_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PPU1_DEBUG_CTRL
 */
#define PMC_GLOBAL_PPU1_DEBUG_CTRL    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000020 )

#define PMC_GLOBAL_PPU1_DEBUG_CTRL_EN_SHIFT   0
#define PMC_GLOBAL_PPU1_DEBUG_CTRL_EN_WIDTH   1
#define PMC_GLOBAL_PPU1_DEBUG_CTRL_EN_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PPU1_DEBUG_LOCK
 */
#define PMC_GLOBAL_PPU1_DEBUG_LOCK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000024 )

#define PMC_GLOBAL_PPU1_DEBUG_LOCK_DIS_SHIFT   0
#define PMC_GLOBAL_PPU1_DEBUG_LOCK_DIS_WIDTH   1
#define PMC_GLOBAL_PPU1_DEBUG_LOCK_DIS_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GLOBAL_GEN_STORAGE0
 */
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000030 )

#define PMC_GLOBAL_GLOBAL_GEN_STORAGE0_DATA_SHIFT   0
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE0_DATA_WIDTH   32
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE0_DATA_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_GLOBAL_GEN_STORAGE1
 */
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000034 )

#define PMC_GLOBAL_GLOBAL_GEN_STORAGE1_DATA_SHIFT   0
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE1_DATA_WIDTH   32
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE1_DATA_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_GLOBAL_GEN_STORAGE2
 */
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE2    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000038 )

#define PMC_GLOBAL_GLOBAL_GEN_STORAGE2_DATA_SHIFT   0
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE2_DATA_WIDTH   32
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE2_DATA_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_GLOBAL_GEN_STORAGE3
 */
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE3    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000003C )

#define PMC_GLOBAL_GLOBAL_GEN_STORAGE3_DATA_SHIFT   0
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE3_DATA_WIDTH   32
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE3_DATA_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_GLOBAL_GEN_STORAGE4
 */
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE4    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000040 )

#define PMC_GLOBAL_GLOBAL_GEN_STORAGE4_DATA_SHIFT   0
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE4_DATA_WIDTH   32
#define PMC_GLOBAL_GLOBAL_GEN_STORAGE4_DATA_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PERS_GLOB_GEN_STORAGE0
 */
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000050 )

#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE0_DATA_SHIFT   0
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE0_DATA_WIDTH   32
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE0_DATA_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PERS_GLOB_GEN_STORAGE1
 */
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000054 )

#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE1_DATA_SHIFT   0
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE1_DATA_WIDTH   32
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE1_DATA_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PERS_GLOB_GEN_STORAGE2
 */
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE2    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000058 )

#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE2_DATA_SHIFT   0
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE2_DATA_WIDTH   32
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE2_DATA_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PERS_GLOB_GEN_STORAGE3
 */
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE3    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000005C )

#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE3_DATA_SHIFT   0
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE3_DATA_WIDTH   32
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE3_DATA_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PERS_GLOB_GEN_STORAGE4
 */
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE4    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000060 )

#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE4_DATA_SHIFT   0
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE4_DATA_WIDTH   32
#define PMC_GLOBAL_PERS_GLOB_GEN_STORAGE4_DATA_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_GSW_ERR
 */
#define PMC_GLOBAL_PMC_GSW_ERR    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000064 )

#define PMC_GLOBAL_PMC_GSW_ERR_NCR_FLAG_SHIFT   31
#define PMC_GLOBAL_PMC_GSW_ERR_NCR_FLAG_WIDTH   1
#define PMC_GLOBAL_PMC_GSW_ERR_NCR_FLAG_MASK    0X80000000

#define PMC_GLOBAL_PMC_GSW_ERR_CR_FLAG_SHIFT   30
#define PMC_GLOBAL_PMC_GSW_ERR_CR_FLAG_WIDTH   1
#define PMC_GLOBAL_PMC_GSW_ERR_CR_FLAG_MASK    0X40000000

#define PMC_GLOBAL_PMC_GSW_ERR_DATA_SHIFT   0
#define PMC_GLOBAL_PMC_GSW_ERR_DATA_WIDTH   30
#define PMC_GLOBAL_PMC_GSW_ERR_DATA_MASK    0X3FFFFFFF

/**
 * Register: PMC_GLOBAL_PWR_STATUS
 */
#define PMC_GLOBAL_PWR_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000100 )

#define PMC_GLOBAL_PWR_STATUS_VCCAUX_VCCRAM_SHIFT   18
#define PMC_GLOBAL_PWR_STATUS_VCCAUX_VCCRAM_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_VCCAUX_VCCRAM_MASK    0X00040000

#define PMC_GLOBAL_PWR_STATUS_VCCRAM_SOC_SHIFT   17
#define PMC_GLOBAL_PWR_STATUS_VCCRAM_SOC_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_VCCRAM_SOC_MASK    0X00020000

#define PMC_GLOBAL_PWR_STATUS_VCCAUX_SOC_SHIFT   16
#define PMC_GLOBAL_PWR_STATUS_VCCAUX_SOC_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_VCCAUX_SOC_MASK    0X00010000

#define PMC_GLOBAL_PWR_STATUS_PL_SOC_SHIFT   15
#define PMC_GLOBAL_PWR_STATUS_PL_SOC_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_PL_SOC_MASK    0X00008000

#define PMC_GLOBAL_PWR_STATUS_PMC_SOC_SHIFT   14
#define PMC_GLOBAL_PWR_STATUS_PMC_SOC_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_PMC_SOC_MASK    0X00004000

#define PMC_GLOBAL_PWR_STATUS_PMC_SOC_NPI_SHIFT   13
#define PMC_GLOBAL_PWR_STATUS_PMC_SOC_NPI_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_PMC_SOC_NPI_MASK    0X00002000

#define PMC_GLOBAL_PWR_STATUS_PMC_PL_SHIFT   12
#define PMC_GLOBAL_PWR_STATUS_PMC_PL_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_PMC_PL_MASK    0X00001000

#define PMC_GLOBAL_PWR_STATUS_PMC_PL_TEST_SHIFT   11
#define PMC_GLOBAL_PWR_STATUS_PMC_PL_TEST_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_PMC_PL_TEST_MASK    0X00000800

#define PMC_GLOBAL_PWR_STATUS_PMC_PL_CFRAME_SHIFT   10
#define PMC_GLOBAL_PWR_STATUS_PMC_PL_CFRAME_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_PMC_PL_CFRAME_MASK    0X00000400

#define PMC_GLOBAL_PWR_STATUS_PMC_LPD_SHIFT   9
#define PMC_GLOBAL_PWR_STATUS_PMC_LPD_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_PMC_LPD_MASK    0X00000200

#define PMC_GLOBAL_PWR_STATUS_PMC_LPD_DFX_SHIFT   8
#define PMC_GLOBAL_PWR_STATUS_PMC_LPD_DFX_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_PMC_LPD_DFX_MASK    0X00000100

#define PMC_GLOBAL_PWR_STATUS_LPD_SOC_SHIFT   7
#define PMC_GLOBAL_PWR_STATUS_LPD_SOC_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_LPD_SOC_MASK    0X00000080

#define PMC_GLOBAL_PWR_STATUS_LPD_PL_SHIFT   6
#define PMC_GLOBAL_PWR_STATUS_LPD_PL_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_LPD_PL_MASK    0X00000040

#define PMC_GLOBAL_PWR_STATUS_LPD_PL_TEST_SHIFT   5
#define PMC_GLOBAL_PWR_STATUS_LPD_PL_TEST_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_LPD_PL_TEST_MASK    0X00000020

#define PMC_GLOBAL_PWR_STATUS_LPD_CPM_SHIFT   4
#define PMC_GLOBAL_PWR_STATUS_LPD_CPM_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_LPD_CPM_MASK    0X00000010

#define PMC_GLOBAL_PWR_STATUS_LPD_CPM_DFX_SHIFT   3
#define PMC_GLOBAL_PWR_STATUS_LPD_CPM_DFX_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_LPD_CPM_DFX_MASK    0X00000008

#define PMC_GLOBAL_PWR_STATUS_FPD_SOC_SHIFT   2
#define PMC_GLOBAL_PWR_STATUS_FPD_SOC_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_FPD_SOC_MASK    0X00000004

#define PMC_GLOBAL_PWR_STATUS_FPD_PL_SHIFT   1
#define PMC_GLOBAL_PWR_STATUS_FPD_PL_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_FPD_PL_MASK    0X00000002

#define PMC_GLOBAL_PWR_STATUS_FPD_PL_TEST_SHIFT   0
#define PMC_GLOBAL_PWR_STATUS_FPD_PL_TEST_WIDTH   1
#define PMC_GLOBAL_PWR_STATUS_FPD_PL_TEST_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PWR_SUPPLY_STATUS
 */
#define PMC_GLOBAL_PWR_SUPPLY_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000010C )

#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_RAM_SHIFT   7
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_RAM_WIDTH   1
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_RAM_MASK    0X00000080

#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_PL_SHIFT   6
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_PL_WIDTH   1
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_PL_MASK    0X00000040

#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCAUX_SHIFT   5
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCAUX_WIDTH   1
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCAUX_MASK    0X00000020

#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_SOC_SHIFT   4
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_SOC_WIDTH   1
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_SOC_MASK    0X00000010

#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_LPD_SHIFT   3
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_LPD_WIDTH   1
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_LPD_MASK    0X00000008

#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_FPD_SHIFT   2
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_FPD_WIDTH   1
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_FPD_MASK    0X00000004

#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_PMC_SHIFT   1
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_PMC_WIDTH   1
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCINT_PMC_MASK    0X00000002

#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCAUX_PMC_SHIFT   0
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCAUX_PMC_WIDTH   1
#define PMC_GLOBAL_PWR_SUPPLY_STATUS_VCCAUX_PMC_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_PWRUP_STATUS
 */
#define PMC_GLOBAL_REQ_PWRUP_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000110 )

#define PMC_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT   2
#define PMC_GLOBAL_REQ_PWRUP_STATUS_PL_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_STATUS_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_PWRUP_STATUS_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_PWRUP_STATUS_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_STATUS_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_PWRUP_STATUS_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_PWRUP_STATUS_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_STATUS_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_PWRUP_INT_MASK
 */
#define PMC_GLOBAL_REQ_PWRUP_INT_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000114 )

#define PMC_GLOBAL_REQ_PWRUP_INT_MASK_PL_SHIFT   2
#define PMC_GLOBAL_REQ_PWRUP_INT_MASK_PL_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_INT_MASK_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_PWRUP_INT_MASK_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_PWRUP_INT_MASK_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_INT_MASK_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_PWRUP_INT_MASK_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_PWRUP_INT_MASK_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_INT_MASK_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_PWRUP_INT_EN
 */
#define PMC_GLOBAL_REQ_PWRUP_INT_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000118 )

#define PMC_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT   2
#define PMC_GLOBAL_REQ_PWRUP_INT_EN_PL_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_PWRUP_INT_EN_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_PWRUP_INT_EN_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_INT_EN_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_PWRUP_INT_EN_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_PWRUP_INT_EN_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_INT_EN_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_PWRUP_INT_DIS
 */
#define PMC_GLOBAL_REQ_PWRUP_INT_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000011C )

#define PMC_GLOBAL_REQ_PWRUP_INT_DIS_PL_SHIFT   2
#define PMC_GLOBAL_REQ_PWRUP_INT_DIS_PL_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_INT_DIS_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_PWRUP_INT_DIS_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_PWRUP_INT_DIS_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_INT_DIS_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_PWRUP_INT_DIS_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_PWRUP_INT_DIS_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_INT_DIS_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_PWRUP_TRIG
 */
#define PMC_GLOBAL_REQ_PWRUP_TRIG    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000120 )

#define PMC_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT   2
#define PMC_GLOBAL_REQ_PWRUP_TRIG_PL_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_TRIG_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_PWRUP_TRIG_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_PWRUP_TRIG_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_TRIG_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_PWRUP_TRIG_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_PWRUP_TRIG_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_PWRUP_TRIG_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_PWRDWN_STATUS
 */
#define PMC_GLOBAL_REQ_PWRDWN_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000210 )

#define PMC_GLOBAL_REQ_PWRDWN_STATUS_PL_SHIFT   2
#define PMC_GLOBAL_REQ_PWRDWN_STATUS_PL_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_STATUS_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_PWRDWN_STATUS_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_PWRDWN_STATUS_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_STATUS_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_PWRDWN_STATUS_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_PWRDWN_STATUS_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_STATUS_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_PWRDWN_INT_MASK
 */
#define PMC_GLOBAL_REQ_PWRDWN_INT_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000214 )

#define PMC_GLOBAL_REQ_PWRDWN_INT_MASK_PL_SHIFT   2
#define PMC_GLOBAL_REQ_PWRDWN_INT_MASK_PL_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_INT_MASK_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_PWRDWN_INT_MASK_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_PWRDWN_INT_MASK_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_INT_MASK_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_PWRDWN_INT_MASK_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_PWRDWN_INT_MASK_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_INT_MASK_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_PWRDWN_INT_EN
 */
#define PMC_GLOBAL_REQ_PWRDWN_INT_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000218 )

#define PMC_GLOBAL_REQ_PWRDWN_INT_EN_PL_SHIFT   2
#define PMC_GLOBAL_REQ_PWRDWN_INT_EN_PL_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_INT_EN_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_PWRDWN_INT_EN_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_PWRDWN_INT_EN_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_INT_EN_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_PWRDWN_INT_EN_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_PWRDWN_INT_EN_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_INT_EN_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_PWRDWN_INT_DIS
 */
#define PMC_GLOBAL_REQ_PWRDWN_INT_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000021C )

#define PMC_GLOBAL_REQ_PWRDWN_INT_DIS_PL_SHIFT   2
#define PMC_GLOBAL_REQ_PWRDWN_INT_DIS_PL_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_INT_DIS_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_PWRDWN_INT_DIS_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_PWRDWN_INT_DIS_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_INT_DIS_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_PWRDWN_INT_DIS_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_PWRDWN_INT_DIS_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_INT_DIS_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_PWRDWN_TRIG
 */
#define PMC_GLOBAL_REQ_PWRDWN_TRIG    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000220 )

#define PMC_GLOBAL_REQ_PWRDWN_TRIG_PL_SHIFT   2
#define PMC_GLOBAL_REQ_PWRDWN_TRIG_PL_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_TRIG_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_PWRDWN_TRIG_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_PWRDWN_TRIG_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_TRIG_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_PWRDWN_TRIG_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_PWRDWN_TRIG_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_PWRDWN_TRIG_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_ISO_STATUS
 */
#define PMC_GLOBAL_REQ_ISO_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000310 )

#define PMC_GLOBAL_REQ_ISO_STATUS_PL_SHIFT   2
#define PMC_GLOBAL_REQ_ISO_STATUS_PL_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_STATUS_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_ISO_STATUS_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_ISO_STATUS_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_STATUS_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_ISO_STATUS_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_ISO_STATUS_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_STATUS_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_ISO_INT_MASK
 */
#define PMC_GLOBAL_REQ_ISO_INT_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000314 )

#define PMC_GLOBAL_REQ_ISO_INT_MASK_PL_SHIFT   2
#define PMC_GLOBAL_REQ_ISO_INT_MASK_PL_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_INT_MASK_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_ISO_INT_MASK_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_ISO_INT_MASK_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_INT_MASK_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_ISO_INT_MASK_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_ISO_INT_MASK_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_INT_MASK_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_ISO_INT_EN
 */
#define PMC_GLOBAL_REQ_ISO_INT_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000318 )

#define PMC_GLOBAL_REQ_ISO_INT_EN_PL_SHIFT   2
#define PMC_GLOBAL_REQ_ISO_INT_EN_PL_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_INT_EN_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_ISO_INT_EN_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_ISO_INT_EN_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_INT_EN_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_ISO_INT_EN_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_ISO_INT_EN_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_INT_EN_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_ISO_INT_DIS
 */
#define PMC_GLOBAL_REQ_ISO_INT_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000031C )

#define PMC_GLOBAL_REQ_ISO_INT_DIS_PL_SHIFT   2
#define PMC_GLOBAL_REQ_ISO_INT_DIS_PL_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_INT_DIS_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_ISO_INT_DIS_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_ISO_INT_DIS_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_INT_DIS_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_ISO_INT_DIS_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_ISO_INT_DIS_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_INT_DIS_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_ISO_TRIG
 */
#define PMC_GLOBAL_REQ_ISO_TRIG    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000320 )

#define PMC_GLOBAL_REQ_ISO_TRIG_PL_SHIFT   2
#define PMC_GLOBAL_REQ_ISO_TRIG_PL_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_TRIG_PL_MASK    0X00000004

#define PMC_GLOBAL_REQ_ISO_TRIG_SOC_SHIFT   1
#define PMC_GLOBAL_REQ_ISO_TRIG_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_TRIG_SOC_MASK    0X00000002

#define PMC_GLOBAL_REQ_ISO_TRIG_LPD_SHIFT   0
#define PMC_GLOBAL_REQ_ISO_TRIG_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_ISO_TRIG_LPD_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_DDR_RETENTION
 */
#define PMC_GLOBAL_DDR_RETENTION    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000324 )

#define PMC_GLOBAL_DDR_RETENTION_VALUE_SHIFT   0
#define PMC_GLOBAL_DDR_RETENTION_VALUE_WIDTH   1
#define PMC_GLOBAL_DDR_RETENTION_VALUE_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_USR_GTS
 */
#define PMC_GLOBAL_USR_GTS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000328 )

#define PMC_GLOBAL_USR_GTS_USR_GTS_SHIFT   0
#define PMC_GLOBAL_USR_GTS_USR_GTS_WIDTH   1
#define PMC_GLOBAL_USR_GTS_USR_GTS_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_SWRST_STATUS
 */
#define PMC_GLOBAL_REQ_SWRST_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000410 )

#define PMC_GLOBAL_REQ_SWRST_STATUS_PL_SHIFT   3
#define PMC_GLOBAL_REQ_SWRST_STATUS_PL_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_STATUS_PL_MASK    0X00000008

#define PMC_GLOBAL_REQ_SWRST_STATUS_SOC_SHIFT   2
#define PMC_GLOBAL_REQ_SWRST_STATUS_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_STATUS_SOC_MASK    0X00000004

#define PMC_GLOBAL_REQ_SWRST_STATUS_LPD_SHIFT   1
#define PMC_GLOBAL_REQ_SWRST_STATUS_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_STATUS_LPD_MASK    0X00000002

#define PMC_GLOBAL_REQ_SWRST_STATUS_PS_ONLY_SHIFT   0
#define PMC_GLOBAL_REQ_SWRST_STATUS_PS_ONLY_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_STATUS_PS_ONLY_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_SWRST_INT_MASK
 */
#define PMC_GLOBAL_REQ_SWRST_INT_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000414 )

#define PMC_GLOBAL_REQ_SWRST_INT_MASK_PL_SHIFT   3
#define PMC_GLOBAL_REQ_SWRST_INT_MASK_PL_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_INT_MASK_PL_MASK    0X00000008

#define PMC_GLOBAL_REQ_SWRST_INT_MASK_SOC_SHIFT   2
#define PMC_GLOBAL_REQ_SWRST_INT_MASK_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_INT_MASK_SOC_MASK    0X00000004

#define PMC_GLOBAL_REQ_SWRST_INT_MASK_LPD_SHIFT   1
#define PMC_GLOBAL_REQ_SWRST_INT_MASK_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_INT_MASK_LPD_MASK    0X00000002

#define PMC_GLOBAL_REQ_SWRST_INT_MASK_PS_ONLY_SHIFT   0
#define PMC_GLOBAL_REQ_SWRST_INT_MASK_PS_ONLY_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_INT_MASK_PS_ONLY_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_SWRST_INT_EN
 */
#define PMC_GLOBAL_REQ_SWRST_INT_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000418 )

#define PMC_GLOBAL_REQ_SWRST_INT_EN_PL_SHIFT   3
#define PMC_GLOBAL_REQ_SWRST_INT_EN_PL_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_INT_EN_PL_MASK    0X00000008

#define PMC_GLOBAL_REQ_SWRST_INT_EN_SOC_SHIFT   2
#define PMC_GLOBAL_REQ_SWRST_INT_EN_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_INT_EN_SOC_MASK    0X00000004

#define PMC_GLOBAL_REQ_SWRST_INT_EN_LPD_SHIFT   1
#define PMC_GLOBAL_REQ_SWRST_INT_EN_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_INT_EN_LPD_MASK    0X00000002

#define PMC_GLOBAL_REQ_SWRST_INT_EN_PS_ONLY_SHIFT   0
#define PMC_GLOBAL_REQ_SWRST_INT_EN_PS_ONLY_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_INT_EN_PS_ONLY_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_SWRST_INT_DIS
 */
#define PMC_GLOBAL_REQ_SWRST_INT_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000041C )

#define PMC_GLOBAL_REQ_SWRST_INT_DIS_PL_SHIFT   3
#define PMC_GLOBAL_REQ_SWRST_INT_DIS_PL_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_INT_DIS_PL_MASK    0X00000008

#define PMC_GLOBAL_REQ_SWRST_INT_DIS_SOC_SHIFT   2
#define PMC_GLOBAL_REQ_SWRST_INT_DIS_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_INT_DIS_SOC_MASK    0X00000004

#define PMC_GLOBAL_REQ_SWRST_INT_DIS_LPD_SHIFT   1
#define PMC_GLOBAL_REQ_SWRST_INT_DIS_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_INT_DIS_LPD_MASK    0X00000002

#define PMC_GLOBAL_REQ_SWRST_INT_DIS_PS_ONLY_SHIFT   0
#define PMC_GLOBAL_REQ_SWRST_INT_DIS_PS_ONLY_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_INT_DIS_PS_ONLY_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_REQ_SWRST_TRIG
 */
#define PMC_GLOBAL_REQ_SWRST_TRIG    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000420 )

#define PMC_GLOBAL_REQ_SWRST_TRIG_PL_SHIFT   3
#define PMC_GLOBAL_REQ_SWRST_TRIG_PL_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_TRIG_PL_MASK    0X00000008

#define PMC_GLOBAL_REQ_SWRST_TRIG_SOC_SHIFT   2
#define PMC_GLOBAL_REQ_SWRST_TRIG_SOC_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_TRIG_SOC_MASK    0X00000004

#define PMC_GLOBAL_REQ_SWRST_TRIG_LPD_SHIFT   1
#define PMC_GLOBAL_REQ_SWRST_TRIG_LPD_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_TRIG_LPD_MASK    0X00000002

#define PMC_GLOBAL_REQ_SWRST_TRIG_PS_ONLY_SHIFT   0
#define PMC_GLOBAL_REQ_SWRST_TRIG_PS_ONLY_WIDTH   1
#define PMC_GLOBAL_REQ_SWRST_TRIG_PS_ONLY_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_WAKEUP_IRQ_STATUS
 */
#define PMC_GLOBAL_WAKEUP_IRQ_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000430 )

#define PMC_GLOBAL_WAKEUP_IRQ_STATUS_CPM_CORESIGHT_SHIFT   1
#define PMC_GLOBAL_WAKEUP_IRQ_STATUS_CPM_CORESIGHT_WIDTH   1
#define PMC_GLOBAL_WAKEUP_IRQ_STATUS_CPM_CORESIGHT_MASK    0X00000002

#define PMC_GLOBAL_WAKEUP_IRQ_STATUS_LPD_CORESIGHT_SHIFT   0
#define PMC_GLOBAL_WAKEUP_IRQ_STATUS_LPD_CORESIGHT_WIDTH   1
#define PMC_GLOBAL_WAKEUP_IRQ_STATUS_LPD_CORESIGHT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_WAKEUP_IRQ_MASK
 */
#define PMC_GLOBAL_WAKEUP_IRQ_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000434 )

#define PMC_GLOBAL_WAKEUP_IRQ_MASK_CPM_CORESIGHT_SHIFT   1
#define PMC_GLOBAL_WAKEUP_IRQ_MASK_CPM_CORESIGHT_WIDTH   1
#define PMC_GLOBAL_WAKEUP_IRQ_MASK_CPM_CORESIGHT_MASK    0X00000002

#define PMC_GLOBAL_WAKEUP_IRQ_MASK_LPD_CORESIGHT_SHIFT   0
#define PMC_GLOBAL_WAKEUP_IRQ_MASK_LPD_CORESIGHT_WIDTH   1
#define PMC_GLOBAL_WAKEUP_IRQ_MASK_LPD_CORESIGHT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_WAKEUP_IRQ_EN
 */
#define PMC_GLOBAL_WAKEUP_IRQ_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000438 )

#define PMC_GLOBAL_WAKEUP_IRQ_EN_CPM_CORESIGHT_SHIFT   1
#define PMC_GLOBAL_WAKEUP_IRQ_EN_CPM_CORESIGHT_WIDTH   1
#define PMC_GLOBAL_WAKEUP_IRQ_EN_CPM_CORESIGHT_MASK    0X00000002

#define PMC_GLOBAL_WAKEUP_IRQ_EN_LPD_CORESIGHT_SHIFT   0
#define PMC_GLOBAL_WAKEUP_IRQ_EN_LPD_CORESIGHT_WIDTH   1
#define PMC_GLOBAL_WAKEUP_IRQ_EN_LPD_CORESIGHT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_WAKEUP_IRQ_DIS
 */
#define PMC_GLOBAL_WAKEUP_IRQ_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000043C )

#define PMC_GLOBAL_WAKEUP_IRQ_DIS_CPM_CORESIGHT_SHIFT   1
#define PMC_GLOBAL_WAKEUP_IRQ_DIS_CPM_CORESIGHT_WIDTH   1
#define PMC_GLOBAL_WAKEUP_IRQ_DIS_CPM_CORESIGHT_MASK    0X00000002

#define PMC_GLOBAL_WAKEUP_IRQ_DIS_LPD_CORESIGHT_SHIFT   0
#define PMC_GLOBAL_WAKEUP_IRQ_DIS_LPD_CORESIGHT_WIDTH   1
#define PMC_GLOBAL_WAKEUP_IRQ_DIS_LPD_CORESIGHT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_WAKEUP_IRQ_TRIG
 */
#define PMC_GLOBAL_WAKEUP_IRQ_TRIG    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000440 )

#define PMC_GLOBAL_WAKEUP_IRQ_TRIG_CPM_CORESIGHT_SHIFT   1
#define PMC_GLOBAL_WAKEUP_IRQ_TRIG_CPM_CORESIGHT_WIDTH   1
#define PMC_GLOBAL_WAKEUP_IRQ_TRIG_CPM_CORESIGHT_MASK    0X00000002

#define PMC_GLOBAL_WAKEUP_IRQ_TRIG_LPD_CORESIGHT_SHIFT   0
#define PMC_GLOBAL_WAKEUP_IRQ_TRIG_LPD_CORESIGHT_WIDTH   1
#define PMC_GLOBAL_WAKEUP_IRQ_TRIG_LPD_CORESIGHT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_DBG_PWR_ACK
 */
#define PMC_GLOBAL_DBG_PWR_ACK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000444 )

#define PMC_GLOBAL_DBG_PWR_ACK_CPM_CORESIGHT_SHIFT   1
#define PMC_GLOBAL_DBG_PWR_ACK_CPM_CORESIGHT_WIDTH   1
#define PMC_GLOBAL_DBG_PWR_ACK_CPM_CORESIGHT_MASK    0X00000002

#define PMC_GLOBAL_DBG_PWR_ACK_LPD_CORESIGHT_SHIFT   0
#define PMC_GLOBAL_DBG_PWR_ACK_LPD_CORESIGHT_WIDTH   1
#define PMC_GLOBAL_DBG_PWR_ACK_LPD_CORESIGHT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_SSS_CFG
 */
#define PMC_GLOBAL_PMC_SSS_CFG    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000500 )

#define PMC_GLOBAL_PMC_SSS_CFG_SBI_CFG_SHIFT   20
#define PMC_GLOBAL_PMC_SSS_CFG_SBI_CFG_WIDTH   4
#define PMC_GLOBAL_PMC_SSS_CFG_SBI_CFG_MASK    0X00F00000

#define PMC_GLOBAL_PMC_SSS_CFG_SHA_CFG_SHIFT   16
#define PMC_GLOBAL_PMC_SSS_CFG_SHA_CFG_WIDTH   4
#define PMC_GLOBAL_PMC_SSS_CFG_SHA_CFG_MASK    0X000F0000

#define PMC_GLOBAL_PMC_SSS_CFG_AES_CFG_SHIFT   12
#define PMC_GLOBAL_PMC_SSS_CFG_AES_CFG_WIDTH   4
#define PMC_GLOBAL_PMC_SSS_CFG_AES_CFG_MASK    0X0000F000

#define PMC_GLOBAL_PMC_SSS_CFG_PTPI_CFG_SHIFT   8
#define PMC_GLOBAL_PMC_SSS_CFG_PTPI_CFG_WIDTH   4
#define PMC_GLOBAL_PMC_SSS_CFG_PTPI_CFG_MASK    0X00000F00

#define PMC_GLOBAL_PMC_SSS_CFG_DMA1_CFG_SHIFT   4
#define PMC_GLOBAL_PMC_SSS_CFG_DMA1_CFG_WIDTH   4
#define PMC_GLOBAL_PMC_SSS_CFG_DMA1_CFG_MASK    0X000000F0

#define PMC_GLOBAL_PMC_SSS_CFG_DMA0_CFG_SHIFT   0
#define PMC_GLOBAL_PMC_SSS_CFG_DMA0_CFG_WIDTH   4
#define PMC_GLOBAL_PMC_SSS_CFG_DMA0_CFG_MASK    0X0000000F

/**
 * Register: PMC_GLOBAL_TEST_PATTERN_CFG
 */
#define PMC_GLOBAL_TEST_PATTERN_CFG    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000514 )

#define PMC_GLOBAL_TEST_PATTERN_CFG_VALUE_SHIFT   0
#define PMC_GLOBAL_TEST_PATTERN_CFG_VALUE_WIDTH   2
#define PMC_GLOBAL_TEST_PATTERN_CFG_VALUE_MASK    0X00000003

/**
 * Register: PMC_GLOBAL_PRAM_ZEROIZE_SIZE
 */
#define PMC_GLOBAL_PRAM_ZEROIZE_SIZE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000518 )

#define PMC_GLOBAL_PRAM_ZEROIZE_SIZE_VALUE_SHIFT   0
#define PMC_GLOBAL_PRAM_ZEROIZE_SIZE_VALUE_WIDTH   32
#define PMC_GLOBAL_PRAM_ZEROIZE_SIZE_VALUE_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_0
 */
#define PMC_GLOBAL_TAMPER_RESP_0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000530 )

#define PMC_GLOBAL_TAMPER_RESP_0_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_0_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_0_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_0_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_0_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_0_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_0_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_0_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_0_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_0_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_0_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_0_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_0_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_0_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_0_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_1
 */
#define PMC_GLOBAL_TAMPER_RESP_1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000534 )

#define PMC_GLOBAL_TAMPER_RESP_1_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_1_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_1_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_1_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_1_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_1_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_1_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_1_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_1_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_1_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_1_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_1_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_1_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_1_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_1_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_2
 */
#define PMC_GLOBAL_TAMPER_RESP_2    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000538 )

#define PMC_GLOBAL_TAMPER_RESP_2_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_2_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_2_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_2_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_2_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_2_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_2_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_2_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_2_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_2_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_2_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_2_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_2_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_2_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_2_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_3
 */
#define PMC_GLOBAL_TAMPER_RESP_3    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000053C )

#define PMC_GLOBAL_TAMPER_RESP_3_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_3_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_3_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_3_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_3_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_3_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_3_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_3_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_3_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_3_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_3_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_3_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_3_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_3_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_3_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_4
 */
#define PMC_GLOBAL_TAMPER_RESP_4    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000540 )

#define PMC_GLOBAL_TAMPER_RESP_4_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_4_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_4_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_4_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_4_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_4_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_4_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_4_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_4_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_4_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_4_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_4_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_4_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_4_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_4_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_5
 */
#define PMC_GLOBAL_TAMPER_RESP_5    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000544 )

#define PMC_GLOBAL_TAMPER_RESP_5_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_5_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_5_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_5_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_5_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_5_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_5_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_5_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_5_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_5_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_5_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_5_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_5_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_5_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_5_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_6
 */
#define PMC_GLOBAL_TAMPER_RESP_6    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000548 )

#define PMC_GLOBAL_TAMPER_RESP_6_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_6_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_6_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_6_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_6_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_6_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_6_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_6_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_6_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_6_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_6_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_6_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_6_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_6_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_6_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_7
 */
#define PMC_GLOBAL_TAMPER_RESP_7    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000054C )

#define PMC_GLOBAL_TAMPER_RESP_7_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_7_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_7_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_7_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_7_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_7_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_7_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_7_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_7_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_7_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_7_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_7_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_7_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_7_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_7_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_8
 */
#define PMC_GLOBAL_TAMPER_RESP_8    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000550 )

#define PMC_GLOBAL_TAMPER_RESP_8_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_8_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_8_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_8_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_8_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_8_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_8_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_8_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_8_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_8_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_8_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_8_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_8_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_8_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_8_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_9
 */
#define PMC_GLOBAL_TAMPER_RESP_9    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000554 )

#define PMC_GLOBAL_TAMPER_RESP_9_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_9_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_9_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_9_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_9_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_9_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_9_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_9_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_9_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_9_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_9_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_9_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_9_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_9_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_9_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_10
 */
#define PMC_GLOBAL_TAMPER_RESP_10    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000558 )

#define PMC_GLOBAL_TAMPER_RESP_10_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_10_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_10_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_10_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_10_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_10_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_10_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_10_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_10_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_10_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_10_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_10_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_10_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_10_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_10_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_11
 */
#define PMC_GLOBAL_TAMPER_RESP_11    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000055C )

#define PMC_GLOBAL_TAMPER_RESP_11_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_11_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_11_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_11_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_11_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_11_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_11_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_11_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_11_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_11_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_11_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_11_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_11_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_11_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_11_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_12
 */
#define PMC_GLOBAL_TAMPER_RESP_12    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000560 )

#define PMC_GLOBAL_TAMPER_RESP_12_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_12_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_12_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_12_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_12_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_12_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_12_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_12_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_12_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_12_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_12_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_12_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_12_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_12_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_12_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_RESP_13
 */
#define PMC_GLOBAL_TAMPER_RESP_13    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000564 )

#define PMC_GLOBAL_TAMPER_RESP_13_BBRAM_ERASE_SHIFT   4
#define PMC_GLOBAL_TAMPER_RESP_13_BBRAM_ERASE_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_13_BBRAM_ERASE_MASK    0X00000010

#define PMC_GLOBAL_TAMPER_RESP_13_SYS_LOCKDOWN_1_SHIFT   3
#define PMC_GLOBAL_TAMPER_RESP_13_SYS_LOCKDOWN_1_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_13_SYS_LOCKDOWN_1_MASK    0X00000008

#define PMC_GLOBAL_TAMPER_RESP_13_SYS_LOCKDOWN_0_SHIFT   2
#define PMC_GLOBAL_TAMPER_RESP_13_SYS_LOCKDOWN_0_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_13_SYS_LOCKDOWN_0_MASK    0X00000004

#define PMC_GLOBAL_TAMPER_RESP_13_SYS_RESET_SHIFT   1
#define PMC_GLOBAL_TAMPER_RESP_13_SYS_RESET_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_13_SYS_RESET_MASK    0X00000002

#define PMC_GLOBAL_TAMPER_RESP_13_SYS_INTERRUPT_SHIFT   0
#define PMC_GLOBAL_TAMPER_RESP_13_SYS_INTERRUPT_WIDTH   1
#define PMC_GLOBAL_TAMPER_RESP_13_SYS_INTERRUPT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_TAMPER_TRIG
 */
#define PMC_GLOBAL_TAMPER_TRIG    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000570 )

#define PMC_GLOBAL_TAMPER_TRIG_TAMPER_SHIFT   0
#define PMC_GLOBAL_TAMPER_TRIG_TAMPER_WIDTH   1
#define PMC_GLOBAL_TAMPER_TRIG_TAMPER_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PPU0_MB_FATAL
 */
#define PMC_GLOBAL_PPU0_MB_FATAL    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000600 )

#define PMC_GLOBAL_PPU0_MB_FATAL_CPU3_SHIFT   2
#define PMC_GLOBAL_PPU0_MB_FATAL_CPU3_WIDTH   1
#define PMC_GLOBAL_PPU0_MB_FATAL_CPU3_MASK    0X00000004

#define PMC_GLOBAL_PPU0_MB_FATAL_CPU2_SHIFT   1
#define PMC_GLOBAL_PPU0_MB_FATAL_CPU2_WIDTH   1
#define PMC_GLOBAL_PPU0_MB_FATAL_CPU2_MASK    0X00000002

#define PMC_GLOBAL_PPU0_MB_FATAL_CPU1_SHIFT   0
#define PMC_GLOBAL_PPU0_MB_FATAL_CPU1_WIDTH   1
#define PMC_GLOBAL_PPU0_MB_FATAL_CPU1_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PPU0_MB1_FT_STATUS
 */
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000604 )

#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_CPU3_SHIFT   14
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_CPU3_WIDTH   1
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_CPU3_MASK    0X00004000

#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_CPU2_SHIFT   13
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_CPU2_WIDTH   1
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_CPU2_MASK    0X00002000

#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_CPU1_SHIFT   12
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_CPU1_WIDTH   1
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_CPU1_MASK    0X00001000

#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_FT_STATE_SHIFT   10
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_FT_STATE_WIDTH   2
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_FT_STATE_MASK    0X00000C00

#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_WDT_EXP_SHIFT   9
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_WDT_EXP_WIDTH   1
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_WDT_EXP_MASK    0X00000200

#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_UNCORR_ERR_SHIFT   8
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_UNCORR_ERR_WIDTH   1
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_UNCORR_ERR_MASK    0X00000100

#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_VOTER_ERR_SHIFT   7
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_VOTER_ERR_WIDTH   1
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_VOTER_ERR_MASK    0X00000080

#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_FTL_MISMATCH_SHIFT   4
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_FTL_MISMATCH_WIDTH   3
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_FTL_MISMATCH_MASK    0X00000070

#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_LS_RECOVER_SHIFT   3
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_LS_RECOVER_WIDTH   1
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_LS_RECOVER_MASK    0X00000008

#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_LS_MISMATCH_SHIFT   0
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_LS_MISMATCH_WIDTH   3
#define PMC_GLOBAL_PPU0_MB1_FT_STATUS_LS_MISMATCH_MASK    0X00000007

/**
 * Register: PMC_GLOBAL_PPU0_MB2_FT_STATUS
 */
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000608 )

#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_CPU3_SHIFT   14
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_CPU3_WIDTH   1
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_CPU3_MASK    0X00004000

#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_CPU2_SHIFT   13
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_CPU2_WIDTH   1
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_CPU2_MASK    0X00002000

#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_CPU1_SHIFT   12
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_CPU1_WIDTH   1
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_CPU1_MASK    0X00001000

#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_FT_STATE_SHIFT   10
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_FT_STATE_WIDTH   2
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_FT_STATE_MASK    0X00000C00

#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_WDT_EXP_SHIFT   9
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_WDT_EXP_WIDTH   1
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_WDT_EXP_MASK    0X00000200

#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_UNCORR_ERR_SHIFT   8
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_UNCORR_ERR_WIDTH   1
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_UNCORR_ERR_MASK    0X00000100

#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_VOTER_ERR_SHIFT   7
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_VOTER_ERR_WIDTH   1
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_VOTER_ERR_MASK    0X00000080

#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_FTL_MISMATCH_SHIFT   4
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_FTL_MISMATCH_WIDTH   3
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_FTL_MISMATCH_MASK    0X00000070

#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_LS_RECOVER_SHIFT   3
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_LS_RECOVER_WIDTH   1
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_LS_RECOVER_MASK    0X00000008

#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_LS_MISMATCH_SHIFT   0
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_LS_MISMATCH_WIDTH   3
#define PMC_GLOBAL_PPU0_MB2_FT_STATUS_LS_MISMATCH_MASK    0X00000007

/**
 * Register: PMC_GLOBAL_PPU0_MB3_FT_STATUS
 */
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000060C )

#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_CPU3_SHIFT   14
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_CPU3_WIDTH   1
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_CPU3_MASK    0X00004000

#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_CPU2_SHIFT   13
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_CPU2_WIDTH   1
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_CPU2_MASK    0X00002000

#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_CPU1_SHIFT   12
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_CPU1_WIDTH   1
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_CPU1_MASK    0X00001000

#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_FT_STATE_SHIFT   10
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_FT_STATE_WIDTH   2
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_FT_STATE_MASK    0X00000C00

#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_WDT_EXP_SHIFT   9
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_WDT_EXP_WIDTH   1
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_WDT_EXP_MASK    0X00000200

#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_UNCORR_ERR_SHIFT   8
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_UNCORR_ERR_WIDTH   1
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_UNCORR_ERR_MASK    0X00000100

#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_VOTER_ERR_SHIFT   7
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_VOTER_ERR_WIDTH   1
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_VOTER_ERR_MASK    0X00000080

#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_FTL_MISMATCH_SHIFT   4
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_FTL_MISMATCH_WIDTH   3
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_FTL_MISMATCH_MASK    0X00000070

#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_LS_RECOVER_SHIFT   3
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_LS_RECOVER_WIDTH   1
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_LS_RECOVER_MASK    0X00000008

#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_LS_MISMATCH_SHIFT   0
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_LS_MISMATCH_WIDTH   3
#define PMC_GLOBAL_PPU0_MB3_FT_STATUS_LS_MISMATCH_MASK    0X00000007

/**
 * Register: PMC_GLOBAL_PPU1_MB_FATAL
 */
#define PMC_GLOBAL_PPU1_MB_FATAL    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000610 )

#define PMC_GLOBAL_PPU1_MB_FATAL_CPU3_SHIFT   2
#define PMC_GLOBAL_PPU1_MB_FATAL_CPU3_WIDTH   1
#define PMC_GLOBAL_PPU1_MB_FATAL_CPU3_MASK    0X00000004

#define PMC_GLOBAL_PPU1_MB_FATAL_CPU2_SHIFT   1
#define PMC_GLOBAL_PPU1_MB_FATAL_CPU2_WIDTH   1
#define PMC_GLOBAL_PPU1_MB_FATAL_CPU2_MASK    0X00000002

#define PMC_GLOBAL_PPU1_MB_FATAL_CPU1_SHIFT   0
#define PMC_GLOBAL_PPU1_MB_FATAL_CPU1_WIDTH   1
#define PMC_GLOBAL_PPU1_MB_FATAL_CPU1_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PPU1_MB1_FT_STATUS
 */
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000614 )

#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_CPU3_SHIFT   14
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_CPU3_WIDTH   1
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_CPU3_MASK    0X00004000

#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_CPU2_SHIFT   13
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_CPU2_WIDTH   1
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_CPU2_MASK    0X00002000

#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_CPU1_SHIFT   12
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_CPU1_WIDTH   1
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_CPU1_MASK    0X00001000

#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_FT_STATE_SHIFT   10
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_FT_STATE_WIDTH   2
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_FT_STATE_MASK    0X00000C00

#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_WDT_EXP_SHIFT   9
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_WDT_EXP_WIDTH   1
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_WDT_EXP_MASK    0X00000200

#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_UNCORR_ERR_SHIFT   8
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_UNCORR_ERR_WIDTH   1
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_UNCORR_ERR_MASK    0X00000100

#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_VOTER_ERR_SHIFT   7
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_VOTER_ERR_WIDTH   1
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_VOTER_ERR_MASK    0X00000080

#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_FTL_MISMATCH_SHIFT   4
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_FTL_MISMATCH_WIDTH   3
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_FTL_MISMATCH_MASK    0X00000070

#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_LS_RECOVER_SHIFT   3
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_LS_RECOVER_WIDTH   1
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_LS_RECOVER_MASK    0X00000008

#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_LS_MISMATCH_SHIFT   0
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_LS_MISMATCH_WIDTH   3
#define PMC_GLOBAL_PPU1_MB1_FT_STATUS_LS_MISMATCH_MASK    0X00000007

/**
 * Register: PMC_GLOBAL_PPU1_MB2_FT_STATUS
 */
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000618 )

#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_CPU3_SHIFT   14
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_CPU3_WIDTH   1
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_CPU3_MASK    0X00004000

#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_CPU2_SHIFT   13
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_CPU2_WIDTH   1
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_CPU2_MASK    0X00002000

#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_CPU1_SHIFT   12
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_CPU1_WIDTH   1
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_CPU1_MASK    0X00001000

#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_FT_STATE_SHIFT   10
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_FT_STATE_WIDTH   2
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_FT_STATE_MASK    0X00000C00

#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_WDT_EXP_SHIFT   9
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_WDT_EXP_WIDTH   1
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_WDT_EXP_MASK    0X00000200

#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_UNCORR_ERR_SHIFT   8
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_UNCORR_ERR_WIDTH   1
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_UNCORR_ERR_MASK    0X00000100

#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_VOTER_ERR_SHIFT   7
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_VOTER_ERR_WIDTH   1
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_VOTER_ERR_MASK    0X00000080

#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_FTL_MISMATCH_SHIFT   4
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_FTL_MISMATCH_WIDTH   3
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_FTL_MISMATCH_MASK    0X00000070

#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_LS_RECOVER_SHIFT   3
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_LS_RECOVER_WIDTH   1
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_LS_RECOVER_MASK    0X00000008

#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_LS_MISMATCH_SHIFT   0
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_LS_MISMATCH_WIDTH   3
#define PMC_GLOBAL_PPU1_MB2_FT_STATUS_LS_MISMATCH_MASK    0X00000007

/**
 * Register: PMC_GLOBAL_PPU1_MB3_FT_STATUS
 */
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000061C )

#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_CPU3_SHIFT   14
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_CPU3_WIDTH   1
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_CPU3_MASK    0X00004000

#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_CPU2_SHIFT   13
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_CPU2_WIDTH   1
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_CPU2_MASK    0X00002000

#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_CPU1_SHIFT   12
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_CPU1_WIDTH   1
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_CPU1_MASK    0X00001000

#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_FT_STATE_SHIFT   10
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_FT_STATE_WIDTH   2
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_FT_STATE_MASK    0X00000C00

#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_WDT_EXP_SHIFT   9
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_WDT_EXP_WIDTH   1
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_WDT_EXP_MASK    0X00000200

#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_UNCORR_ERR_SHIFT   8
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_UNCORR_ERR_WIDTH   1
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_UNCORR_ERR_MASK    0X00000100

#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_VOTER_ERR_SHIFT   7
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_VOTER_ERR_WIDTH   1
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_VOTER_ERR_MASK    0X00000080

#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_FTL_MISMATCH_SHIFT   4
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_FTL_MISMATCH_WIDTH   3
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_FTL_MISMATCH_MASK    0X00000070

#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_LS_RECOVER_SHIFT   3
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_LS_RECOVER_WIDTH   1
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_LS_RECOVER_MASK    0X00000008

#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_LS_MISMATCH_SHIFT   0
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_LS_MISMATCH_WIDTH   3
#define PMC_GLOBAL_PPU1_MB3_FT_STATUS_LS_MISMATCH_MASK    0X00000007

/**
 * Register: PMC_GLOBAL_PPU_1_RST
 */
#define PMC_GLOBAL_PPU_1_RST    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000620 )

#define PMC_GLOBAL_PPU_1_RST_RST_N_SHIFT   0
#define PMC_GLOBAL_PPU_1_RST_RST_N_WIDTH   1
#define PMC_GLOBAL_PPU_1_RST_RST_N_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PPU_1_RST_MODE
 */
#define PMC_GLOBAL_PPU_1_RST_MODE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000624 )

#define PMC_GLOBAL_PPU_1_RST_MODE_WAKEUP_SHIFT   4
#define PMC_GLOBAL_PPU_1_RST_MODE_WAKEUP_WIDTH   1
#define PMC_GLOBAL_PPU_1_RST_MODE_WAKEUP_MASK    0X00000010

#define PMC_GLOBAL_PPU_1_RST_MODE_RST_MODE_SHIFT   0
#define PMC_GLOBAL_PPU_1_RST_MODE_RST_MODE_WIDTH   2
#define PMC_GLOBAL_PPU_1_RST_MODE_RST_MODE_MASK    0X00000003

/**
 * Register: PMC_GLOBAL_PPU0_AXI
 */
#define PMC_GLOBAL_PPU0_AXI    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000630 )

#define PMC_GLOBAL_PPU0_AXI_ARQOS_SHIFT   4
#define PMC_GLOBAL_PPU0_AXI_ARQOS_WIDTH   4
#define PMC_GLOBAL_PPU0_AXI_ARQOS_MASK    0X000000F0

#define PMC_GLOBAL_PPU0_AXI_AWQOS_SHIFT   0
#define PMC_GLOBAL_PPU0_AXI_AWQOS_WIDTH   4
#define PMC_GLOBAL_PPU0_AXI_AWQOS_MASK    0X0000000F

/**
 * Register: PMC_GLOBAL_PPU1_AXI
 */
#define PMC_GLOBAL_PPU1_AXI    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000634 )

#define PMC_GLOBAL_PPU1_AXI_ARQOS_SHIFT   4
#define PMC_GLOBAL_PPU1_AXI_ARQOS_WIDTH   4
#define PMC_GLOBAL_PPU1_AXI_ARQOS_MASK    0X000000F0

#define PMC_GLOBAL_PPU1_AXI_AWQOS_SHIFT   0
#define PMC_GLOBAL_PPU1_AXI_AWQOS_WIDTH   4
#define PMC_GLOBAL_PPU1_AXI_AWQOS_MASK    0X0000000F

/**
 * Register: PMC_GLOBAL_ROM_VALIDATION_STATUS
 */
#define PMC_GLOBAL_ROM_VALIDATION_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000700 )

#define PMC_GLOBAL_ROM_VALIDATION_STATUS_PASS_SHIFT   1
#define PMC_GLOBAL_ROM_VALIDATION_STATUS_PASS_WIDTH   1
#define PMC_GLOBAL_ROM_VALIDATION_STATUS_PASS_MASK    0X00000002

#define PMC_GLOBAL_ROM_VALIDATION_STATUS_DONE_SHIFT   0
#define PMC_GLOBAL_ROM_VALIDATION_STATUS_DONE_WIDTH   1
#define PMC_GLOBAL_ROM_VALIDATION_STATUS_DONE_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_ROM_VALIDATION_DIGEST_0
 */
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000704 )

#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_0_WORD_SHIFT   0
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_0_WORD_WIDTH   32
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_0_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_ROM_VALIDATION_DIGEST_1
 */
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000708 )

#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_1_WORD_SHIFT   0
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_1_WORD_WIDTH   32
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_1_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_ROM_VALIDATION_DIGEST_2
 */
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_2    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000070C )

#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_2_WORD_SHIFT   0
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_2_WORD_WIDTH   32
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_2_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_ROM_VALIDATION_DIGEST_3
 */
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_3    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000710 )

#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_3_WORD_SHIFT   0
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_3_WORD_WIDTH   32
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_3_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_ROM_VALIDATION_DIGEST_4
 */
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_4    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000714 )

#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_4_WORD_SHIFT   0
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_4_WORD_WIDTH   32
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_4_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_ROM_VALIDATION_DIGEST_5
 */
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_5    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000718 )

#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_5_WORD_SHIFT   0
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_5_WORD_WIDTH   32
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_5_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_ROM_VALIDATION_DIGEST_6
 */
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_6    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000071C )

#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_6_WORD_SHIFT   0
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_6_WORD_WIDTH   32
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_6_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_ROM_VALIDATION_DIGEST_7
 */
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_7    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000720 )

#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_7_WORD_SHIFT   0
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_7_WORD_WIDTH   32
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_7_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_ROM_VALIDATION_DIGEST_8
 */
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_8    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000724 )

#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_8_WORD_SHIFT   0
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_8_WORD_WIDTH   32
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_8_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_ROM_VALIDATION_DIGEST_9
 */
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_9    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000728 )

#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_9_WORD_SHIFT   0
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_9_WORD_WIDTH   32
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_9_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_ROM_VALIDATION_DIGEST_10
 */
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_10    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000072C )

#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_10_WORD_SHIFT   0
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_10_WORD_WIDTH   32
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_10_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_ROM_VALIDATION_DIGEST_11
 */
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_11    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000730 )

#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_11_WORD_SHIFT   0
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_11_WORD_WIDTH   32
#define PMC_GLOBAL_ROM_VALIDATION_DIGEST_11_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_FW_AUTH_HASH_0
 */
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000750 )

#define PMC_GLOBAL_PMC_FW_AUTH_HASH_0_WORD_SHIFT   0
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_0_WORD_WIDTH   32
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_0_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_FW_AUTH_HASH_1
 */
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000754 )

#define PMC_GLOBAL_PMC_FW_AUTH_HASH_1_WORD_SHIFT   0
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_1_WORD_WIDTH   32
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_1_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_FW_AUTH_HASH_2
 */
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_2    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000758 )

#define PMC_GLOBAL_PMC_FW_AUTH_HASH_2_WORD_SHIFT   0
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_2_WORD_WIDTH   32
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_2_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_FW_AUTH_HASH_3
 */
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_3    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000075C )

#define PMC_GLOBAL_PMC_FW_AUTH_HASH_3_WORD_SHIFT   0
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_3_WORD_WIDTH   32
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_3_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_FW_AUTH_HASH_4
 */
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_4    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000760 )

#define PMC_GLOBAL_PMC_FW_AUTH_HASH_4_WORD_SHIFT   0
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_4_WORD_WIDTH   32
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_4_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_FW_AUTH_HASH_5
 */
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_5    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000764 )

#define PMC_GLOBAL_PMC_FW_AUTH_HASH_5_WORD_SHIFT   0
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_5_WORD_WIDTH   32
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_5_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_FW_AUTH_HASH_6
 */
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_6    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000768 )

#define PMC_GLOBAL_PMC_FW_AUTH_HASH_6_WORD_SHIFT   0
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_6_WORD_WIDTH   32
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_6_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_FW_AUTH_HASH_7
 */
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_7    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000076C )

#define PMC_GLOBAL_PMC_FW_AUTH_HASH_7_WORD_SHIFT   0
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_7_WORD_WIDTH   32
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_7_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_FW_AUTH_HASH_8
 */
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_8    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000770 )

#define PMC_GLOBAL_PMC_FW_AUTH_HASH_8_WORD_SHIFT   0
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_8_WORD_WIDTH   32
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_8_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_FW_AUTH_HASH_9
 */
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_9    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000774 )

#define PMC_GLOBAL_PMC_FW_AUTH_HASH_9_WORD_SHIFT   0
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_9_WORD_WIDTH   32
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_9_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_FW_AUTH_HASH_10
 */
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_10    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000778 )

#define PMC_GLOBAL_PMC_FW_AUTH_HASH_10_WORD_SHIFT   0
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_10_WORD_WIDTH   32
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_10_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_FW_AUTH_HASH_11
 */
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_11    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000077C )

#define PMC_GLOBAL_PMC_FW_AUTH_HASH_11_WORD_SHIFT   0
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_11_WORD_WIDTH   32
#define PMC_GLOBAL_PMC_FW_AUTH_HASH_11_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_SAFETY_CHK
 */
#define PMC_GLOBAL_SAFETY_CHK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000800 )

#define PMC_GLOBAL_SAFETY_CHK_DATA_SHIFT   0
#define PMC_GLOBAL_SAFETY_CHK_DATA_WIDTH   32
#define PMC_GLOBAL_SAFETY_CHK_DATA_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_SAFETY_CNTRL
 */
#define PMC_GLOBAL_SAFETY_CNTRL    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000804 )

#define PMC_GLOBAL_SAFETY_CNTRL_SAFETY_MISSION_DIS_SHIFT   0
#define PMC_GLOBAL_SAFETY_CNTRL_SAFETY_MISSION_DIS_WIDTH   1
#define PMC_GLOBAL_SAFETY_CNTRL_SAFETY_MISSION_DIS_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_ECO_1
 */
#define PMC_GLOBAL_ECO_1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000810 )

#define PMC_GLOBAL_ECO_1_VALUE_SHIFT   0
#define PMC_GLOBAL_ECO_1_VALUE_WIDTH   32
#define PMC_GLOBAL_ECO_1_VALUE_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_GLOBAL_CNTRL_2
 */
#define PMC_GLOBAL_GLOBAL_CNTRL_2    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000814 )

#define PMC_GLOBAL_GLOBAL_CNTRL_2_VALUE_SHIFT   0
#define PMC_GLOBAL_GLOBAL_CNTRL_2_VALUE_WIDTH   32
#define PMC_GLOBAL_GLOBAL_CNTRL_2_VALUE_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_NOC_ECO_0
 */
#define PMC_GLOBAL_PMC_NOC_ECO_0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000820 )

#define PMC_GLOBAL_PMC_NOC_ECO_0_VALUE_SHIFT   0
#define PMC_GLOBAL_PMC_NOC_ECO_0_VALUE_WIDTH   1
#define PMC_GLOBAL_PMC_NOC_ECO_0_VALUE_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_NOC_ECO_1
 */
#define PMC_GLOBAL_PMC_NOC_ECO_1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000824 )

#define PMC_GLOBAL_PMC_NOC_ECO_1_VALUE_SHIFT   0
#define PMC_GLOBAL_PMC_NOC_ECO_1_VALUE_WIDTH   1
#define PMC_GLOBAL_PMC_NOC_ECO_1_VALUE_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_NOC_ECO_2
 */
#define PMC_GLOBAL_PMC_NOC_ECO_2    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000828 )

#define PMC_GLOBAL_PMC_NOC_ECO_2_VALUE_SHIFT   0
#define PMC_GLOBAL_PMC_NOC_ECO_2_VALUE_WIDTH   1
#define PMC_GLOBAL_PMC_NOC_ECO_2_VALUE_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_NOC_ECO_3
 */
#define PMC_GLOBAL_PMC_NOC_ECO_3    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000082C )

#define PMC_GLOBAL_PMC_NOC_ECO_3_VALUE_SHIFT   0
#define PMC_GLOBAL_PMC_NOC_ECO_3_VALUE_WIDTH   1
#define PMC_GLOBAL_PMC_NOC_ECO_3_VALUE_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_NOC_ECO_4
 */
#define PMC_GLOBAL_PMC_NOC_ECO_4    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000830 )

#define PMC_GLOBAL_PMC_NOC_ECO_4_VALUE_SHIFT   0
#define PMC_GLOBAL_PMC_NOC_ECO_4_VALUE_WIDTH   1
#define PMC_GLOBAL_PMC_NOC_ECO_4_VALUE_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_NOC_PMC_ECO_0
 */
#define PMC_GLOBAL_NOC_PMC_ECO_0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000834 )

#define PMC_GLOBAL_NOC_PMC_ECO_0_VALUE_SHIFT   0
#define PMC_GLOBAL_NOC_PMC_ECO_0_VALUE_WIDTH   1
#define PMC_GLOBAL_NOC_PMC_ECO_0_VALUE_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_NOC_PMC_ECO_1
 */
#define PMC_GLOBAL_NOC_PMC_ECO_1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000838 )

#define PMC_GLOBAL_NOC_PMC_ECO_1_VALUE_SHIFT   0
#define PMC_GLOBAL_NOC_PMC_ECO_1_VALUE_WIDTH   1
#define PMC_GLOBAL_NOC_PMC_ECO_1_VALUE_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_NOC_PMC_ECO_2
 */
#define PMC_GLOBAL_NOC_PMC_ECO_2    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000083C )

#define PMC_GLOBAL_NOC_PMC_ECO_2_VALUE_SHIFT   0
#define PMC_GLOBAL_NOC_PMC_ECO_2_VALUE_WIDTH   1
#define PMC_GLOBAL_NOC_PMC_ECO_2_VALUE_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_NOC_PMC_ECO_3
 */
#define PMC_GLOBAL_NOC_PMC_ECO_3    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000840 )

#define PMC_GLOBAL_NOC_PMC_ECO_3_VALUE_SHIFT   0
#define PMC_GLOBAL_NOC_PMC_ECO_3_VALUE_WIDTH   1
#define PMC_GLOBAL_NOC_PMC_ECO_3_VALUE_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_NOC_PMC_ECO_4
 */
#define PMC_GLOBAL_NOC_PMC_ECO_4    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000844 )

#define PMC_GLOBAL_NOC_PMC_ECO_4_VALUE_SHIFT   0
#define PMC_GLOBAL_NOC_PMC_ECO_4_VALUE_WIDTH   1
#define PMC_GLOBAL_NOC_PMC_ECO_4_VALUE_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PL_STATUS
 */
#define PMC_GLOBAL_PL_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000880 )

#define PMC_GLOBAL_PL_STATUS_POR_PL_B_SHIFT   0
#define PMC_GLOBAL_PL_STATUS_POR_PL_B_WIDTH   1
#define PMC_GLOBAL_PL_STATUS_POR_PL_B_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_DONE
 */
#define PMC_GLOBAL_DONE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000884 )

#define PMC_GLOBAL_DONE_DONE_SHIFT   0
#define PMC_GLOBAL_DONE_DONE_WIDTH   1
#define PMC_GLOBAL_DONE_DONE_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_PL_GPO
 */
#define PMC_GLOBAL_PMC_PL_GPO    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000900 )

#define PMC_GLOBAL_PMC_PL_GPO_GPO_SHIFT   0
#define PMC_GLOBAL_PMC_PL_GPO_GPO_WIDTH   32
#define PMC_GLOBAL_PMC_PL_GPO_GPO_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_PPU1_GPI
 */
#define PMC_GLOBAL_PMC_PPU1_GPI    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000910 )

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_31_SHIFT   31
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_31_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_31_MASK    0X80000000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_30_SHIFT   30
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_30_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_30_MASK    0X40000000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_29_SHIFT   29
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_29_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_29_MASK    0X20000000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_28_SHIFT   28
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_28_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_28_MASK    0X10000000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_27_SHIFT   27
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_27_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_27_MASK    0X08000000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_26_SHIFT   26
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_26_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_26_MASK    0X04000000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_25_SHIFT   25
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_25_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_25_MASK    0X02000000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_24_SHIFT   24
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_24_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_24_MASK    0X01000000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_23_SHIFT   23
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_23_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_23_MASK    0X00800000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_22_SHIFT   22
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_22_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_22_MASK    0X00400000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_21_SHIFT   21
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_21_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_21_MASK    0X00200000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_20_SHIFT   20
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_20_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_20_MASK    0X00100000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_19_SHIFT   19
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_19_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_19_MASK    0X00080000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_18_SHIFT   18
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_18_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_18_MASK    0X00040000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_17_SHIFT   17
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_17_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_17_MASK    0X00020000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_16_SHIFT   16
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_16_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_16_MASK    0X00010000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_15_SHIFT   15
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_15_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_15_MASK    0X00008000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_14_SHIFT   14
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_14_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_14_MASK    0X00004000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_13_SHIFT   13
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_13_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_13_MASK    0X00002000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_12_SHIFT   12
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_12_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_12_MASK    0X00001000

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_11_SHIFT   11
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_11_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_11_MASK    0X00000800

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_10_SHIFT   10
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_10_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_10_MASK    0X00000400

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_9_SHIFT   9
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_9_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_9_MASK    0X00000200

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_8_SHIFT   8
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_8_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_8_MASK    0X00000100

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_7_SHIFT   7
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_7_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_7_MASK    0X00000080

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_6_SHIFT   6
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_6_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_6_MASK    0X00000040

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_5_SHIFT   5
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_5_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_5_MASK    0X00000020

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_4_SHIFT   4
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_4_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_4_MASK    0X00000010

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_3_SHIFT   3
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_3_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_3_MASK    0X00000008

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_2_SHIFT   2
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_2_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_2_MASK    0X00000004

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_1_SHIFT   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_1_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_1_MASK    0X00000002

#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_0_SHIFT   0
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_0_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_GPI_0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_PPU1_GPI_MASK
 */
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000914 )

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_31_SHIFT   31
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_31_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_31_MASK    0X80000000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_30_SHIFT   30
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_30_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_30_MASK    0X40000000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_29_SHIFT   29
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_29_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_29_MASK    0X20000000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_28_SHIFT   28
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_28_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_28_MASK    0X10000000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_27_SHIFT   27
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_27_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_27_MASK    0X08000000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_26_SHIFT   26
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_26_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_26_MASK    0X04000000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_25_SHIFT   25
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_25_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_25_MASK    0X02000000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_24_SHIFT   24
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_24_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_24_MASK    0X01000000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_23_SHIFT   23
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_23_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_23_MASK    0X00800000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_22_SHIFT   22
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_22_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_22_MASK    0X00400000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_21_SHIFT   21
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_21_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_21_MASK    0X00200000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_20_SHIFT   20
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_20_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_20_MASK    0X00100000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_19_SHIFT   19
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_19_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_19_MASK    0X00080000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_18_SHIFT   18
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_18_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_18_MASK    0X00040000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_17_SHIFT   17
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_17_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_17_MASK    0X00020000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_16_SHIFT   16
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_16_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_16_MASK    0X00010000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_15_SHIFT   15
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_15_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_15_MASK    0X00008000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_14_SHIFT   14
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_14_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_14_MASK    0X00004000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_13_SHIFT   13
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_13_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_13_MASK    0X00002000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_12_SHIFT   12
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_12_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_12_MASK    0X00001000

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_11_SHIFT   11
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_11_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_11_MASK    0X00000800

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_10_SHIFT   10
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_10_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_10_MASK    0X00000400

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_9_SHIFT   9
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_9_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_9_MASK    0X00000200

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_8_SHIFT   8
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_8_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_8_MASK    0X00000100

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_7_SHIFT   7
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_7_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_7_MASK    0X00000080

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_6_SHIFT   6
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_6_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_6_MASK    0X00000040

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_5_SHIFT   5
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_5_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_5_MASK    0X00000020

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_4_SHIFT   4
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_4_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_4_MASK    0X00000010

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_3_SHIFT   3
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_3_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_3_MASK    0X00000008

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_2_SHIFT   2
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_2_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_2_MASK    0X00000004

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_1_SHIFT   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_1_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_1_MASK    0X00000002

#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_0_SHIFT   0
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_0_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_MASK_GPI_0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_PPU1_GPI_EN
 */
#define PMC_GLOBAL_PMC_PPU1_GPI_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000918 )

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_31_SHIFT   31
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_31_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_31_MASK    0X80000000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_30_SHIFT   30
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_30_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_30_MASK    0X40000000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_29_SHIFT   29
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_29_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_29_MASK    0X20000000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_28_SHIFT   28
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_28_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_28_MASK    0X10000000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_27_SHIFT   27
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_27_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_27_MASK    0X08000000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_26_SHIFT   26
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_26_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_26_MASK    0X04000000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_25_SHIFT   25
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_25_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_25_MASK    0X02000000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_24_SHIFT   24
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_24_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_24_MASK    0X01000000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_23_SHIFT   23
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_23_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_23_MASK    0X00800000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_22_SHIFT   22
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_22_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_22_MASK    0X00400000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_21_SHIFT   21
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_21_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_21_MASK    0X00200000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_20_SHIFT   20
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_20_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_20_MASK    0X00100000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_19_SHIFT   19
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_19_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_19_MASK    0X00080000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_18_SHIFT   18
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_18_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_18_MASK    0X00040000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_17_SHIFT   17
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_17_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_17_MASK    0X00020000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_16_SHIFT   16
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_16_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_16_MASK    0X00010000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_15_SHIFT   15
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_15_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_15_MASK    0X00008000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_14_SHIFT   14
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_14_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_14_MASK    0X00004000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_13_SHIFT   13
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_13_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_13_MASK    0X00002000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_12_SHIFT   12
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_12_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_12_MASK    0X00001000

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_11_SHIFT   11
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_11_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_11_MASK    0X00000800

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_10_SHIFT   10
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_10_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_10_MASK    0X00000400

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_9_SHIFT   9
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_9_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_9_MASK    0X00000200

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_8_SHIFT   8
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_8_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_8_MASK    0X00000100

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_7_SHIFT   7
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_7_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_7_MASK    0X00000080

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_6_SHIFT   6
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_6_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_6_MASK    0X00000040

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_5_SHIFT   5
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_5_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_5_MASK    0X00000020

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_4_SHIFT   4
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_4_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_4_MASK    0X00000010

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_3_SHIFT   3
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_3_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_3_MASK    0X00000008

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_2_SHIFT   2
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_2_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_2_MASK    0X00000004

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_1_SHIFT   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_1_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_1_MASK    0X00000002

#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_0_SHIFT   0
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_0_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_EN_GPI_0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_PPU1_GPI_DIS
 */
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000091C )

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_31_SHIFT   31
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_31_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_31_MASK    0X80000000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_30_SHIFT   30
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_30_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_30_MASK    0X40000000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_29_SHIFT   29
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_29_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_29_MASK    0X20000000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_28_SHIFT   28
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_28_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_28_MASK    0X10000000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_27_SHIFT   27
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_27_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_27_MASK    0X08000000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_26_SHIFT   26
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_26_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_26_MASK    0X04000000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_25_SHIFT   25
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_25_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_25_MASK    0X02000000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_24_SHIFT   24
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_24_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_24_MASK    0X01000000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_23_SHIFT   23
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_23_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_23_MASK    0X00800000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_22_SHIFT   22
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_22_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_22_MASK    0X00400000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_21_SHIFT   21
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_21_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_21_MASK    0X00200000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_20_SHIFT   20
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_20_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_20_MASK    0X00100000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_19_SHIFT   19
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_19_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_19_MASK    0X00080000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_18_SHIFT   18
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_18_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_18_MASK    0X00040000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_17_SHIFT   17
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_17_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_17_MASK    0X00020000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_16_SHIFT   16
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_16_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_16_MASK    0X00010000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_15_SHIFT   15
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_15_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_15_MASK    0X00008000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_14_SHIFT   14
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_14_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_14_MASK    0X00004000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_13_SHIFT   13
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_13_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_13_MASK    0X00002000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_12_SHIFT   12
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_12_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_12_MASK    0X00001000

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_11_SHIFT   11
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_11_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_11_MASK    0X00000800

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_10_SHIFT   10
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_10_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_10_MASK    0X00000400

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_9_SHIFT   9
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_9_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_9_MASK    0X00000200

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_8_SHIFT   8
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_8_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_8_MASK    0X00000100

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_7_SHIFT   7
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_7_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_7_MASK    0X00000080

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_6_SHIFT   6
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_6_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_6_MASK    0X00000040

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_5_SHIFT   5
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_5_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_5_MASK    0X00000020

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_4_SHIFT   4
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_4_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_4_MASK    0X00000010

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_3_SHIFT   3
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_3_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_3_MASK    0X00000008

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_2_SHIFT   2
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_2_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_2_MASK    0X00000004

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_1_SHIFT   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_1_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_1_MASK    0X00000002

#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_0_SHIFT   0
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_0_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_DIS_GPI_0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_PPU1_GPI_TRIG
 */
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000920 )

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_31_SHIFT   31
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_31_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_31_MASK    0X80000000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_30_SHIFT   30
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_30_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_30_MASK    0X40000000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_29_SHIFT   29
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_29_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_29_MASK    0X20000000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_28_SHIFT   28
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_28_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_28_MASK    0X10000000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_27_SHIFT   27
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_27_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_27_MASK    0X08000000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_26_SHIFT   26
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_26_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_26_MASK    0X04000000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_25_SHIFT   25
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_25_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_25_MASK    0X02000000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_24_SHIFT   24
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_24_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_24_MASK    0X01000000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_23_SHIFT   23
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_23_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_23_MASK    0X00800000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_22_SHIFT   22
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_22_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_22_MASK    0X00400000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_21_SHIFT   21
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_21_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_21_MASK    0X00200000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_20_SHIFT   20
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_20_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_20_MASK    0X00100000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_19_SHIFT   19
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_19_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_19_MASK    0X00080000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_18_SHIFT   18
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_18_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_18_MASK    0X00040000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_17_SHIFT   17
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_17_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_17_MASK    0X00020000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_16_SHIFT   16
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_16_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_16_MASK    0X00010000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_15_SHIFT   15
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_15_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_15_MASK    0X00008000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_14_SHIFT   14
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_14_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_14_MASK    0X00004000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_13_SHIFT   13
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_13_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_13_MASK    0X00002000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_12_SHIFT   12
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_12_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_12_MASK    0X00001000

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_11_SHIFT   11
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_11_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_11_MASK    0X00000800

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_10_SHIFT   10
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_10_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_10_MASK    0X00000400

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_9_SHIFT   9
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_9_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_9_MASK    0X00000200

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_8_SHIFT   8
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_8_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_8_MASK    0X00000100

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_7_SHIFT   7
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_7_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_7_MASK    0X00000080

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_6_SHIFT   6
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_6_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_6_MASK    0X00000040

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_5_SHIFT   5
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_5_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_5_MASK    0X00000020

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_4_SHIFT   4
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_4_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_4_MASK    0X00000010

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_3_SHIFT   3
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_3_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_3_MASK    0X00000008

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_2_SHIFT   2
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_2_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_2_MASK    0X00000004

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_1_SHIFT   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_1_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_1_MASK    0X00000002

#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_0_SHIFT   0
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_0_WIDTH   1
#define PMC_GLOBAL_PMC_PPU1_GPI_TRIG_GPI_0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_PL_IRQ
 */
#define PMC_GLOBAL_PMC_PL_IRQ    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000930 )

#define PMC_GLOBAL_PMC_PL_IRQ_IRQ_3_SHIFT   3
#define PMC_GLOBAL_PMC_PL_IRQ_IRQ_3_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_IRQ_3_MASK    0X00000008

#define PMC_GLOBAL_PMC_PL_IRQ_IRQ_2_SHIFT   2
#define PMC_GLOBAL_PMC_PL_IRQ_IRQ_2_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_IRQ_2_MASK    0X00000004

#define PMC_GLOBAL_PMC_PL_IRQ_IRQ_1_SHIFT   1
#define PMC_GLOBAL_PMC_PL_IRQ_IRQ_1_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_IRQ_1_MASK    0X00000002

#define PMC_GLOBAL_PMC_PL_IRQ_IRQ_0_SHIFT   0
#define PMC_GLOBAL_PMC_PL_IRQ_IRQ_0_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_IRQ_0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_PL_IRQ_MASK
 */
#define PMC_GLOBAL_PMC_PL_IRQ_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000934 )

#define PMC_GLOBAL_PMC_PL_IRQ_MASK_IRQ_3_SHIFT   3
#define PMC_GLOBAL_PMC_PL_IRQ_MASK_IRQ_3_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_MASK_IRQ_3_MASK    0X00000008

#define PMC_GLOBAL_PMC_PL_IRQ_MASK_IRQ_2_SHIFT   2
#define PMC_GLOBAL_PMC_PL_IRQ_MASK_IRQ_2_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_MASK_IRQ_2_MASK    0X00000004

#define PMC_GLOBAL_PMC_PL_IRQ_MASK_IRQ_1_SHIFT   1
#define PMC_GLOBAL_PMC_PL_IRQ_MASK_IRQ_1_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_MASK_IRQ_1_MASK    0X00000002

#define PMC_GLOBAL_PMC_PL_IRQ_MASK_IRQ_0_SHIFT   0
#define PMC_GLOBAL_PMC_PL_IRQ_MASK_IRQ_0_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_MASK_IRQ_0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_PL_IRQ_EN
 */
#define PMC_GLOBAL_PMC_PL_IRQ_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000938 )

#define PMC_GLOBAL_PMC_PL_IRQ_EN_IRQ_3_SHIFT   3
#define PMC_GLOBAL_PMC_PL_IRQ_EN_IRQ_3_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_EN_IRQ_3_MASK    0X00000008

#define PMC_GLOBAL_PMC_PL_IRQ_EN_IRQ_2_SHIFT   2
#define PMC_GLOBAL_PMC_PL_IRQ_EN_IRQ_2_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_EN_IRQ_2_MASK    0X00000004

#define PMC_GLOBAL_PMC_PL_IRQ_EN_IRQ_1_SHIFT   1
#define PMC_GLOBAL_PMC_PL_IRQ_EN_IRQ_1_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_EN_IRQ_1_MASK    0X00000002

#define PMC_GLOBAL_PMC_PL_IRQ_EN_IRQ_0_SHIFT   0
#define PMC_GLOBAL_PMC_PL_IRQ_EN_IRQ_0_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_EN_IRQ_0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_PL_IRQ_DIS
 */
#define PMC_GLOBAL_PMC_PL_IRQ_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000093C )

#define PMC_GLOBAL_PMC_PL_IRQ_DIS_IRQ_3_SHIFT   3
#define PMC_GLOBAL_PMC_PL_IRQ_DIS_IRQ_3_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_DIS_IRQ_3_MASK    0X00000008

#define PMC_GLOBAL_PMC_PL_IRQ_DIS_IRQ_2_SHIFT   2
#define PMC_GLOBAL_PMC_PL_IRQ_DIS_IRQ_2_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_DIS_IRQ_2_MASK    0X00000004

#define PMC_GLOBAL_PMC_PL_IRQ_DIS_IRQ_1_SHIFT   1
#define PMC_GLOBAL_PMC_PL_IRQ_DIS_IRQ_1_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_DIS_IRQ_1_MASK    0X00000002

#define PMC_GLOBAL_PMC_PL_IRQ_DIS_IRQ_0_SHIFT   0
#define PMC_GLOBAL_PMC_PL_IRQ_DIS_IRQ_0_WIDTH   1
#define PMC_GLOBAL_PMC_PL_IRQ_DIS_IRQ_0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_SSIT_NOC_ID
 */
#define PMC_GLOBAL_SSIT_NOC_ID    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000950 )

#define PMC_GLOBAL_SSIT_NOC_ID_SWITCHID_SHIFT   0
#define PMC_GLOBAL_SSIT_NOC_ID_SWITCHID_WIDTH   14
#define PMC_GLOBAL_SSIT_NOC_ID_SWITCHID_MASK    0X00003FFF

/**
 * Register: PMC_GLOBAL_SSIT_SEC_STATUS
 */
#define PMC_GLOBAL_SSIT_SEC_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000954 )

#define PMC_GLOBAL_SSIT_SEC_STATUS_DEC_EFUSE_SHIFT   1
#define PMC_GLOBAL_SSIT_SEC_STATUS_DEC_EFUSE_WIDTH   1
#define PMC_GLOBAL_SSIT_SEC_STATUS_DEC_EFUSE_MASK    0X00000002

#define PMC_GLOBAL_SSIT_SEC_STATUS_DEC_BBRAM_SHIFT   0
#define PMC_GLOBAL_SSIT_SEC_STATUS_DEC_BBRAM_WIDTH   1
#define PMC_GLOBAL_SSIT_SEC_STATUS_DEC_BBRAM_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_SSIT_ERR
 */
#define PMC_GLOBAL_SSIT_ERR    ( ( PMC_GLOBAL_BASEADDR ) + 0X00000958 )

#define PMC_GLOBAL_SSIT_ERR_IRQ_OUT_SHIFT   0
#define PMC_GLOBAL_SSIT_ERR_IRQ_OUT_WIDTH   3
#define PMC_GLOBAL_SSIT_ERR_IRQ_OUT_MASK    0X00000007

/**
 * Register: PMC_GLOBAL_SEM_CRAM_ATTRIB
 */
#define PMC_GLOBAL_SEM_CRAM_ATTRIB    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001000 )

#define PMC_GLOBAL_SEM_CRAM_ATTRIB_UNUSED_SHIFT   9
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_UNUSED_WIDTH   7
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_UNUSED_MASK    0X0000FE00

#define PMC_GLOBAL_SEM_CRAM_ATTRIB_RDBCRC_ONEROW_SHIFT   8
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_RDBCRC_ONEROW_WIDTH   1
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_RDBCRC_ONEROW_MASK    0X00000100

#define PMC_GLOBAL_SEM_CRAM_ATTRIB_SWCRC_SEL_SHIFT   7
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_SWCRC_SEL_WIDTH   1
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_SWCRC_SEL_MASK    0X00000080

#define PMC_GLOBAL_SEM_CRAM_ATTRIB_EN_SCAN_CHECK_SHIFT   6
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_EN_SCAN_CHECK_WIDTH   1
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_EN_SCAN_CHECK_MASK    0X00000040

#define PMC_GLOBAL_SEM_CRAM_ATTRIB_EN_SCAN_POST_CONFIG_SHIFT   5
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_EN_SCAN_POST_CONFIG_WIDTH   1
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_EN_SCAN_POST_CONFIG_MASK    0X00000020

#define PMC_GLOBAL_SEM_CRAM_ATTRIB_EN_ERR_INJ_SHIFT   4
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_EN_ERR_INJ_WIDTH   1
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_EN_ERR_INJ_MASK    0X00000010

#define PMC_GLOBAL_SEM_CRAM_ATTRIB_SWECC_SEL_SHIFT   3
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_SWECC_SEL_WIDTH   1
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_SWECC_SEL_MASK    0X00000008

#define PMC_GLOBAL_SEM_CRAM_ATTRIB_EN_CORR_SHIFT   2
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_EN_CORR_WIDTH   1
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_EN_CORR_MASK    0X00000004

#define PMC_GLOBAL_SEM_CRAM_ATTRIB_MODE_SHIFT   0
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_MODE_WIDTH   2
#define PMC_GLOBAL_SEM_CRAM_ATTRIB_MODE_MASK    0X00000003

/**
 * Register: PMC_GLOBAL_SEM_NPI_ATTRIB
 */
#define PMC_GLOBAL_SEM_NPI_ATTRIB    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001004 )

#define PMC_GLOBAL_SEM_NPI_ATTRIB_UNUSED0_SHIFT   18
#define PMC_GLOBAL_SEM_NPI_ATTRIB_UNUSED0_WIDTH   6
#define PMC_GLOBAL_SEM_NPI_ATTRIB_UNUSED0_MASK    0X00FC0000

#define PMC_GLOBAL_SEM_NPI_ATTRIB_PERIOD_SCAN_TIME_SHIFT   8
#define PMC_GLOBAL_SEM_NPI_ATTRIB_PERIOD_SCAN_TIME_WIDTH   10
#define PMC_GLOBAL_SEM_NPI_ATTRIB_PERIOD_SCAN_TIME_MASK    0X0003FF00

#define PMC_GLOBAL_SEM_NPI_ATTRIB_UNUSED1_SHIFT   6
#define PMC_GLOBAL_SEM_NPI_ATTRIB_UNUSED1_WIDTH   2
#define PMC_GLOBAL_SEM_NPI_ATTRIB_UNUSED1_MASK    0X000000C0

#define PMC_GLOBAL_SEM_NPI_ATTRIB_EN_SCAN_CHECK_SHIFT   5
#define PMC_GLOBAL_SEM_NPI_ATTRIB_EN_SCAN_CHECK_WIDTH   1
#define PMC_GLOBAL_SEM_NPI_ATTRIB_EN_SCAN_CHECK_MASK    0X00000020

#define PMC_GLOBAL_SEM_NPI_ATTRIB_EN_SCAN_POST_CONFIG_SHIFT   4
#define PMC_GLOBAL_SEM_NPI_ATTRIB_EN_SCAN_POST_CONFIG_WIDTH   1
#define PMC_GLOBAL_SEM_NPI_ATTRIB_EN_SCAN_POST_CONFIG_MASK    0X00000010

#define PMC_GLOBAL_SEM_NPI_ATTRIB_EN_ERR_INJ_SHIFT   3
#define PMC_GLOBAL_SEM_NPI_ATTRIB_EN_ERR_INJ_WIDTH   1
#define PMC_GLOBAL_SEM_NPI_ATTRIB_EN_ERR_INJ_MASK    0X00000008

#define PMC_GLOBAL_SEM_NPI_ATTRIB_SWSHA_SEL_SHIFT   2
#define PMC_GLOBAL_SEM_NPI_ATTRIB_SWSHA_SEL_WIDTH   1
#define PMC_GLOBAL_SEM_NPI_ATTRIB_SWSHA_SEL_MASK    0X00000004

#define PMC_GLOBAL_SEM_NPI_ATTRIB_MODE_SHIFT   0
#define PMC_GLOBAL_SEM_NPI_ATTRIB_MODE_WIDTH   2
#define PMC_GLOBAL_SEM_NPI_ATTRIB_MODE_MASK    0X00000003

/**
 * Register: PMC_GLOBAL_SEM_NPI_HDR_ADDR_0
 */
#define PMC_GLOBAL_SEM_NPI_HDR_ADDR_0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001008 )

#define PMC_GLOBAL_SEM_NPI_HDR_ADDR_0_ADDR_SHIFT   0
#define PMC_GLOBAL_SEM_NPI_HDR_ADDR_0_ADDR_WIDTH   32
#define PMC_GLOBAL_SEM_NPI_HDR_ADDR_0_ADDR_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_SEM_NPI_HDR_ADDR_1
 */
#define PMC_GLOBAL_SEM_NPI_HDR_ADDR_1    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000100C )

#define PMC_GLOBAL_SEM_NPI_HDR_ADDR_1_ADDR_SHIFT   0
#define PMC_GLOBAL_SEM_NPI_HDR_ADDR_1_ADDR_WIDTH   32
#define PMC_GLOBAL_SEM_NPI_HDR_ADDR_1_ADDR_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_SEM_CLASSIFICATION_0
 */
#define PMC_GLOBAL_SEM_CLASSIFICATION_0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001010 )

#define PMC_GLOBAL_SEM_CLASSIFICATION_0_CLASSIFICATION_TBLADDR_SHIFT   0
#define PMC_GLOBAL_SEM_CLASSIFICATION_0_CLASSIFICATION_TBLADDR_WIDTH   32
#define PMC_GLOBAL_SEM_CLASSIFICATION_0_CLASSIFICATION_TBLADDR_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_SEM_CLASSIFICATION_1
 */
#define PMC_GLOBAL_SEM_CLASSIFICATION_1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001014 )

#define PMC_GLOBAL_SEM_CLASSIFICATION_1_CLASSIFICATION_TBLADDR_SHIFT   0
#define PMC_GLOBAL_SEM_CLASSIFICATION_1_CLASSIFICATION_TBLADDR_WIDTH   32
#define PMC_GLOBAL_SEM_CLASSIFICATION_1_CLASSIFICATION_TBLADDR_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_SEM_STATUS
 */
#define PMC_GLOBAL_SEM_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001018 )

#define PMC_GLOBAL_SEM_STATUS_UNUSED0_SHIFT   27
#define PMC_GLOBAL_SEM_STATUS_UNUSED0_WIDTH   5
#define PMC_GLOBAL_SEM_STATUS_UNUSED0_MASK    0XF8000000

#define PMC_GLOBAL_SEM_STATUS_NPI_LAST_SHIFT   26
#define PMC_GLOBAL_SEM_STATUS_NPI_LAST_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_NPI_LAST_MASK    0X04000000

#define PMC_GLOBAL_SEM_STATUS_NPI_FATAL_STATE_SHIFT   25
#define PMC_GLOBAL_SEM_STATUS_NPI_FATAL_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_NPI_FATAL_STATE_MASK    0X02000000

#define PMC_GLOBAL_SEM_STATUS_NPI_INJ_STATE_SHIFT   24
#define PMC_GLOBAL_SEM_STATUS_NPI_INJ_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_NPI_INJ_STATE_MASK    0X01000000

#define PMC_GLOBAL_SEM_STATUS_NPI_IDLE_STATE_SHIFT   23
#define PMC_GLOBAL_SEM_STATUS_NPI_IDLE_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_NPI_IDLE_STATE_MASK    0X00800000

#define PMC_GLOBAL_SEM_STATUS_NPI_CLASS_STATE_SHIFT   22
#define PMC_GLOBAL_SEM_STATUS_NPI_CLASS_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_NPI_CLASS_STATE_MASK    0X00400000

#define PMC_GLOBAL_SEM_STATUS_NPI_SCAN_STATE_SHIFT   21
#define PMC_GLOBAL_SEM_STATUS_NPI_SCAN_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_NPI_SCAN_STATE_MASK    0X00200000

#define PMC_GLOBAL_SEM_STATUS_NPI_SCANCHK_STATE_SHIFT   20
#define PMC_GLOBAL_SEM_STATUS_NPI_SCANCHK_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_NPI_SCANCHK_STATE_MASK    0X00100000

#define PMC_GLOBAL_SEM_STATUS_NPI_INIT_STATE_SHIFT   19
#define PMC_GLOBAL_SEM_STATUS_NPI_INIT_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_NPI_INIT_STATE_MASK    0X00080000

#define PMC_GLOBAL_SEM_STATUS_NPI_FUNC_SUSPENDED_SHIFT   18
#define PMC_GLOBAL_SEM_STATUS_NPI_FUNC_SUSPENDED_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_NPI_FUNC_SUSPENDED_MASK    0X00040000

#define PMC_GLOBAL_SEM_STATUS_NPI_FUNC_ACTIVE_SHIFT   17
#define PMC_GLOBAL_SEM_STATUS_NPI_FUNC_ACTIVE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_NPI_FUNC_ACTIVE_MASK    0X00020000

#define PMC_GLOBAL_SEM_STATUS_NPI_FUNC_PRESENT_SHIFT   16
#define PMC_GLOBAL_SEM_STATUS_NPI_FUNC_PRESENT_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_NPI_FUNC_PRESENT_MASK    0X00010000

#define PMC_GLOBAL_SEM_STATUS_UNUSED1_SHIFT   11
#define PMC_GLOBAL_SEM_STATUS_UNUSED1_WIDTH   5
#define PMC_GLOBAL_SEM_STATUS_UNUSED1_MASK    0X0000F800

#define PMC_GLOBAL_SEM_STATUS_CRAM_FATAL_STATE_SHIFT   10
#define PMC_GLOBAL_SEM_STATUS_CRAM_FATAL_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_CRAM_FATAL_STATE_MASK    0X00000400

#define PMC_GLOBAL_SEM_STATUS_CRAM_INJ_STATE_SHIFT   9
#define PMC_GLOBAL_SEM_STATUS_CRAM_INJ_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_CRAM_INJ_STATE_MASK    0X00000200

#define PMC_GLOBAL_SEM_STATUS_CRAM_IDLE_STATE_SHIFT   8
#define PMC_GLOBAL_SEM_STATUS_CRAM_IDLE_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_CRAM_IDLE_STATE_MASK    0X00000100

#define PMC_GLOBAL_SEM_STATUS_CRAM_DETECT_STATE_SHIFT   7
#define PMC_GLOBAL_SEM_STATUS_CRAM_DETECT_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_CRAM_DETECT_STATE_MASK    0X00000080

#define PMC_GLOBAL_SEM_STATUS_CRAM_CLASS_STATE_SHIFT   6
#define PMC_GLOBAL_SEM_STATUS_CRAM_CLASS_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_CRAM_CLASS_STATE_MASK    0X00000040

#define PMC_GLOBAL_SEM_STATUS_CRAM_CORR_STATE_SHIFT   5
#define PMC_GLOBAL_SEM_STATUS_CRAM_CORR_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_CRAM_CORR_STATE_MASK    0X00000020

#define PMC_GLOBAL_SEM_STATUS_CRAM_OBS_STATE_SHIFT   4
#define PMC_GLOBAL_SEM_STATUS_CRAM_OBS_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_CRAM_OBS_STATE_MASK    0X00000010

#define PMC_GLOBAL_SEM_STATUS_CRAM_SCANCHK_STATE_SHIFT   3
#define PMC_GLOBAL_SEM_STATUS_CRAM_SCANCHK_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_CRAM_SCANCHK_STATE_MASK    0X00000008

#define PMC_GLOBAL_SEM_STATUS_CRAM_INIT_STATE_SHIFT   2
#define PMC_GLOBAL_SEM_STATUS_CRAM_INIT_STATE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_CRAM_INIT_STATE_MASK    0X00000004

#define PMC_GLOBAL_SEM_STATUS_CRAM_FUNC_ACTIVE_SHIFT   1
#define PMC_GLOBAL_SEM_STATUS_CRAM_FUNC_ACTIVE_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_CRAM_FUNC_ACTIVE_MASK    0X00000002

#define PMC_GLOBAL_SEM_STATUS_CRAM_FUNC_PRESENT_SHIFT   0
#define PMC_GLOBAL_SEM_STATUS_CRAM_FUNC_PRESENT_WIDTH   1
#define PMC_GLOBAL_SEM_STATUS_CRAM_FUNC_PRESENT_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_SEM_ERROR
 */
#define PMC_GLOBAL_SEM_ERROR    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000101C )

#define PMC_GLOBAL_SEM_ERROR_UNUSED0_SHIFT   28
#define PMC_GLOBAL_SEM_ERROR_UNUSED0_WIDTH   4
#define PMC_GLOBAL_SEM_ERROR_UNUSED0_MASK    0XF0000000

#define PMC_GLOBAL_SEM_ERROR_NPI_HRT_ERR_SHIFT   27
#define PMC_GLOBAL_SEM_ERROR_NPI_HRT_ERR_WIDTH   1
#define PMC_GLOBAL_SEM_ERROR_NPI_HRT_ERR_MASK    0X08000000

#define PMC_GLOBAL_SEM_ERROR_NPI_UNCOR_ERR_SHIFT   26
#define PMC_GLOBAL_SEM_ERROR_NPI_UNCOR_ERR_WIDTH   1
#define PMC_GLOBAL_SEM_ERROR_NPI_UNCOR_ERR_MASK    0X04000000

#define PMC_GLOBAL_SEM_ERROR_NPI_INIT_ERR_SHIFT   24
#define PMC_GLOBAL_SEM_ERROR_NPI_INIT_ERR_WIDTH   2
#define PMC_GLOBAL_SEM_ERROR_NPI_INIT_ERR_MASK    0X03000000

#define PMC_GLOBAL_SEM_ERROR_UNUSED1_SHIFT   18
#define PMC_GLOBAL_SEM_ERROR_UNUSED1_WIDTH   6
#define PMC_GLOBAL_SEM_ERROR_UNUSED1_MASK    0X00FC0000

#define PMC_GLOBAL_SEM_ERROR_CRAM_HRT_ERR_SHIFT   17
#define PMC_GLOBAL_SEM_ERROR_CRAM_HRT_ERR_WIDTH   1
#define PMC_GLOBAL_SEM_ERROR_CRAM_HRT_ERR_MASK    0X00020000

#define PMC_GLOBAL_SEM_ERROR_CRAM_COR_ERR_CNT_SHIFT   9
#define PMC_GLOBAL_SEM_ERROR_CRAM_COR_ERR_CNT_WIDTH   8
#define PMC_GLOBAL_SEM_ERROR_CRAM_COR_ERR_CNT_MASK    0X0001FE00

#define PMC_GLOBAL_SEM_ERROR_CRAM_RES_SHIFT   6
#define PMC_GLOBAL_SEM_ERROR_CRAM_RES_WIDTH   3
#define PMC_GLOBAL_SEM_ERROR_CRAM_RES_MASK    0X000001C0

#define PMC_GLOBAL_SEM_ERROR_CRAM_COR_ERR_SHIFT   4
#define PMC_GLOBAL_SEM_ERROR_CRAM_COR_ERR_WIDTH   2
#define PMC_GLOBAL_SEM_ERROR_CRAM_COR_ERR_MASK    0X00000030

#define PMC_GLOBAL_SEM_ERROR_CRAM_CRC_ERR_SHIFT   3
#define PMC_GLOBAL_SEM_ERROR_CRAM_CRC_ERR_WIDTH   1
#define PMC_GLOBAL_SEM_ERROR_CRAM_CRC_ERR_MASK    0X00000008

#define PMC_GLOBAL_SEM_ERROR_CRAM_UNCOR_ERR_SHIFT   2
#define PMC_GLOBAL_SEM_ERROR_CRAM_UNCOR_ERR_WIDTH   1
#define PMC_GLOBAL_SEM_ERROR_CRAM_UNCOR_ERR_MASK    0X00000004

#define PMC_GLOBAL_SEM_ERROR_CRAM_INIT_ERR_SHIFT   0
#define PMC_GLOBAL_SEM_ERROR_CRAM_INIT_ERR_WIDTH   2
#define PMC_GLOBAL_SEM_ERROR_CRAM_INIT_ERR_MASK    0X00000003

/**
 * Register: PMC_GLOBAL_SEM_CMD_REG0
 */
#define PMC_GLOBAL_SEM_CMD_REG0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001020 )

#define PMC_GLOBAL_SEM_CMD_REG0_CMD_CODE_SHIFT   8
#define PMC_GLOBAL_SEM_CMD_REG0_CMD_CODE_WIDTH   20
#define PMC_GLOBAL_SEM_CMD_REG0_CMD_CODE_MASK    0X0FFFFF00

#define PMC_GLOBAL_SEM_CMD_REG0_UNUSED_SHIFT   4
#define PMC_GLOBAL_SEM_CMD_REG0_UNUSED_WIDTH   4
#define PMC_GLOBAL_SEM_CMD_REG0_UNUSED_MASK    0X000000F0

#define PMC_GLOBAL_SEM_CMD_REG0_CMD_PROCESSED_SHIFT   3
#define PMC_GLOBAL_SEM_CMD_REG0_CMD_PROCESSED_WIDTH   1
#define PMC_GLOBAL_SEM_CMD_REG0_CMD_PROCESSED_MASK    0X00000008

#define PMC_GLOBAL_SEM_CMD_REG0_CMD_GO_SHIFT   2
#define PMC_GLOBAL_SEM_CMD_REG0_CMD_GO_WIDTH   1
#define PMC_GLOBAL_SEM_CMD_REG0_CMD_GO_MASK    0X00000004

#define PMC_GLOBAL_SEM_CMD_REG0_CMD_READY_SHIFT   1
#define PMC_GLOBAL_SEM_CMD_REG0_CMD_READY_WIDTH   1
#define PMC_GLOBAL_SEM_CMD_REG0_CMD_READY_MASK    0X00000002

#define PMC_GLOBAL_SEM_CMD_REG0_CMD_VALID_SHIFT   0
#define PMC_GLOBAL_SEM_CMD_REG0_CMD_VALID_WIDTH   1
#define PMC_GLOBAL_SEM_CMD_REG0_CMD_VALID_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_SEM_CMD_REG0_EXT
 */
#define PMC_GLOBAL_SEM_CMD_REG0_EXT    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001024 )

#define PMC_GLOBAL_SEM_CMD_REG0_EXT_CMD_CODE_SHIFT   0
#define PMC_GLOBAL_SEM_CMD_REG0_EXT_CMD_CODE_WIDTH   32
#define PMC_GLOBAL_SEM_CMD_REG0_EXT_CMD_CODE_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_SEM_CMD_REG1
 */
#define PMC_GLOBAL_SEM_CMD_REG1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001028 )

#define PMC_GLOBAL_SEM_CMD_REG1_CMD_CODE_SHIFT   8
#define PMC_GLOBAL_SEM_CMD_REG1_CMD_CODE_WIDTH   20
#define PMC_GLOBAL_SEM_CMD_REG1_CMD_CODE_MASK    0X0FFFFF00

#define PMC_GLOBAL_SEM_CMD_REG1_UNUSED_SHIFT   1
#define PMC_GLOBAL_SEM_CMD_REG1_UNUSED_WIDTH   7
#define PMC_GLOBAL_SEM_CMD_REG1_UNUSED_MASK    0X000000FE

#define PMC_GLOBAL_SEM_CMD_REG1_CMD_VALID_SHIFT   0
#define PMC_GLOBAL_SEM_CMD_REG1_CMD_VALID_WIDTH   1
#define PMC_GLOBAL_SEM_CMD_REG1_CMD_VALID_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_SEM_CMD_REG1_EXT
 */
#define PMC_GLOBAL_SEM_CMD_REG1_EXT    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000102C )

#define PMC_GLOBAL_SEM_CMD_REG1_EXT_CMD_CODE_SHIFT   0
#define PMC_GLOBAL_SEM_CMD_REG1_EXT_CMD_CODE_WIDTH   32
#define PMC_GLOBAL_SEM_CMD_REG1_EXT_CMD_CODE_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_SEM_CMD_REG2
 */
#define PMC_GLOBAL_SEM_CMD_REG2    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001030 )

#define PMC_GLOBAL_SEM_CMD_REG2_CMD_CODE_SHIFT   8
#define PMC_GLOBAL_SEM_CMD_REG2_CMD_CODE_WIDTH   20
#define PMC_GLOBAL_SEM_CMD_REG2_CMD_CODE_MASK    0X0FFFFF00

#define PMC_GLOBAL_SEM_CMD_REG2_UNUSED_SHIFT   1
#define PMC_GLOBAL_SEM_CMD_REG2_UNUSED_WIDTH   7
#define PMC_GLOBAL_SEM_CMD_REG2_UNUSED_MASK    0X000000FE

#define PMC_GLOBAL_SEM_CMD_REG2_CMD_VALID_SHIFT   0
#define PMC_GLOBAL_SEM_CMD_REG2_CMD_VALID_WIDTH   1
#define PMC_GLOBAL_SEM_CMD_REG2_CMD_VALID_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_SEM_CMD_REG2_EXT
 */
#define PMC_GLOBAL_SEM_CMD_REG2_EXT    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001034 )

#define PMC_GLOBAL_SEM_CMD_REG2_EXT_CMD_CODE_SHIFT   0
#define PMC_GLOBAL_SEM_CMD_REG2_EXT_CMD_CODE_WIDTH   32
#define PMC_GLOBAL_SEM_CMD_REG2_EXT_CMD_CODE_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_SEM_CMD_REG3
 */
#define PMC_GLOBAL_SEM_CMD_REG3    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001038 )

#define PMC_GLOBAL_SEM_CMD_REG3_CMD_CODE_SHIFT   8
#define PMC_GLOBAL_SEM_CMD_REG3_CMD_CODE_WIDTH   20
#define PMC_GLOBAL_SEM_CMD_REG3_CMD_CODE_MASK    0X0FFFFF00

#define PMC_GLOBAL_SEM_CMD_REG3_UNUSED_SHIFT   1
#define PMC_GLOBAL_SEM_CMD_REG3_UNUSED_WIDTH   7
#define PMC_GLOBAL_SEM_CMD_REG3_UNUSED_MASK    0X000000FE

#define PMC_GLOBAL_SEM_CMD_REG3_CMD_VALID_SHIFT   0
#define PMC_GLOBAL_SEM_CMD_REG3_CMD_VALID_WIDTH   1
#define PMC_GLOBAL_SEM_CMD_REG3_CMD_VALID_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_SEM_CMD_REG3_EXT
 */
#define PMC_GLOBAL_SEM_CMD_REG3_EXT    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000103C )

#define PMC_GLOBAL_SEM_CMD_REG3_EXT_CMD_CODE_SHIFT   0
#define PMC_GLOBAL_SEM_CMD_REG3_EXT_CMD_CODE_WIDTH   32
#define PMC_GLOBAL_SEM_CMD_REG3_EXT_CMD_CODE_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_SEM_CRAMERR_ADDRL0
 */
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001040 )

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_QWORDS_SHIFT   23
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_QWORDS_WIDTH   5
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_QWORDS_MASK    0X0F800000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_BITS_SHIFT   16
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_BITS_WIDTH   7
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_BITS_MASK    0X007F0000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_UNUSED_SHIFT   4
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_UNUSED_WIDTH   12
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_UNUSED_MASK    0X0000FFF0

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_UNCORRECTABLE_SHIFT   3
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_UNCORRECTABLE_WIDTH   1
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_UNCORRECTABLE_MASK    0X00000008

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_CLASSIFICATION_SHIFT   2
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_CLASSIFICATION_WIDTH   1
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_CLASSIFICATION_MASK    0X00000004

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_VALID_SHIFT   0
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_VALID_WIDTH   2
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL0_VALID_MASK    0X00000003

/**
 * Register: PMC_GLOBAL_SEM_CRAMERR_ADDRH0
 */
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001044 )

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_UNUSED_SHIFT   30
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_UNUSED_WIDTH   2
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_UNUSED_MASK    0XC0000000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_SLR_SHIFT   27
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_SLR_WIDTH   3
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_SLR_MASK    0X38000000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_ROW_SHIFT   23
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_ROW_WIDTH   4
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_ROW_MASK    0X07800000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_BLOCKTYPE_SHIFT   20
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_BLOCKTYPE_WIDTH   3
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_BLOCKTYPE_MASK    0X00700000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_FRAME_ADDR_SHIFT   0
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_FRAME_ADDR_WIDTH   20
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH0_FRAME_ADDR_MASK    0X000FFFFF

/**
 * Register: PMC_GLOBAL_SEM_CRAMERR_ADDRL1
 */
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001048 )

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_QWORDS_SHIFT   23
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_QWORDS_WIDTH   5
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_QWORDS_MASK    0X0F800000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_BITS_SHIFT   16
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_BITS_WIDTH   7
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_BITS_MASK    0X007F0000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_UNUSED_SHIFT   4
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_UNUSED_WIDTH   12
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_UNUSED_MASK    0X0000FFF0

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_UNCORRECTABLE_SHIFT   3
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_UNCORRECTABLE_WIDTH   1
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_UNCORRECTABLE_MASK    0X00000008

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_CLASSIFICATION_SHIFT   2
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_CLASSIFICATION_WIDTH   1
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_CLASSIFICATION_MASK    0X00000004

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_VALID_SHIFT   0
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_VALID_WIDTH   2
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL1_VALID_MASK    0X00000003

/**
 * Register: PMC_GLOBAL_SEM_CRAMERR_ADDRH1
 */
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000104C )

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_UNUSED_SHIFT   30
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_UNUSED_WIDTH   2
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_UNUSED_MASK    0XC0000000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_SLR_SHIFT   27
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_SLR_WIDTH   3
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_SLR_MASK    0X38000000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_ROW_SHIFT   23
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_ROW_WIDTH   4
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_ROW_MASK    0X07800000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_BLOCKTYPE_SHIFT   20
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_BLOCKTYPE_WIDTH   3
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_BLOCKTYPE_MASK    0X00700000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_FRAME_ADDR_SHIFT   0
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_FRAME_ADDR_WIDTH   20
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH1_FRAME_ADDR_MASK    0X000FFFFF

/**
 * Register: PMC_GLOBAL_SEM_CRAMERR_ADDRL2
 */
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001050 )

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_QWORDS_SHIFT   23
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_QWORDS_WIDTH   5
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_QWORDS_MASK    0X0F800000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_BITS_SHIFT   16
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_BITS_WIDTH   7
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_BITS_MASK    0X007F0000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_UNUSED_SHIFT   4
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_UNUSED_WIDTH   12
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_UNUSED_MASK    0X0000FFF0

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_UNCORRECTABLE_SHIFT   3
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_UNCORRECTABLE_WIDTH   1
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_UNCORRECTABLE_MASK    0X00000008

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_CLASSIFICATION_SHIFT   2
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_CLASSIFICATION_WIDTH   1
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_CLASSIFICATION_MASK    0X00000004

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_VALID_SHIFT   0
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_VALID_WIDTH   2
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL2_VALID_MASK    0X00000003

/**
 * Register: PMC_GLOBAL_SEM_CRAMERR_ADDRH2
 */
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001054 )

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_UNUSED_SHIFT   30
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_UNUSED_WIDTH   2
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_UNUSED_MASK    0XC0000000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_SLR_SHIFT   27
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_SLR_WIDTH   3
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_SLR_MASK    0X38000000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_ROW_SHIFT   23
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_ROW_WIDTH   4
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_ROW_MASK    0X07800000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_BLOCKTYPE_SHIFT   20
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_BLOCKTYPE_WIDTH   3
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_BLOCKTYPE_MASK    0X00700000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_FRAME_ADDR_SHIFT   0
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_FRAME_ADDR_WIDTH   20
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH2_FRAME_ADDR_MASK    0X000FFFFF

/**
 * Register: PMC_GLOBAL_SEM_CRAMERR_ADDRL3
 */
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001058 )

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_QWORDS_SHIFT   23
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_QWORDS_WIDTH   5
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_QWORDS_MASK    0X0F800000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_BITS_SHIFT   16
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_BITS_WIDTH   7
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_BITS_MASK    0X007F0000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_UNUSED_SHIFT   4
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_UNUSED_WIDTH   12
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_UNUSED_MASK    0X0000FFF0

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_UNCORRECTABLE_SHIFT   3
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_UNCORRECTABLE_WIDTH   1
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_UNCORRECTABLE_MASK    0X00000008

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_CLASSIFICATION_SHIFT   2
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_CLASSIFICATION_WIDTH   1
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_CLASSIFICATION_MASK    0X00000004

#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_VALID_SHIFT   0
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_VALID_WIDTH   2
#define PMC_GLOBAL_SEM_CRAMERR_ADDRL3_VALID_MASK    0X00000003

/**
 * Register: PMC_GLOBAL_SEM_CRAMERR_ADDRH3
 */
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000105C )

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_UNUSED_SHIFT   30
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_UNUSED_WIDTH   2
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_UNUSED_MASK    0XC0000000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_SLR_SHIFT   27
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_SLR_WIDTH   3
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_SLR_MASK    0X38000000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_ROW_SHIFT   23
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_ROW_WIDTH   4
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_ROW_MASK    0X07800000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_BLOCKTYPE_SHIFT   20
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_BLOCKTYPE_WIDTH   3
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_BLOCKTYPE_MASK    0X00700000

#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_FRAME_ADDR_SHIFT   0
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_FRAME_ADDR_WIDTH   20
#define PMC_GLOBAL_SEM_CRAMERR_ADDRH3_FRAME_ADDR_MASK    0X000FFFFF

/**
 * Register: PMC_GLOBAL_SEM_RESERVED_0
 */
#define PMC_GLOBAL_SEM_RESERVED_0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001060 )

#define PMC_GLOBAL_SEM_RESERVED_0_UNUSED_SHIFT   0
#define PMC_GLOBAL_SEM_RESERVED_0_UNUSED_WIDTH   32
#define PMC_GLOBAL_SEM_RESERVED_0_UNUSED_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_SEM_RESERVED_1
 */
#define PMC_GLOBAL_SEM_RESERVED_1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001064 )

#define PMC_GLOBAL_SEM_RESERVED_1_UNUSED_SHIFT   0
#define PMC_GLOBAL_SEM_RESERVED_1_UNUSED_WIDTH   32
#define PMC_GLOBAL_SEM_RESERVED_1_UNUSED_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_SEM_RESERVED_2
 */
#define PMC_GLOBAL_SEM_RESERVED_2    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001068 )

#define PMC_GLOBAL_SEM_RESERVED_2_UNUSED_SHIFT   0
#define PMC_GLOBAL_SEM_RESERVED_2_UNUSED_WIDTH   32
#define PMC_GLOBAL_SEM_RESERVED_2_UNUSED_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_SEM_RESERVED_3
 */
#define PMC_GLOBAL_SEM_RESERVED_3    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000106C )

#define PMC_GLOBAL_SEM_RESERVED_3_UNUSED_SHIFT   0
#define PMC_GLOBAL_SEM_RESERVED_3_UNUSED_WIDTH   32
#define PMC_GLOBAL_SEM_RESERVED_3_UNUSED_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_0
 */
#define PMC_GLOBAL_PMC_MUTEX_0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001100 )

#define PMC_GLOBAL_PMC_MUTEX_0_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_0_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_0_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_1
 */
#define PMC_GLOBAL_PMC_MUTEX_1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001104 )

#define PMC_GLOBAL_PMC_MUTEX_1_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_1_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_1_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_2
 */
#define PMC_GLOBAL_PMC_MUTEX_2    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001108 )

#define PMC_GLOBAL_PMC_MUTEX_2_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_2_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_2_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_3
 */
#define PMC_GLOBAL_PMC_MUTEX_3    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000110C )

#define PMC_GLOBAL_PMC_MUTEX_3_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_3_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_3_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_4
 */
#define PMC_GLOBAL_PMC_MUTEX_4    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001110 )

#define PMC_GLOBAL_PMC_MUTEX_4_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_4_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_4_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_5
 */
#define PMC_GLOBAL_PMC_MUTEX_5    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001114 )

#define PMC_GLOBAL_PMC_MUTEX_5_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_5_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_5_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_6
 */
#define PMC_GLOBAL_PMC_MUTEX_6    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001118 )

#define PMC_GLOBAL_PMC_MUTEX_6_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_6_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_6_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_7
 */
#define PMC_GLOBAL_PMC_MUTEX_7    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000111C )

#define PMC_GLOBAL_PMC_MUTEX_7_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_7_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_7_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_8
 */
#define PMC_GLOBAL_PMC_MUTEX_8    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001120 )

#define PMC_GLOBAL_PMC_MUTEX_8_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_8_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_8_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_9
 */
#define PMC_GLOBAL_PMC_MUTEX_9    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001124 )

#define PMC_GLOBAL_PMC_MUTEX_9_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_9_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_9_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_10
 */
#define PMC_GLOBAL_PMC_MUTEX_10    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001128 )

#define PMC_GLOBAL_PMC_MUTEX_10_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_10_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_10_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_11
 */
#define PMC_GLOBAL_PMC_MUTEX_11    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000112C )

#define PMC_GLOBAL_PMC_MUTEX_11_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_11_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_11_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_12
 */
#define PMC_GLOBAL_PMC_MUTEX_12    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001130 )

#define PMC_GLOBAL_PMC_MUTEX_12_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_12_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_12_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_13
 */
#define PMC_GLOBAL_PMC_MUTEX_13    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001134 )

#define PMC_GLOBAL_PMC_MUTEX_13_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_13_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_13_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_14
 */
#define PMC_GLOBAL_PMC_MUTEX_14    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001138 )

#define PMC_GLOBAL_PMC_MUTEX_14_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_14_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_14_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_15
 */
#define PMC_GLOBAL_PMC_MUTEX_15    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000113C )

#define PMC_GLOBAL_PMC_MUTEX_15_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_15_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_15_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_16
 */
#define PMC_GLOBAL_PMC_MUTEX_16    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001140 )

#define PMC_GLOBAL_PMC_MUTEX_16_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_16_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_16_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_17
 */
#define PMC_GLOBAL_PMC_MUTEX_17    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001144 )

#define PMC_GLOBAL_PMC_MUTEX_17_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_17_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_17_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_18
 */
#define PMC_GLOBAL_PMC_MUTEX_18    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001148 )

#define PMC_GLOBAL_PMC_MUTEX_18_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_18_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_18_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_19
 */
#define PMC_GLOBAL_PMC_MUTEX_19    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000114C )

#define PMC_GLOBAL_PMC_MUTEX_19_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_19_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_19_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_20
 */
#define PMC_GLOBAL_PMC_MUTEX_20    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001150 )

#define PMC_GLOBAL_PMC_MUTEX_20_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_20_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_20_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_21
 */
#define PMC_GLOBAL_PMC_MUTEX_21    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001154 )

#define PMC_GLOBAL_PMC_MUTEX_21_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_21_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_21_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_22
 */
#define PMC_GLOBAL_PMC_MUTEX_22    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001158 )

#define PMC_GLOBAL_PMC_MUTEX_22_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_22_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_22_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_23
 */
#define PMC_GLOBAL_PMC_MUTEX_23    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000115C )

#define PMC_GLOBAL_PMC_MUTEX_23_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_23_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_23_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_24
 */
#define PMC_GLOBAL_PMC_MUTEX_24    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001160 )

#define PMC_GLOBAL_PMC_MUTEX_24_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_24_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_24_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_25
 */
#define PMC_GLOBAL_PMC_MUTEX_25    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001164 )

#define PMC_GLOBAL_PMC_MUTEX_25_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_25_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_25_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_26
 */
#define PMC_GLOBAL_PMC_MUTEX_26    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001168 )

#define PMC_GLOBAL_PMC_MUTEX_26_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_26_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_26_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_27
 */
#define PMC_GLOBAL_PMC_MUTEX_27    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000116C )

#define PMC_GLOBAL_PMC_MUTEX_27_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_27_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_27_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_28
 */
#define PMC_GLOBAL_PMC_MUTEX_28    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001170 )

#define PMC_GLOBAL_PMC_MUTEX_28_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_28_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_28_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_29
 */
#define PMC_GLOBAL_PMC_MUTEX_29    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001174 )

#define PMC_GLOBAL_PMC_MUTEX_29_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_29_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_29_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_30
 */
#define PMC_GLOBAL_PMC_MUTEX_30    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001178 )

#define PMC_GLOBAL_PMC_MUTEX_30_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_30_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_30_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PMC_MUTEX_31
 */
#define PMC_GLOBAL_PMC_MUTEX_31    ( ( PMC_GLOBAL_BASEADDR ) + 0X0000117C )

#define PMC_GLOBAL_PMC_MUTEX_31_ID_SHIFT   0
#define PMC_GLOBAL_PMC_MUTEX_31_ID_WIDTH   32
#define PMC_GLOBAL_PMC_MUTEX_31_ID_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PPU_1_RST_LOCK
 */
#define PMC_GLOBAL_PPU_1_RST_LOCK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001200 )

#define PMC_GLOBAL_PPU_1_RST_LOCK_LOCK_SHIFT   0
#define PMC_GLOBAL_PPU_1_RST_LOCK_LOCK_WIDTH   1
#define PMC_GLOBAL_PPU_1_RST_LOCK_LOCK_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_POR_LOCK
 */
#define PMC_GLOBAL_POR_LOCK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00001204 )

#define PMC_GLOBAL_POR_LOCK_LOCK_SHIFT   0
#define PMC_GLOBAL_POR_LOCK_LOCK_WIDTH   1
#define PMC_GLOBAL_POR_LOCK_LOCK_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_DOMAIN_ISO_CNTRL
 */
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL    ( ( PMC_GLOBAL_BASEADDR ) + 0X00010000 )

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_VCCRAM_SHIFT   18
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_VCCRAM_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_VCCRAM_MASK    0X00040000

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCRAM_SOC_SHIFT   17
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCRAM_SOC_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCRAM_SOC_MASK    0X00020000

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_SOC_SHIFT   16
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_SOC_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_SOC_MASK    0X00010000

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PL_SOC_SHIFT   15
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PL_SOC_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PL_SOC_MASK    0X00008000

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_SHIFT   14
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_MASK    0X00004000

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_NPI_SHIFT   13
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_NPI_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_NPI_MASK    0X00002000

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_SHIFT   12
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_MASK    0X00001000

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_TEST_SHIFT   11
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_TEST_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_TEST_MASK    0X00000800

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_CFRAME_SHIFT   10
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_CFRAME_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_CFRAME_MASK    0X00000400

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_SHIFT   9
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_MASK    0X00000200

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_DFX_SHIFT   8
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_DFX_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_DFX_MASK    0X00000100

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_SOC_SHIFT   7
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_SOC_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_SOC_MASK    0X00000080

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_SHIFT   6
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_MASK    0X00000040

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_TEST_SHIFT   5
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_TEST_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_TEST_MASK    0X00000020

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_SHIFT   4
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_MASK    0X00000010

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_DFX_SHIFT   3
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_DFX_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_DFX_MASK    0X00000008

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_SOC_SHIFT   2
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_SOC_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_SOC_MASK    0X00000004

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_SHIFT   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_MASK    0X00000002

#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_TEST_SHIFT   0
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_TEST_WIDTH   1
#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_TEST_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PUDC_B_OVERRIDE
 */
#define PMC_GLOBAL_PUDC_B_OVERRIDE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00010004 )

#define PMC_GLOBAL_PUDC_B_OVERRIDE_VAL_SHIFT   0
#define PMC_GLOBAL_PUDC_B_OVERRIDE_VAL_WIDTH   1
#define PMC_GLOBAL_PUDC_B_OVERRIDE_VAL_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_FW_ERR
 */
#define PMC_GLOBAL_PMC_FW_ERR    ( ( PMC_GLOBAL_BASEADDR ) + 0X00010100 )

#define PMC_GLOBAL_PMC_FW_ERR_NCR_FLAG_SHIFT   31
#define PMC_GLOBAL_PMC_FW_ERR_NCR_FLAG_WIDTH   1
#define PMC_GLOBAL_PMC_FW_ERR_NCR_FLAG_MASK    0X80000000

#define PMC_GLOBAL_PMC_FW_ERR_CR_FLAG_SHIFT   30
#define PMC_GLOBAL_PMC_FW_ERR_CR_FLAG_WIDTH   1
#define PMC_GLOBAL_PMC_FW_ERR_CR_FLAG_MASK    0X40000000

#define PMC_GLOBAL_PMC_FW_ERR_DATA_SHIFT   0
#define PMC_GLOBAL_PMC_FW_ERR_DATA_WIDTH   30
#define PMC_GLOBAL_PMC_FW_ERR_DATA_MASK    0X3FFFFFFF

/**
 * Register: PMC_GLOBAL_PPU1_PRIVATE_POR_LOCK
 */
#define PMC_GLOBAL_PPU1_PRIVATE_POR_LOCK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00010200 )

#define PMC_GLOBAL_PPU1_PRIVATE_POR_LOCK_LOCK_SHIFT   0
#define PMC_GLOBAL_PPU1_PRIVATE_POR_LOCK_LOCK_WIDTH   1
#define PMC_GLOBAL_PPU1_PRIVATE_POR_LOCK_LOCK_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_ERR1_STATUS
 */
#define PMC_GLOBAL_PMC_ERR1_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020000 )

#define PMC_GLOBAL_PMC_ERR1_STATUS_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_ERR1_STATUS_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_ERR1_STATUS_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_ERR1_STATUS_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_ERR1_STATUS_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_ERR1_STATUS_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_ERR1_STATUS_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_ERR1_STATUS_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_ERR1_STATUS_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_ERR1_STATUS_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_ERR1_STATUS_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_ERR1_STATUS_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_ERR1_STATUS_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_ERR1_STATUS_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_ERR1_STATUS_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_ERR1_STATUS_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_ERR1_STATUS_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_ERR1_STATUS_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_ERR1_STATUS_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_ERR1_STATUS_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_ERR1_STATUS_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_ERR1_STATUS_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_ERR1_STATUS_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_ERR1_STATUS_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_ERR1_STATUS_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_ERR1_STATUS_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_ERR1_STATUS_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_ERR1_STATUS_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_ERR1_STATUS_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_ERR1_STATUS_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_ERR1_STATUS_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_ERR1_STATUS_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_ERR1_STATUS_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_ERR1_STATUS_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_ERR1_STATUS_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_ERR1_STATUS_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_ERR1_STATUS_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_ERR1_STATUS_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_ERR1_STATUS_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_ERR1_STATUS_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_ERR1_STATUS_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_ERR1_STATUS_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_ERR1_STATUS_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_ERR1_STATUS_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_ERR1_STATUS_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_ERR1_STATUS_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_ERR1_STATUS_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_ERR1_STATUS_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_ERR1_STATUS_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_ERR1_STATUS_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_ERR1_STATUS_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_ERR1_STATUS_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_ERR1_STATUS_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_ERR1_STATUS_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_ERR1_STATUS_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_ERR1_STATUS_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_ERR1_STATUS_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_ERR1_STATUS_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_ERR1_STATUS_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_ERR1_STATUS_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_ERR1_STATUS_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_ERR1_STATUS_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_ERR1_STATUS_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_STATUS_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_ERR2_STATUS
 */
#define PMC_GLOBAL_PMC_ERR2_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020004 )

#define PMC_GLOBAL_PMC_ERR2_STATUS_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_ERR2_STATUS_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_ERR2_STATUS_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_ERR2_STATUS_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_ERR2_STATUS_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_ERR2_STATUS_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_ERR2_STATUS_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_ERR2_STATUS_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_ERR2_STATUS_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_ERR2_STATUS_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_ERR2_STATUS_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_ERR2_STATUS_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_ERR2_STATUS_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_ERR2_STATUS_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_ERR2_STATUS_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_ERR2_STATUS_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_ERR2_STATUS_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_ERR2_STATUS_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_ERR2_STATUS_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_ERR2_STATUS_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_ERR2_STATUS_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_ERR2_STATUS_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_ERR2_STATUS_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_ERR2_STATUS_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_ERR2_STATUS_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_ERR2_STATUS_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_ERR2_STATUS_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_ERR2_STATUS_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_STATUS_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_ERR1_TRIG
 */
#define PMC_GLOBAL_PMC_ERR1_TRIG    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020010 )

#define PMC_GLOBAL_PMC_ERR1_TRIG_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_ERR1_TRIG_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_ERR1_TRIG_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_ERR1_TRIG_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_ERR1_TRIG_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_ERR1_TRIG_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_ERR1_TRIG_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_ERR1_TRIG_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_ERR1_TRIG_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_ERR1_TRIG_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_ERR1_TRIG_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_ERR1_TRIG_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_ERR1_TRIG_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_ERR1_TRIG_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_ERR1_TRIG_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_ERR1_TRIG_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_ERR1_TRIG_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_ERR1_TRIG_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_ERR1_TRIG_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_ERR1_TRIG_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_ERR1_TRIG_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_ERR1_TRIG_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_ERR1_TRIG_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_ERR1_TRIG_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_ERR1_TRIG_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_ERR1_TRIG_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_ERR1_TRIG_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_ERR1_TRIG_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_ERR1_TRIG_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_ERR1_TRIG_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_ERR1_TRIG_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_ERR1_TRIG_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_ERR1_TRIG_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_ERR1_TRIG_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_ERR1_TRIG_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_ERR1_TRIG_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_ERR1_TRIG_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_ERR1_TRIG_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_ERR1_TRIG_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_ERR1_TRIG_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_ERR1_TRIG_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_ERR1_TRIG_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_ERR1_TRIG_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_ERR1_TRIG_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_ERR1_TRIG_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_ERR1_TRIG_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_ERR1_TRIG_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_ERR1_TRIG_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_ERR1_TRIG_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_ERR1_TRIG_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_ERR1_TRIG_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_ERR1_TRIG_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_ERR1_TRIG_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_ERR1_TRIG_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_ERR1_TRIG_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_ERR1_TRIG_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_ERR1_TRIG_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_ERR1_TRIG_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_ERR1_TRIG_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_ERR1_TRIG_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_ERR1_TRIG_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_ERR1_TRIG_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_ERR1_TRIG_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR1_TRIG_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_ERR2_TRIG
 */
#define PMC_GLOBAL_PMC_ERR2_TRIG    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020014 )

#define PMC_GLOBAL_PMC_ERR2_TRIG_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_ERR2_TRIG_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_ERR2_TRIG_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_ERR2_TRIG_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_ERR2_TRIG_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_ERR2_TRIG_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_ERR2_TRIG_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_ERR2_TRIG_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_ERR2_TRIG_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_ERR2_TRIG_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_ERR2_TRIG_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_ERR2_TRIG_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_ERR2_TRIG_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_ERR2_TRIG_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_ERR2_TRIG_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_ERR2_TRIG_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_ERR2_TRIG_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_ERR2_TRIG_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_ERR2_TRIG_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_ERR2_TRIG_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_ERR2_TRIG_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_ERR2_TRIG_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_ERR2_TRIG_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_ERR2_TRIG_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_ERR2_TRIG_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_ERR2_TRIG_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_ERR2_TRIG_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_ERR2_TRIG_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_ERR2_TRIG_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_ERR_OUT1_MASK
 */
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020020 )

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_MASK_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_ERR_OUT1_EN
 */
#define PMC_GLOBAL_PMC_ERR_OUT1_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020024 )

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_ERR_OUT1_EN_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_EN_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_ERR_OUT1_DIS
 */
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020028 )

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT1_DIS_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_ERR_OUT2_MASK
 */
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020030 )

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_MASK_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_ERR_OUT2_EN
 */
#define PMC_GLOBAL_PMC_ERR_OUT2_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020034 )

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_EN_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_ERR_OUT2_DIS
 */
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020038 )

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_ERR_OUT2_DIS_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_POR1_MASK
 */
#define PMC_GLOBAL_PMC_POR1_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020040 )

#define PMC_GLOBAL_PMC_POR1_MASK_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_POR1_MASK_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_POR1_MASK_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_POR1_MASK_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_POR1_MASK_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_POR1_MASK_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_POR1_MASK_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_POR1_MASK_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_POR1_MASK_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_POR1_MASK_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_POR1_MASK_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_POR1_MASK_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_POR1_MASK_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_POR1_MASK_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_POR1_MASK_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_POR1_MASK_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_POR1_MASK_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_POR1_MASK_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_POR1_MASK_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_POR1_MASK_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_POR1_MASK_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_POR1_MASK_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_POR1_MASK_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_POR1_MASK_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_POR1_MASK_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_POR1_MASK_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_POR1_MASK_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_POR1_MASK_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_POR1_MASK_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_POR1_MASK_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_POR1_MASK_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_POR1_MASK_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_POR1_MASK_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_POR1_MASK_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_POR1_MASK_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_POR1_MASK_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_POR1_MASK_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_POR1_MASK_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_POR1_MASK_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_POR1_MASK_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_POR1_MASK_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_POR1_MASK_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_POR1_MASK_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_POR1_MASK_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_POR1_MASK_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_POR1_MASK_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_POR1_MASK_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_POR1_MASK_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_POR1_MASK_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_POR1_MASK_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_POR1_MASK_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_POR1_MASK_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_POR1_MASK_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_POR1_MASK_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_POR1_MASK_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_POR1_MASK_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_POR1_MASK_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_POR1_MASK_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_POR1_MASK_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_POR1_MASK_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_POR1_MASK_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_POR1_MASK_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_POR1_MASK_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_POR1_MASK_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_MASK_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_POR1_EN
 */
#define PMC_GLOBAL_PMC_POR1_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020044 )

#define PMC_GLOBAL_PMC_POR1_EN_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_POR1_EN_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_POR1_EN_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_POR1_EN_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_POR1_EN_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_POR1_EN_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_POR1_EN_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_POR1_EN_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_POR1_EN_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_POR1_EN_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_POR1_EN_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_POR1_EN_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_POR1_EN_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_POR1_EN_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_POR1_EN_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_POR1_EN_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_POR1_EN_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_POR1_EN_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_POR1_EN_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_POR1_EN_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_POR1_EN_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_POR1_EN_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_POR1_EN_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_POR1_EN_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_POR1_EN_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_POR1_EN_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_POR1_EN_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_POR1_EN_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_POR1_EN_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_POR1_EN_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_POR1_EN_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_POR1_EN_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_POR1_EN_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_POR1_EN_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_POR1_EN_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_POR1_EN_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_POR1_EN_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_POR1_EN_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_POR1_EN_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_POR1_EN_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_POR1_EN_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_POR1_EN_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_POR1_EN_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_POR1_EN_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_POR1_EN_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_POR1_EN_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_POR1_EN_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_POR1_EN_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_POR1_EN_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_POR1_EN_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_POR1_EN_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_POR1_EN_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_POR1_EN_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_POR1_EN_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_POR1_EN_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_POR1_EN_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_POR1_EN_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_POR1_EN_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_POR1_EN_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_POR1_EN_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_POR1_EN_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_POR1_EN_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_POR1_EN_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_POR1_EN_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_EN_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_POR1_DIS
 */
#define PMC_GLOBAL_PMC_POR1_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020048 )

#define PMC_GLOBAL_PMC_POR1_DIS_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_POR1_DIS_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_POR1_DIS_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_POR1_DIS_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_POR1_DIS_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_POR1_DIS_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_POR1_DIS_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_POR1_DIS_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_POR1_DIS_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_POR1_DIS_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_POR1_DIS_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_POR1_DIS_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_POR1_DIS_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_POR1_DIS_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_POR1_DIS_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_POR1_DIS_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_POR1_DIS_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_POR1_DIS_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_POR1_DIS_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_POR1_DIS_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_POR1_DIS_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_POR1_DIS_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_POR1_DIS_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_POR1_DIS_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_POR1_DIS_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_POR1_DIS_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_POR1_DIS_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_POR1_DIS_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_POR1_DIS_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_POR1_DIS_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_POR1_DIS_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_POR1_DIS_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_POR1_DIS_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_POR1_DIS_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_POR1_DIS_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_POR1_DIS_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_POR1_DIS_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_POR1_DIS_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_POR1_DIS_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_POR1_DIS_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_POR1_DIS_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_POR1_DIS_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_POR1_DIS_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_POR1_DIS_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_POR1_DIS_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_POR1_DIS_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_POR1_DIS_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_POR1_DIS_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_POR1_DIS_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_POR1_DIS_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_POR1_DIS_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_POR1_DIS_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_POR1_DIS_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_POR1_DIS_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_POR1_DIS_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_POR1_DIS_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_POR1_DIS_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_POR1_DIS_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_POR1_DIS_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_POR1_DIS_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_POR1_DIS_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_POR1_DIS_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_POR1_DIS_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_POR1_DIS_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR1_DIS_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_POR2_MASK
 */
#define PMC_GLOBAL_PMC_POR2_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020050 )

#define PMC_GLOBAL_PMC_POR2_MASK_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_POR2_MASK_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_POR2_MASK_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_POR2_MASK_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_POR2_MASK_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_POR2_MASK_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_POR2_MASK_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_POR2_MASK_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_POR2_MASK_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_POR2_MASK_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_POR2_MASK_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_POR2_MASK_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_POR2_MASK_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_POR2_MASK_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_POR2_MASK_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_POR2_MASK_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_POR2_MASK_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_POR2_MASK_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_POR2_MASK_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_POR2_MASK_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_POR2_MASK_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_POR2_MASK_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_POR2_MASK_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_POR2_MASK_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_POR2_MASK_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_POR2_MASK_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_POR2_MASK_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_POR2_MASK_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_POR2_MASK_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_MASK_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_POR2_EN
 */
#define PMC_GLOBAL_PMC_POR2_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020054 )

#define PMC_GLOBAL_PMC_POR2_EN_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_POR2_EN_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_POR2_EN_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_POR2_EN_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_POR2_EN_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_POR2_EN_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_POR2_EN_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_POR2_EN_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_POR2_EN_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_POR2_EN_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_POR2_EN_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_POR2_EN_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_POR2_EN_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_POR2_EN_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_POR2_EN_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_POR2_EN_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_POR2_EN_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_POR2_EN_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_POR2_EN_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_POR2_EN_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_POR2_EN_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_POR2_EN_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_POR2_EN_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_POR2_EN_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_POR2_EN_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_POR2_EN_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_POR2_EN_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_POR2_EN_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_POR2_EN_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_POR2_EN_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_POR2_EN_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_POR2_EN_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_POR2_EN_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_POR2_EN_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_POR2_EN_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_POR2_EN_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_POR2_EN_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_POR2_EN_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_POR2_EN_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_POR2_EN_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_POR2_EN_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_POR2_EN_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_POR2_EN_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_EN_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_POR2_DIS
 */
#define PMC_GLOBAL_PMC_POR2_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020058 )

#define PMC_GLOBAL_PMC_POR2_DIS_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_POR2_DIS_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_POR2_DIS_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_POR2_DIS_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_POR2_DIS_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_POR2_DIS_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_POR2_DIS_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_POR2_DIS_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_POR2_DIS_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_POR2_DIS_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_POR2_DIS_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_POR2_DIS_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_POR2_DIS_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_POR2_DIS_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_POR2_DIS_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_POR2_DIS_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_POR2_DIS_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_POR2_DIS_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_POR2_DIS_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_POR2_DIS_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_POR2_DIS_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_POR2_DIS_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_POR2_DIS_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_POR2_DIS_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_POR2_DIS_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_POR2_DIS_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_POR2_DIS_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_POR2_DIS_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_POR2_DIS_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_POR2_DIS_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_IRQ1_MASK
 */
#define PMC_GLOBAL_PMC_IRQ1_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020060 )

#define PMC_GLOBAL_PMC_IRQ1_MASK_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_IRQ1_MASK_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_IRQ1_MASK_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_IRQ1_MASK_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_IRQ1_MASK_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_IRQ1_MASK_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_IRQ1_MASK_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_IRQ1_MASK_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_IRQ1_MASK_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_IRQ1_MASK_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_IRQ1_MASK_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_IRQ1_MASK_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_IRQ1_MASK_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_IRQ1_MASK_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_IRQ1_MASK_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_IRQ1_MASK_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_IRQ1_MASK_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_IRQ1_MASK_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_IRQ1_MASK_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_IRQ1_MASK_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_IRQ1_MASK_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_IRQ1_MASK_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_IRQ1_MASK_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_IRQ1_MASK_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_IRQ1_MASK_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_IRQ1_MASK_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_IRQ1_MASK_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_IRQ1_MASK_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_IRQ1_MASK_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_IRQ1_MASK_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_IRQ1_MASK_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_IRQ1_MASK_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_IRQ1_MASK_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_IRQ1_MASK_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_IRQ1_MASK_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_IRQ1_MASK_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_IRQ1_MASK_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_IRQ1_MASK_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_IRQ1_MASK_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_IRQ1_MASK_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_IRQ1_MASK_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_IRQ1_MASK_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_IRQ1_MASK_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_IRQ1_MASK_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_IRQ1_MASK_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_IRQ1_MASK_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_IRQ1_MASK_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_IRQ1_MASK_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_IRQ1_MASK_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_IRQ1_MASK_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_IRQ1_MASK_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_IRQ1_MASK_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_IRQ1_MASK_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_IRQ1_MASK_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_IRQ1_MASK_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_IRQ1_MASK_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_IRQ1_MASK_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_IRQ1_MASK_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_IRQ1_MASK_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_IRQ1_MASK_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_IRQ1_MASK_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_IRQ1_MASK_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_IRQ1_MASK_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_MASK_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_IRQ1_EN
 */
#define PMC_GLOBAL_PMC_IRQ1_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020064 )

#define PMC_GLOBAL_PMC_IRQ1_EN_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_IRQ1_EN_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_IRQ1_EN_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_IRQ1_EN_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_IRQ1_EN_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_IRQ1_EN_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_IRQ1_EN_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_IRQ1_EN_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_IRQ1_EN_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_IRQ1_EN_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_IRQ1_EN_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_IRQ1_EN_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_IRQ1_EN_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_IRQ1_EN_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_IRQ1_EN_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_IRQ1_EN_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_IRQ1_EN_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_IRQ1_EN_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_IRQ1_EN_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_IRQ1_EN_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_IRQ1_EN_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_IRQ1_EN_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_IRQ1_EN_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_IRQ1_EN_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_IRQ1_EN_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_IRQ1_EN_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_IRQ1_EN_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_IRQ1_EN_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_IRQ1_EN_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_IRQ1_EN_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_IRQ1_EN_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_IRQ1_EN_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_IRQ1_EN_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_IRQ1_EN_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_IRQ1_EN_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_IRQ1_EN_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_IRQ1_EN_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_IRQ1_EN_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_IRQ1_EN_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_IRQ1_EN_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_IRQ1_EN_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_IRQ1_EN_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_IRQ1_EN_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_IRQ1_EN_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_IRQ1_EN_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_IRQ1_EN_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_IRQ1_EN_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_IRQ1_EN_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_IRQ1_EN_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_IRQ1_EN_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_IRQ1_EN_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_IRQ1_EN_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_IRQ1_EN_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_IRQ1_EN_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_IRQ1_EN_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_IRQ1_EN_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_IRQ1_EN_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_IRQ1_EN_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_IRQ1_EN_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_IRQ1_EN_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_IRQ1_EN_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_IRQ1_EN_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_IRQ1_EN_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_IRQ1_EN_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_EN_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_IRQ1_DIS
 */
#define PMC_GLOBAL_PMC_IRQ1_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020068 )

#define PMC_GLOBAL_PMC_IRQ1_DIS_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_IRQ1_DIS_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_IRQ1_DIS_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_IRQ1_DIS_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_IRQ1_DIS_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_IRQ1_DIS_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_IRQ1_DIS_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_IRQ1_DIS_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_IRQ1_DIS_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_IRQ1_DIS_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_IRQ1_DIS_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_IRQ1_DIS_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_IRQ1_DIS_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_IRQ1_DIS_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_IRQ1_DIS_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_IRQ1_DIS_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_IRQ1_DIS_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_IRQ1_DIS_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_IRQ1_DIS_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_IRQ1_DIS_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_IRQ1_DIS_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_IRQ1_DIS_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_IRQ1_DIS_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_IRQ1_DIS_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_IRQ1_DIS_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_IRQ1_DIS_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_IRQ1_DIS_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_IRQ1_DIS_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_IRQ1_DIS_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_IRQ1_DIS_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_IRQ1_DIS_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_IRQ1_DIS_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_IRQ1_DIS_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_IRQ1_DIS_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_IRQ1_DIS_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_IRQ1_DIS_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_IRQ1_DIS_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_IRQ1_DIS_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_IRQ1_DIS_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_IRQ1_DIS_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_IRQ1_DIS_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_IRQ1_DIS_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_IRQ1_DIS_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_IRQ1_DIS_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_IRQ1_DIS_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_IRQ1_DIS_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_IRQ1_DIS_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_IRQ1_DIS_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_IRQ1_DIS_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_IRQ1_DIS_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_IRQ1_DIS_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_IRQ1_DIS_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_IRQ1_DIS_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_IRQ1_DIS_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_IRQ1_DIS_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_IRQ1_DIS_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_IRQ1_DIS_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_IRQ1_DIS_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_IRQ1_DIS_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_IRQ1_DIS_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_IRQ1_DIS_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_IRQ1_DIS_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_IRQ1_DIS_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ1_DIS_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_IRQ2_MASK
 */
#define PMC_GLOBAL_PMC_IRQ2_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020070 )

#define PMC_GLOBAL_PMC_IRQ2_MASK_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_IRQ2_MASK_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_IRQ2_MASK_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_IRQ2_MASK_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_IRQ2_MASK_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_IRQ2_MASK_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_IRQ2_MASK_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_IRQ2_MASK_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_IRQ2_MASK_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_IRQ2_MASK_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_IRQ2_MASK_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_IRQ2_MASK_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_IRQ2_MASK_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_IRQ2_MASK_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_IRQ2_MASK_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_IRQ2_MASK_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_IRQ2_MASK_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_IRQ2_MASK_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_IRQ2_MASK_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_IRQ2_MASK_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_IRQ2_MASK_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_IRQ2_MASK_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_IRQ2_MASK_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_IRQ2_MASK_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_IRQ2_MASK_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_IRQ2_MASK_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_IRQ2_MASK_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_IRQ2_MASK_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_MASK_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_IRQ2_EN
 */
#define PMC_GLOBAL_PMC_IRQ2_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020074 )

#define PMC_GLOBAL_PMC_IRQ2_EN_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_IRQ2_EN_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_IRQ2_EN_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_IRQ2_EN_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_IRQ2_EN_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_IRQ2_EN_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_IRQ2_EN_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_IRQ2_EN_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_IRQ2_EN_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_IRQ2_EN_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_IRQ2_EN_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_IRQ2_EN_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_IRQ2_EN_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_IRQ2_EN_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_IRQ2_EN_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_IRQ2_EN_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_IRQ2_EN_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_IRQ2_EN_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_IRQ2_EN_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_IRQ2_EN_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_IRQ2_EN_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_IRQ2_EN_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_IRQ2_EN_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_IRQ2_EN_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_IRQ2_EN_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_IRQ2_EN_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_IRQ2_EN_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_IRQ2_EN_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_EN_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_IRQ2_DIS
 */
#define PMC_GLOBAL_PMC_IRQ2_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020078 )

#define PMC_GLOBAL_PMC_IRQ2_DIS_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_IRQ2_DIS_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_IRQ2_DIS_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_IRQ2_DIS_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_IRQ2_DIS_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_IRQ2_DIS_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_IRQ2_DIS_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_IRQ2_DIS_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_IRQ2_DIS_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_IRQ2_DIS_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_IRQ2_DIS_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_IRQ2_DIS_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_IRQ2_DIS_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_IRQ2_DIS_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_IRQ2_DIS_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_IRQ2_DIS_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_IRQ2_DIS_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_IRQ2_DIS_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_IRQ2_DIS_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_IRQ2_DIS_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_IRQ2_DIS_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_IRQ2_DIS_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_IRQ2_DIS_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_IRQ2_DIS_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_IRQ2_DIS_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_IRQ2_DIS_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_IRQ2_DIS_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_IRQ2_DIS_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_IRQ2_DIS_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_SRST1_MASK
 */
#define PMC_GLOBAL_PMC_SRST1_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020080 )

#define PMC_GLOBAL_PMC_SRST1_MASK_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_SRST1_MASK_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_SRST1_MASK_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_SRST1_MASK_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_SRST1_MASK_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_SRST1_MASK_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_SRST1_MASK_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_SRST1_MASK_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_SRST1_MASK_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_SRST1_MASK_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_SRST1_MASK_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_SRST1_MASK_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_SRST1_MASK_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_SRST1_MASK_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_SRST1_MASK_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_SRST1_MASK_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_SRST1_MASK_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_SRST1_MASK_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_SRST1_MASK_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_SRST1_MASK_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_SRST1_MASK_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_SRST1_MASK_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_SRST1_MASK_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_SRST1_MASK_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_SRST1_MASK_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_SRST1_MASK_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_SRST1_MASK_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_SRST1_MASK_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_SRST1_MASK_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_SRST1_MASK_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_SRST1_MASK_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_SRST1_MASK_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_SRST1_MASK_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_SRST1_MASK_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_SRST1_MASK_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_SRST1_MASK_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_SRST1_MASK_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_SRST1_MASK_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_SRST1_MASK_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_SRST1_MASK_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_SRST1_MASK_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_SRST1_MASK_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_SRST1_MASK_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_SRST1_MASK_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_SRST1_MASK_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_SRST1_MASK_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_SRST1_MASK_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_SRST1_MASK_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_SRST1_MASK_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_SRST1_MASK_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_SRST1_MASK_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_SRST1_MASK_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_SRST1_MASK_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_SRST1_MASK_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_SRST1_MASK_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_SRST1_MASK_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_SRST1_MASK_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_SRST1_MASK_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_SRST1_MASK_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_SRST1_MASK_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_SRST1_MASK_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_SRST1_MASK_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_SRST1_MASK_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_SRST1_MASK_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_MASK_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_SRST1_EN
 */
#define PMC_GLOBAL_PMC_SRST1_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020084 )

#define PMC_GLOBAL_PMC_SRST1_EN_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_SRST1_EN_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_SRST1_EN_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_SRST1_EN_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_SRST1_EN_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_SRST1_EN_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_SRST1_EN_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_SRST1_EN_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_SRST1_EN_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_SRST1_EN_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_SRST1_EN_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_SRST1_EN_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_SRST1_EN_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_SRST1_EN_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_SRST1_EN_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_SRST1_EN_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_SRST1_EN_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_SRST1_EN_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_SRST1_EN_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_SRST1_EN_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_SRST1_EN_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_SRST1_EN_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_SRST1_EN_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_SRST1_EN_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_SRST1_EN_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_SRST1_EN_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_SRST1_EN_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_SRST1_EN_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_SRST1_EN_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_SRST1_EN_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_SRST1_EN_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_SRST1_EN_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_SRST1_EN_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_SRST1_EN_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_SRST1_EN_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_SRST1_EN_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_SRST1_EN_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_SRST1_EN_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_SRST1_EN_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_SRST1_EN_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_SRST1_EN_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_SRST1_EN_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_SRST1_EN_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_SRST1_EN_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_SRST1_EN_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_SRST1_EN_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_SRST1_EN_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_SRST1_EN_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_SRST1_EN_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_SRST1_EN_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_SRST1_EN_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_SRST1_EN_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_SRST1_EN_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_SRST1_EN_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_SRST1_EN_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_SRST1_EN_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_SRST1_EN_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_SRST1_EN_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_SRST1_EN_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_SRST1_EN_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_SRST1_EN_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_SRST1_EN_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_SRST1_EN_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_SRST1_EN_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_EN_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_SRST1_DIS
 */
#define PMC_GLOBAL_PMC_SRST1_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020088 )

#define PMC_GLOBAL_PMC_SRST1_DIS_SSIT_ERR5_SHIFT   31
#define PMC_GLOBAL_PMC_SRST1_DIS_SSIT_ERR5_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_SSIT_ERR5_MASK    0X80000000

#define PMC_GLOBAL_PMC_SRST1_DIS_SSIT_ERR4_SHIFT   30
#define PMC_GLOBAL_PMC_SRST1_DIS_SSIT_ERR4_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_SSIT_ERR4_MASK    0X40000000

#define PMC_GLOBAL_PMC_SRST1_DIS_SSIT_ERR3_SHIFT   29
#define PMC_GLOBAL_PMC_SRST1_DIS_SSIT_ERR3_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_SSIT_ERR3_MASK    0X20000000

#define PMC_GLOBAL_PMC_SRST1_DIS_NPI_ROOT_SHIFT   28
#define PMC_GLOBAL_PMC_SRST1_DIS_NPI_ROOT_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_NPI_ROOT_MASK    0X10000000

#define PMC_GLOBAL_PMC_SRST1_DIS_PL3_SHIFT   27
#define PMC_GLOBAL_PMC_SRST1_DIS_PL3_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_PL3_MASK    0X08000000

#define PMC_GLOBAL_PMC_SRST1_DIS_PL2_SHIFT   26
#define PMC_GLOBAL_PMC_SRST1_DIS_PL2_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_PL2_MASK    0X04000000

#define PMC_GLOBAL_PMC_SRST1_DIS_PL1_SHIFT   25
#define PMC_GLOBAL_PMC_SRST1_DIS_PL1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_PL1_MASK    0X02000000

#define PMC_GLOBAL_PMC_SRST1_DIS_PL0_SHIFT   24
#define PMC_GLOBAL_PMC_SRST1_DIS_PL0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_PL0_MASK    0X01000000

#define PMC_GLOBAL_PMC_SRST1_DIS_PL_SMON_NCR_SHIFT   23
#define PMC_GLOBAL_PMC_SRST1_DIS_PL_SMON_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_PL_SMON_NCR_MASK    0X00800000

#define PMC_GLOBAL_PMC_SRST1_DIS_PL_SMON_CR_SHIFT   22
#define PMC_GLOBAL_PMC_SRST1_DIS_PL_SMON_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_PL_SMON_CR_MASK    0X00400000

#define PMC_GLOBAL_PMC_SRST1_DIS_GT_NCR_SHIFT   21
#define PMC_GLOBAL_PMC_SRST1_DIS_GT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_GT_NCR_MASK    0X00200000

#define PMC_GLOBAL_PMC_SRST1_DIS_GT_CR_SHIFT   20
#define PMC_GLOBAL_PMC_SRST1_DIS_GT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_GT_CR_MASK    0X00100000

#define PMC_GLOBAL_PMC_SRST1_DIS_DDRMC_MC_NCR_SHIFT   19
#define PMC_GLOBAL_PMC_SRST1_DIS_DDRMC_MC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_DDRMC_MC_NCR_MASK    0X00080000

#define PMC_GLOBAL_PMC_SRST1_DIS_DDRMC_MC_CR_SHIFT   18
#define PMC_GLOBAL_PMC_SRST1_DIS_DDRMC_MC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_DDRMC_MC_CR_MASK    0X00040000

#define PMC_GLOBAL_PMC_SRST1_DIS_ME_NCR_SHIFT   17
#define PMC_GLOBAL_PMC_SRST1_DIS_ME_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_ME_NCR_MASK    0X00020000

#define PMC_GLOBAL_PMC_SRST1_DIS_ME_CR_SHIFT   16
#define PMC_GLOBAL_PMC_SRST1_DIS_ME_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_ME_CR_MASK    0X00010000

#define PMC_GLOBAL_PMC_SRST1_DIS_MMCM_SHIFT   15
#define PMC_GLOBAL_PMC_SRST1_DIS_MMCM_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_MMCM_MASK    0X00008000

#define PMC_GLOBAL_PMC_SRST1_DIS_NOC_USER_SHIFT   14
#define PMC_GLOBAL_PMC_SRST1_DIS_NOC_USER_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_NOC_USER_MASK    0X00004000

#define PMC_GLOBAL_PMC_SRST1_DIS_NOC_TYPE1_NCR_SHIFT   13
#define PMC_GLOBAL_PMC_SRST1_DIS_NOC_TYPE1_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_NOC_TYPE1_NCR_MASK    0X00002000

#define PMC_GLOBAL_PMC_SRST1_DIS_NOC_TYPE1_CR_SHIFT   12
#define PMC_GLOBAL_PMC_SRST1_DIS_NOC_TYPE1_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_NOC_TYPE1_CR_MASK    0X00001000

#define PMC_GLOBAL_PMC_SRST1_DIS_DDRMC_MB_NCR_SHIFT   11
#define PMC_GLOBAL_PMC_SRST1_DIS_DDRMC_MB_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_DDRMC_MB_NCR_MASK    0X00000800

#define PMC_GLOBAL_PMC_SRST1_DIS_DDRMC_MB_CR_SHIFT   10
#define PMC_GLOBAL_PMC_SRST1_DIS_DDRMC_MB_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_DDRMC_MB_CR_MASK    0X00000400

#define PMC_GLOBAL_PMC_SRST1_DIS_PSM_NCR_SHIFT   9
#define PMC_GLOBAL_PMC_SRST1_DIS_PSM_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_PSM_NCR_MASK    0X00000200

#define PMC_GLOBAL_PMC_SRST1_DIS_PSM_CR_SHIFT   8
#define PMC_GLOBAL_PMC_SRST1_DIS_PSM_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_PSM_CR_MASK    0X00000100

#define PMC_GLOBAL_PMC_SRST1_DIS_CFRAME_SHIFT   7
#define PMC_GLOBAL_PMC_SRST1_DIS_CFRAME_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_CFRAME_MASK    0X00000080

#define PMC_GLOBAL_PMC_SRST1_DIS_CFU_SHIFT   6
#define PMC_GLOBAL_PMC_SRST1_DIS_CFU_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_CFU_MASK    0X00000040

#define PMC_GLOBAL_PMC_SRST1_DIS_GSW_NCR_SHIFT   5
#define PMC_GLOBAL_PMC_SRST1_DIS_GSW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_GSW_NCR_MASK    0X00000020

#define PMC_GLOBAL_PMC_SRST1_DIS_GSW_CR_SHIFT   4
#define PMC_GLOBAL_PMC_SRST1_DIS_GSW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_GSW_CR_MASK    0X00000010

#define PMC_GLOBAL_PMC_SRST1_DIS_FW_NCR_SHIFT   3
#define PMC_GLOBAL_PMC_SRST1_DIS_FW_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_FW_NCR_MASK    0X00000008

#define PMC_GLOBAL_PMC_SRST1_DIS_FW_CR_SHIFT   2
#define PMC_GLOBAL_PMC_SRST1_DIS_FW_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_FW_CR_MASK    0X00000004

#define PMC_GLOBAL_PMC_SRST1_DIS_BOOT_NCR_SHIFT   1
#define PMC_GLOBAL_PMC_SRST1_DIS_BOOT_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_BOOT_NCR_MASK    0X00000002

#define PMC_GLOBAL_PMC_SRST1_DIS_BOOT_CR_SHIFT   0
#define PMC_GLOBAL_PMC_SRST1_DIS_BOOT_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST1_DIS_BOOT_CR_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_SRST2_MASK
 */
#define PMC_GLOBAL_PMC_SRST2_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020090 )

#define PMC_GLOBAL_PMC_SRST2_MASK_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_SRST2_MASK_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_SRST2_MASK_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_SRST2_MASK_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_SRST2_MASK_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_SRST2_MASK_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_SRST2_MASK_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_SRST2_MASK_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_SRST2_MASK_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_SRST2_MASK_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_SRST2_MASK_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_SRST2_MASK_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_SRST2_MASK_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_SRST2_MASK_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_SRST2_MASK_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_SRST2_MASK_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_SRST2_MASK_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_SRST2_MASK_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_SRST2_MASK_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_SRST2_MASK_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_SRST2_MASK_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_SRST2_MASK_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_SRST2_MASK_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_SRST2_MASK_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_SRST2_MASK_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_SRST2_MASK_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_SRST2_MASK_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_SRST2_MASK_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_MASK_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_SRST2_EN
 */
#define PMC_GLOBAL_PMC_SRST2_EN    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020094 )

#define PMC_GLOBAL_PMC_SRST2_EN_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_SRST2_EN_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_SRST2_EN_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_SRST2_EN_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_SRST2_EN_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_SRST2_EN_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_SRST2_EN_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_SRST2_EN_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_SRST2_EN_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_SRST2_EN_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_SRST2_EN_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_SRST2_EN_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_SRST2_EN_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_SRST2_EN_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_SRST2_EN_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_SRST2_EN_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_SRST2_EN_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_SRST2_EN_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_SRST2_EN_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_SRST2_EN_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_SRST2_EN_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_SRST2_EN_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_SRST2_EN_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_SRST2_EN_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_SRST2_EN_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_SRST2_EN_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_SRST2_EN_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_SRST2_EN_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_SRST2_EN_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_EN_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_SRST2_DIS
 */
#define PMC_GLOBAL_PMC_SRST2_DIS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020098 )

#define PMC_GLOBAL_PMC_SRST2_DIS_SSIT_ERR2_SHIFT   31
#define PMC_GLOBAL_PMC_SRST2_DIS_SSIT_ERR2_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_SSIT_ERR2_MASK    0X80000000

#define PMC_GLOBAL_PMC_SRST2_DIS_SSIT_ERR1_SHIFT   30
#define PMC_GLOBAL_PMC_SRST2_DIS_SSIT_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_SSIT_ERR1_MASK    0X40000000

#define PMC_GLOBAL_PMC_SRST2_DIS_SSIT_ERR0_SHIFT   29
#define PMC_GLOBAL_PMC_SRST2_DIS_SSIT_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_SSIT_ERR0_MASK    0X20000000

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_XPPU_SHIFT   28
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_XPPU_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_XPPU_MASK    0X10000000

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_XMPU_SHIFT   27
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_XMPU_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_XMPU_MASK    0X08000000

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_TO_SHIFT   26
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_TO_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_TO_MASK    0X04000000

#define PMC_GLOBAL_PMC_SRST2_DIS_CLK_MON_SHIFT   25
#define PMC_GLOBAL_PMC_SRST2_DIS_CLK_MON_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_CLK_MON_MASK    0X02000000

#define PMC_GLOBAL_PMC_SRST2_DIS_PPLL_SHIFT   24
#define PMC_GLOBAL_PMC_SRST2_DIS_PPLL_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PPLL_MASK    0X01000000

#define PMC_GLOBAL_PMC_SRST2_DIS_NPLL_SHIFT   23
#define PMC_GLOBAL_PMC_SRST2_DIS_NPLL_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_NPLL_MASK    0X00800000

#define PMC_GLOBAL_PMC_SRST2_DIS_RTC_ALARM_SHIFT   22
#define PMC_GLOBAL_PMC_SRST2_DIS_RTC_ALARM_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_RTC_ALARM_MASK    0X00400000

#define PMC_GLOBAL_PMC_SRST2_DIS_RSRV_ERR1_SHIFT   21
#define PMC_GLOBAL_PMC_SRST2_DIS_RSRV_ERR1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_RSRV_ERR1_MASK    0X00200000

#define PMC_GLOBAL_PMC_SRST2_DIS_RSRV_ERR0_SHIFT   20
#define PMC_GLOBAL_PMC_SRST2_DIS_RSRV_ERR0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_RSRV_ERR0_MASK    0X00100000

#define PMC_GLOBAL_PMC_SRST2_DIS_CFRAME_SEU_ECC_SHIFT   19
#define PMC_GLOBAL_PMC_SRST2_DIS_CFRAME_SEU_ECC_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_CFRAME_SEU_ECC_MASK    0X00080000

#define PMC_GLOBAL_PMC_SRST2_DIS_CFRAME_SEU_CRC_SHIFT   18
#define PMC_GLOBAL_PMC_SRST2_DIS_CFRAME_SEU_CRC_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_CFRAME_SEU_CRC_MASK    0X00040000

#define PMC_GLOBAL_PMC_SRST2_DIS_CFI_SHIFT   17
#define PMC_GLOBAL_PMC_SRST2_DIS_CFI_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_CFI_MASK    0X00020000

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON9_SHIFT   16
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON9_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON9_MASK    0X00010000

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON8_SHIFT   15
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON8_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON8_MASK    0X00008000

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON7_SHIFT   14
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON7_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON7_MASK    0X00004000

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON6_SHIFT   13
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON6_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON6_MASK    0X00002000

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON5_SHIFT   12
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON5_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON5_MASK    0X00001000

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON4_SHIFT   11
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON4_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON4_MASK    0X00000800

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON3_SHIFT   10
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON3_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON3_MASK    0X00000400

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON2_SHIFT   9
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON2_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON2_MASK    0X00000200

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON1_SHIFT   8
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON1_MASK    0X00000100

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON0_SHIFT   7
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_SMON0_MASK    0X00000080

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_NCR_SHIFT   6
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_NCR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_NCR_MASK    0X00000040

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_CR_SHIFT   5
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_CR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_CR_MASK    0X00000020

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_PAR_SHIFT   4
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_PAR_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_PAR_MASK    0X00000010

#define PMC_GLOBAL_PMC_SRST2_DIS_MB_FATAL1_SHIFT   3
#define PMC_GLOBAL_PMC_SRST2_DIS_MB_FATAL1_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_MB_FATAL1_MASK    0X00000008

#define PMC_GLOBAL_PMC_SRST2_DIS_MB_FATAL0_SHIFT   2
#define PMC_GLOBAL_PMC_SRST2_DIS_MB_FATAL0_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_MB_FATAL0_MASK    0X00000004

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_ROM_SHIFT   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_ROM_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_ROM_MASK    0X00000002

#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_APB_SHIFT   0
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_APB_WIDTH   1
#define PMC_GLOBAL_PMC_SRST2_DIS_PMC_APB_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PMC_BOOT_ERR
 */
#define PMC_GLOBAL_PMC_BOOT_ERR    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020100 )

#define PMC_GLOBAL_PMC_BOOT_ERR_DATA_SHIFT   0
#define PMC_GLOBAL_PMC_BOOT_ERR_DATA_WIDTH   30
#define PMC_GLOBAL_PMC_BOOT_ERR_DATA_MASK    0X3FFFFFFF

/**
 * Register: PMC_GLOBAL_ERROR_MANAGEMENT_POR_LOCK
 */
#define PMC_GLOBAL_ERROR_MANAGEMENT_POR_LOCK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00020200 )

#define PMC_GLOBAL_ERROR_MANAGEMENT_POR_LOCK_LOCK_SHIFT   0
#define PMC_GLOBAL_ERROR_MANAGEMENT_POR_LOCK_LOCK_WIDTH   1
#define PMC_GLOBAL_ERROR_MANAGEMENT_POR_LOCK_LOCK_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP0_IRQ_STATUS
 */
#define PMC_GLOBAL_GICP0_IRQ_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030000 )

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_STATUS_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP0_IRQ_MASK
 */
#define PMC_GLOBAL_GICP0_IRQ_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030004 )

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_MASK_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP0_IRQ_ENABLE
 */
#define PMC_GLOBAL_GICP0_IRQ_ENABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030008 )

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_ENABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP0_IRQ_DISABLE
 */
#define PMC_GLOBAL_GICP0_IRQ_DISABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X0003000C )

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_DISABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP0_IRQ_TRIGGER
 */
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030010 )

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP0_IRQ_TRIGGER_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP1_IRQ_STATUS
 */
#define PMC_GLOBAL_GICP1_IRQ_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030014 )

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_STATUS_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP1_IRQ_MASK
 */
#define PMC_GLOBAL_GICP1_IRQ_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030018 )

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_MASK_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP1_IRQ_ENABLE
 */
#define PMC_GLOBAL_GICP1_IRQ_ENABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X0003001C )

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_ENABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP1_IRQ_DISABLE
 */
#define PMC_GLOBAL_GICP1_IRQ_DISABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030020 )

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_DISABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP1_IRQ_TRIGGER
 */
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030024 )

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP1_IRQ_TRIGGER_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP2_IRQ_STATUS
 */
#define PMC_GLOBAL_GICP2_IRQ_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030028 )

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_STATUS_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP2_IRQ_MASK
 */
#define PMC_GLOBAL_GICP2_IRQ_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X0003002C )

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_MASK_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP2_IRQ_ENABLE
 */
#define PMC_GLOBAL_GICP2_IRQ_ENABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030030 )

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_ENABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP2_IRQ_DISABLE
 */
#define PMC_GLOBAL_GICP2_IRQ_DISABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030034 )

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_DISABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP2_IRQ_TRIGGER
 */
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030038 )

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP2_IRQ_TRIGGER_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP3_IRQ_STATUS
 */
#define PMC_GLOBAL_GICP3_IRQ_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X0003003C )

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_STATUS_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP3_IRQ_MASK
 */
#define PMC_GLOBAL_GICP3_IRQ_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030040 )

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_MASK_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP3_IRQ_ENABLE
 */
#define PMC_GLOBAL_GICP3_IRQ_ENABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030044 )

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_ENABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP3_IRQ_DISABLE
 */
#define PMC_GLOBAL_GICP3_IRQ_DISABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030048 )

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_DISABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP3_IRQ_TRIGGER
 */
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER    ( ( PMC_GLOBAL_BASEADDR ) + 0X0003004C )

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP3_IRQ_TRIGGER_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP4_IRQ_STATUS
 */
#define PMC_GLOBAL_GICP4_IRQ_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030050 )

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_STATUS_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP4_IRQ_MASK
 */
#define PMC_GLOBAL_GICP4_IRQ_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030054 )

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_MASK_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP4_IRQ_ENABLE
 */
#define PMC_GLOBAL_GICP4_IRQ_ENABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030058 )

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_ENABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP4_IRQ_DISABLE
 */
#define PMC_GLOBAL_GICP4_IRQ_DISABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X0003005C )

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_DISABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP4_IRQ_TRIGGER
 */
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030060 )

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP4_IRQ_TRIGGER_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP5_IRQ_STATUS
 */
#define PMC_GLOBAL_GICP5_IRQ_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030064 )

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_STATUS_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP5_IRQ_MASK
 */
#define PMC_GLOBAL_GICP5_IRQ_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030068 )

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_MASK_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP5_IRQ_ENABLE
 */
#define PMC_GLOBAL_GICP5_IRQ_ENABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X0003006C )

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_ENABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP5_IRQ_DISABLE
 */
#define PMC_GLOBAL_GICP5_IRQ_DISABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030070 )

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_DISABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP5_IRQ_TRIGGER
 */
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030074 )

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP5_IRQ_TRIGGER_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP6_IRQ_STATUS
 */
#define PMC_GLOBAL_GICP6_IRQ_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030078 )

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_STATUS_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP6_IRQ_MASK
 */
#define PMC_GLOBAL_GICP6_IRQ_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X0003007C )

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_MASK_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP6_IRQ_ENABLE
 */
#define PMC_GLOBAL_GICP6_IRQ_ENABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030080 )

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_ENABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP6_IRQ_DISABLE
 */
#define PMC_GLOBAL_GICP6_IRQ_DISABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030084 )

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_DISABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP6_IRQ_TRIGGER
 */
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030088 )

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP6_IRQ_TRIGGER_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP7_IRQ_STATUS
 */
#define PMC_GLOBAL_GICP7_IRQ_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X0003008C )

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_STATUS_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP7_IRQ_MASK
 */
#define PMC_GLOBAL_GICP7_IRQ_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030090 )

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_MASK_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP7_IRQ_ENABLE
 */
#define PMC_GLOBAL_GICP7_IRQ_ENABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030094 )

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_ENABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP7_IRQ_DISABLE
 */
#define PMC_GLOBAL_GICP7_IRQ_DISABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X00030098 )

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_DISABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP7_IRQ_TRIGGER
 */
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER    ( ( PMC_GLOBAL_BASEADDR ) + 0X0003009C )

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC31_SHIFT   31
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC31_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC31_MASK    0X80000000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC30_SHIFT   30
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC30_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC30_MASK    0X40000000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC29_SHIFT   29
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC29_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC29_MASK    0X20000000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC28_SHIFT   28
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC28_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC28_MASK    0X10000000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC27_SHIFT   27
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC27_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC27_MASK    0X08000000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC26_SHIFT   26
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC26_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC26_MASK    0X04000000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC25_SHIFT   25
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC25_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC25_MASK    0X02000000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC24_SHIFT   24
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC24_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC24_MASK    0X01000000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC23_SHIFT   23
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC23_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC23_MASK    0X00800000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC22_SHIFT   22
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC22_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC22_MASK    0X00400000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC21_SHIFT   21
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC21_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC21_MASK    0X00200000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC20_SHIFT   20
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC20_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC20_MASK    0X00100000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC19_SHIFT   19
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC19_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC19_MASK    0X00080000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC18_SHIFT   18
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC18_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC18_MASK    0X00040000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC17_SHIFT   17
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC17_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC17_MASK    0X00020000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC16_SHIFT   16
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC16_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC16_MASK    0X00010000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC15_SHIFT   15
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC15_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC15_MASK    0X00008000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC14_SHIFT   14
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC14_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC14_MASK    0X00004000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC13_SHIFT   13
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC13_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC13_MASK    0X00002000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC12_SHIFT   12
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC12_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC12_MASK    0X00001000

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC11_SHIFT   11
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC11_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC11_MASK    0X00000800

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC10_SHIFT   10
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC10_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC10_MASK    0X00000400

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC9_SHIFT   9
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC9_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC9_MASK    0X00000200

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC8_SHIFT   8
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC8_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC8_MASK    0X00000100

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP7_IRQ_TRIGGER_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP_PMC_IRQ_STATUS
 */
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X000300A0 )

#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_STATUS_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP_PMC_IRQ_MASK
 */
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK    ( ( PMC_GLOBAL_BASEADDR ) + 0X000300A4 )

#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_MASK_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP_PMC_IRQ_ENABLE
 */
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X000300A8 )

#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_ENABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP_PMC_IRQ_DISABLE
 */
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE    ( ( PMC_GLOBAL_BASEADDR ) + 0X000300AC )

#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_DISABLE_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER
 */
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER    ( ( PMC_GLOBAL_BASEADDR ) + 0X000300B0 )

#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC7_SHIFT   7
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC7_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC7_MASK    0X00000080

#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC6_SHIFT   6
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC6_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC6_MASK    0X00000040

#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC5_SHIFT   5
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC5_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC5_MASK    0X00000020

#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC4_SHIFT   4
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC4_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC4_MASK    0X00000010

#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC3_SHIFT   3
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC3_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC3_MASK    0X00000008

#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC2_SHIFT   2
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC2_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC2_MASK    0X00000004

#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC1_SHIFT   1
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC1_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC1_MASK    0X00000002

#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC0_SHIFT   0
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC0_WIDTH   1
#define PMC_GLOBAL_GICP_PMC_IRQ_TRIGGER_SRC0_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PUF_CMD
 */
#define PMC_GLOBAL_PUF_CMD    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040000 )

#define PMC_GLOBAL_PUF_CMD_CMD_SHIFT   0
#define PMC_GLOBAL_PUF_CMD_CMD_WIDTH   32
#define PMC_GLOBAL_PUF_CMD_CMD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_CFG0
 */
#define PMC_GLOBAL_PUF_CFG0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040004 )

#define PMC_GLOBAL_PUF_CFG0_CFG0_SHIFT   2
#define PMC_GLOBAL_PUF_CFG0_CFG0_WIDTH   30
#define PMC_GLOBAL_PUF_CFG0_CFG0_MASK    0XFFFFFFFC

#define PMC_GLOBAL_PUF_CFG0_HASH_SEL_SHIFT   1
#define PMC_GLOBAL_PUF_CFG0_HASH_SEL_WIDTH   1
#define PMC_GLOBAL_PUF_CFG0_HASH_SEL_MASK    0X00000002

#define PMC_GLOBAL_PUF_CFG0_GLBL_FILTER_SHIFT   0
#define PMC_GLOBAL_PUF_CFG0_GLBL_FILTER_WIDTH   1
#define PMC_GLOBAL_PUF_CFG0_GLBL_FILTER_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PUF_CFG1
 */
#define PMC_GLOBAL_PUF_CFG1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040008 )

#define PMC_GLOBAL_PUF_CFG1_CFG1_SHIFT   0
#define PMC_GLOBAL_PUF_CFG1_CFG1_WIDTH   32
#define PMC_GLOBAL_PUF_CFG1_CFG1_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SHUT
 */
#define PMC_GLOBAL_PUF_SHUT    ( ( PMC_GLOBAL_BASEADDR ) + 0X0004000C )

#define PMC_GLOBAL_PUF_SHUT_SOSET_SHIFT   24
#define PMC_GLOBAL_PUF_SHUT_SOSET_WIDTH   8
#define PMC_GLOBAL_PUF_SHUT_SOSET_MASK    0XFF000000

#define PMC_GLOBAL_PUF_SHUT_SOPEN_SHIFT   0
#define PMC_GLOBAL_PUF_SHUT_SOPEN_WIDTH   24
#define PMC_GLOBAL_PUF_SHUT_SOPEN_MASK    0X00FFFFFF

/**
 * Register: PMC_GLOBAL_PUF_STATUS
 */
#define PMC_GLOBAL_PUF_STATUS    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040010 )

#define PMC_GLOBAL_PUF_STATUS_DONE_SHIFT   30
#define PMC_GLOBAL_PUF_STATUS_DONE_WIDTH   1
#define PMC_GLOBAL_PUF_STATUS_DONE_MASK    0X40000000

#define PMC_GLOBAL_PUF_STATUS_KEY_RDY_SHIFT   3
#define PMC_GLOBAL_PUF_STATUS_KEY_RDY_WIDTH   1
#define PMC_GLOBAL_PUF_STATUS_KEY_RDY_MASK    0X00000008

#define PMC_GLOBAL_PUF_STATUS_ID_RDY_SHIFT   2
#define PMC_GLOBAL_PUF_STATUS_ID_RDY_WIDTH   1
#define PMC_GLOBAL_PUF_STATUS_ID_RDY_MASK    0X00000004

#define PMC_GLOBAL_PUF_STATUS_ID_ZERO_SHIFT   1
#define PMC_GLOBAL_PUF_STATUS_ID_ZERO_WIDTH   1
#define PMC_GLOBAL_PUF_STATUS_ID_ZERO_MASK    0X00000002

#define PMC_GLOBAL_PUF_STATUS_SYN_WRD_RDY_SHIFT   0
#define PMC_GLOBAL_PUF_STATUS_SYN_WRD_RDY_WIDTH   1
#define PMC_GLOBAL_PUF_STATUS_SYN_WRD_RDY_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PUF_WORD
 */
#define PMC_GLOBAL_PUF_WORD    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040018 )

#define PMC_GLOBAL_PUF_WORD_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_WORD_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_WORD_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SYN_ADDR
 */
#define PMC_GLOBAL_PUF_SYN_ADDR    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040020 )

#define PMC_GLOBAL_PUF_SYN_ADDR_ADDR_SHIFT   0
#define PMC_GLOBAL_PUF_SYN_ADDR_ADDR_WIDTH   32
#define PMC_GLOBAL_PUF_SYN_ADDR_ADDR_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_AUX
 */
#define PMC_GLOBAL_PUF_AUX    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040024 )

#define PMC_GLOBAL_PUF_AUX_DATA_SHIFT   4
#define PMC_GLOBAL_PUF_AUX_DATA_WIDTH   24
#define PMC_GLOBAL_PUF_AUX_DATA_MASK    0X0FFFFFF0

/**
 * Register: PMC_GLOBAL_PUF_CHASH
 */
#define PMC_GLOBAL_PUF_CHASH    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040028 )

#define PMC_GLOBAL_PUF_CHASH_DATA_SHIFT   0
#define PMC_GLOBAL_PUF_CHASH_DATA_WIDTH   32
#define PMC_GLOBAL_PUF_CHASH_DATA_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_CLEAR
 */
#define PMC_GLOBAL_PUF_CLEAR    ( ( PMC_GLOBAL_BASEADDR ) + 0X0004002C )

#define PMC_GLOBAL_PUF_CLEAR_ID_SHIFT   0
#define PMC_GLOBAL_PUF_CLEAR_ID_WIDTH   1
#define PMC_GLOBAL_PUF_CLEAR_ID_MASK    0X00000001

/**
 * Register: PMC_GLOBAL_PUF_ID_0
 */
#define PMC_GLOBAL_PUF_ID_0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040030 )

#define PMC_GLOBAL_PUF_ID_0_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_ID_0_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_ID_0_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_ID_1
 */
#define PMC_GLOBAL_PUF_ID_1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040034 )

#define PMC_GLOBAL_PUF_ID_1_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_ID_1_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_ID_1_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_ID_2
 */
#define PMC_GLOBAL_PUF_ID_2    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040038 )

#define PMC_GLOBAL_PUF_ID_2_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_ID_2_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_ID_2_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_ID_3
 */
#define PMC_GLOBAL_PUF_ID_3    ( ( PMC_GLOBAL_BASEADDR ) + 0X0004003C )

#define PMC_GLOBAL_PUF_ID_3_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_ID_3_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_ID_3_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_ID_4
 */
#define PMC_GLOBAL_PUF_ID_4    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040040 )

#define PMC_GLOBAL_PUF_ID_4_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_ID_4_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_ID_4_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_ID_5
 */
#define PMC_GLOBAL_PUF_ID_5    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040044 )

#define PMC_GLOBAL_PUF_ID_5_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_ID_5_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_ID_5_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_ID_6
 */
#define PMC_GLOBAL_PUF_ID_6    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040048 )

#define PMC_GLOBAL_PUF_ID_6_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_ID_6_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_ID_6_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_ID_7
 */
#define PMC_GLOBAL_PUF_ID_7    ( ( PMC_GLOBAL_BASEADDR ) + 0X0004004C )

#define PMC_GLOBAL_PUF_ID_7_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_ID_7_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_ID_7_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_0
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_0    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040050 )

#define PMC_GLOBAL_PUF_SEG_STATUS_0_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_0_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_0_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_1
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_1    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040054 )

#define PMC_GLOBAL_PUF_SEG_STATUS_1_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_1_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_1_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_2
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_2    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040058 )

#define PMC_GLOBAL_PUF_SEG_STATUS_2_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_2_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_2_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_3
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_3    ( ( PMC_GLOBAL_BASEADDR ) + 0X0004005C )

#define PMC_GLOBAL_PUF_SEG_STATUS_3_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_3_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_3_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_4
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_4    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040060 )

#define PMC_GLOBAL_PUF_SEG_STATUS_4_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_4_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_4_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_5
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_5    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040064 )

#define PMC_GLOBAL_PUF_SEG_STATUS_5_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_5_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_5_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_6
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_6    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040068 )

#define PMC_GLOBAL_PUF_SEG_STATUS_6_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_6_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_6_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_7
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_7    ( ( PMC_GLOBAL_BASEADDR ) + 0X0004006C )

#define PMC_GLOBAL_PUF_SEG_STATUS_7_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_7_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_7_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_8
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_8    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040070 )

#define PMC_GLOBAL_PUF_SEG_STATUS_8_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_8_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_8_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_9
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_9    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040074 )

#define PMC_GLOBAL_PUF_SEG_STATUS_9_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_9_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_9_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_10
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_10    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040078 )

#define PMC_GLOBAL_PUF_SEG_STATUS_10_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_10_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_10_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_11
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_11    ( ( PMC_GLOBAL_BASEADDR ) + 0X0004007C )

#define PMC_GLOBAL_PUF_SEG_STATUS_11_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_11_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_11_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_12
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_12    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040080 )

#define PMC_GLOBAL_PUF_SEG_STATUS_12_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_12_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_12_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_13
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_13    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040084 )

#define PMC_GLOBAL_PUF_SEG_STATUS_13_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_13_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_13_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_14
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_14    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040088 )

#define PMC_GLOBAL_PUF_SEG_STATUS_14_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_14_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_14_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_15
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_15    ( ( PMC_GLOBAL_BASEADDR ) + 0X0004008C )

#define PMC_GLOBAL_PUF_SEG_STATUS_15_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_15_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_15_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_16
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_16    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040090 )

#define PMC_GLOBAL_PUF_SEG_STATUS_16_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_16_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_16_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_17
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_17    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040094 )

#define PMC_GLOBAL_PUF_SEG_STATUS_17_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_17_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_17_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_18
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_18    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040098 )

#define PMC_GLOBAL_PUF_SEG_STATUS_18_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_18_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_18_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_19
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_19    ( ( PMC_GLOBAL_BASEADDR ) + 0X0004009C )

#define PMC_GLOBAL_PUF_SEG_STATUS_19_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_19_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_19_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_20
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_20    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400A0 )

#define PMC_GLOBAL_PUF_SEG_STATUS_20_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_20_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_20_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_21
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_21    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400A4 )

#define PMC_GLOBAL_PUF_SEG_STATUS_21_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_21_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_21_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_22
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_22    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400A8 )

#define PMC_GLOBAL_PUF_SEG_STATUS_22_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_22_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_22_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_23
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_23    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400AC )

#define PMC_GLOBAL_PUF_SEG_STATUS_23_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_23_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_23_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_24
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_24    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400B0 )

#define PMC_GLOBAL_PUF_SEG_STATUS_24_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_24_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_24_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_25
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_25    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400B4 )

#define PMC_GLOBAL_PUF_SEG_STATUS_25_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_25_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_25_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_26
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_26    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400B8 )

#define PMC_GLOBAL_PUF_SEG_STATUS_26_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_26_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_26_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_27
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_27    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400BC )

#define PMC_GLOBAL_PUF_SEG_STATUS_27_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_27_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_27_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_28
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_28    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400C0 )

#define PMC_GLOBAL_PUF_SEG_STATUS_28_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_28_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_28_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_29
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_29    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400C4 )

#define PMC_GLOBAL_PUF_SEG_STATUS_29_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_29_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_29_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_30
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_30    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400C8 )

#define PMC_GLOBAL_PUF_SEG_STATUS_30_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_30_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_30_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_31
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_31    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400CC )

#define PMC_GLOBAL_PUF_SEG_STATUS_31_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_31_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_31_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_32
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_32    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400D0 )

#define PMC_GLOBAL_PUF_SEG_STATUS_32_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_32_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_32_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_33
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_33    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400D4 )

#define PMC_GLOBAL_PUF_SEG_STATUS_33_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_33_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_33_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_SEG_STATUS_34
 */
#define PMC_GLOBAL_PUF_SEG_STATUS_34    ( ( PMC_GLOBAL_BASEADDR ) + 0X000400D8 )

#define PMC_GLOBAL_PUF_SEG_STATUS_34_WORD_SHIFT   0
#define PMC_GLOBAL_PUF_SEG_STATUS_34_WORD_WIDTH   32
#define PMC_GLOBAL_PUF_SEG_STATUS_34_WORD_MASK    0XFFFFFFFF

/**
 * Register: PMC_GLOBAL_PUF_TM_UL
 */
#define PMC_GLOBAL_PUF_TM_UL    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040808 )

#define PMC_GLOBAL_PUF_TM_UL_UL_SHIFT   0
#define PMC_GLOBAL_PUF_TM_UL_UL_WIDTH   18
#define PMC_GLOBAL_PUF_TM_UL_UL_MASK    0X0003FFFF

/**
 * Register: PMC_GLOBAL_PUF_TM_LL
 */
#define PMC_GLOBAL_PUF_TM_LL    ( ( PMC_GLOBAL_BASEADDR ) + 0X0004080C )

#define PMC_GLOBAL_PUF_TM_LL_LL_SHIFT   0
#define PMC_GLOBAL_PUF_TM_LL_LL_WIDTH   18
#define PMC_GLOBAL_PUF_TM_LL_LL_MASK    0X0003FFFF

/**
 * Register: PMC_GLOBAL_PUF_TM_SW
 */
#define PMC_GLOBAL_PUF_TM_SW    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040810 )

#define PMC_GLOBAL_PUF_TM_SW_OFF_SHIFT   24
#define PMC_GLOBAL_PUF_TM_SW_OFF_WIDTH   8
#define PMC_GLOBAL_PUF_TM_SW_OFF_MASK    0XFF000000

#define PMC_GLOBAL_PUF_TM_SW_SW_SHIFT   0
#define PMC_GLOBAL_PUF_TM_SW_SW_WIDTH   24
#define PMC_GLOBAL_PUF_TM_SW_SW_MASK    0X00FFFFFF

/**
 * Register: PMC_GLOBAL_PUF_TM_TR
 */
#define PMC_GLOBAL_PUF_TM_TR    ( ( PMC_GLOBAL_BASEADDR ) + 0X00040814 )

#define PMC_GLOBAL_PUF_TM_TR_US_SHIFT   24
#define PMC_GLOBAL_PUF_TM_TR_US_WIDTH   2
#define PMC_GLOBAL_PUF_TM_TR_US_MASK    0X03000000

#define PMC_GLOBAL_PUF_TM_TR_ER_SHIFT   16
#define PMC_GLOBAL_PUF_TM_TR_ER_WIDTH   8
#define PMC_GLOBAL_PUF_TM_TR_ER_MASK    0X00FF0000

#define PMC_GLOBAL_PUF_TM_TR_FRR_SHIFT   0
#define PMC_GLOBAL_PUF_TM_TR_FRR_WIDTH   1
#define PMC_GLOBAL_PUF_TM_TR_FRR_MASK    0X00000001

#ifdef __cplusplus
}
#endif


#endif /* _PMC_GLOBAL_H_ */
