axidma: xaxidma_example_multichan_sg_intr.c File Reference

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xaxidma_example_multichan_sg_intr.c File Reference

## Overview

This file demonstrates how to use the xaxidma driver on the Xilinx AXI DMA core v6_00_a (AXIDMA) to transfer packets in interrupt mode for Multiple Channel capability.

Thi example is designed to work only when AXIDMA core is configured in Scatter Gather Mode and Multiple Channel mode.

We show how to do multiple packets transfers, as well as how to do multiple BDs per packet transfers.

This code is tested only with two channels on both Tx and Rx. This code assumes a loopback hardware widget is connected to the AXI DMA core for data packet loopback. The loopback widget is configured in a way that, when a packet is transmitted on "Tx Channel 0" it will be received on the "Rx channel 1" and if "Tx Channel 1" it is on Rx Channel 0. Both the cases are included in this example.

To see the debug print, you need a Uart16550 or uartlite in your system, and please set "-DDEBUG" in your compiler options. You need to rebuild your software executable.

Make sure that MEMORY_BASE is defined properly as per the HW system. The h/w system built in Area mode has a maximum DDR memory limit of 64MB. In throughput mode, it is 512MB. These limits are need to ensured for proper operation of this code.

NOTE: The AXI DMA multichannel support is deprecated in the IP and it is no longer actively supported. For multichannel support, refer to the AXI multichannel direct memory access IP product guide(PG228) and it's example. This example is planned to be removed in next release.

    MODIFICATION HISTORY:

    Ver   Who  Date     Changes
    ----- ---- -------- -------------------------------------------------------
    1.00a srt  03/27/12 First release
    2.00a srt  06/18/12 API calls are reverted back for backward compatibility.
    2.01a srt  11/02/12 Buffer sizes (Tx and Rx) are modified to meet maximum
                   DDR memory limit of the h/w system built with Area mode
    7.02a srt  03/01/13 Updated DDR base address for IPI designs (CR 703656).
    9.1   adk  01/07/16 Updated DDR base address for Ultrascale (CR 799532) and
                   removed the defines for S6/V6.
    9.3   ms   01/23/17 Modified xil_printf statement in main function to
                        ensure that "Successfully ran" and "Failed" strings are
                        available in all examples. This is a fix for CR-965028.
          ms   04/05/17 Added tabspace for return statements in functions
                        for proper documentation while generating doxygen.
    9.6   rsp  02/14/18 Support data buffers above 4GB. Use UINTPTR for storing
                        and typecasting buffer address(CR-992638).
    9.9   rsp  01/21/19 Fix use of #elif check in deriving DDR_BASE_ADDR.
    9.10  rsp  09/17/19 Fix cache maintenance ops for source and dest buffer.

## Functions
int | main (void)
| Main function. More...

## Function Documentation

int main | ( | void |  | ) |

Main function.

This function is the main entry of the interrupt test. It does the following:

- Set up the output terminal if UART16550 is in the hardware build
- Initialize the DMA engine
- Set up Tx and Rx channels
- Set up the interrupt system for the Tx and Rx interrupts
- Submit a transfer
- Wait for the transfer to finish
- Check transfer status
- Disable Tx and Rx interrupts
- Print test status and exit

Parameters

  None |

Returns
  - XST_SUCCESS if tests pass
  - XST_FAILURE if fails.

Note
  None.

References XAxiDma_CfgInitialize(), XAxiDma_HasSg, and XAxiDma_LookupConfig().