trafgen: Trafgen_v4_2

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Data Structures | Macros | Typedefs | Functions
Trafgen_v4_2

## Data Structures
struct | XTrafGen_CRamCmd
| Command Ram word fields. More...
struct | XTrafGen_PRamCmd
| Parameter Ram word fields. More...
struct | XTrafGen_Cmd
| Command structure exposed to user. More...
struct | XTrafGen_CmdEntry
| Command Entry structure. More...
struct | XTrafGen_Config
| The configuration structure for Traffic Generator device. More...
struct | XTrafGen_CmdInfo
| Command Information Structure. More...
struct | XTrafGen
| The XTrafGen driver instance data. More...

## Macros
#define | XTrafGen_GetCmdInfo(InstancePtr) (&((InstancePtr)->CmdInfo))
| Get Command Info pointer. More...
#define | MAX_NUM_ENTRIES 256
| Number of command entries per region. More...
#define | NUM_BLOCKS 2
| Number of Read and write regions. More...
#define | XTG_WRITE 1
| Write Direction Flag. More...
#define | XTG_READ 0
| Read Direction Flag. More...
#define | XTG_MODE_FULL 0
| Full Mode. More...
#define | XTG_MODE_BASIC 1
| Basic Mode. More...
#define | XTG_MODE_STATIC 2
| Static Mode. More...
#define | XTG_MODE_STREAMING 3
| Streaming Mode. More...
#define | XTG_MODE_SYS_INIT 4
| System Init Mode. More...
#define | XTG_MWIDTH_32 0
| Master Width - 32. More...
#define | XTG_MWIDTH_64 1
| Master Width - 64. More...
#define | XTG_SWIDTH_32 0
| Slave Width - 32. More...
#define | XTG_SWIDTH_64 1
| Slave Width - 64. More...
#define | XTG_PRM_RAM_BLOCK_SIZE 0x400
| PARAM Block Size (1KB) More...
#define | XTG_CMD_RAM_BLOCK_SIZE 0x1000
| Cmd RAM Block Size (4KB) More...
#define | XTG_EXTCMD_RAM_BLOCK_SIZE 0x400
| Extended CMDRAM Block Size (1KB) More...
#define | XTG_PARAM_RAM_SIZE 0x800
| Parameter RAM (2KB) More...
#define | XTG_COMMAND_RAM_SIZE 0x2000
| Command RAM (8KB) More...
#define | XTG_MASTER_RAM_SIZE 0x2000
| Master RAM (8KB) More...
#define | XTrafGen_ReadCoreRevision(InstancePtr)
| XTrafGen_ReadCoreRevision reads revision of core. More...
#define | XTrafGen_ReadIdWidth(InstancePtr)
| XTrafGen_ReadIdWidth reads M_ID_WIDTH. More...
#define | XTrafGen_StartMasterLogic(InstancePtr)
| XTrafGen_StartMasterLogic starts traffic generator master logic. More...
#define | XTrafGen_IsMasterLogicDone(InstancePtr)
| XTrafGen_IsMasterLogicDone checks for traffic generator master logic completed bit. More...
#define | XTrafGen_LoopEnable(InstancePtr)
| XTrafGen_LoopEnable loops through the command set created using CMDRAM and PARAMRAM indefinitely in Advanced mode/Basic mode of ATG. More...
#define | XTrafGen_LoopDisable(InstancePtr)
| XTrafGen_LoopDisable Disables the loop bit in Master control regiset in Advanced mode/Basic mode of ATG. More...
#define | XTrafGen_WriteSlaveControlReg(InstancePtr, Value)
| XTrafGen_WriteSlaveControlReg enables control bits of Slave Control Register. More...
#define | XTrafGen_CheckforMasterComplete(InstancePtr)
| XTrafGen_CheckforMasterComplete checks for master complete. More...
#define | XTrafGen_ReadErrors(InstancePtr)
| XTrafGen_ReadErrors read master and slave errors. More...
#define | XTrafGen_EnableMasterCmpInterrupt(InstancePtr)
| XTrafGen_EnableMasterCmpInterrupt enables Master logic complete bit. More...
#define | XTrafGen_ClearMasterCmpInterrupt(InstancePtr)
| XTrafGen_ClearMasterCmpInterrupt clear Master logic complete interrupt bit. More...
#define | XTrafGen_ClearErrors(InstancePtr, Mask)
| XTrafGen_ClearErrors clear errors specified in Mask. More...
#define | XTrafGen_EnableErrors(InstancePtr, Mask)
| XTrafGen_EnableErrors enable errors specified in Mask. More...
#define | XTrafGen_MasterErrIntrEnable(InstancePtr)
| XTrafGen_MasterErrIntrEnable enables Global Master error bit. More...
#define | XTrafGen_MasterErrIntrDisable(InstancePtr)
| XTrafGen_MasterErrIntrDisable disables Global Master error bit. More...
#define | XTrafGen_SlaveErrIntrEnable(InstancePtr)
| XTrafGen_SlaveErrIntrEnable enables Global Slave error bit. More...
#define | XTrafGen_SlaveErrIntrDisable(InstancePtr)
| XTrafGen_SlaveErrIntrDisable disables Global Slave error bit. More...
#define | XTrafGen_ReadConfigStatus(InstancePtr)
| XTrafGen_ReadConfigStatus reads Config status register. More...
#define | XTrafGen_StaticEnable(InstancePtr)
| XTrafGen_StaticEnable enable the traffic generation when the core is configured Static Mode. More...
#define | XTrafGen_StaticDisable(InstancePtr)
| XTrafGen_StaticDisable disables the traffic generation on the Axi TrafGen when the core is configured in Static Mode. More...
#define | XTrafGen_StaticVersion(InstancePtr)
| XTrafGen_StaticVersion returns the version value for the Axi TrafGen When configured in Static Mode. More...
#define | XTrafGen_SetStaticBurstLen(InstancePtr, Value)
| XTrafGen_SetStaticBurstLen Configures the Burst Length for AxiTrafGen In Static Mode. More...
#define | XTrafGen_GetStaticBurstLen(InstancePtr)
| XTrafGen_GetStaticBurstLen Gets the Burst Length for AxiTrafGen in StaticMode. More...
#define | XTrafGen_GetStaticTransferDone(InstancePtr)
| XTrafGen_GetStaticTransferDone gets the state of Transfer done bit in Control register When the TraficGen is configured in Static Mode. More...
#define | XTrafGen_SetStaticTransferDone(InstancePtr)
| XTrafGen_SetStaticTransferDone sets the Transfer done bit in Control register When AxiTrafGen is Configured in Static Mode. More...
#define | XTrafGen_IsStaticTransferDone(InstancePtr)
| XTrafGen_IsStaticTransferDone checks for reset value When Static Traffic generation Completed by reading Control Register. More...
#define | XTrafGen_StreamEnable(InstancePtr)
| XTrafGen_StreamEnable enable the traffic generation on the Axi TrafGen When the core is configured in Streaming Mode. More...
#define | XTrafGen_StreamDisable(InstancePtr)
| XTrafGen_StreamDisable Disable the traffic generation on the Axi TrafGen When core is configured in Streaming Mode. More...
#define | XTrafGen_StreamVersion(InstancePtr)
| XTrafGen_StreamVersion returns the version value for the Axi TrafGen When configured in Streaming Mode. More...
#define | XTrafGen_SetStreamingTransLen(InstancePtr, Value)
| XTrafGen_SetStreamingTransLen Configures the length of transaction for AxiTrafGen in Streaming Mode. More...
#define | XTrafGen_GetStreamingTransLen(InstancePtr)
| XTrafGen_GetStreamingTransLen Gets the length of transaction for AxiTrafGen in Streaming Mode. More...
#define | XTrafGen_GetStreamingTransCnt(InstancePtr)
| XTrafGen_GetStreamingTransCnt Gets the transfer count for AxiTrafGen in Streaming Mode. More...
#define | XTrafGen_SetStreamingRandomLen(InstancePtr, Value)
| XTrafGen_SetStreamingRandomLen Configures the random transaction length for AxiTrafGen in Streaming Mode. More...
#define | XTrafGen_GetStreamingProgDelay(InstancePtr)
| XTrafGen_GetStreamingProgDelay Gets the Programmable Delay for AxiTrafGen in Streaming Mode. More...
#define | XTrafGen_SetStreamingTransCnt(InstancePtr, Value)
| XTrafGen_SetStreamingTransCnt Configures the transfer count for AxiTrafGen in Streaming Mode. More...
#define | XTrafGen_SetStreamingProgDelay(InstancePtr, Value)
| XTrafGen_SetStreamingProgDelay Configures the Programmable Delay for AxiTrafGen in Streaming Mode. More...
#define | XTrafGen_SetStreamingTdestPort(InstancePtr, Value)
| XTrafGen_SetStreamingTdestPort Configures the Value to drive on TDEST port for Axi TrafGen in Streaming Mode. More...
#define | XTrafGen_SetStreamingTransferDone(InstancePtr)
| XTrafGen_SetTransferDone sets the Transfer done bit in Control register When AxiTrafGen is Configured in Streaming Mode. More...
#define | XTrafGen_IsStreamingTransferDone(InstancePtr)
| XTrafGen_IsStreamingTransferDone checks for reset value When Streaming Traffic generation is Completed by reading Stream Control Register. More...
#define | XTrafGen_ResetStreamingRandomLen(InstancePtr)
| XTrafGen_ResetStreamingRandomLen resets the random transaction length for AxiTrafGen in Streaming Mode. More...

## Typedefs
typedef struct XTrafGen_CRamCmd | XTrafGen_CRamCmd
| Command Ram word fields. More...
typedef struct XTrafGen_PRamCmd | XTrafGen_PRamCmd
| Parameter Ram word fields. More...
typedef struct XTrafGen_Cmd | XTrafGen_Cmd
| Command structure exposed to user. More...
typedef struct XTrafGen_CmdEntry | XTrafGen_CmdEntry
| Command Entry structure. More...
typedef struct XTrafGen_Config | XTrafGen_Config
| The configuration structure for Traffic Generator device. More...
typedef struct XTrafGen_CmdInfo | XTrafGen_CmdInfo
| Command Information Structure. More...
typedef struct XTrafGen | XTrafGen
| The XTrafGen driver instance data. More...

## Functions
int | XTrafGen_CfgInitialize (XTrafGen *InstancePtr, XTrafGen_Config *Config, UINTPTR EffectiveAddress)
| This function initializes a AXI Traffic Generator device. More...
int | XTrafGen_AddCommand (XTrafGen *InstancePtr, XTrafGen_Cmd *CmdPtr)
| Add a command to the software list of commands. More...
int | XTrafGen_GetLastValidIndex (XTrafGen *InstancePtr, u32 RdWrFlag)
| Get last Valid Command Index of Write/Read region. More...
int | XTrafGen_WriteCmdsToHw (XTrafGen *InstancePtr)
| Write Commands to internal Command and Parameter RAMs. More...
int | XTrafGen_EraseAllCommands (XTrafGen *InstancePtr)
| Erase all Command Entry values. More...
void | XTrafGen_AccessMasterRam (XTrafGen *InstancePtr, u32 Offset, int Length, u8 RdWrFlag, u32 *Data)
| Write or Read Master RAM. More...
void | XTrafGen_PrintCmds (XTrafGen *InstancePtr)
| Display Command Entry values. More...
XTrafGen_Config * | XTrafGen_LookupConfig (u32 DeviceId)
| Look up the hardware configuration for a device instance. More...

## Device registers
#define | XTG_MCNTL_OFFSET 0x00
| Master Control. More...
#define | XTG_SCNTL_OFFSET 0x04
| Slave Control. More...
#define | XTG_ERR_STS_OFFSET 0x08
| Error Status. More...
#define | XTG_ERR_EN_OFFSET 0x0C
| Error Enable. More...
#define | XTG_MSTERR_INTR_OFFSET 0x10
| Master Err Interrupt Enable. More...
#define | XTG_CFG_STS_OFFSET 0x14
| Config Status. More...
#define | XTG_STREAM_CNTL_OFFSET 0x30
| Streaming Control. More...
#define | XTG_STREAM_CFG_OFFSET 0x34
| Streaming Config. More...
#define | XTG_STREAM_TL_OFFSET 0x38
| Streaming Transfer Length. More...
#define | XTG_STATIC_CNTL_OFFSET 0x60
| Static Mode Register Descrptions. More...
#define | XTG_STATIC_LEN_OFFSET 0x64
| Static Length. More...

## Internal RAM Offsets
#define | XTG_PARAM_RAM_OFFSET 0x1000
| Parameter RAM Offset. More...
#define | XTG_COMMAND_RAM_OFFSET 0x8000
| Command RAM Offset. More...
#define | XTG_MASTER_RAM_OFFSET 0xC000
| Master RAM Offset. More...
#define | XTG_COMMAND_RAM_MSB_OFFSET 0xa000
| Command RAM MSB Offset. More...

## Master Control Register bit definitions.
These bits are associated with the XTG_MCNTL_OFFSET register.
#define | XTG_MCNTL_REV_MASK 0xFF000000
| Core Revision Mask. More...
#define | XTG_MCNTL_MSTID_MASK 0x00E00000
| M_ID_WIDTH Mask. More...
#define | XTG_MCNTL_MSTEN_MASK 0x00100000
| Master Logic Enable Mask. More...
#define | XTG_MCNTL_LOOPEN_MASK 0x00080000
| Loop enable Mask. More...
#define | XTG_MCNTL_REV_SHIFT 24
| Core Rev shift. More...
#define | XTG_MCNTL_MSTID_SHIFT 21
| M_ID_WIDTH shift. More...

## Slave Control Register bit definitions.
These bits are associated with the XTG_SCNTL_OFFSET register.
#define | XTG_SCNTL_BLKRD_MASK 0x00080000
| Enable Block Read. More...
#define | XTG_SCNTL_DISEXCL_MASK 0x00040000
| Disable Exclusive Access. More...
#define | XTG_SCNTL_WORDR_MASK 0x00020000
| Write Response Order Enable. More...
#define | XTG_SCNTL_RORDR_MASK 0x00010000
| Read Response Order Enable. More...
#define | XTG_SCNTL_ERREN_MASK 0x00008000
| Slv Error Interrupt Enable. More...

## Error bitmasks
These bits are shared with the XTG_ERR_STS_OFFSET and XTG_ERR_EN_OFFSET register.
#define | XTG_ERR_ALL_MSTERR_MASK 0x001F0000
| Master Errors Mask. More...
#define | XTG_ERR_ALL_SLVERR_MASK 0x00000003
| Slave Errors Mask. More...
#define | XTG_ERR_ALL_ERR_MASK 0x001F0003
| All Errors Mask. More...
#define | XTG_ERR_MSTCMP_MASK 0x80000000
| Master Complete Mask. More...
#define | XTG_ERR_RIDER_MASK 0x00100000
| Master Invalid RVALID Mask. More...
#define | XTG_ERR_WIDER_MASK 0x00080000
| Master Invalid BVALID Mask. More...
#define | XTG_ERR_WRSPER_MASK 0x00040000
| MW Invalid RESP Mask. More...
#define | XTG_ERR_RERRSP_MASK 0x00020000
| MR Invalid RESP Mask. More...
#define | XTG_ERR_RLENER_MASK 0x00010000
| Master Read Length Mask. More...
#define | XTG_ERR_SWSTRB_MASK 0x00000002
| Slave WSTRB Illegal Mask. More...
#define | XTG_ERR_SWLENER_MASK 0x00000001
| Slave Read Length Mask. More...

## Macro Definition Documentation

#define MAX_NUM_ENTRIES 256

Number of command entries per region.

Referenced by XTrafGen_AddCommand(), XTrafGen_EraseAllCommands(), and XTrafGen_PrintCmds().

#define NUM_BLOCKS 2

Number of Read and write regions.

Referenced by XTrafGen_EraseAllCommands(), and XTrafGen_WriteCmdsToHw().

#define XTG_CFG_STS_OFFSET 0x14

Config Status.

#define XTG_CMD_RAM_BLOCK_SIZE 0x1000

Cmd RAM Block Size (4KB)

#define XTG_COMMAND_RAM_MSB_OFFSET 0xa000

Command RAM MSB Offset.

#define XTG_COMMAND_RAM_OFFSET 0x8000

Command RAM Offset.

#define XTG_COMMAND_RAM_SIZE 0x2000

Command RAM (8KB)

#define XTG_ERR_ALL_ERR_MASK 0x001F0003

All Errors Mask.

#define XTG_ERR_ALL_MSTERR_MASK 0x001F0000

Master Errors Mask.

#define XTG_ERR_ALL_SLVERR_MASK 0x00000003

Slave Errors Mask.

#define XTG_ERR_EN_OFFSET 0x0C

Error Enable.

#define XTG_ERR_MSTCMP_MASK 0x80000000

Master Complete Mask.

#define XTG_ERR_RERRSP_MASK 0x00020000

MR Invalid RESP Mask.

#define XTG_ERR_RIDER_MASK 0x00100000

Master Invalid RVALID Mask.

#define XTG_ERR_RLENER_MASK 0x00010000

Master Read Length Mask.

#define XTG_ERR_STS_OFFSET 0x08

Error Status.

#define XTG_ERR_SWLENER_MASK 0x00000001

Slave Read Length Mask.

#define XTG_ERR_SWSTRB_MASK 0x00000002

Slave WSTRB Illegal Mask.

#define XTG_ERR_WIDER_MASK 0x00080000

Master Invalid BVALID Mask.

#define XTG_ERR_WRSPER_MASK 0x00040000

MW Invalid RESP Mask.

#define XTG_EXTCMD_RAM_BLOCK_SIZE 0x400

Extended CMDRAM Block Size (1KB)

#define XTG_MASTER_RAM_OFFSET 0xC000

Master RAM Offset.

#define XTG_MASTER_RAM_SIZE 0x2000

Master RAM (8KB)

Referenced by XTrafGen_AccessMasterRam().

#define XTG_MCNTL_LOOPEN_MASK 0x00080000

Loop enable Mask.

#define XTG_MCNTL_MSTEN_MASK 0x00100000

Master Logic Enable Mask.

#define XTG_MCNTL_MSTID_MASK 0x00E00000

M_ID_WIDTH Mask.

#define XTG_MCNTL_MSTID_SHIFT 21

M_ID_WIDTH shift.

#define XTG_MCNTL_OFFSET 0x00

Master Control.

#define XTG_MCNTL_REV_MASK 0xFF000000

Core Revision Mask.

#define XTG_MCNTL_REV_SHIFT 24

Core Rev shift.

#define XTG_MODE_BASIC 1

Basic Mode.

Referenced by XTrafGen_CfgInitialize().

#define XTG_MODE_FULL 0

Full Mode.

Referenced by XTrafGen_CfgInitialize().

#define XTG_MODE_STATIC 2

Static Mode.

Referenced by XTrafGen_CfgInitialize(), and XTrafGenStaticModeExample().

#define XTG_MODE_STREAMING 3

Streaming Mode.

Referenced by XTrafGen_CfgInitialize(), and XTrafGenStremingModeMasterExample().

#define XTG_MODE_SYS_INIT 4

System Init Mode.

Referenced by XTrafGen_CfgInitialize().

#define XTG_MSTERR_INTR_OFFSET 0x10

Master Err Interrupt Enable.

#define XTG_MWIDTH_32 0

Master Width - 32.

#define XTG_MWIDTH_64 1

Master Width - 64.

#define XTG_PARAM_RAM_OFFSET 0x1000

Parameter RAM Offset.

#define XTG_PARAM_RAM_SIZE 0x800

Parameter RAM (2KB)

#define XTG_PRM_RAM_BLOCK_SIZE 0x400

PARAM Block Size (1KB)

#define XTG_READ 0

Read Direction Flag.

Referenced by XTrafGenInterruptExample(), and XTrafGenPollingExample().

#define XTG_SCNTL_BLKRD_MASK 0x00080000

Enable Block Read.

#define XTG_SCNTL_DISEXCL_MASK 0x00040000

Disable Exclusive Access.

#define XTG_SCNTL_ERREN_MASK 0x00008000

Slv Error Interrupt Enable.

#define XTG_SCNTL_OFFSET 0x04

Slave Control.

#define XTG_SCNTL_RORDR_MASK 0x00010000

Read Response Order Enable.

#define XTG_SCNTL_WORDR_MASK 0x00020000

Write Response Order Enable.

#define XTG_STATIC_CNTL_OFFSET 0x60

Static Mode Register Descrptions.

Static Control

#define XTG_STATIC_LEN_OFFSET 0x64

Static Length.

#define XTG_STREAM_CFG_OFFSET 0x34

Streaming Config.

#define XTG_STREAM_CNTL_OFFSET 0x30

Streaming Control.

#define XTG_STREAM_TL_OFFSET 0x38

Streaming Transfer Length.

#define XTG_SWIDTH_32 0

Slave Width - 32.

#define XTG_SWIDTH_64 1

Slave Width - 64.

#define XTG_WRITE 1

Write Direction Flag.

Referenced by XTrafGen_AccessMasterRam(), XTrafGen_AddCommand(), XTrafGen_GetLastValidIndex(), XTrafGenInterruptExample(), and XTrafGenPollingExample().

#define XTrafGen_CheckforMasterComplete | ( |  | InstancePtr | ) |

Value:
((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_ERR_STS_OFFSET) & XTG_ERR_MSTCMP_MASK) ? TRUE : FALSE)
XTG_ERR_STS_OFFSET
#define XTG_ERR_STS_OFFSET
Error Status.
Definition: xtrafgen_hw.h:82
XTG_ERR_MSTCMP_MASK
#define XTG_ERR_MSTCMP_MASK
Master Complete Mask.
Definition: xtrafgen_hw.h:161
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_CheckforMasterComplete checks for master complete.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  TRUE if master complete bit is set. FALSE if master complete bit is not set.

Note
  C-style signature: u8 XTrafGen_CheckforMasterComplete(XTrafGen *InstancePtr)

#define XTrafGen_ClearErrors | ( |  | InstancePtr,
|  |  | Mask
| ) |  |

Value:
XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_ERR_STS_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_ERR_STS_OFFSET) | Mask))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_ERR_STS_OFFSET
#define XTG_ERR_STS_OFFSET
Error Status.
Definition: xtrafgen_hw.h:82
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_ClearErrors clear errors specified in Mask.

The corresponding error for each bit set to 1 in Mask, will be enabled.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.
  Mask | contains a bit mask of the errors to clear. The mask can be formed using a set of bit wise or'd values from the definitions in xtrafgen_hw.h file.

Returns
  None.

Note
  C-style signature: void XTrafGen_ClearErrors(XTrafGen *InstancePtr, u32 Mask)

Referenced by XTrafGenPollingExample().

#define XTrafGen_ClearMasterCmpInterrupt | ( |  | InstancePtr | ) |

Value:
XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_ERR_STS_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_ERR_STS_OFFSET) | \
XTG_ERR_MSTCMP_MASK))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_ERR_STS_OFFSET
#define XTG_ERR_STS_OFFSET
Error Status.
Definition: xtrafgen_hw.h:82
XTG_ERR_MSTCMP_MASK
#define XTG_ERR_MSTCMP_MASK
Master Complete Mask.
Definition: xtrafgen_hw.h:161
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_ClearMasterCmpInterrupt clear Master logic complete interrupt bit.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None.

Note
  C-style signature: u8 XTrafGen_ClearMasterCmpInterrupt(XTrafGen *InstancePtr)

#define XTrafGen_EnableErrors | ( |  | InstancePtr,
|  |  | Mask
| ) |  |

Value:
XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_ERR_EN_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_ERR_EN_OFFSET) | Mask))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_ERR_EN_OFFSET
#define XTG_ERR_EN_OFFSET
Error Enable.
Definition: xtrafgen_hw.h:83
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_EnableErrors enable errors specified in Mask.

The corresponding error for each bit set to 1 in Mask, will be enabled.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.
  Mask | contains a bit mask of the errors to enable. The mask can be formed using a set of bit wise or'd values from the definitions in xtrafgen_hw.h file.

Returns
  None.

Note
  C-style signature: void XTrafGen_EnableErrors(XTrafGen *InstancePtr, u32 Mask)

#define XTrafGen_EnableMasterCmpInterrupt | ( |  | InstancePtr | ) |

Value:
XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_ERR_EN_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_ERR_EN_OFFSET) | \
XTG_ERR_MSTCMP_MASK))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_ERR_EN_OFFSET
#define XTG_ERR_EN_OFFSET
Error Enable.
Definition: xtrafgen_hw.h:83
XTG_ERR_MSTCMP_MASK
#define XTG_ERR_MSTCMP_MASK
Master Complete Mask.
Definition: xtrafgen_hw.h:161
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_EnableMasterCmpInterrupt enables Master logic complete bit.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None.

Note
  C-style signature: void XTrafGen_EnableMasterCmpInterrupt(XTrafGen *InstancePtr)

Referenced by XTrafGenInterruptExample().

#define XTrafGen_GetCmdInfo | ( |  | InstancePtr | ) | (&((InstancePtr)->CmdInfo))

Get Command Info pointer.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  Pointer to the Command Info structure

Note
  C-style signature: XTrafGen_CmdInfo *XTrafGen_GetCmdInfo(XTrafGen *InstancePtr)

Referenced by XTrafGen_AddCommand(), XTrafGen_EraseAllCommands(), XTrafGen_GetLastValidIndex(), and XTrafGen_PrintCmds().

#define XTrafGen_GetStaticBurstLen | ( |  | InstancePtr | ) |

Value:
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STATIC_LEN_OFFSET))
XTG_STATIC_LEN_OFFSET
#define XTG_STATIC_LEN_OFFSET
Static Length.
Definition: xtrafgen_hw.h:94
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_GetStaticBurstLen Gets the Burst Length for AxiTrafGen in StaticMode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  Burst length value.

Note
  C-style signature: u32 XTrafGen_GetStaticBurstLen(XTrafGen *InstancePtr)

#define XTrafGen_GetStaticTransferDone | ( |  | InstancePtr | ) |

Value:
((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STATIC_CNTL_OFFSET)) & XTG_STATIC_CNTL_TD_MASK)
XTG_STATIC_CNTL_OFFSET
#define XTG_STATIC_CNTL_OFFSET
Static Mode Register Descrptions.
Definition: xtrafgen_hw.h:93
XTG_STATIC_CNTL_TD_MASK
#define XTG_STATIC_CNTL_TD_MASK
Transfer Done Mask.
Definition: xtrafgen_hw.h:282
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_GetStaticTransferDone gets the state of Transfer done bit in Control register When the TraficGen is configured in Static Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  Value of the Transfer Done bit.

Note
  C-style signature: u32 XTrafGen_GetStaticTransferDone(XTrafGen *InstancePtr)

Referenced by XTrafGenStaticModeExample().

#define XTrafGen_GetStreamingProgDelay | ( |  | InstancePtr | ) |

Value:
((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_TL_OFFSET ) \
& XTG_STREAM_CFG_PDLY_MASK) >> XTG_STREAM_CFG_PDLY_SHIFT)
XTG_STREAM_CFG_PDLY_SHIFT
#define XTG_STREAM_CFG_PDLY_SHIFT
Programmable Delay Shift.
Definition: xtrafgen_hw.h:249
XTG_STREAM_TL_OFFSET
#define XTG_STREAM_TL_OFFSET
Streaming Transfer Length.
Definition: xtrafgen_hw.h:88
XTG_STREAM_CFG_PDLY_MASK
#define XTG_STREAM_CFG_PDLY_MASK
Programmable Delay Mask.
Definition: xtrafgen_hw.h:250
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_GetStreamingProgDelay Gets the Programmable Delay for AxiTrafGen in Streaming Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  Propagation Delay Value

Note
  C-style signature: u16 XTrafGen_GetProgDelay(XTrafGen *InstancePtr)

#define XTrafGen_GetStreamingTransCnt | ( |  | InstancePtr | ) |

Value:
((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_TL_OFFSET ) & XTG_STREAM_TL_TCNT_MASK) \
>> XTG_STREAM_TL_TCNT_SHIFT)
XTG_STREAM_TL_OFFSET
#define XTG_STREAM_TL_OFFSET
Streaming Transfer Length.
Definition: xtrafgen_hw.h:88
XTG_STREAM_TL_TCNT_SHIFT
#define XTG_STREAM_TL_TCNT_SHIFT
Transfer Count Shift.
Definition: xtrafgen_hw.h:267
XTG_STREAM_TL_TCNT_MASK
#define XTG_STREAM_TL_TCNT_MASK
Transfer Count Mask.
Definition: xtrafgen_hw.h:268
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_GetStreamingTransCnt Gets the transfer count for AxiTrafGen in Streaming Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  Transfer Count value.

Note
  C-style signature: u16 XTrafGen_GetStreamingTransCnt(XTrafGen *InstancePtr)

Referenced by XTrafGenStremingModeMasterExample().

#define XTrafGen_GetStreamingTransLen | ( |  | InstancePtr | ) |

Value:
(XTrafGen_ReadReg(InstancePtr->Config.BaseAddress, \
XTG_STREAM_TL_OFFSET)& XTG_STREAM_TL_TLEN_MASK)
XTG_STREAM_TL_TLEN_MASK
#define XTG_STREAM_TL_TLEN_MASK
Transfer Length Mask.
Definition: xtrafgen_hw.h:270
XTG_STREAM_TL_OFFSET
#define XTG_STREAM_TL_OFFSET
Streaming Transfer Length.
Definition: xtrafgen_hw.h:88
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_GetStreamingTransLen Gets the length of transaction for AxiTrafGen in Streaming Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  Transfer Length value.

Note
  C-style signature: u16 XTrafGen_GetStreamingTransLen(XTrafGen *InstancePtr)

Referenced by XTrafGenStremingModeMasterExample().

#define XTrafGen_IsMasterLogicDone | ( |  | InstancePtr | ) |

Value:
((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_MCNTL_OFFSET) & XTG_MCNTL_MSTEN_MASK) ? \
FALSE : TRUE)
XTG_MCNTL_MSTEN_MASK
#define XTG_MCNTL_MSTEN_MASK
Master Logic Enable Mask.
Definition: xtrafgen_hw.h:114
XTG_MCNTL_OFFSET
#define XTG_MCNTL_OFFSET
Master Control.
Definition: xtrafgen_hw.h:80
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_IsMasterLogicDone checks for traffic generator master logic completed bit.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  TRUE if master logic completed. FALSE if master logic not completed.

Note
  C-style signature: u8 XTrafGen_IsMasterLogicDone(XTrafGen *InstancePtr)

Referenced by XTrafGenPollingExample().

#define XTrafGen_IsStaticTransferDone | ( |  | InstancePtr | ) |

Value:
(((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STATIC_CNTL_OFFSET) & XTG_STATIC_CNTL_TD_MASK) == \
XTG_STATIC_CNTL_RESET_MASK) ? \
TRUE : FALSE)
XTG_STATIC_CNTL_RESET_MASK
#define XTG_STATIC_CNTL_RESET_MASK
Static Disable Mask.
Definition: xtrafgen_hw.h:285
XTG_STATIC_CNTL_OFFSET
#define XTG_STATIC_CNTL_OFFSET
Static Mode Register Descrptions.
Definition: xtrafgen_hw.h:93
XTG_STATIC_CNTL_TD_MASK
#define XTG_STATIC_CNTL_TD_MASK
Transfer Done Mask.
Definition: xtrafgen_hw.h:282
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_IsStaticTransferDone checks for reset value When Static Traffic generation Completed by reading Control Register.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  TRUE if reset Success full FALSE if failed to reset

Note
  C-style signature: u8 XTrafGen_IsStaticTransferDone(XTrafGen *InstancePtr)

Referenced by XTrafGenStaticModeExample().

#define XTrafGen_IsStreamingTransferDone | ( |  | InstancePtr | ) |

Value:
(((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CNTL_OFFSET) & XTG_STREAM_CNTL_TD_MASK) == \
XTG_STREAM_CNTL_RESET_MASK) ? \
TRUE : FALSE)
XTG_STREAM_CNTL_RESET_MASK
#define XTG_STREAM_CNTL_RESET_MASK
Streaming Disable Mask.
Definition: xtrafgen_hw.h:241
XTG_STREAM_CNTL_OFFSET
#define XTG_STREAM_CNTL_OFFSET
Streaming Control.
Definition: xtrafgen_hw.h:86
XTG_STREAM_CNTL_TD_MASK
#define XTG_STREAM_CNTL_TD_MASK
Transfer Done Mask.
Definition: xtrafgen_hw.h:238
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_IsStreamingTransferDone checks for reset value When Streaming Traffic generation is Completed by reading Stream Control Register.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  TRUE if reset Success full FALSE if failed to reset

Note
  C-style signature: u8 XTrafGen_IsStreamingTransferDone(XTrafGen *InstancePtr)

#define XTrafGen_LoopDisable | ( |  | InstancePtr | ) |

Value:
XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_MCNTL_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_MCNTL_OFFSET) & ~XTG_MCNTL_LOOPEN_MASK))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_MCNTL_LOOPEN_MASK
#define XTG_MCNTL_LOOPEN_MASK
Loop enable Mask.
Definition: xtrafgen_hw.h:117
XTG_MCNTL_OFFSET
#define XTG_MCNTL_OFFSET
Master Control.
Definition: xtrafgen_hw.h:80
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_LoopDisable Disables the loop bit in Master control regiset in Advanced mode/Basic mode of ATG.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None

Note
  C-style signature: void XTrafGen_LoopDisable(XTrafGen *InstancePtr)

#define XTrafGen_LoopEnable | ( |  | InstancePtr | ) |

Value:
XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_MCNTL_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_MCNTL_OFFSET) | XTG_MCNTL_LOOPEN_MASK))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_MCNTL_LOOPEN_MASK
#define XTG_MCNTL_LOOPEN_MASK
Loop enable Mask.
Definition: xtrafgen_hw.h:117
XTG_MCNTL_OFFSET
#define XTG_MCNTL_OFFSET
Master Control.
Definition: xtrafgen_hw.h:80
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_LoopEnable loops through the command set created using CMDRAM and PARAMRAM indefinitely in Advanced mode/Basic mode of ATG.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None

Note
  C-style signature: void XTrafGen_LoopEnable(XTrafGen *InstancePtr)

#define XTrafGen_MasterErrIntrDisable | ( |  | InstancePtr | ) |

Value:
XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_MSTERR_INTR_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_MSTERR_INTR_OFFSET) & \
~XTG_MSTERR_INTR_MINTREN_MASK))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_MSTERR_INTR_OFFSET
#define XTG_MSTERR_INTR_OFFSET
Master Err Interrupt Enable.
Definition: xtrafgen_hw.h:84
XTG_MSTERR_INTR_MINTREN_MASK
#define XTG_MSTERR_INTR_MINTREN_MASK
Master Err Interrupt Enable.
Definition: xtrafgen_hw.h:208
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_MasterErrIntrDisable disables Global Master error bit.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None

Note
  C-style signature: void XTrafGen_MasterErrIntrDisable(XTrafGen *InstancePtr)

#define XTrafGen_MasterErrIntrEnable | ( |  | InstancePtr | ) |

Value:
XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_MSTERR_INTR_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_MSTERR_INTR_OFFSET) | \
XTG_MSTERR_INTR_MINTREN_MASK))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_MSTERR_INTR_OFFSET
#define XTG_MSTERR_INTR_OFFSET
Master Err Interrupt Enable.
Definition: xtrafgen_hw.h:84
XTG_MSTERR_INTR_MINTREN_MASK
#define XTG_MSTERR_INTR_MINTREN_MASK
Master Err Interrupt Enable.
Definition: xtrafgen_hw.h:208
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_MasterErrIntrEnable enables Global Master error bit.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None

Note
  C-style signature: void XTrafGen_MasterErrIntrEnable(XTrafGen *InstancePtr)

#define XTrafGen_ReadConfigStatus | ( |  | InstancePtr | ) |

Value:
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_CFG_STS_OFFSET))
XTG_CFG_STS_OFFSET
#define XTG_CFG_STS_OFFSET
Config Status.
Definition: xtrafgen_hw.h:85
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_ReadConfigStatus reads Config status register.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  Config Status Register value

Note
  C-style signature: u32 XTrafGen_ReadConfigStatus(XTrafGen *InstancePtr)

Referenced by XTrafGen_CfgInitialize().

#define XTrafGen_ReadCoreRevision | ( |  | InstancePtr | ) |

Value:
((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_MCNTL_OFFSET) & XTG_MCNTL_REV_MASK) >> \
XTG_MCNTL_REV_SHIFT)
XTG_MCNTL_REV_MASK
#define XTG_MCNTL_REV_MASK
Core Revision Mask.
Definition: xtrafgen_hw.h:112
XTG_MCNTL_REV_SHIFT
#define XTG_MCNTL_REV_SHIFT
Core Rev shift.
Definition: xtrafgen_hw.h:119
XTG_MCNTL_OFFSET
#define XTG_MCNTL_OFFSET
Master Control.
Definition: xtrafgen_hw.h:80
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_ReadCoreRevision reads revision of core.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  Core Revision Value

Note
  C-style signature: u8 XTrafGen_ReadCoreRevision(XTrafGen *InstancePtr)

#define XTrafGen_ReadErrors | ( |  | InstancePtr | ) |

Value:
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_ERR_STS_OFFSET) & XTG_ERR_ALL_ERR_MASK)
XTG_ERR_ALL_ERR_MASK
#define XTG_ERR_ALL_ERR_MASK
All Errors Mask.
Definition: xtrafgen_hw.h:157
XTG_ERR_STS_OFFSET
#define XTG_ERR_STS_OFFSET
Error Status.
Definition: xtrafgen_hw.h:82
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_ReadErrors read master and slave errors.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  Both Master and Slave error value.

Note
  C-style signature: u32 XTrafGen_ReadErrors(XTrafGen *InstancePtr)

Referenced by XTrafGenPollingExample().

#define XTrafGen_ReadIdWidth | ( |  | InstancePtr | ) |

Value:
((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_MCNTL_OFFSET) & XTG_MCNTL_MSTID_MASK) >> \
XTG_MCNTL_MSTID_SHIFT)
XTG_MCNTL_MSTID_MASK
#define XTG_MCNTL_MSTID_MASK
M_ID_WIDTH Mask.
Definition: xtrafgen_hw.h:113
XTG_MCNTL_MSTID_SHIFT
#define XTG_MCNTL_MSTID_SHIFT
M_ID_WIDTH shift.
Definition: xtrafgen_hw.h:120
XTG_MCNTL_OFFSET
#define XTG_MCNTL_OFFSET
Master Control.
Definition: xtrafgen_hw.h:80
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_ReadIdWidth reads M_ID_WIDTH.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  Value of M_ID_WIDTH

Note
  C-style signature: u8 XTrafGen_ReadIdWidth(XTrafGen *InstancePtr)

#define XTrafGen_ResetStreamingRandomLen | ( |  | InstancePtr | ) |

Value:
(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CFG_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CFG_OFFSET) & ~XTG_STREAM_CFG_RANDL_MASK)))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_STREAM_CFG_RANDL_MASK
#define XTG_STREAM_CFG_RANDL_MASK
Random Length Mask.
Definition: xtrafgen_hw.h:258
XTG_STREAM_CFG_OFFSET
#define XTG_STREAM_CFG_OFFSET
Streaming Config.
Definition: xtrafgen_hw.h:87
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_ResetStreamingRandomLen resets the random transaction length for AxiTrafGen in Streaming Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None.

Note
  C-style signature: void XTrafGen_ResetStreamingRandomLen(XTrafGen *InstancePtr)

Referenced by XTrafGenStremingModeMasterExample().

#define XTrafGen_SetStaticBurstLen | ( |  | InstancePtr,
|  |  | Value
| ) |  |

Value:
(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_STATIC_LEN_OFFSET,Value))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_STATIC_LEN_OFFSET
#define XTG_STATIC_LEN_OFFSET
Static Length.
Definition: xtrafgen_hw.h:94

XTrafGen_SetStaticBurstLen Configures the Burst Length for AxiTrafGen In Static Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.
  Value | is the Burst length to set in the Static length register.

Returns
  None.

Note
  C-style signature: void XTrafGen_SetStaticBurstLen(XTrafGen *InstancePtr, u32 Value)

Referenced by XTrafGenStaticModeExample().

#define XTrafGen_SetStaticTransferDone | ( |  | InstancePtr | ) |

Value:
XTrafGen_WriteReg(InstancePtr->Config.BaseAddress, \
XTG_STATIC_CNTL_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STATIC_CNTL_OFFSET) | XTG_STATIC_CNTL_TD_MASK))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_STATIC_CNTL_OFFSET
#define XTG_STATIC_CNTL_OFFSET
Static Mode Register Descrptions.
Definition: xtrafgen_hw.h:93
XTG_STATIC_CNTL_TD_MASK
#define XTG_STATIC_CNTL_TD_MASK
Transfer Done Mask.
Definition: xtrafgen_hw.h:282
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_SetStaticTransferDone sets the Transfer done bit in Control register When AxiTrafGen is Configured in Static Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None.

Note
  C-style signature: void XTrafGen_SetStaticTransferDone(XTrafGen *InstancePtr)

Referenced by XTrafGenStaticModeExample().

#define XTrafGen_SetStreamingProgDelay | ( |  | InstancePtr,
|  |  | Value
| ) |  |

Value:
(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CFG_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CFG_OFFSET)|(Value << XTG_STREAM_CFG_PDLY_SHIFT)) \
& XTG_STREAM_CFG_PDLY_MASK))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_STREAM_CFG_PDLY_SHIFT
#define XTG_STREAM_CFG_PDLY_SHIFT
Programmable Delay Shift.
Definition: xtrafgen_hw.h:249
XTG_STREAM_CFG_OFFSET
#define XTG_STREAM_CFG_OFFSET
Streaming Config.
Definition: xtrafgen_hw.h:87
XTG_STREAM_CFG_PDLY_MASK
#define XTG_STREAM_CFG_PDLY_MASK
Programmable Delay Mask.
Definition: xtrafgen_hw.h:250
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_SetStreamingProgDelay Configures the Programmable Delay for AxiTrafGen in Streaming Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.
  Value | is the value that's need to be configure in the Stream Config Register.

Returns
  None.

Note
  C-style signature: void XTrafGen_SetStreamingProgDelay(XTrafGen *InstancePtr, u32 Value)

#define XTrafGen_SetStreamingRandomLen | ( |  | InstancePtr,
|  |  | Value
| ) |  |

Value:
(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CFG_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CFG_OFFSET) | Value)))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_STREAM_CFG_OFFSET
#define XTG_STREAM_CFG_OFFSET
Streaming Config.
Definition: xtrafgen_hw.h:87
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_SetStreamingRandomLen Configures the random transaction length for AxiTrafGen in Streaming Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.
  Value | is the random length that's need to be Configure in the Streaming Config register.

Returns
  None.

Note
  C-style signature: void XTrafGen_SetStreamingRandomLen(XTrafGen *InstancePtr, u32 Value)

#define XTrafGen_SetStreamingTdestPort | ( |  | InstancePtr,
|  |  | Value
| ) |  |

Value:
(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CFG_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CFG_OFFSET)|(Value << XTG_STREAM_CFG_TDEST_SHIFT)) \
& XTG_STREAM_CFG_TDEST_MASK))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_STREAM_CFG_TDEST_SHIFT
#define XTG_STREAM_CFG_TDEST_SHIFT
TDEST PORT Shift.
Definition: xtrafgen_hw.h:252
XTG_STREAM_CFG_OFFSET
#define XTG_STREAM_CFG_OFFSET
Streaming Config.
Definition: xtrafgen_hw.h:87
XTG_STREAM_CFG_TDEST_MASK
#define XTG_STREAM_CFG_TDEST_MASK
TDEST PORT Mask.
Definition: xtrafgen_hw.h:253
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_SetStreamingTdestPort Configures the Value to drive on TDEST port for Axi TrafGen in Streaming Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.
  Value | is the Port value that's need to be set.

Returns
  None.

Note
  C-style signature: void XTrafGen_SetStreamingTdestPort(XTrafGen *InstancePtr, u8 Value)

#define XTrafGen_SetStreamingTransCnt | ( |  | InstancePtr,
|  |  | Value
| ) |  |

Value:
(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_TL_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_TL_OFFSET) |((Value << XTG_STREAM_TL_TCNT_SHIFT) \
& XTG_STREAM_TL_TCNT_MASK))))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_STREAM_TL_OFFSET
#define XTG_STREAM_TL_OFFSET
Streaming Transfer Length.
Definition: xtrafgen_hw.h:88
XTG_STREAM_TL_TCNT_SHIFT
#define XTG_STREAM_TL_TCNT_SHIFT
Transfer Count Shift.
Definition: xtrafgen_hw.h:267
XTG_STREAM_TL_TCNT_MASK
#define XTG_STREAM_TL_TCNT_MASK
Transfer Count Mask.
Definition: xtrafgen_hw.h:268
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_SetStreamingTransCnt Configures the transfer count for AxiTrafGen in Streaming Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.
  Value | is the transfer length that needs to be configured in Transfer length register.

Returns
  None.

Note
  C-style signature: void XTrafGen_SetStreamingTransCnt(XTrafGen *InstancePtr, u32 Value)

Referenced by XTrafGenStremingModeMasterExample().

#define XTrafGen_SetStreamingTransferDone | ( |  | InstancePtr | ) |

Value:
XTrafGen_WriteReg(InstancePtr->Config.BaseAddress, \
XTG_STREAM_CNTL_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CNTL_OFFSET) | XTG_STREAM_CNTL_TD_MASK))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_STREAM_CNTL_OFFSET
#define XTG_STREAM_CNTL_OFFSET
Streaming Control.
Definition: xtrafgen_hw.h:86
XTG_STREAM_CNTL_TD_MASK
#define XTG_STREAM_CNTL_TD_MASK
Transfer Done Mask.
Definition: xtrafgen_hw.h:238
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_SetTransferDone sets the Transfer done bit in Control register When AxiTrafGen is Configured in Streaming Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None.

Note
  C-style signature: void XTrafGen_SetStreamingTransferDone(XTrafGen *InstancePtr)

#define XTrafGen_SetStreamingTransLen | ( |  | InstancePtr,
|  |  | Value
| ) |  |

Value:
(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_TL_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_TL_OFFSET) | Value)))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_STREAM_TL_OFFSET
#define XTG_STREAM_TL_OFFSET
Streaming Transfer Length.
Definition: xtrafgen_hw.h:88
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_SetStreamingTransLen Configures the length of transaction for AxiTrafGen in Streaming Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.
  Value | is the transfer length to set in the transfer length Register.

Returns
  None.

Note
  C-style signature: void XTrafGen_SetStreamingTransLen(XTrafGen *InstancePtr, u32 Value)

Referenced by XTrafGenStremingModeMasterExample().

#define XTrafGen_SlaveErrIntrDisable | ( |  | InstancePtr | ) |

Value:
XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_SCNTL_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_SCNTL_OFFSET) & \
~XTG_SCNTL_ERREN_MASK))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_SCNTL_OFFSET
#define XTG_SCNTL_OFFSET
Slave Control.
Definition: xtrafgen_hw.h:81
XTG_SCNTL_ERREN_MASK
#define XTG_SCNTL_ERREN_MASK
Slv Error Interrupt Enable.
Definition: xtrafgen_hw.h:140
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_SlaveErrIntrDisable disables Global Slave error bit.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None

Note
  C-style signature: void XTrafGen_SlaveErrIntrDisable(XTrafGen *InstancePtr)

#define XTrafGen_SlaveErrIntrEnable | ( |  | InstancePtr | ) |

Value:
XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_SCNTL_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_SCNTL_OFFSET) | XTG_SCNTL_ERREN_MASK))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_SCNTL_OFFSET
#define XTG_SCNTL_OFFSET
Slave Control.
Definition: xtrafgen_hw.h:81
XTG_SCNTL_ERREN_MASK
#define XTG_SCNTL_ERREN_MASK
Slv Error Interrupt Enable.
Definition: xtrafgen_hw.h:140
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_SlaveErrIntrEnable enables Global Slave error bit.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None

Note
  C-style signature: void XTrafGen_SlaveErrIntrEnable(XTrafGen *InstancePtr)

#define XTrafGen_StartMasterLogic | ( |  | InstancePtr | ) |

Value:
XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_MCNTL_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_MCNTL_OFFSET) | XTG_MCNTL_MSTEN_MASK))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_MCNTL_MSTEN_MASK
#define XTG_MCNTL_MSTEN_MASK
Master Logic Enable Mask.
Definition: xtrafgen_hw.h:114
XTG_MCNTL_OFFSET
#define XTG_MCNTL_OFFSET
Master Control.
Definition: xtrafgen_hw.h:80
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_StartMasterLogic starts traffic generator master logic.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None

Note
  C-style signature: void XTrafGen_StartMasterLogic(XTrafGen *InstancePtr)

Referenced by XTrafGenInterruptExample(), and XTrafGenPollingExample().

#define XTrafGen_StaticDisable | ( |  | InstancePtr | ) |

Value:
(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_STATIC_CNTL_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STATIC_CNTL_OFFSET) & XTG_STATIC_CNTL_RESET_MASK)))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_STATIC_CNTL_RESET_MASK
#define XTG_STATIC_CNTL_RESET_MASK
Static Disable Mask.
Definition: xtrafgen_hw.h:285
XTG_STATIC_CNTL_OFFSET
#define XTG_STATIC_CNTL_OFFSET
Static Mode Register Descrptions.
Definition: xtrafgen_hw.h:93
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_StaticDisable disables the traffic generation on the Axi TrafGen when the core is configured in Static Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None.

Note
  C-style signature: void XTrafGen_StaticDisable(XTrafGen *InstancePtr)

Referenced by XTrafGenStaticModeExample().

#define XTrafGen_StaticEnable | ( |  | InstancePtr | ) |

Value:
(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_STATIC_CNTL_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STATIC_CNTL_OFFSET) | XTG_STATIC_CNTL_STEN_MASK)))
XTG_STATIC_CNTL_STEN_MASK
#define XTG_STATIC_CNTL_STEN_MASK
Static enable Mask.
Definition: xtrafgen_hw.h:284
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_STATIC_CNTL_OFFSET
#define XTG_STATIC_CNTL_OFFSET
Static Mode Register Descrptions.
Definition: xtrafgen_hw.h:93
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_StaticEnable enable the traffic generation when the core is configured Static Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None.

Note
  C-style signature: void XTrafGen_StaticEnable(XTrafGen *InstancePtr)

Referenced by XTrafGenStaticModeExample().

#define XTrafGen_StaticVersion | ( |  | InstancePtr | ) |

Value:
((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STATIC_CNTL_OFFSET) & XTG_STATIC_CNTL_VER_MASK) >> \
XTG_STATIC_CNTL_VER_SHIFT )
XTG_STATIC_CNTL_VER_MASK
#define XTG_STATIC_CNTL_VER_MASK
Version Mask.
Definition: xtrafgen_hw.h:279
XTG_STATIC_CNTL_OFFSET
#define XTG_STATIC_CNTL_OFFSET
Static Mode Register Descrptions.
Definition: xtrafgen_hw.h:93
XTG_STATIC_CNTL_VER_SHIFT
#define XTG_STATIC_CNTL_VER_SHIFT
Version Shift.
Definition: xtrafgen_hw.h:278
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_StaticVersion returns the version value for the Axi TrafGen When configured in Static Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  Static version value.

Note
  C-style signature: u32 XTrafGen_StaticVersion(XTrafGen *InstancePtr)

#define XTrafGen_StreamDisable | ( |  | InstancePtr | ) |

Value:
(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CNTL_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CNTL_OFFSET) & XTG_STREAM_CNTL_RESET_MASK)))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_STREAM_CNTL_RESET_MASK
#define XTG_STREAM_CNTL_RESET_MASK
Streaming Disable Mask.
Definition: xtrafgen_hw.h:241
XTG_STREAM_CNTL_OFFSET
#define XTG_STREAM_CNTL_OFFSET
Streaming Control.
Definition: xtrafgen_hw.h:86
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_StreamDisable Disable the traffic generation on the Axi TrafGen When core is configured in Streaming Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None.

Note
  C-style signature: void XTrafGen_StreamDisable(XTrafGen *InstancePtr)

#define XTrafGen_StreamEnable | ( |  | InstancePtr | ) |

Value:
(XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CNTL_OFFSET, \
(XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CNTL_OFFSET) | XTG_STREAM_CNTL_STEN_MASK)))
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_STREAM_CNTL_STEN_MASK
#define XTG_STREAM_CNTL_STEN_MASK
Streaming Enable Mask.
Definition: xtrafgen_hw.h:240
XTG_STREAM_CNTL_OFFSET
#define XTG_STREAM_CNTL_OFFSET
Streaming Control.
Definition: xtrafgen_hw.h:86
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_StreamEnable enable the traffic generation on the Axi TrafGen When the core is configured in Streaming Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  None.

Note
  C-style signature: void XTrafGen_StreamEnable(XTrafGen *InstancePtr)

Referenced by XTrafGenStremingModeMasterExample().

#define XTrafGen_StreamVersion | ( |  | InstancePtr | ) |

Value:
((XTrafGen_ReadReg((InstancePtr)->Config.BaseAddress, \
XTG_STREAM_CNTL_OFFSET) & XTG_STREAM_CNTL_VER_MASK) \
>> XTG_STREAM_CNTL_VER_SHIFT )
XTG_STREAM_CNTL_VER_MASK
#define XTG_STREAM_CNTL_VER_MASK
Version Mask.
Definition: xtrafgen_hw.h:235
XTG_STREAM_CNTL_VER_SHIFT
#define XTG_STREAM_CNTL_VER_SHIFT
Version Shift.
Definition: xtrafgen_hw.h:234
XTG_STREAM_CNTL_OFFSET
#define XTG_STREAM_CNTL_OFFSET
Streaming Control.
Definition: xtrafgen_hw.h:86
XTrafGen_ReadReg
#define XTrafGen_ReadReg(BaseAddress, RegOffset)
XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...
Definition: xtrafgen_hw.h:398

XTrafGen_StreamVersion returns the version value for the Axi TrafGen When configured in Streaming Mode.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  Streaming Version Value.

Note
  C-style signature: u8 XTrafGen_StreamVersion(XTrafGen *InstancePtr)

#define XTrafGen_WriteSlaveControlReg | ( |  | InstancePtr,
|  |  | Value
| ) |  |

Value:
XTrafGen_WriteReg((InstancePtr)->Config.BaseAddress, \
XTG_SCNTL_OFFSET, Value)
XTrafGen_WriteReg
#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data)
XTrafGen_WriteReg, writes Data to the register specified by RegOffset.
Definition: xtrafgen_hw.h:418
XTG_SCNTL_OFFSET
#define XTG_SCNTL_OFFSET
Slave Control.
Definition: xtrafgen_hw.h:81

XTrafGen_WriteSlaveControlReg enables control bits of Slave Control Register.

This API will write the value passed from the user.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.
  Value | is the Slave Control Register value to set

Returns
  None

Note
  C-style signature: void XTrafGen_WriteSlaveControlReg(XTrafGen *InstancePtr, u32 Value)

## Typedef Documentation

typedef struct XTrafGen XTrafGen

The XTrafGen driver instance data.

An instance must be allocated for each Traffic Generator device in use.

typedef struct XTrafGen_Cmd XTrafGen_Cmd

Command structure exposed to user.

This structure should be updated by user with required configuration

typedef struct XTrafGen_CmdEntry XTrafGen_CmdEntry

Command Entry structure.

This structure denotes each entry of 256 commands.

typedef struct XTrafGen_CmdInfo XTrafGen_CmdInfo

Command Information Structure.

This structure is maintained by the driver

typedef struct XTrafGen_Config XTrafGen_Config

The configuration structure for Traffic Generator device.

This structure passes the hardware building information to the driver

typedef struct XTrafGen_CRamCmd XTrafGen_CRamCmd

Command Ram word fields.

typedef struct XTrafGen_PRamCmd XTrafGen_PRamCmd

Parameter Ram word fields.

## Function Documentation

void XTrafGen_AccessMasterRam | ( | XTrafGen * | InstancePtr,
|  | u32 | Offset,
|  | int | Length,
|  | u8 | RdWrFlag,
|  | u32 * | Data
| ) |  |

Write or Read Master RAM.

The MSTRAM has 8 KB of internal RAM used for the following:

- Take data from this RAM for write transactions
- Store data to this RAM for read transaction

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.
  Offset | is the offset value in Master RAM.
  Length | is the size of data to write/read.
  RdWrFlag | specifies whether to write or read
  Data | is the pointer to array which contains data to write or reads data into.

References XTrafGen_Config::BaseAddress, XTrafGen::Config, XTG_MASTER_RAM_SIZE, XTG_WRITE, XTrafGen_ReadMasterRam, and XTrafGen_WriteMasterRam.

Referenced by XTrafGenInterruptExample(), and XTrafGenPollingExample().

int XTrafGen_AddCommand | ( | XTrafGen * | InstancePtr,
|  | XTrafGen_Cmd * | CmdPtr
| ) |  |

Add a command to the software list of commands.

This function prepares the four Command Words and one Parameter Word from the Command structure passed from the user application. It then adds to a list of commands (maintained in the software). Both CMDRAM and PARAMRAM are divided into two regions, one for reads and one for writes. Each region can hold 256 commands with each entry containing four Command RAM words and one Parameter RAM word.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.
  CmdPtr | is a pointer to Command structure.

Returns
  - XST_SUCCESS if successful
  - XST_FAILURE if reached max number of command entries

References XTrafGen_CmdInfo::CmdEntry, XTrafGen_CmdEntry::CmdWords, XTrafGen_Cmd::CRamCmd, XTrafGen_CmdInfo::LastRdValidIndex, XTrafGen_CmdInfo::LastWrValidIndex, MAX_NUM_ENTRIES, XTrafGen_CmdEntry::ParamWord, XTrafGen_CmdInfo::RdIndex, XTrafGen_CmdInfo::RdIndexEnd, XTrafGen_Cmd::RdWrFlag, XTrafGen_CRamCmd::ValidCmd, XTrafGen_CmdInfo::WrIndex, XTrafGen_CmdInfo::WrIndexEnd, XTG_WRITE, and XTrafGen_GetCmdInfo.

Referenced by XTrafGenInterruptExample(), and XTrafGenPollingExample().

int XTrafGen_CfgInitialize | ( | XTrafGen * | InstancePtr,
|  | XTrafGen_Config * | Config,
|  | UINTPTR | EffectiveAddress
| ) |  |

This function initializes a AXI Traffic Generator device.

This function must be called prior to using a AXI Traffic Generator Device. Initializing a engine includes setting up the register base address, setting up the instance data, and ensuring the hardware is in a quiescent state.

Parameters

  InstancePtr | is a pointer to the Axi Traffic Generator instance to be worked on.
  CfgPtr | references the structure holding the hardware configuration for the Axi Traffic Generator core to initialize.
  EffectiveAddr | is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use Config->BaseAddress for this parameters, passing the physical address instead.

Returns
  - XST_SUCCESS for successful initialization
  - XST_INVALID_PARAM if pointer to the configuration structure is NULL

References XTrafGen_Config::AddressWidth, XTrafGen_Config::BaseAddress, XTrafGen_Config::BusType, XTrafGen::CmdInfo, XTrafGen::Config, XTrafGen_Config::DeviceId, XTrafGen_CmdInfo::LastRdValidIndex, XTrafGen_CmdInfo::LastWrValidIndex, XTrafGen::MasterWidth, XTrafGen_Config::Mode, XTrafGen_Config::ModeType, XTrafGen::OperatingMode, XTrafGen::SlaveWidth, XTG_CFG_STS_MBASIC_MASK, XTG_CFG_STS_MFULL_MASK, XTG_CFG_STS_MWIDTH_MASK, XTG_CFG_STS_MWIDTH_SHIFT, XTG_CFG_STS_SWIDTH_MASK, XTG_CFG_STS_SWIDTH_SHIFT, XTG_MODE_BASIC, XTG_MODE_FULL, XTG_MODE_STATIC, XTG_MODE_STREAMING, XTG_MODE_SYS_INIT, and XTrafGen_ReadConfigStatus.

Referenced by XTrafGenInterruptExample(), XTrafGenPollingExample(), XTrafGenStaticModeExample(), and XTrafGenStremingModeMasterExample().

int XTrafGen_EraseAllCommands | ( | XTrafGen * | InstancePtr | ) |

Erase all Command Entry values.

This function erases all the 256 entries of both write and read regions with each entry containing four command words and parameter word.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  - XST_SUCCESS if successful
    - XST_FAILURE if programming internal RAMs failed

References XTrafGen_CmdInfo::CmdEntry, XTrafGen_CmdInfo::LastRdValidIndex, XTrafGen_CmdInfo::LastWrValidIndex, MAX_NUM_ENTRIES, NUM_BLOCKS, XTrafGen_CmdInfo::RdIndex, XTrafGen_CmdInfo::RdIndexEnd, XTrafGen_CmdInfo::WrIndex, XTrafGen_CmdInfo::WrIndexEnd, and XTrafGen_GetCmdInfo.

int XTrafGen_GetLastValidIndex | ( | XTrafGen * | InstancePtr,
|  | u32 | RdWrFlag
| ) |  |

Get last Valid Command Index of Write/Read region.

The last valid command index is used to set 'my_depend' and 'other_depend' fields of the Command RAM (Word 2).

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.
  RdWrFlag | specifies a Read or Write Region

Returns
  - Last Valid Command Index

References XTrafGen_CmdInfo::LastRdValidIndex, XTrafGen_CmdInfo::LastWrValidIndex, XTG_WRITE, and XTrafGen_GetCmdInfo.

Referenced by XTrafGenInterruptExample(), and XTrafGenPollingExample().

XTrafGen_Config * XTrafGen_LookupConfig | ( | u32 | DeviceId | ) |

Look up the hardware configuration for a device instance.

Parameters

  DeviceId | is the unique device ID of the device to lookup for

Returns
  The configuration structure for the device. If the device ID is not found,a NULL pointer is returned.

Note
  None

Referenced by XTrafGenInterruptExample(), XTrafGenPollingExample(), XTrafGenStaticModeExample(), and XTrafGenStremingModeMasterExample().

void XTrafGen_PrintCmds | ( | XTrafGen * | InstancePtr | ) |

Display Command Entry values.

This function prints all the 256 entries of both write and read regions with each entry containing four command words and parameter word.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

References XTrafGen_CmdInfo::CmdEntry, XTrafGen_CmdEntry::CmdWords, MAX_NUM_ENTRIES, XTrafGen_CmdEntry::ParamWord, and XTrafGen_GetCmdInfo.

Referenced by XTrafGenInterruptExample(), and XTrafGenPollingExample().

int XTrafGen_WriteCmdsToHw | ( | XTrafGen * | InstancePtr | ) |

Write Commands to internal Command and Parameter RAMs.

This function writes all the prepared commands to hardware.

Parameters

  InstancePtr | is a pointer to the Axi TrafGen instance to be worked on.

Returns
  - XST_SUCCESS if successful
    - XST_FAILURE if programming internal RAMs failed

References NUM_BLOCKS.

Referenced by XTrafGenInterruptExample(), and XTrafGenPollingExample().