clk_wiz: xclk_wiz_hw.h File Reference

| clk_wiz Xilinx SDK Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List
- Examples

Macros
xclk_wiz_hw.h File Reference

## Macros
#define | XCLK_WIZ_IER_ALLINTR_MASK 0x0000FFFF
| All interrupts enable mask. More...
#define | XCLK_WIZ_IER_ALLINTR_SHIFT 0
| All interrupts enable shift bits. More...
#define | XCLK_WIZ_ISR_ALLINTR_MASK 0x0000FFFF
| All interrupt status register mask. More...
#define | XCLK_WIZ_ISR_ALLINTR_SHIFT 0
| All interrupts status register shift. More...
Device registers
Register sets of CLK_WIZ
#define | XCLK_WIZ_ISR_OFFSET 0x0000000C
| Interrupt Status Register. More...
#define | XCLK_WIZ_IER_OFFSET 0x00000010
| Interrupt Enable Register. More...
Bitmasks and offsets of XCLK_WIZ_ISR_OFFSET register
This register is used to display interrupt status register
#define | XCLK_WIZ_ISR_CLK3_STOP_MASK 0x00008000
| User clock 3 stopped. More...
#define | XCLK_WIZ_ISR_CLK2_STOP_MASK 0x00004000
| User clock 2 stopped. More...
#define | XCLK_WIZ_ISR_CLK1_STOP_MASK 0x00002000
| User clock 1 stopped. More...
#define | XCLK_WIZ_ISR_CLK0_STOP_MASK 0x00001000
| User clock 0 stopped. More...
#define | XCLK_WIZ_ISR_CLK3_GLITCH_MASK 0x00000800
| User clock 3 has glitch. More...
#define | XCLK_WIZ_ISR_CLK2_GLITCH_MASK 0x00000400
| User clock 2 has glitch. More...
#define | XCLK_WIZ_ISR_CLK1_GLITCH_MASK 0x00000200
| User clock 1 has glitch. More...
#define | XCLK_WIZ_ISR_CLK0_GLITCH_MASK 0x00000100
| User clock 0 has glitch. More...
#define | XCLK_WIZ_ISR_CLK3_MINFREQ_MASK 0x00000080
| User clock 3 is less than specification. More...
#define | XCLK_WIZ_ISR_CLK2_MINFREQ_MASK 0x00000040
| User clock 2 is less than specification. More...
#define | XCLK_WIZ_ISR_CLK1_MINFREQ_MASK 0x00000020
| User clock 1 is less than specification. More...
#define | XCLK_WIZ_ISR_CLK0_MINFREQ_MASK 0x00000010
| User clock 0 is less than specification. More...
#define | XCLK_WIZ_ISR_CLK3_MAXFREQ_MASK 0x00000008
| User clock 3 is max than specification. More...
#define | XCLK_WIZ_ISR_CLK2_MAXFREQ_MASK 0x00000004
| User clock 2 is max than specification. More...
#define | XCLK_WIZ_ISR_CLK1_MAXFREQ_MASK 0x00000002
| User clock 1 is max than specification. More...
#define | XCLK_WIZ_ISR_CLK0_MAXFREQ_MASK 0x00000001
| User clock 0 is max than specification. More...
#define | XCLK_WIZ_ISR_CLKALL_STOP_MASK 0x0000F000
| User clock[0-3] has stopped. More...
#define | XCLK_WIZ_ISR_CLKALL_GLITCH_MASK 0x00000F00
| User clock[0-3] has glitch. More...
#define | XCLK_WIZ_ISR_CLKALL_MINFREQ_MASK 0x000000F0
| User clock[0-3] is min than specification. More...
#define | XCLK_WIZ_ISR_CLKALL_MAXFREQ_MASK 0x0000000F
| User clock[0-3] is max than specification. More...
#define | XCLK_WIZ_ISR_CLK3_STOP_SHIFT 15
| Shift bits for User clock 3 stop. More...
#define | XCLK_WIZ_ISR_CLK2_STOP_SHIFT 14
| Shift bits for User clock 2 stop. More...
#define | XCLK_WIZ_ISR_CLK1_STOP_SHIFT 13
| Shift bits for User clock 1 stop. More...
#define | XCLK_WIZ_ISR_CLK0_STOP_SHIFT 12
| Shift bits for User clock 0 stop. More...
#define | XCLK_WIZ_ISR_CLK3_GLITCH_SHIFT 11
| Shift bits for User clock 3 glitch. More...
#define | XCLK_WIZ_ISR_CLK2_GLITCH_SHIFT 10
| Shift bits for User clock 2 glitch. More...
#define | XCLK_WIZ_ISR_CLK1_GLITCH_SHIFT 9
| Shift bits for User clock 1 glitch. More...
#define | XCLK_WIZ_ISR_CLK0_GLITCH_SHIFT 8
| Shift bits for User clock 0 glitch. More...
#define | XCLK_WIZ_ISR_CLK3_MINFREQ_SHIFT 7
| Shift bits for User clock 3 less. More...
#define | XCLK_WIZ_ISR_CLK2_MINFREQ_SHIFT 6
| Shift bits for User clock 2 less. More...
#define | XCLK_WIZ_ISR_CLK1_MINFREQ_SHIFT 5
| Shift bits for User clock 1 less. More...
#define | XCLK_WIZ_ISR_CLK0_MINFREQ_SHIFT 4
| Shift bits for User clock 0 less. More...
#define | XCLK_WIZ_ISR_CLK3_MAXFREQ_SHIFT 3
| Shift bits for User clock 3 max. More...
#define | XCLK_WIZ_ISR_CLK2_MAXFREQ_SHIFT 2
| Shift bits for User clock 2 max. More...
#define | XCLK_WIZ_ISR_CLK1_MAXFREQ_SHIFT 1
| Shift bits for User clock 1 max. More...
#define | XCLK_WIZ_ISR_CLK0_MAXFREQ_SHIFT 0
| Shift bits for User clock 0 max. More...
Bitmasks and offsets of XCLK_WIZ_IER_OFFSET register
This register is used to display interrupt status register
#define | XCLK_WIZ_IER_CLK3_STOP_MASK 0x00008000
| User clock 3 stopped. More...
#define | XCLK_WIZ_IER_CLK2_STOP_MASK 0x00004000
| User clock 2 stopped. More...
#define | XCLK_WIZ_IER_CLK1_STOP_MASK 0x00002000
| User clock 1 stopped. More...
#define | XCLK_WIZ_IER_CLK0_STOP_MASK 0x00001000
| User clock 0 stopped. More...
#define | XCLK_WIZ_IER_CLK3_GLITCH_MASK 0x00000800
| User clock 3 has glitch. More...
#define | XCLK_WIZ_IER_CLK2_GLITCH_MASK 0x00000400
| User clock 2 has glitch. More...
#define | XCLK_WIZ_IER_CLK1_GLITCH_MASK 0x00000200
| User clock 1 has glitch. More...
#define | XCLK_WIZ_IER_CLK0_GLITCH_MASK 0x00000100
| User clock 0 has glitch. More...
#define | XCLK_WIZ_IER_CLK3_MINFREQ_MASK 0x00000080
| User clock 3 is less than specification. More...
#define | XCLK_WIZ_IER_CLK2_MINFREQ_MASK 0x00000040
| User clock 2 is less than specification. More...
#define | XCLK_WIZ_IER_CLK1_MINFREQ_MASK 0x00000020
| User clock 1 is less than specification. More...
#define | XCLK_WIZ_IER_CLK0_MINFREQ_MASK 0x00000010
| User clock 0 is less than specification. More...
#define | XCLK_WIZ_IER_CLK3_MAXFREQ_MASK 0x00000008
| User clock 3 is max than specification. More...
#define | XCLK_WIZ_IER_CLK2_MAXFREQ_MASK 0x00000004
| User clock 2 is max than specification. More...
#define | XCLK_WIZ_IER_CLK1_MAXFREQ_MASK 0x00000002
| User clock 1 is max than specification. More...
#define | XCLK_WIZ_IER_CLK0_MAXFREQ_MASK 0x00000001
| User clock 0 is max than specification. More...
#define | XCLK_WIZ_IER_CLK3_STOP_SHIFT 15
| Shift bits for User clock 3 stop. More...
#define | XCLK_WIZ_IER_CLK2_STOP_SHIFT 14
| Shift bits for User clock 2 stop. More...
#define | XCLK_WIZ_IER_CLK1_STOP_SHIFT 13
| Shift bits for User clock 1 stop. More...
#define | XCLK_WIZ_IER_CLK0_STOP_SHIFT 12
| Shift bits for User clock 0 stop. More...
#define | XCLK_WIZ_IER_CLK3_GLITCH_SHIFT 11
| Shift bits for User clock 3 glitch. More...
#define | XCLK_WIZ_IER_CLK2_GLITCH_SHIFT 10
| Shift bits for User clock 2 glitch. More...
#define | XCLK_WIZ_IER_CLK1_GLITCH_SHIFT 9
| Shift bits for User clock 1 glitch. More...
#define | XCLK_WIZ_IER_CLK0_GLITCH_SHIFT 8
| Shift bits for User clock 0 glitch. More...
#define | XCLK_WIZ_IER_CLK3_MINFREQ_SHIFT 7
| Shift bits for User clock 3 less. More...
#define | XCLK_WIZ_IER_CLK2_MINFREQ_SHIFT 6
| Shift bits for User clock 2 less. More...
#define | XCLK_WIZ_IER_CLK1_MINFREQ_SHIFT 5
| Shift bits for User clock 1 less. More...
#define | XCLK_WIZ_IER_CLK0_MINFREQ_SHIFT 4
| Shift bits for User clock 0 less. More...
#define | XCLK_WIZ_IER_CLK3_MAXFREQ_SHIFT 3
| Shift bits for User clock 3 max. More...
#define | XCLK_WIZ_IER_CLK2_MAXFREQ_SHIFT 2
| Shift bits for User clock 2 max. More...
#define | XCLK_WIZ_IER_CLK1_MAXFREQ_SHIFT 1
| Shift bits for User clock 1 max. More...
#define | XCLK_WIZ_IER_CLK0_MAXFREQ_SHIFT 0
| Shift bits for User clock 0 max. More...