axidma: Axidma_v9_10

| axidma Xilinx SDK Drivers API Documentation

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Data Structures | Macros | Typedefs | Functions
Axidma_v9_10

## Data Structures
struct | XAxiDma
| The XAxiDma driver instance data. More...
struct | XAxiDma_Config
| The configuration structure for AXI DMA engine. More...
struct | XAxiDma_BdRing
| Container structure for descriptor storage control. More...

## Macros
#define | XAxiDma_GetTxRing(InstancePtr) (&((InstancePtr)->TxBdRing))
| Get Transmit (Tx) Ring ptr. More...
#define | XAxiDma_GetRxRing(InstancePtr) (&((InstancePtr)->RxBdRing[0]))
| Get Receive (Rx) Ring ptr. More...
#define | XAxiDma_GetRxIndexRing(InstancePtr, RingIndex) (&((InstancePtr)->RxBdRing[RingIndex]))
| Get Receive (Rx) Ring ptr of a Index. More...
#define | XAxiDma_HasSg(InstancePtr) ((InstancePtr)->HasSg) ? TRUE : FALSE
| This function checks whether system is configured as Simple or Scatter Gather mode. More...
#define | XAxiDma_IntrEnable(InstancePtr, Mask, Direction)
| This function enables interrupts specified by the Mask in specified direction, Interrupts that are not in the mask are not affected. More...
#define | XAxiDma_IntrGetEnabled(InstancePtr, Direction)
| This function gets the mask for the interrupts that are currently enabled. More...
#define | XAxiDma_IntrDisable(InstancePtr, Mask, Direction)
| This function disables interrupts specified by the Mask. More...
#define | XAxiDma_IntrGetIrq(InstancePtr, Direction)
| This function gets the interrupts that are asserted. More...
#define | XAxiDma_IntrAckIrq(InstancePtr, Mask, Direction)
| This function acknowledges the interrupts that are specified in Mask. More...
#define | XAxiDma_BdRead(BaseAddress, Offset) (*(u32 *)((UINTPTR)(BaseAddress) + (u32)(Offset)))
| Read the given Buffer Descriptor word. More...
#define | XAxiDma_BdWrite(BaseAddress, Offset, Data) (*(u32 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u32)(Data)
| Write the given Buffer Descriptor word. More...
#define | XAxiDma_BdWrite64(BaseAddress, Offset, Data) (*(u64 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u64)(Data)
| Write the given Buffer Descriptor word. More...
#define | XAxiDma_BdClear(BdPtr)
| Zero out BD specific fields. More...
#define | XAxiDma_BdGetCtrl(BdPtr)
| Get the control bits for the BD. More...
#define | XAxiDma_BdGetSts(BdPtr)
| Retrieve the status of a BD. More...
#define | XAxiDma_BdGetLength(BdPtr, LengthMask)
| Retrieve the length field value from the given BD. More...
#define | XAxiDma_BdSetId(BdPtr, Id) (XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_ID_OFFSET, (UINTPTR)(Id)))
| Set the ID field of the given BD. More...
#define | XAxiDma_BdGetId(BdPtr) (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_ID_OFFSET))
| Retrieve the ID field of the given BD previously set with XAxiDma_BdSetId. More...
#define | XAxiDma_BdGetBufAddr(BdPtr) (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_BUFA_OFFSET))
| Get the BD's buffer address. More...
#define | XAxiDma_BdHwCompleted(BdPtr)
| Check whether a BD has completed in hardware. More...
#define | XAxiDma_BdGetActualLength(BdPtr, LengthMask)
| Get the actual transfer length of a BD. More...
#define | XAxiDma_BdSetTId(BdPtr, TId)
| Set the TID field of the TX BD. More...
#define | XAxiDma_BdGetTId(BdPtr)
| Retrieve the TID field of the RX BD previously set with XAxiDma_BdSetTId. More...
#define | XAxiDma_BdSetTDest(BdPtr, TDest)
| Set the TDEST field of the TX BD. More...
#define | XAxiDma_BdGetTDest(BdPtr)
| Retrieve the TDest field of the RX BD previously set with i XAxiDma_BdSetTDest. More...
#define | XAxiDma_BdSetTUser(BdPtr, TUser)
| Set the TUSER field of the TX BD. More...
#define | XAxiDma_BdGetTUser(BdPtr)
| Retrieve the TUSER field of the RX BD previously set with XAxiDma_BdSetTUser. More...
#define | XAxiDma_BdSetARCache(BdPtr, ARCache)
| Set the ARCACHE field of the given BD. More...
#define | XAxiDma_BdGetARCache(BdPtr)
| Retrieve the ARCACHE field of the given BD previously set with XAxiDma_BdSetARCache. More...
#define | XAxiDma_BdSetARUser(BdPtr, ARUser)
| Set the ARUSER field of the given BD. More...
#define | XAxiDma_BdGetARUser(BdPtr)
| Retrieve the ARUSER field of the given BD previously set with XAxiDma_BdSetARUser. More...
#define | XAxiDma_BdSetStride(BdPtr, Stride)
| Set the STRIDE field of the given BD. More...
#define | XAxiDma_BdGetStride(BdPtr)
| Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetStride. More...
#define | XAxiDma_BdSetVSize(BdPtr, VSize)
| Set the VSIZE field of the given BD. More...
#define | XAxiDma_BdGetVSize(BdPtr)
| Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetVSize. More...
#define | XAxiDma_BdRingCntCalc(Alignment, Bytes) (uint32_t)((Bytes)/((sizeof(XAxiDma_Bd)+((Alignment)-1))&~((Alignment)-1)))
| Use this macro at initialization time to determine how many BDs will fit within the given memory constraints. More...
#define | XAxiDma_BdRingMemCalc(Alignment, NumBd) (int)((sizeof(XAxiDma_Bd)+((Alignment)-1)) & ~((Alignment)-1))*(NumBd)
| Use this macro at initialization time to determine how many bytes of memory are required to contain a given number of BDs at a given alignment. More...
#define | XAxiDma_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
| Return the total number of BDs allocated by this channel with XAxiDma_BdRingCreate(). More...
#define | XAxiDma_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
| Return the number of BDs allocatable with XAxiDma_BdRingAlloc() for pre- processing. More...
#define | XAxiDma_BdRingSnapShotCurrBd(RingPtr)
| Snap shot the latest BD a BD ring is processing. More...
#define | XAxiDma_BdRingGetCurrBd(RingPtr)
| Get the BD a BD ring is processing. More...
#define | XAxiDma_BdRingNext(RingPtr, BdPtr)
| Return the next BD in the ring. More...
#define | XAxiDma_BdRingPrev(RingPtr, BdPtr)
| Return the previous BD in the ring. More...
#define | XAxiDma_BdRingGetSr(RingPtr) XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET)
| Retrieve the contents of the channel status register. More...
#define | XAxiDma_BdRingGetError(RingPtr)
| Get error bits of a DMA channel. More...
#define | XAxiDma_BdRingHwIsStarted(RingPtr)
| Check whether a DMA channel is started, meaning the channel is not halted. More...
#define | XAxiDma_BdRingBusy(RingPtr)
| Check if the current DMA channel is busy with a DMA operation. More...
#define | XAxiDma_BdRingIntEnable(RingPtr, Mask)
| Set interrupt enable bits for a channel. More...
#define | XAxiDma_BdRingIntGetEnabled(RingPtr)
| Get enabled interrupts of a channel. More...
#define | XAxiDma_BdRingIntDisable(RingPtr, Mask)
| Clear interrupt enable bits for a channel. More...
#define | XAxiDma_BdRingGetIrq(RingPtr)
| Retrieve the contents of the channel's IRQ register XAXIDMA_SR_OFFSET. More...
#define | XAxiDma_BdRingAckIrq(RingPtr, Mask)
| Acknowledge asserted interrupts. More...
#define | XAxiDma_BdRingEnableCyclicDMA(RingPtr) (RingPtr->Cyclic = 1)
| Enable Cyclic DMA Mode. More...
#define | XAXIDMA_DESC_LSB_MASK (0xFFFFFFC0U)
| LSB Address mask. More...
#define | XAxiDma_ReadReg(BaseAddress, RegOffset) XAxiDma_In32((BaseAddress) + (RegOffset))
| Read the given register. More...
#define | XAxiDma_WriteReg(BaseAddress, RegOffset, Data) XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))
| Write the given register. More...

## Typedefs
typedef struct XAxiDma | XAxiDma
| The XAxiDma driver instance data. More...
typedef u32 | XAxiDma_Bd [XAXIDMA_BD_NUM_WORDS]
| The XAxiDma_Bd is the type for a buffer descriptor (BD). More...

## Functions
int | XAxiDma_CfgInitialize (XAxiDma *InstancePtr, XAxiDma_Config *Config)
| This function initializes a DMA engine. More...
void | XAxiDma_Reset (XAxiDma *InstancePtr)
| Reset both TX and RX channels of a DMA engine. More...
int | XAxiDma_ResetIsDone (XAxiDma *InstancePtr)
| Check whether reset is done. More...
int | XAxiDma_Pause (XAxiDma *InstancePtr)
| Pause DMA transactions on both channels. More...
int | XAxiDma_Resume (XAxiDma *InstancePtr)
| Resume DMA transactions on both channels. More...
u32 | XAxiDma_Busy (XAxiDma *InstancePtr, int Direction)
| This function checks whether specified DMA channel is busy. More...
int | XAxiDma_SelectKeyHole (XAxiDma *InstancePtr, int Direction, int Select)
| This function Enable or Disable KeyHole Feature. More...
int | XAxiDma_SelectCyclicMode (XAxiDma *InstancePtr, int Direction, int Select)
| This function Enable or Disable Cyclic Mode Feature. More...
u32 | XAxiDma_SimpleTransfer (XAxiDma *InstancePtr, UINTPTR BuffAddr, u32 Length, int Direction)
| This function does one simple transfer submission. More...
XAxiDma_Config * | XAxiDma_LookupConfig (u32 DeviceId)
| Look up the hardware configuration for a device instance. More...
XAxiDma_Config * | XAxiDma_LookupConfigBaseAddr (UINTPTR Baseaddr)
| Look up the hardware configuration for a device instance based on base address. More...
int | XAxiDma_Selftest (XAxiDma *InstancePtr)
| Runs a self-test on the driver/device. More...
int | XAxiDma_BdSetLength (XAxiDma_Bd *BdPtr, u32 LenBytes, u32 LengthMask)
| Set the length field for the given BD. More...
u32 | XAxiDma_BdSetBufAddr (XAxiDma_Bd *BdPtr, UINTPTR Addr)
| Set the BD's buffer address. More...
u32 | XAxiDma_BdSetBufAddrMicroMode (XAxiDma_Bd *BdPtr, UINTPTR Addr)
| Set the BD's buffer address when configured for Micro Mode. More...
int | XAxiDma_BdSetAppWord (XAxiDma_Bd *BdPtr, int Offset, u32 Word)
| Set the APP word at the specified APP word offset for a BD. More...
u32 | XAxiDma_BdGetAppWord (XAxiDma_Bd *BdPtr, int Offset, int *Valid)
| Get the APP word at the specified APP word offset for a BD. More...
void | XAxiDma_BdSetCtrl (XAxiDma_Bd *BdPtr, u32 Data)
| Set the control bits for a BD. More...
void | XAxiDma_DumpBd (XAxiDma_Bd *BdPtr)
| Dump the fields of a BD. More...
int | XAxiDma_UpdateBdRingCDesc (XAxiDma_BdRing *RingPtr)
| Update Current Descriptor. More...
u32 | XAxiDma_BdRingCreate (XAxiDma_BdRing *RingPtr, UINTPTR PhysAddr, UINTPTR VirtAddr, u32 Alignment, int BdCount)
| Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring. More...
int | XAxiDma_BdRingClone (XAxiDma_BdRing *RingPtr, XAxiDma_Bd *SrcBdPtr)
| Clone the given BD into every BD in the ring. More...
int | XAxiDma_StartBdRingHw (XAxiDma_BdRing *RingPtr)
| Start a DMA channel and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed. More...
int | XAxiDma_BdRingStart (XAxiDma_BdRing *RingPtr)
| Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed. More...
int | XAxiDma_BdRingSetCoalesce (XAxiDma_BdRing *RingPtr, u32 Counter, u32 Timer)
| Set interrupt coalescing parameters for the given descriptor ring channel. More...
void | XAxiDma_BdRingGetCoalesce (XAxiDma_BdRing *RingPtr, u32 *CounterPtr, u32 *TimerPtr)
| Retrieve current interrupt coalescing parameters from the given descriptor ring channel. More...
int | XAxiDma_BdRingAlloc (XAxiDma_BdRing *RingPtr, int NumBd, XAxiDma_Bd **BdSetPtr)
| Reserve locations in the BD ring. More...
int | XAxiDma_BdRingUnAlloc (XAxiDma_BdRing *RingPtr, int NumBd, XAxiDma_Bd *BdSetPtr)
| Fully or partially undo an XAxiDma_BdRingAlloc() operation. More...
int | XAxiDma_BdRingToHw (XAxiDma_BdRing *RingPtr, int NumBd, XAxiDma_Bd *BdSetPtr)
| Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc(). More...
int | XAxiDma_BdRingFromHw (XAxiDma_BdRing *RingPtr, int BdLimit, XAxiDma_Bd **BdSetPtr)
| Returns a set of BD(s) that have been processed by hardware. More...
int | XAxiDma_BdRingFree (XAxiDma_BdRing *RingPtr, int NumBd, XAxiDma_Bd *BdSetPtr)
| Frees a set of BDs that had been previously retrieved with XAxiDma_BdRingFromHw(). More...
int | XAxiDma_BdRingCheck (XAxiDma_BdRing *RingPtr)
| Check the internal data structures of the BD ring for the provided channel. More...
void | XAxiDma_BdRingDumpRegs (XAxiDma_BdRing *RingPtr)
| Dump the registers for a channel. More...

## DMA Transfer Direction
#define | XAXIDMA_DMA_TO_DEVICE 0x00
#define | XAXIDMA_DEVICE_TO_DMA 0x01

## Buffer Descriptor Alignment
#define | XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40
| Minimum byte alignment requirement for descriptors to satisfy both hardware/software needs. More...

## Micro DMA Buffer Address Alignment
#define | XAXIDMA_MICROMODE_MIN_BUF_ALIGN 0xFFF
| Minimum byte alignment requirement for buffer address in Micro DMA mode. More...

## Maximum transfer length
This is determined by hardware
#define | XAXIDMA_MCHAN_MAX_TRANSFER_LEN

## Device registers
Register sets on TX and RX channels are identical
#define | XAXIDMA_TX_OFFSET 0x00000000
| TX channel registers base offset. More...
#define | XAXIDMA_RX_OFFSET 0x00000030
| RX channel registers base offset. More...
#define | XAXIDMA_CR_OFFSET 0x00000000
| Channel control. More...
#define | XAXIDMA_SR_OFFSET 0x00000004
| Status. More...
#define | XAXIDMA_CDESC_OFFSET 0x00000008
| Current descriptor pointer. More...
#define | XAXIDMA_CDESC_MSB_OFFSET 0x0000000C
| Current descriptor pointer. More...
#define | XAXIDMA_TDESC_OFFSET 0x00000010
| Tail descriptor pointer. More...
#define | XAXIDMA_TDESC_MSB_OFFSET 0x00000014
| Tail descriptor pointer. More...
#define | XAXIDMA_SRCADDR_OFFSET 0x00000018
| Simple mode source address pointer. More...
#define | XAXIDMA_SRCADDR_MSB_OFFSET 0x0000001C
| Simple mode source address pointer. More...
#define | XAXIDMA_DESTADDR_OFFSET 0x00000018
| Simple mode destination address pointer. More...
#define | XAXIDMA_DESTADDR_MSB_OFFSET 0x0000001C
| Simple mode destination address pointer. More...
#define | XAXIDMA_BUFFLEN_OFFSET 0x00000028
| Tail descriptor pointer. More...
#define | XAXIDMA_SGCTL_OFFSET 0x0000002c
| SG Control Register. More...
#define | XAXIDMA_RX_CDESC0_OFFSET 0x00000040
| Multi-Channel DMA Descriptor Offsets. More...
#define | XAXIDMA_RX_CDESC0_MSB_OFFSET 0x00000044
| Rx Current Descriptor 0. More...
#define | XAXIDMA_RX_TDESC0_OFFSET 0x00000048
| Rx Tail Descriptor 0. More...
#define | XAXIDMA_RX_TDESC0_MSB_OFFSET 0x0000004C
| Rx Tail Descriptor 0. More...
#define | XAXIDMA_RX_NDESC_OFFSET 0x00000020
| Rx Next Descriptor Offset. More...

## Bitmasks of XAXIDMA_CR_OFFSET register
#define | XAXIDMA_CR_RUNSTOP_MASK 0x00000001
| Start/stop DMA channel. More...
#define | XAXIDMA_CR_RESET_MASK 0x00000004
| Reset DMA engine. More...
#define | XAXIDMA_CR_KEYHOLE_MASK 0x00000008
| Keyhole feature. More...
#define | XAXIDMA_CR_CYCLIC_MASK 0x00000010
| Cyclic Mode. More...

## Bitmasks of XAXIDMA_SR_OFFSET register
This register reports status of a DMA channel, including run/stop/idle state, errors, and interrupts (note that interrupt masks are shared with XAXIDMA_CR_OFFSET register, and are defined in the IRQ section. The interrupt coalescing threshold value and delay counter value are also shared with XAXIDMA_CR_OFFSET register, and are defined in a later section.
#define | XAXIDMA_HALTED_MASK 0x00000001
| DMA channel halted. More...
#define | XAXIDMA_IDLE_MASK 0x00000002
| DMA channel idle. More...
#define | XAXIDMA_ERR_INTERNAL_MASK 0x00000010
| Datamover internal err. More...
#define | XAXIDMA_ERR_SLAVE_MASK 0x00000020
| Datamover slave err. More...
#define | XAXIDMA_ERR_DECODE_MASK 0x00000040
| Datamover decode err. More...
#define | XAXIDMA_ERR_SG_INT_MASK 0x00000100
| SG internal err. More...
#define | XAXIDMA_ERR_SG_SLV_MASK 0x00000200
| SG slave err. More...
#define | XAXIDMA_ERR_SG_DEC_MASK 0x00000400
| SG decode err. More...
#define | XAXIDMA_ERR_ALL_MASK 0x00000770
| All errors. More...

## Bitmask for interrupts
These masks are shared by XAXIDMA_CR_OFFSET register and XAXIDMA_SR_OFFSET register
#define | XAXIDMA_IRQ_IOC_MASK 0x00001000
| Completion intr. More...
#define | XAXIDMA_IRQ_DELAY_MASK 0x00002000
| Delay interrupt. More...
#define | XAXIDMA_IRQ_ERROR_MASK 0x00004000
| Error interrupt. More...
#define | XAXIDMA_IRQ_ALL_MASK 0x00007000
| All interrupts. More...

## Bitmask and shift for delay and coalesce
These masks are shared by XAXIDMA_CR_OFFSET register and XAXIDMA_SR_OFFSET register
#define | XAXIDMA_DELAY_MASK 0xFF000000
| Delay timeout counter. More...
#define | XAXIDMA_COALESCE_MASK 0x00FF0000
| Coalesce counter. More...
#define | XAXIDMA_DELAY_SHIFT 24
#define | XAXIDMA_COALESCE_SHIFT 16

## Buffer Descriptor offsets
USR* fields are defined by higher level IP. setup for EMAC type devices. The first 13 words are used by hardware. All words after the 13rd word are for software use only.
#define | XAXIDMA_BD_NDESC_OFFSET 0x00
| Next descriptor pointer. More...
#define | XAXIDMA_BD_NDESC_MSB_OFFSET 0x04
| Next descriptor pointer. More...
#define | XAXIDMA_BD_BUFA_OFFSET 0x08
| Buffer address. More...
#define | XAXIDMA_BD_BUFA_MSB_OFFSET 0x0C
| Buffer address. More...
#define | XAXIDMA_BD_MCCTL_OFFSET 0x10
| Multichannel Control Fields. More...
#define | XAXIDMA_BD_STRIDE_VSIZE_OFFSET 0x14
| 2D Transfer Sizes More...
#define | XAXIDMA_BD_CTRL_LEN_OFFSET 0x18
| Control/buffer length. More...
#define | XAXIDMA_BD_STS_OFFSET 0x1C
| Status. More...
#define | XAXIDMA_BD_USR0_OFFSET 0x20
| User IP specific word0. More...
#define | XAXIDMA_BD_USR1_OFFSET 0x24
| User IP specific word1. More...
#define | XAXIDMA_BD_USR2_OFFSET 0x28
| User IP specific word2. More...
#define | XAXIDMA_BD_USR3_OFFSET 0x2C
| User IP specific word3. More...
#define | XAXIDMA_BD_USR4_OFFSET 0x30
| User IP specific word4. More...
#define | XAXIDMA_BD_ID_OFFSET 0x34
| Sw ID. More...
#define | XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38
| Whether has stscntrl strm. More...
#define | XAXIDMA_BD_HAS_DRE_OFFSET 0x3C
| Whether has DRE. More...
#define | XAXIDMA_BD_HAS_DRE_MASK 0xF00
| Whether has DRE mask. More...
#define | XAXIDMA_BD_WORDLEN_MASK 0xFF
| Whether has DRE mask. More...
#define | XAXIDMA_BD_HAS_DRE_SHIFT 8
| Whether has DRE shift. More...
#define | XAXIDMA_BD_WORDLEN_SHIFT 0
| Whether has DRE shift. More...
#define | XAXIDMA_BD_START_CLEAR 8
| Offset to start clear. More...
#define | XAXIDMA_BD_BYTES_TO_CLEAR 48
| BD specific bytes to be cleared. More...
#define | XAXIDMA_BD_NUM_WORDS 16U
| Total number of words for one BD. More...
#define | XAXIDMA_BD_HW_NUM_BYTES 52
| Number of bytes hw used. More...
#define | XAXIDMA_LAST_APPWORD 4

## Bitmasks of XAXIDMA_BD_CTRL_OFFSET register
#define | XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000
| First tx packet. More...
#define | XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000
| Last tx packet. More...
#define | XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000
| All control bits. More...

## Bitmasks of XAXIDMA_BD_STS_OFFSET register
#define | XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000
| Completed. More...
#define | XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000
| Decode error. More...
#define | XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000
| Slave error. More...
#define | XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000
| Internal err. More...
#define | XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000
| All errors. More...
#define | XAXIDMA_BD_STS_RXSOF_MASK 0x08000000
| First rx pkt. More...
#define | XAXIDMA_BD_STS_RXEOF_MASK 0x04000000
| Last rx pkt. More...
#define | XAXIDMA_BD_STS_ALL_MASK 0xFC000000
| All status bits. More...

## Bitmasks and shift values for XAXIDMA_BD_MCCTL_OFFSET register
#define | XAXIDMA_BD_TDEST_FIELD_MASK 0x0000000F
#define | XAXIDMA_BD_TID_FIELD_MASK 0x00000F00
#define | XAXIDMA_BD_TUSER_FIELD_MASK 0x000F0000
#define | XAXIDMA_BD_ARCACHE_FIELD_MASK 0x0F000000
#define | XAXIDMA_BD_ARUSER_FIELD_MASK 0xF0000000
#define | XAXIDMA_BD_TDEST_FIELD_SHIFT 0
#define | XAXIDMA_BD_TID_FIELD_SHIFT 8
#define | XAXIDMA_BD_TUSER_FIELD_SHIFT 16
#define | XAXIDMA_BD_ARCACHE_FIELD_SHIFT 24
#define | XAXIDMA_BD_ARUSER_FIELD_SHIFT 28

## Bitmasks and shift values for XAXIDMA_BD_STRIDE_VSIZE_OFFSET register
#define | XAXIDMA_BD_STRIDE_FIELD_MASK 0x0000FFFF
#define | XAXIDMA_BD_VSIZE_FIELD_MASK 0xFFF80000
#define | XAXIDMA_BD_STRIDE_FIELD_SHIFT 0
#define | XAXIDMA_BD_VSIZE_FIELD_SHIFT 19

## Macro Definition Documentation

#define XAXIDMA_BD_BUFA_MSB_OFFSET 0x0C

Buffer address.

#define XAXIDMA_BD_BUFA_OFFSET 0x08

Buffer address.

Referenced by XAxiDma_BdSetBufAddr(), XAxiDma_BdSetBufAddrMicroMode(), and XAxiDma_DumpBd().

#define XAXIDMA_BD_BYTES_TO_CLEAR 48

BD specific bytes to be cleared.

Referenced by XAxiDma_BdRingClone().

#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000

All control bits.

Referenced by XAxiDma_BdSetCtrl().

#define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18

Control/buffer length.

Referenced by XAxiDma_BdRingFromHw(), XAxiDma_BdRingToHw(), XAxiDma_BdSetCtrl(), XAxiDma_BdSetLength(), and XAxiDma_DumpBd().

#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000

Last tx packet.

Referenced by XAxiDma_BdRingFromHw(), and XAxiDma_BdRingToHw().

#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000

First tx packet.

Referenced by XAxiDma_BdRingToHw().

#define XAXIDMA_BD_HAS_DRE_MASK 0xF00

Whether has DRE mask.

Referenced by XAxiDma_BdSetBufAddr().

#define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C

Whether has DRE.

Referenced by XAxiDma_BdRingCreate(), XAxiDma_BdSetBufAddr(), and XAxiDma_DumpBd().

#define XAXIDMA_BD_HAS_DRE_SHIFT 8

Whether has DRE shift.

Referenced by XAxiDma_BdRingCreate().

#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38

Whether has stscntrl strm.

Referenced by XAxiDma_BdGetAppWord(), XAxiDma_BdRingCreate(), XAxiDma_BdSetAppWord(), and XAxiDma_DumpBd().

#define XAXIDMA_BD_HW_NUM_BYTES 52

Number of bytes hw used.

#define XAXIDMA_BD_ID_OFFSET 0x34

Sw ID.

Referenced by XAxiDma_DumpBd().

#define XAXIDMA_BD_MCCTL_OFFSET 0x10

Multichannel Control Fields.

Referenced by XAxiDma_DumpBd().

#define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40

Minimum byte alignment requirement for descriptors to satisfy both hardware/software needs.

Referenced by XAxiDma_BdRingCreate().

#define XAXIDMA_BD_NDESC_MSB_OFFSET 0x04

Next descriptor pointer.

Referenced by XAxiDma_BdRingCreate().

#define XAXIDMA_BD_NDESC_OFFSET 0x00

Next descriptor pointer.

Referenced by XAxiDma_BdRingCheck(), XAxiDma_BdRingCreate(), and XAxiDma_DumpBd().

#define XAXIDMA_BD_NUM_WORDS 16U

Total number of words for one BD.

#define XAXIDMA_BD_START_CLEAR 8

Offset to start clear.

Referenced by XAxiDma_BdRingClone().

#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET 0x14

2D Transfer Sizes

Referenced by XAxiDma_DumpBd().

#define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000

All errors.

#define XAXIDMA_BD_STS_ALL_MASK 0xFC000000

All status bits.

#define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000

Completed.

Referenced by XAxiDma_BdRingClone(), XAxiDma_BdRingFromHw(), XAxiDma_BdRingToHw(), and XAxiDma_StartBdRingHw().

#define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000

Decode error.

#define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000

Internal err.

#define XAXIDMA_BD_STS_OFFSET 0x1C

Status.

Referenced by XAxiDma_BdRingClone(), XAxiDma_BdRingFromHw(), XAxiDma_BdRingToHw(), XAxiDma_DumpBd(), and XAxiDma_StartBdRingHw().

#define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000

Last rx pkt.

Referenced by XAxiDma_BdRingFromHw().

#define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000

First rx pkt.

#define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000

Slave error.

#define XAXIDMA_BD_USR0_OFFSET 0x20

User IP specific word0.

Referenced by XAxiDma_BdGetAppWord(), XAxiDma_BdSetAppWord(), and XAxiDma_DumpBd().

#define XAXIDMA_BD_USR1_OFFSET 0x24

User IP specific word1.

Referenced by XAxiDma_DumpBd().

#define XAXIDMA_BD_USR2_OFFSET 0x28

User IP specific word2.

Referenced by XAxiDma_DumpBd().

#define XAXIDMA_BD_USR3_OFFSET 0x2C

User IP specific word3.

Referenced by XAxiDma_DumpBd().

#define XAXIDMA_BD_USR4_OFFSET 0x30

User IP specific word4.

Referenced by XAxiDma_DumpBd().

#define XAXIDMA_BD_WORDLEN_MASK 0xFF

Whether has DRE mask.

Referenced by XAxiDma_BdSetBufAddr().

#define XAXIDMA_BD_WORDLEN_SHIFT 0

Whether has DRE shift.

#define XAxiDma_BdClear | ( |  | BdPtr | ) |

Value:
memset((void *)(((UINTPTR)(BdPtr)) + XAXIDMA_BD_START_CLEAR), 0, \
XAXIDMA_BD_BYTES_TO_CLEAR)
XAXIDMA_BD_BYTES_TO_CLEAR
#define XAXIDMA_BD_BYTES_TO_CLEAR
BD specific bytes to be cleared.
Definition: xaxidma_hw.h:242
XAXIDMA_BD_START_CLEAR
#define XAXIDMA_BD_START_CLEAR
Offset to start clear.
Definition: xaxidma_hw.h:241

Zero out BD specific fields.

BD fields that are for the BD ring or for the system hardware build information are not touched.

Parameters

  BdPtr | is the BD to operate on

Returns
  None

Note
  C-style signature: void XAxiDma_BdClear(XAxiDma_Bd* BdPtr)

#define XAxiDma_BdGetActualLength | ( |  | BdPtr,
|  |  | LengthMask
| ) |  |

Value:
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
LengthMask)
XAXIDMA_BD_STS_OFFSET
#define XAXIDMA_BD_STS_OFFSET
Status.
Definition: xaxidma_hw.h:223
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Get the actual transfer length of a BD.

The BD has completed in hw.

This function may not work if the BD is in cached memory.

Parameters

  BdPtr | is the BD to check on
  LengthMask | is the Maximum Transfer Length.

Returns
  None

Note
  C-style signature: int XAxiDma_BdGetActualLength(XAxiDma_Bd* BdPtr)

#define XAxiDma_BdGetARCache | ( |  | BdPtr | ) |

Value:
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) & \
XAXIDMA_BD_ARCACHE_FIELD_MASK)
XAXIDMA_BD_MCCTL_OFFSET
#define XAXIDMA_BD_MCCTL_OFFSET
Multichannel Control Fields.
Definition: xaxidma_hw.h:220
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Retrieve the ARCACHE field of the given BD previously set with XAxiDma_BdSetARCache.

Parameters

  BdPtr | is the BD to operate on

Returns
  None

Note
  C-style signature: u32 XAxiDma_BdGetARCache(XAxiDma_Bd* BdPtr)

#define XAxiDma_BdGetARUser | ( |  | BdPtr | ) |

Value:
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET)) & \
XAXIDMA_BD_ARUSER_FIELD_MASK)
XAXIDMA_BD_MCCTL_OFFSET
#define XAXIDMA_BD_MCCTL_OFFSET
Multichannel Control Fields.
Definition: xaxidma_hw.h:220
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Retrieve the ARUSER field of the given BD previously set with XAxiDma_BdSetARUser.

Parameters

  BdPtr | is the BD to operate on

Returns
  None

Note
  C-style signature: u32 XAxiDma_BdGetARUser(XAxiDma_Bd* BdPtr)

#define XAxiDma_BdGetBufAddr | ( |  | BdPtr | ) | (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_BUFA_OFFSET))

Get the BD's buffer address.

Parameters

  BdPtr | is the BD to operate on

Returns
  None

Note
  C-style signature: u32 XAxiDma_BdGetBufAddr(XAxiDma_Bd* BdPtr)

#define XAxiDma_BdGetCtrl | ( |  | BdPtr | ) |

Value:
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) \
& XAXIDMA_BD_CTRL_ALL_MASK)
XAXIDMA_BD_CTRL_LEN_OFFSET
#define XAXIDMA_BD_CTRL_LEN_OFFSET
Control/buffer length.
Definition: xaxidma_hw.h:222
XAXIDMA_BD_CTRL_ALL_MASK
#define XAXIDMA_BD_CTRL_ALL_MASK
All control bits.
Definition: xaxidma_hw.h:263
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Get the control bits for the BD.

Parameters

  BdPtr | is the BD to operate on

Returns
  The bit mask for the control of the BD

Note
  C-style signature: u32 XAxiDma_BdGetCtrl(XAxiDma_Bd* BdPtr)

Referenced by XAxiDma_BdRingToHw().

#define XAxiDma_BdGetId | ( |  | BdPtr | ) | (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_ID_OFFSET))

Retrieve the ID field of the given BD previously set with XAxiDma_BdSetId.

Parameters

  BdPtr | is the BD to operate on

Returns
  None

Note
  C-style signature: u32 XAxiDma_BdGetId(XAxiDma_Bd* BdPtr)

#define XAxiDma_BdGetLength | ( |  | BdPtr,
|  |  | LengthMask
| ) |  |

Value:
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_CTRL_LEN_OFFSET) & \
LengthMask)
XAXIDMA_BD_CTRL_LEN_OFFSET
#define XAXIDMA_BD_CTRL_LEN_OFFSET
Control/buffer length.
Definition: xaxidma_hw.h:222
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Retrieve the length field value from the given BD.

The returned value is the same as what was written with XAxiDma_BdSetLength(). Note that in the this value does not reflect the real length of received data. See the comments of XAxiDma_BdSetLength() for more details. To obtain the actual transfer length, use XAxiDma_BdGetActualLength().

Parameters

  BdPtr | is the BD to operate on.
  LengthMask | is the Maximum Transfer Length.

Returns
  The length value set in the BD.

Note
  C-style signature: u32 XAxiDma_BdGetLength(XAxiDma_Bd* BdPtr)

Referenced by XAxiDma_BdRingToHw().

#define XAxiDma_BdGetStride | ( |  | BdPtr | ) |

Value:
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) & \
XAXIDMA_BD_STRIDE_FIELD_MASK)
XAXIDMA_BD_STRIDE_VSIZE_OFFSET
#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET
2D Transfer Sizes
Definition: xaxidma_hw.h:221
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetStride.

Parameters

  BdPtr | is the BD to operate on

Returns
  None

Note
  C-style signature: u32 XAxiDma_BdGetStride(XAxiDma_Bd* BdPtr)

#define XAxiDma_BdGetSts | ( |  | BdPtr | ) |

Value:
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
XAXIDMA_BD_STS_ALL_MASK)
XAXIDMA_BD_STS_ALL_MASK
#define XAXIDMA_BD_STS_ALL_MASK
All status bits.
Definition: xaxidma_hw.h:276
XAXIDMA_BD_STS_OFFSET
#define XAXIDMA_BD_STS_OFFSET
Status.
Definition: xaxidma_hw.h:223
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Retrieve the status of a BD.

Parameters

  BdPtr | is the BD to operate on

Returns
  Word at offset XAXIDMA_BD_DMASR_OFFSET. Use XAXIDMA_BD_STS_*** values defined in xaxidma_hw.h to interpret the returned value

Note
  C-style signature: u32 XAxiDma_BdGetSts(XAxiDma_Bd* BdPtr)

Referenced by XAxiDma_BdRingToHw().

#define XAxiDma_BdGetTDest | ( |  | BdPtr | ) |

Value:
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) & \
XAXIDMA_BD_TDEST_FIELD_MASK)
XAXIDMA_BD_STS_OFFSET
#define XAXIDMA_BD_STS_OFFSET
Status.
Definition: xaxidma_hw.h:223
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Retrieve the TDest field of the RX BD previously set with i XAxiDma_BdSetTDest.

Parameters

  BdPtr | is the BD to operate on

Returns
  None

Note
  C-style signature: u32 XAxiDma_BdGetTDest(XAxiDma_Bd* BdPtr)

#define XAxiDma_BdGetTId | ( |  | BdPtr | ) |

Value:
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) & \
XAXIDMA_BD_TID_FIELD_MASK)
XAXIDMA_BD_STS_OFFSET
#define XAXIDMA_BD_STS_OFFSET
Status.
Definition: xaxidma_hw.h:223
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Retrieve the TID field of the RX BD previously set with XAxiDma_BdSetTId.

Parameters

  BdPtr | is the BD to operate on

Returns
  None

Note
  C-style signature: u32 XAxiDma_BdGetTId(XAxiDma_Bd* BdPtr)

#define XAxiDma_BdGetTUser | ( |  | BdPtr | ) |

Value:
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET)) & \
XAXIDMA_BD_TUSER_FIELD_MASK)
XAXIDMA_BD_STS_OFFSET
#define XAXIDMA_BD_STS_OFFSET
Status.
Definition: xaxidma_hw.h:223
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Retrieve the TUSER field of the RX BD previously set with XAxiDma_BdSetTUser.

Parameters

  BdPtr | is the BD to operate on

Returns
  None

Note
  C-style signature: u32 XAxiDma_BdGetTUser(XAxiDma_Bd* BdPtr)

#define XAxiDma_BdGetVSize | ( |  | BdPtr | ) |

Value:
((XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET)) & \
XAXIDMA_BD_VSIZE_FIELD_MASK)
XAXIDMA_BD_STRIDE_VSIZE_OFFSET
#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET
2D Transfer Sizes
Definition: xaxidma_hw.h:221
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Retrieve the STRIDE field of the given BD previously set with XAxiDma_BdSetVSize.

Parameters

  BdPtr | is the BD to operate on

Returns
  None

Note
  C-style signature: u32 XAxiDma_BdGetVSize(XAxiDma_Bd* BdPtr)

#define XAxiDma_BdHwCompleted | ( |  | BdPtr | ) |

Value:
(XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STS_OFFSET) & \
XAXIDMA_BD_STS_COMPLETE_MASK)
XAXIDMA_BD_STS_COMPLETE_MASK
#define XAXIDMA_BD_STS_COMPLETE_MASK
Completed.
Definition: xaxidma_hw.h:269
XAXIDMA_BD_STS_OFFSET
#define XAXIDMA_BD_STS_OFFSET
Status.
Definition: xaxidma_hw.h:223
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Check whether a BD has completed in hardware.

This BD has been submitted to hardware. The application can use this function to poll for the completion of the BD.

This function may not work if the BD is in cached memory.

Parameters

  BdPtr | is the BD to check on

Returns
  - 0 if not complete
  - XAXIDMA_BD_STS_COMPLETE_MASK if completed, may contain XAXIDMA_BD_STS_*_ERR_MASK bits.

Note
  C-style signature: int XAxiDma_BdHwCompleted(XAxiDma_Bd* BdPtr)

Referenced by XAxiDma_UpdateBdRingCDesc().

#define XAxiDma_BdRead | ( |  | BaseAddress,
|  |  | Offset
| ) |  | (*(u32 *)((UINTPTR)(BaseAddress) + (u32)(Offset)))

Read the given Buffer Descriptor word.

Parameters

  BaseAddress | is the base address of the BD to read
  Offset | is the word offset to be read

Returns
  The 32-bit value of the field

Note
  C-style signature: u32 XAxiDma_BdRead(u32 BaseAddress, u32 Offset)

Referenced by XAxiDma_BdGetAppWord(), XAxiDma_BdRingCheck(), XAxiDma_BdRingClone(), XAxiDma_BdRingFromHw(), XAxiDma_BdRingToHw(), XAxiDma_BdSetAppWord(), XAxiDma_BdSetBufAddr(), XAxiDma_BdSetCtrl(), XAxiDma_BdSetLength(), XAxiDma_DumpBd(), and XAxiDma_StartBdRingHw().

#define XAxiDma_BdRingAckIrq | ( |  | RingPtr,
|  |  | Mask
| ) |  |

Value:
XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET,\
(Mask) & XAXIDMA_IRQ_ALL_MASK)
XAxiDma_WriteReg
#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)
Write the given register.
Definition: xaxidma_hw.h:346
XAXIDMA_IRQ_ALL_MASK
#define XAXIDMA_IRQ_ALL_MASK
All interrupts.
Definition: xaxidma_hw.h:189
XAXIDMA_SR_OFFSET
#define XAXIDMA_SR_OFFSET
Status.
Definition: xaxidma_hw.h:122

Acknowledge asserted interrupts.

It modifies XAXIDMA_SR_OFFSET register. A mask bit set for an unasserted interrupt has no effect.

Parameters

  RingPtr | is the channel instance to operate on.
  Mask | are the interrupt signals to acknowledge

Note
  C-style signature: void XAxiDma_BdRingAckIrq(XAxiDma_BdRing* RingPtr) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingBusy | ( |  | RingPtr | ) |

Value:
(XAxiDma_BdRingHwIsStarted(RingPtr) && \
((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
& XAXIDMA_IDLE_MASK) ? FALSE : TRUE))
XAXIDMA_IDLE_MASK
#define XAXIDMA_IDLE_MASK
DMA channel idle.
Definition: xaxidma_hw.h:168
XAxiDma_ReadReg
#define XAxiDma_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xaxidma_hw.h:327
XAXIDMA_SR_OFFSET
#define XAXIDMA_SR_OFFSET
Status.
Definition: xaxidma_hw.h:122
XAxiDma_BdRingHwIsStarted
#define XAxiDma_BdRingHwIsStarted(RingPtr)
Check whether a DMA channel is started, meaning the channel is not halted.
Definition: xaxidma_bdring.h:366

Check if the current DMA channel is busy with a DMA operation.

Parameters

  RingPtr | is the channel instance to operate on.

Returns
  - 1 if the DMA is busy.
  - 0 otherwise

Note
  C-style signature: int XAxiDma_BdRingBusy(XAxiDma_BdRing* RingPtr) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingCntCalc | ( |  | Alignment,
|  |  | Bytes
| ) |  | (uint32_t)((Bytes)/((sizeof(XAxiDma_Bd)+((Alignment)-1))&~((Alignment)-1)))

Use this macro at initialization time to determine how many BDs will fit within the given memory constraints.

The results of this macro can be provided to XAxiDma_BdRingCreate().

Parameters

  Alignment | specifies what byte alignment the BDs must fall on and must be a power of 2 to get an accurate calculation (32, 64, 126,...)
  Bytes | is the number of bytes to be used to store BDs.

Returns
  Number of BDs that can fit in the given memory area

Note
  C-style signature: int XAxiDma_BdRingCntCalc(u32 Alignment, u32 Bytes) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingEnableCyclicDMA | ( |  | RingPtr | ) | (RingPtr->Cyclic = 1)

Enable Cyclic DMA Mode.

Parameters

  RingPtr | is the channel instance to operate on.

Note
  C-style signature: void XAxiDma_BdRingEnableCyclicDMA(XAxiDma_BdRing* RingPtr) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingGetCnt | ( |  | RingPtr | ) | ((RingPtr)->AllCnt)

Return the total number of BDs allocated by this channel with XAxiDma_BdRingCreate().

Parameters

  RingPtr | is the BD ring to operate on.

Returns
  The total number of BDs allocated for this channel.

Note
  C-style signature: int XAxiDma_BdRingGetCnt(XAxiDma_BdRing* RingPtr) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingGetCurrBd | ( |  | RingPtr | ) |

Value:
(XAxiDma_Bd *)XAxiDma_ReadReg((RingPtr)->ChanBase, \
XAXIDMA_CDESC_OFFSET) \
XAxiDma_ReadReg
#define XAxiDma_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xaxidma_hw.h:327
XAxiDma_Bd
u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]
The XAxiDma_Bd is the type for a buffer descriptor (BD).
Definition: xaxidma_bd.h:131
XAXIDMA_CDESC_OFFSET
#define XAXIDMA_CDESC_OFFSET
Current descriptor pointer.
Definition: xaxidma_hw.h:123

Get the BD a BD ring is processing.

Parameters

  RingPtr | is the BD ring to operate on.

Returns
  The current BD that the BD ring is working on

Note
  C-style signature: XAxiDma_Bd * XAxiDma_BdRingGetCurrBd(XAxiDma_BdRing* RingPtr) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingGetError | ( |  | RingPtr | ) |

Value:
(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
& XAXIDMA_ERR_ALL_MASK)
XAxiDma_ReadReg
#define XAxiDma_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xaxidma_hw.h:327
XAXIDMA_ERR_ALL_MASK
#define XAXIDMA_ERR_ALL_MASK
All errors.
Definition: xaxidma_hw.h:179
XAXIDMA_SR_OFFSET
#define XAXIDMA_SR_OFFSET
Status.
Definition: xaxidma_hw.h:122

Get error bits of a DMA channel.

Parameters

  RingPtr | is the channel instance to operate on.

Returns
  Rrror bits in the status register, they should be interpreted with XAXIDMA_ERR_*_MASK defined in xaxidma_hw.h

Note
  C-style signature: u32 XAxiDma_BdRingGetError(XAxiDma_BdRing* RingPtr) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingGetFreeCnt | ( |  | RingPtr | ) | ((RingPtr)->FreeCnt)

Return the number of BDs allocatable with XAxiDma_BdRingAlloc() for pre- processing.

Parameters

  RingPtr | is the BD ring to operate on.

Returns
  The number of BDs currently allocatable.

Note
  C-style signature: int XAxiDma_BdRingGetFreeCnt(XAxiDma_BdRing* RingPtr) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingGetIrq | ( |  | RingPtr | ) |

Value:
(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
& XAXIDMA_IRQ_ALL_MASK)
XAxiDma_ReadReg
#define XAxiDma_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xaxidma_hw.h:327
XAXIDMA_IRQ_ALL_MASK
#define XAXIDMA_IRQ_ALL_MASK
All interrupts.
Definition: xaxidma_hw.h:189
XAXIDMA_SR_OFFSET
#define XAXIDMA_SR_OFFSET
Status.
Definition: xaxidma_hw.h:122

Retrieve the contents of the channel's IRQ register XAXIDMA_SR_OFFSET.

This operation can be used to see which interrupts are pending.

Parameters

  RingPtr | is the channel instance to operate on.

Returns
  Current contents of the IRQ_OFFSET register. Use XAXIDMA_IRQ_*** values defined in xaxidma_hw.h to interpret the returned value.

Note
  C-style signature: u32 XAxiDma_BdRingGetIrq(XAxiDma_BdRing* RingPtr) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingGetSr | ( |  | RingPtr | ) | XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET)

Retrieve the contents of the channel status register.

Parameters

  RingPtr | is the channel instance to operate on.

Returns
  Current contents of status register

Note
  C-style signature: u32 XAxiDma_BdRingGetSr(XAxiDma_BdRing* RingPtr) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingHwIsStarted | ( |  | RingPtr | ) |

Value:
((XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_SR_OFFSET) \
& XAXIDMA_HALTED_MASK) ? FALSE : TRUE)
XAxiDma_ReadReg
#define XAxiDma_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xaxidma_hw.h:327
XAXIDMA_SR_OFFSET
#define XAXIDMA_SR_OFFSET
Status.
Definition: xaxidma_hw.h:122
XAXIDMA_HALTED_MASK
#define XAXIDMA_HALTED_MASK
DMA channel halted.
Definition: xaxidma_hw.h:167

Check whether a DMA channel is started, meaning the channel is not halted.

Parameters

  RingPtr | is the channel instance to operate on.

Returns
  - 1 if channel is started
  - 0 otherwise

Note
  C-style signature: int XAxiDma_BdRingHwIsStarted(XAxiDma_BdRing* RingPtr)

Referenced by XAxiDma_StartBdRingHw(), and XAxiDma_UpdateBdRingCDesc().

#define XAxiDma_BdRingIntDisable | ( |  | RingPtr,
|  |  | Mask
| ) |  |

Value:
(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \
XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) & \
~((Mask) & XAXIDMA_IRQ_ALL_MASK)))
XAXIDMA_CR_OFFSET
#define XAXIDMA_CR_OFFSET
Channel control.
Definition: xaxidma_hw.h:121
XAxiDma_ReadReg
#define XAxiDma_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xaxidma_hw.h:327
XAxiDma_WriteReg
#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)
Write the given register.
Definition: xaxidma_hw.h:346
XAXIDMA_IRQ_ALL_MASK
#define XAXIDMA_IRQ_ALL_MASK
All interrupts.
Definition: xaxidma_hw.h:189

Clear interrupt enable bits for a channel.

It modifies the XAXIDMA_CR_OFFSET register.

Parameters

  RingPtr | is the channel instance to operate on.
  Mask | consists of the interrupt signals to disable.Bits not specified in the Mask are not affected.

Note
  C-style signature: void XAxiDma_BdRingIntDisable(XAxiDma_BdRing* RingPtr, u32 Mask) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingIntEnable | ( |  | RingPtr,
|  |  | Mask
| ) |  |

Value:
(XAxiDma_WriteReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET, \
XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \
| ((Mask) & XAXIDMA_IRQ_ALL_MASK)))
XAXIDMA_CR_OFFSET
#define XAXIDMA_CR_OFFSET
Channel control.
Definition: xaxidma_hw.h:121
XAxiDma_ReadReg
#define XAxiDma_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xaxidma_hw.h:327
XAxiDma_WriteReg
#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)
Write the given register.
Definition: xaxidma_hw.h:346
XAXIDMA_IRQ_ALL_MASK
#define XAXIDMA_IRQ_ALL_MASK
All interrupts.
Definition: xaxidma_hw.h:189

Set interrupt enable bits for a channel.

This operation will modify the XAXIDMA_CR_OFFSET register.

Parameters

  RingPtr | is the channel instance to operate on.
  Mask | consists of the interrupt signals to enable.Bits not specified in the mask are not affected.

Note
  C-style signature: void XAxiDma_BdRingIntEnable(XAxiDma_BdRing* RingPtr, u32 Mask) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingIntGetEnabled | ( |  | RingPtr | ) |

Value:
(XAxiDma_ReadReg((RingPtr)->ChanBase, XAXIDMA_CR_OFFSET) \
& XAXIDMA_IRQ_ALL_MASK)
XAXIDMA_CR_OFFSET
#define XAXIDMA_CR_OFFSET
Channel control.
Definition: xaxidma_hw.h:121
XAxiDma_ReadReg
#define XAxiDma_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xaxidma_hw.h:327
XAXIDMA_IRQ_ALL_MASK
#define XAXIDMA_IRQ_ALL_MASK
All interrupts.
Definition: xaxidma_hw.h:189

Get enabled interrupts of a channel.

It is in XAXIDMA_CR_OFFSET register.

Parameters

  RingPtr | is the channel instance to operate on.

Returns
  Enabled interrupts of a channel. Use XAXIDMA_IRQ_* defined in xaxidma_hw.h to interpret this returned value.

Note
  C-style signature: u32 XAxiDma_BdRingIntGetEnabled(XAxiDma_BdRing* RingPtr) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingMemCalc | ( |  | Alignment,
|  |  | NumBd
| ) |  | (int)((sizeof(XAxiDma_Bd)+((Alignment)-1)) & ~((Alignment)-1))*(NumBd)

Use this macro at initialization time to determine how many bytes of memory are required to contain a given number of BDs at a given alignment.

Parameters

  Alignment | specifies what byte alignment the BDs must fall on. This parameter must be a power of 2 to get an accurate calculation (32, 64,128,...)
  NumBd | is the number of BDs to calculate memory size requirements

Returns
  The number of bytes of memory required to create a BD list with the given memory constraints.

Note
  C-style signature: int XAxiDma_BdRingMemCalc(u32 Alignment, u32 NumBd) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingNext | ( |  | RingPtr,
|  |  | BdPtr
| ) |  |

Value:
(((UINTPTR)(BdPtr) >= (RingPtr)->LastBdAddr) ? \
(UINTPTR)(RingPtr)->FirstBdAddr : \
(UINTPTR)((UINTPTR)(BdPtr) + (RingPtr)->Separation))

Return the next BD in the ring.

Parameters

  RingPtr | is the BD ring to operate on.
  BdPtr | is the current BD.

Returns
  The next BD in the ring relative to the BdPtr parameter.

Note
  C-style signature: XAxiDma_Bd XAxiDma_BdRingNext(XAxiDma_BdRing RingPtr, XAxiDma_Bd *BdPtr) This function is used only when system is configured as SG mode

Referenced by XAxiDma_BdRingFromHw(), XAxiDma_BdRingToHw(), and XAxiDma_UpdateBdRingCDesc().

#define XAxiDma_BdRingPrev | ( |  | RingPtr,
|  |  | BdPtr
| ) |  |

Value:
(((u32)(BdPtr) <= (RingPtr)->FirstBdAddr) ? \
(XAxiDma_Bd*)(RingPtr)->LastBdAddr : \
(XAxiDma_Bd*)((u32)(BdPtr) - (RingPtr)->Separation))
XAxiDma_Bd
u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]
The XAxiDma_Bd is the type for a buffer descriptor (BD).
Definition: xaxidma_bd.h:131

Return the previous BD in the ring.

Parameters

  RingPtr | is the DMA channel to operate on.
  BdPtr | is the current BD.

Returns
  The previous BD in the ring relative to the BdPtr parameter.

Note
  C-style signature: XAxiDma_Bd XAxiDma_BdRingPrev(XAxiDma_BdRing RingPtr, XAxiDma_Bd *BdPtr) This function is used only when system is configured as SG mode

#define XAxiDma_BdRingSnapShotCurrBd | ( |  | RingPtr | ) |

Value:
{ \
if (!RingPtr->IsRxChannel) { \
(RingPtr)->BdaRestart = \
(XAxiDma_Bd *)(UINTPTR)XAxiDma_ReadReg( \
(RingPtr)->ChanBase, \
XAXIDMA_CDESC_OFFSET); \
} else { \
if (!RingPtr->RingIndex) { \
(RingPtr)->BdaRestart = \
(XAxiDma_Bd *)(UINTPTR)XAxiDma_ReadReg( \
(RingPtr)->ChanBase, \
XAXIDMA_CDESC_OFFSET); \
} else { \
(RingPtr)->BdaRestart = \
(XAxiDma_Bd *)(UINTPTR)XAxiDma_ReadReg( \
(RingPtr)->ChanBase, \
(XAXIDMA_RX_CDESC0_OFFSET + \
(RingPtr->RingIndex - 1) * \
XAXIDMA_RX_NDESC_OFFSET)); \
} \
} \
}
XAxiDma_ReadReg
#define XAxiDma_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xaxidma_hw.h:327
XAxiDma_Bd
u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]
The XAxiDma_Bd is the type for a buffer descriptor (BD).
Definition: xaxidma_bd.h:131
XAXIDMA_RX_NDESC_OFFSET
#define XAXIDMA_RX_NDESC_OFFSET
Rx Next Descriptor Offset.
Definition: xaxidma_hw.h:143
XAXIDMA_CDESC_OFFSET
#define XAXIDMA_CDESC_OFFSET
Current descriptor pointer.
Definition: xaxidma_hw.h:123
XAXIDMA_RX_CDESC0_OFFSET
#define XAXIDMA_RX_CDESC0_OFFSET
Multi-Channel DMA Descriptor Offsets.
Definition: xaxidma_hw.h:139

Snap shot the latest BD a BD ring is processing.

Parameters

  RingPtr | is the BD ring to operate on.

Returns
  None

Note
  C-style signature: void XAxiDma_BdRingSnapShotCurrBd(XAxiDma_BdRing* RingPtr) This function is used only when system is configured as SG mode

Referenced by XAxiDma_Reset().

#define XAxiDma_BdSetARCache | ( |  | BdPtr,
|  |  | ARCache
| ) |  |

Value:
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_ARCACHE_FIELD_MASK); \
val |= ((u32)(ARCache) << XAXIDMA_BD_ARCACHE_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
XAXIDMA_BD_MCCTL_OFFSET
#define XAXIDMA_BD_MCCTL_OFFSET
Multichannel Control Fields.
Definition: xaxidma_hw.h:220
XAxiDma_BdWrite
#define XAxiDma_BdWrite(BaseAddress, Offset, Data)
Write the given Buffer Descriptor word.
Definition: xaxidma_bd.h:185
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Set the ARCACHE field of the given BD.

This signal provides additional information about the cacheable characteristics of the transfer.

Parameters

  BdPtr | is the BD to operate on
  ARCache | is a 8 bit quantity to set in the BD

Returns
  None

Note
  C-style signature: void XAxiDma_BdSetARCache(XAxiDma_Bd* BdPtr, void ARCache)

#define XAxiDma_BdSetARUser | ( |  | BdPtr,
|  |  | ARUser
| ) |  |

Value:
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_ARUSER_FIELD_MASK); \
val |= ((u32)(ARUser) << XAXIDMA_BD_ARUSER_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
XAXIDMA_BD_MCCTL_OFFSET
#define XAXIDMA_BD_MCCTL_OFFSET
Multichannel Control Fields.
Definition: xaxidma_hw.h:220
XAxiDma_BdWrite
#define XAxiDma_BdWrite(BaseAddress, Offset, Data)
Write the given Buffer Descriptor word.
Definition: xaxidma_bd.h:185
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Set the ARUSER field of the given BD.

Sideband signals used for user defined information.

Parameters

  BdPtr | is the BD to operate on
  ARUser | is a 8 bit quantity to set in the BD

Returns
  None

Note
  C-style signature: void XAxiDma_BdSetARUser(XAxiDma_Bd* BdPtr, void ARUser)

#define XAxiDma_BdSetId | ( |  | BdPtr,
|  |  | Id
| ) |  | (XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_ID_OFFSET, (UINTPTR)(Id)))

Set the ID field of the given BD.

The ID is an arbitrary piece of data the application can associate with a specific BD.

Parameters

  BdPtr | is the BD to operate on
  Id | is a 32 bit quantity to set in the BD

Returns
  None

Note
  C-style signature: void XAxiDma_BdSetId(XAxiDma_Bd* BdPtr, void Id)

#define XAxiDma_BdSetStride | ( |  | BdPtr,
|  |  | Stride
| ) |  |

Value:
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \
~XAXIDMA_BD_STRIDE_FIELD_MASK); \
val |= ((u32)(Stride) << XAXIDMA_BD_STRIDE_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \
}
XAxiDma_BdWrite
#define XAxiDma_BdWrite(BaseAddress, Offset, Data)
Write the given Buffer Descriptor word.
Definition: xaxidma_bd.h:185
XAXIDMA_BD_STRIDE_VSIZE_OFFSET
#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET
2D Transfer Sizes
Definition: xaxidma_hw.h:221
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Set the STRIDE field of the given BD.

It is the address distance between the first address of successive horizontal reads.

Parameters

  BdPtr | is the BD to operate on
  Stride | is a 32 bit quantity to set in the BD

Returns
  None

Note
  C-style signature: void XAxiDma_BdSetStride(XAxiDma_Bd* BdPtr, void Stride)

#define XAxiDma_BdSetTDest | ( |  | BdPtr,
|  |  | TDest
| ) |  |

Value:
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_TDEST_FIELD_MASK); \
val |= ((u32)(TDest) << XAXIDMA_BD_TDEST_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
XAXIDMA_BD_MCCTL_OFFSET
#define XAXIDMA_BD_MCCTL_OFFSET
Multichannel Control Fields.
Definition: xaxidma_hw.h:220
XAxiDma_BdWrite
#define XAxiDma_BdWrite(BaseAddress, Offset, Data)
Write the given Buffer Descriptor word.
Definition: xaxidma_bd.h:185
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Set the TDEST field of the TX BD.

Provides coarse routing information for the data stream.

Parameters

  BdPtr | is the BD to operate on
  TDest | is a 8 bit quantity to set in the BD

Returns
  None

Note
  C-style signature: void XAxiDma_BdSetTDest(XAxiDma_Bd* BdPtr, void TDest)

#define XAxiDma_BdSetTId | ( |  | BdPtr,
|  |  | TId
| ) |  |

Value:
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_TID_FIELD_MASK); \
val |= ((u32)(TId) << XAXIDMA_BD_TID_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
XAXIDMA_BD_MCCTL_OFFSET
#define XAXIDMA_BD_MCCTL_OFFSET
Multichannel Control Fields.
Definition: xaxidma_hw.h:220
XAxiDma_BdWrite
#define XAxiDma_BdWrite(BaseAddress, Offset, Data)
Write the given Buffer Descriptor word.
Definition: xaxidma_bd.h:185
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Set the TID field of the TX BD.

Provides a stream identifier and can be used to differentiate between multiple streams of data that are being transferred across the same interface.

Parameters

  BdPtr | is the BD to operate on
  TId | is a 8 bit quantity to set in the BD

Returns
  None

Note
  C-style signature: void XAxiDma_BdSetTId(XAxiDma_Bd* BdPtr, void TId)

#define XAxiDma_BdSetTUser | ( |  | BdPtr,
|  |  | TUser
| ) |  |

Value:
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_MCCTL_OFFSET) & \
~XAXIDMA_BD_TUSER_FIELD_MASK); \
val |= ((u32)(TUser) << XAXIDMA_BD_TUSER_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_MCCTL_OFFSET, val); \
}
XAXIDMA_BD_MCCTL_OFFSET
#define XAXIDMA_BD_MCCTL_OFFSET
Multichannel Control Fields.
Definition: xaxidma_hw.h:220
XAxiDma_BdWrite
#define XAxiDma_BdWrite(BaseAddress, Offset, Data)
Write the given Buffer Descriptor word.
Definition: xaxidma_bd.h:185
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Set the TUSER field of the TX BD.

User defined sideband signaling.

Parameters

  BdPtr | is the BD to operate on
  TUser | is a 8 bit quantity to set in the BD

Returns
  None

Note
  C-style signature: void XAxiDma_BdSetTUser(XAxiDma_Bd* BdPtr, void TUser)

#define XAxiDma_BdSetVSize | ( |  | BdPtr,
|  |  | VSize
| ) |  |

Value:
{ \
u32 val; \
val = (XAxiDma_BdRead((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET) & \
~XAXIDMA_BD_VSIZE_FIELD_MASK); \
val |= ((u32)(VSize) << XAXIDMA_BD_VSIZE_FIELD_SHIFT); \
XAxiDma_BdWrite((BdPtr), XAXIDMA_BD_STRIDE_VSIZE_OFFSET, val); \
}
XAxiDma_BdWrite
#define XAxiDma_BdWrite(BaseAddress, Offset, Data)
Write the given Buffer Descriptor word.
Definition: xaxidma_bd.h:185
XAXIDMA_BD_STRIDE_VSIZE_OFFSET
#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET
2D Transfer Sizes
Definition: xaxidma_hw.h:221
XAxiDma_BdRead
#define XAxiDma_BdRead(BaseAddress, Offset)
Read the given Buffer Descriptor word.
Definition: xaxidma_bd.h:166

Set the VSIZE field of the given BD.

Number of horizontal lines for strided access.

Parameters

  BdPtr | is the BD to operate on
  VSize | is a 32 bit quantity to set in the BD

Returns
  None

Note
  C-style signature: void XAxiDma_BdSetVSize(XAxiDma_Bd* BdPtr, void VSize)

#define XAxiDma_BdWrite | ( |  | BaseAddress,
|  |  | Offset,
|  |  | Data
| ) |  | (*(u32 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u32)(Data)

Write the given Buffer Descriptor word.

Parameters

  BaseAddress | is the base address of the BD to write
  Offset | is the word offset to be written
  Data | is the 32-bit value to write to the field

Returns
  None.

Note
  C-style signature: void XAxiDma_BdWrite(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XAxiDma_BdRingClone(), XAxiDma_BdRingCreate(), XAxiDma_BdRingFromHw(), XAxiDma_BdRingToHw(), XAxiDma_BdSetAppWord(), XAxiDma_BdSetBufAddr(), XAxiDma_BdSetBufAddrMicroMode(), XAxiDma_BdSetCtrl(), and XAxiDma_BdSetLength().

#define XAxiDma_BdWrite64 | ( |  | BaseAddress,
|  |  | Offset,
|  |  | Data
| ) |  | (*(u64 *)((UINTPTR)(void *)(BaseAddress) + (u32)(Offset))) = (u64)(Data)

Write the given Buffer Descriptor word.

Parameters

  BaseAddress | is the base address of the BD to write
  Offset | is the word offset to be written
  Data | is the 64-bit value to write to the field

Returns
  None.

Note
  C-style signature: void XAxiDma_BdWrite(u64 BaseAddress, u32 RegOffset, u64 Data)

Referenced by XAxiDma_BdSetBufAddr(), and XAxiDma_BdSetBufAddrMicroMode().

#define XAXIDMA_BUFFLEN_OFFSET 0x00000028

Tail descriptor pointer.

Referenced by XAxiDma_SimpleTransfer().

#define XAXIDMA_CDESC_MSB_OFFSET 0x0000000C

Current descriptor pointer.

Referenced by XAxiDma_UpdateBdRingCDesc().

#define XAXIDMA_CDESC_OFFSET 0x00000008

Current descriptor pointer.

Referenced by XAxiDma_BdRingDumpRegs(), and XAxiDma_UpdateBdRingCDesc().

#define XAXIDMA_COALESCE_MASK 0x00FF0000

Coalesce counter.

Referenced by XAxiDma_BdRingGetCoalesce(), and XAxiDma_BdRingSetCoalesce().

#define XAXIDMA_CR_CYCLIC_MASK 0x00000010

Cyclic Mode.

Referenced by XAxiDma_SelectCyclicMode().

#define XAXIDMA_CR_KEYHOLE_MASK 0x00000008

Keyhole feature.

Referenced by XAxiDma_SelectKeyHole().

#define XAXIDMA_CR_OFFSET 0x00000000

Channel control.

Referenced by XAxiDma_BdRingDumpRegs(), XAxiDma_BdRingGetCoalesce(), XAxiDma_BdRingSetCoalesce(), XAxiDma_Pause(), XAxiDma_Reset(), XAxiDma_ResetIsDone(), XAxiDma_SelectCyclicMode(), XAxiDma_SelectKeyHole(), XAxiDma_SimpleTransfer(), and XAxiDma_StartBdRingHw().

#define XAXIDMA_CR_RESET_MASK 0x00000004

Reset DMA engine.

Referenced by XAxiDma_Reset(), and XAxiDma_ResetIsDone().

#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001

Start/stop DMA channel.

Referenced by XAxiDma_Pause(), XAxiDma_SimpleTransfer(), and XAxiDma_StartBdRingHw().

#define XAXIDMA_DELAY_MASK 0xFF000000

Delay timeout counter.

Referenced by XAxiDma_BdRingGetCoalesce(), and XAxiDma_BdRingSetCoalesce().

#define XAXIDMA_DESC_LSB_MASK (0xFFFFFFC0U)

LSB Address mask.

Referenced by XAxiDma_BdRingCreate(), XAxiDma_BdRingToHw(), XAxiDma_StartBdRingHw(), and XAxiDma_UpdateBdRingCDesc().

#define XAXIDMA_DESTADDR_MSB_OFFSET 0x0000001C

Simple mode destination address pointer.

Referenced by XAxiDma_SimpleTransfer().

#define XAXIDMA_DESTADDR_OFFSET 0x00000018

Simple mode destination address pointer.

Referenced by XAxiDma_SimpleTransfer().

#define XAXIDMA_ERR_ALL_MASK 0x00000770

All errors.

#define XAXIDMA_ERR_DECODE_MASK 0x00000040

Datamover decode err.

#define XAXIDMA_ERR_INTERNAL_MASK 0x00000010

Datamover internal err.

#define XAXIDMA_ERR_SG_DEC_MASK 0x00000400

SG decode err.

#define XAXIDMA_ERR_SG_INT_MASK 0x00000100

SG internal err.

#define XAXIDMA_ERR_SG_SLV_MASK 0x00000200

SG slave err.

#define XAXIDMA_ERR_SLAVE_MASK 0x00000020

Datamover slave err.

#define XAxiDma_GetRxIndexRing | ( |  | InstancePtr,
|  |  | RingIndex
| ) |  | (&((InstancePtr)->RxBdRing[RingIndex]))

Get Receive (Rx) Ring ptr of a Index.

Warning: This has a different API than the LLDMA driver. It now returns the pointer to the BD ring.

Parameters

  InstancePtr | is a pointer to the DMA engine instance to be worked on.
  RingIndex | is the channel Index.

Returns
  Pointer to the Rx Ring

Note
  C-style signature: XAxiDma_BdRing * XAxiDma_GetRxIndexRing(XAxiDma * InstancePtr, int RingIndex) This function is used only when system is configured as SG mode

Referenced by XAxiDma_Pause(), XAxiDma_Reset(), and XAxiDma_Resume().

#define XAxiDma_GetRxRing | ( |  | InstancePtr | ) | (&((InstancePtr)->RxBdRing[0]))

Get Receive (Rx) Ring ptr.

Warning: This has a different API than the LLDMA driver. It now returns the pointer to the BD ring.

Parameters

  InstancePtr | is a pointer to the DMA engine instance to be worked on.

Returns
  Pointer to the Rx Ring

Note
  C-style signature: XAxiDma_BdRing * XAxiDma_GetRxRing(XAxiDma * InstancePtr) This function is used only when system is configured as SG mode

Referenced by XAxiDma_ResetIsDone().

#define XAxiDma_GetTxRing | ( |  | InstancePtr | ) | (&((InstancePtr)->TxBdRing))

Get Transmit (Tx) Ring ptr.

Warning: This has a different API than the LLDMA driver. It now returns the pointer to the BD ring.

Parameters

  InstancePtr | is a pointer to the DMA engine instance to be worked on.

Returns
  Pointer to the Tx Ring

Note
  C-style signature: XAxiDma_BdRing * XAxiDma_GetTxRing(XAxiDma * InstancePtr) This function is used only when system is configured as SG mode

Referenced by XAxiDma_Pause(), XAxiDma_Reset(), XAxiDma_ResetIsDone(), and XAxiDma_Resume().

#define XAXIDMA_HALTED_MASK 0x00000001

DMA channel halted.

Referenced by XAxiDma_SimpleTransfer().

#define XAxiDma_HasSg | ( |  | InstancePtr | ) | ((InstancePtr)->HasSg) ? TRUE : FALSE

This function checks whether system is configured as Simple or Scatter Gather mode.

Parameters

  InstancePtr | is a pointer to the DMA engine instance to be worked on.

Returns
  - TRUE if configured as SG mode
  - FALSE if configured as simple mode

Note
  None

Referenced by main(), XAxiDma_Pause(), XAxiDma_Reset(), XAxiDma_Resume(), XAxiDma_SimplePollExample(), and XAxiDma_SimpleTransfer().

#define XAXIDMA_IDLE_MASK 0x00000002

DMA channel idle.

Referenced by XAxiDma_Busy().

#define XAxiDma_IntrAckIrq | ( |  | InstancePtr,
|  |  | Mask,
|  |  | Direction
| ) |  |

Value:
XAxiDma_WriteReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET, \
(Mask) & XAXIDMA_IRQ_ALL_MASK)
XAXIDMA_RX_OFFSET
#define XAXIDMA_RX_OFFSET
RX channel registers base offset.
Definition: xaxidma_hw.h:113
XAxiDma_WriteReg
#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)
Write the given register.
Definition: xaxidma_hw.h:346
XAXIDMA_IRQ_ALL_MASK
#define XAXIDMA_IRQ_ALL_MASK
All interrupts.
Definition: xaxidma_hw.h:189
XAXIDMA_SR_OFFSET
#define XAXIDMA_SR_OFFSET
Status.
Definition: xaxidma_hw.h:122

This function acknowledges the interrupts that are specified in Mask.

Parameters

  InstancePtr | is the driver instance we are working on
  Mask | is the mask for the interrupts to be acknowledge
  Direction | is DMA transfer direction, valid values are XAXIDMA_DMA_TO_DEVICE. XAXIDMA_DEVICE_TO_DMA.

Returns
  None

Note
  None.

#define XAxiDma_IntrDisable | ( |  | InstancePtr,
|  |  | Mask,
|  |  | Direction
| ) |  |

Value:
XAxiDma_WriteReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
(XAxiDma_ReadReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
& ~(Mask & XAXIDMA_IRQ_ALL_MASK))
XAXIDMA_RX_OFFSET
#define XAXIDMA_RX_OFFSET
RX channel registers base offset.
Definition: xaxidma_hw.h:113
XAXIDMA_CR_OFFSET
#define XAXIDMA_CR_OFFSET
Channel control.
Definition: xaxidma_hw.h:121
XAxiDma_ReadReg
#define XAxiDma_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xaxidma_hw.h:327
XAxiDma_WriteReg
#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)
Write the given register.
Definition: xaxidma_hw.h:346
XAXIDMA_IRQ_ALL_MASK
#define XAXIDMA_IRQ_ALL_MASK
All interrupts.
Definition: xaxidma_hw.h:189

This function disables interrupts specified by the Mask.

Interrupts that are not in the mask are not affected.

Parameters

  InstancePtr | is the driver instance we are working on
  Mask | is the mask for the interrupts to be disabled
  Direction | is DMA transfer direction, valid values are XAXIDMA_DMA_TO_DEVICE. XAXIDMA_DEVICE_TO_DMA.

Returns
  None

Note
  None

Referenced by main(), and XAxiDma_SimplePollExample().

#define XAxiDma_IntrEnable | ( |  | InstancePtr,
|  |  | Mask,
|  |  | Direction
| ) |  |

Value:
XAxiDma_WriteReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET, \
(XAxiDma_ReadReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET)) \
| (Mask & XAXIDMA_IRQ_ALL_MASK))
XAXIDMA_RX_OFFSET
#define XAXIDMA_RX_OFFSET
RX channel registers base offset.
Definition: xaxidma_hw.h:113
XAXIDMA_CR_OFFSET
#define XAXIDMA_CR_OFFSET
Channel control.
Definition: xaxidma_hw.h:121
XAxiDma_ReadReg
#define XAxiDma_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xaxidma_hw.h:327
XAxiDma_WriteReg
#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)
Write the given register.
Definition: xaxidma_hw.h:346
XAXIDMA_IRQ_ALL_MASK
#define XAXIDMA_IRQ_ALL_MASK
All interrupts.
Definition: xaxidma_hw.h:189

This function enables interrupts specified by the Mask in specified direction, Interrupts that are not in the mask are not affected.

Parameters

  InstancePtr | is the driver instance we are working on
  Mask | is the mask for the interrupts to be enabled
  Direction | is DMA transfer direction, valid values are XAXIDMA_DMA_TO_DEVICE. XAXIDMA_DEVICE_TO_DMA.

Returns
  None

Note
  None

Referenced by main().

#define XAxiDma_IntrGetEnabled | ( |  | InstancePtr,
|  |  | Direction
| ) |  |

Value:
XAxiDma_ReadReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_CR_OFFSET) &\
XAXIDMA_IRQ_ALL_MASK)
XAXIDMA_RX_OFFSET
#define XAXIDMA_RX_OFFSET
RX channel registers base offset.
Definition: xaxidma_hw.h:113
XAXIDMA_CR_OFFSET
#define XAXIDMA_CR_OFFSET
Channel control.
Definition: xaxidma_hw.h:121
XAxiDma_ReadReg
#define XAxiDma_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xaxidma_hw.h:327
XAXIDMA_IRQ_ALL_MASK
#define XAXIDMA_IRQ_ALL_MASK
All interrupts.
Definition: xaxidma_hw.h:189

This function gets the mask for the interrupts that are currently enabled.

Parameters

  InstancePtr | is the driver instance we are working on
  Direction | is DMA transfer direction, valid values are XAXIDMA_DMA_TO_DEVICE. XAXIDMA_DEVICE_TO_DMA.

Returns
  The bit mask for the interrupts that are currently enabled

Note
  None

#define XAxiDma_IntrGetIrq | ( |  | InstancePtr,
|  |  | Direction
| ) |  |

Value:
(XAxiDma_ReadReg((InstancePtr)->RegBase + \
(XAXIDMA_RX_OFFSET * Direction), XAXIDMA_SR_OFFSET) &\
XAXIDMA_IRQ_ALL_MASK)
XAXIDMA_RX_OFFSET
#define XAXIDMA_RX_OFFSET
RX channel registers base offset.
Definition: xaxidma_hw.h:113
XAxiDma_ReadReg
#define XAxiDma_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xaxidma_hw.h:327
XAXIDMA_IRQ_ALL_MASK
#define XAXIDMA_IRQ_ALL_MASK
All interrupts.
Definition: xaxidma_hw.h:189
XAXIDMA_SR_OFFSET
#define XAXIDMA_SR_OFFSET
Status.
Definition: xaxidma_hw.h:122

This function gets the interrupts that are asserted.

Parameters

  InstancePtr | is the driver instance we are working on
  Direction | is DMA transfer direction, valid values are XAXIDMA_DMA_TO_DEVICE. XAXIDMA_DEVICE_TO_DMA.

Returns
  The bit mask for the interrupts asserted.

Note
  None

#define XAXIDMA_IRQ_ALL_MASK 0x00007000

All interrupts.

Referenced by main(), and XAxiDma_SimplePollExample().

#define XAXIDMA_IRQ_DELAY_MASK 0x00002000

Delay interrupt.

#define XAXIDMA_IRQ_ERROR_MASK 0x00004000

Error interrupt.

#define XAXIDMA_IRQ_IOC_MASK 0x00001000

Completion intr.

#define XAXIDMA_MICROMODE_MIN_BUF_ALIGN 0xFFF

Minimum byte alignment requirement for buffer address in Micro DMA mode.

Referenced by XAxiDma_BdSetBufAddrMicroMode(), and XAxiDma_SimpleTransfer().

#define XAxiDma_ReadReg | ( |  | BaseAddress,
|  |  | RegOffset
| ) |  | XAxiDma_In32((BaseAddress) + (RegOffset))

Read the given register.

Parameters

  BaseAddress | is the base address of the device
  RegOffset | is the register offset to be read

Returns
  The 32-bit value of the register

Note
  C-style signature: u32 XAxiDma_ReadReg(u32 BaseAddress, u32 RegOffset)

Referenced by XAxiDma_BdRingDumpRegs(), XAxiDma_BdRingGetCoalesce(), XAxiDma_BdRingSetCoalesce(), XAxiDma_Busy(), XAxiDma_Pause(), XAxiDma_ResetIsDone(), XAxiDma_SelectCyclicMode(), XAxiDma_SelectKeyHole(), XAxiDma_SimpleTransfer(), and XAxiDma_StartBdRingHw().

#define XAXIDMA_RX_CDESC0_MSB_OFFSET 0x00000044

Rx Current Descriptor 0.

Referenced by XAxiDma_UpdateBdRingCDesc().

#define XAXIDMA_RX_CDESC0_OFFSET 0x00000040

Multi-Channel DMA Descriptor Offsets.

Rx Current Descriptor 0

Referenced by XAxiDma_BdRingDumpRegs(), and XAxiDma_UpdateBdRingCDesc().

#define XAXIDMA_RX_NDESC_OFFSET 0x00000020

Rx Next Descriptor Offset.

Referenced by XAxiDma_BdRingDumpRegs(), XAxiDma_BdRingToHw(), XAxiDma_StartBdRingHw(), and XAxiDma_UpdateBdRingCDesc().

#define XAXIDMA_RX_OFFSET 0x00000030

RX channel registers base offset.

Referenced by XAxiDma_Busy(), XAxiDma_CfgInitialize(), XAxiDma_Reset(), XAxiDma_SelectCyclicMode(), and XAxiDma_SelectKeyHole().

#define XAXIDMA_RX_TDESC0_MSB_OFFSET 0x0000004C

Rx Tail Descriptor 0.

Referenced by XAxiDma_BdRingToHw(), and XAxiDma_StartBdRingHw().

#define XAXIDMA_RX_TDESC0_OFFSET 0x00000048

Rx Tail Descriptor 0.

Referenced by XAxiDma_BdRingDumpRegs(), XAxiDma_BdRingToHw(), and XAxiDma_StartBdRingHw().

#define XAXIDMA_SGCTL_OFFSET 0x0000002c

SG Control Register.

#define XAXIDMA_SR_OFFSET 0x00000004

Status.

Referenced by XAxiDma_BdRingDumpRegs(), XAxiDma_Busy(), and XAxiDma_SimpleTransfer().

#define XAXIDMA_SRCADDR_MSB_OFFSET 0x0000001C

Simple mode source address pointer.

Referenced by XAxiDma_SimpleTransfer().

#define XAXIDMA_SRCADDR_OFFSET 0x00000018

Simple mode source address pointer.

Referenced by XAxiDma_SimpleTransfer().

#define XAXIDMA_TDESC_MSB_OFFSET 0x00000014

Tail descriptor pointer.

Referenced by XAxiDma_BdRingToHw(), and XAxiDma_StartBdRingHw().

#define XAXIDMA_TDESC_OFFSET 0x00000010

Tail descriptor pointer.

Referenced by XAxiDma_BdRingDumpRegs(), XAxiDma_BdRingToHw(), and XAxiDma_StartBdRingHw().

#define XAXIDMA_TX_OFFSET 0x00000000

TX channel registers base offset.

Referenced by XAxiDma_CfgInitialize(), and XAxiDma_Reset().

#define XAxiDma_WriteReg | ( |  | BaseAddress,
|  |  | RegOffset,
|  |  | Data
| ) |  | XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))

Write the given register.

Parameters

  BaseAddress | is the base address of the device
  RegOffset | is the register offset to be written
  Data | is the 32-bit value to write to the register

Returns
  None.

Note
  C-style signature: void XAxiDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XAxiDma_BdRingSetCoalesce(), XAxiDma_BdRingToHw(), XAxiDma_Pause(), XAxiDma_Reset(), XAxiDma_SelectCyclicMode(), XAxiDma_SelectKeyHole(), XAxiDma_SimpleTransfer(), XAxiDma_StartBdRingHw(), and XAxiDma_UpdateBdRingCDesc().

## Typedef Documentation

typedef struct XAxiDma XAxiDma

The XAxiDma driver instance data.

An instance must be allocated for each DMA engine in use.

typedef u32 XAxiDma_Bd[XAXIDMA_BD_NUM_WORDS]

The XAxiDma_Bd is the type for a buffer descriptor (BD).

## Function Documentation

u32 XAxiDma_BdGetAppWord | ( | XAxiDma_Bd * | BdPtr,
|  | int | Offset,
|  | int * | Valid
| ) |  |

Get the APP word at the specified APP word offset for a BD.

Parameters

  BdPtr | is the BD to operate on.
  Offset | is the offset inside the APP word, it is valid from 0 to 4
  Valid | is to tell the caller whether parameters are valid

Returns
  The APP word. Passed in parameter Valid holds 0 for failure, and 1 for success.

Note
  This function can be used only when DMA is in SG mode

References XAXIDMA_BD_HAS_STSCNTRL_OFFSET, XAXIDMA_BD_USR0_OFFSET, and XAxiDma_BdRead.

int XAxiDma_BdRingAlloc | ( | XAxiDma_BdRing * | RingPtr,
|  | int | NumBd,
|  | XAxiDma_Bd ** | BdSetPtr
| ) |  |

Reserve locations in the BD ring.

The set of returned BDs may be modified in preparation for future DMA transactions. Once the BDs are ready to be submitted to hardware, the application must call XAxiDma_BdRingToHw() in the same order which they were allocated here. Example:

           NumBd = 2;
           Status = XDsma_RingBdAlloc(MyRingPtr, NumBd, &MyBdSet);

           if (Status != XST_SUCCESS)
           {
               // Not enough BDs available for the request
           }

           CurBd = MyBdSet;
           for (i=0; i<NumBd; i++)
           {
               // Prepare CurBd.....

               // Onto next BD
               CurBd = XAxiDma_BdRingNext(MyRingPtr, CurBd);
           }

           // Give list to hardware
           Status = XAxiDma_BdRingToHw(MyRingPtr, NumBd, MyBdSet);

A more advanced use of this function may allocate multiple sets of BDs. They must be allocated and given to hardware in the correct sequence:

           // Legal
           XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &MySet1);
           XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1);

           // Legal
           XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &MySet1);
           XAxiDma_BdRingAlloc(MyRingPtr, NumBd2, &MySet2);
           XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1);
           XAxiDma_BdRingToHw(MyRingPtr, NumBd2, MySet2);

           // Not legal
           XAxiDma_BdRingAlloc(MyRingPtr, NumBd1, &MySet1);
           XAxiDma_BdRingAlloc(MyRingPtr, NumBd2, &MySet2);
           XAxiDma_BdRingToHw(MyRingPtr, NumBd2, MySet2);
           XAxiDma_BdRingToHw(MyRingPtr, NumBd1, MySet1);

Use the API defined in xaxidmabd.h to modify individual BDs. Traversal of the BD set can be done using XAxiDma_BdRingNext() and XAxiDma_BdRingPrev().

Parameters

  RingPtr | is a pointer to the descriptor ring instance to be worked on.
  NumBd | is the number of BDs to allocate
  BdSetPtr | is an output parameter, it points to the first BD available for modification.

Returns
  - XST_SUCCESS if the requested number of BDs were returned in the BdSetPtr parameter.
  - XST_INVALID_PARAM if passed in NumBd is not positive
  - XST_FAILURE if there were not enough free BDs to satisfy the request.

Note
  This function should not be preempted by another XAxiDma_BdRing function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.

Do not modify more BDs than the number requested with the NumBd parameter. Doing so will lead to data corruption and system instability.

This function can be used only when DMA is in SG mode

References XAxiDma_BdRing::FreeCnt, XAxiDma_BdRing::FreeHead, and XAxiDma_BdRing::PreCnt.

int XAxiDma_BdRingCheck | ( | XAxiDma_BdRing * | RingPtr | ) |

Check the internal data structures of the BD ring for the provided channel.

The following checks are made:

     - The BD ring is linked correctly in physical address space.
     - The internal pointers point to BDs in the ring.
     - The internal counters add up.

The channel should be stopped (through XAxiDma_Pause() or XAxiDma_Reset()) prior to calling this function.

Parameters

  RingPtr | is a pointer to the descriptor ring to be worked on.

Returns
  - XST_SUCCESS if no errors were found.
  - XST_DMA_SG_NO_LIST if the ring has not been created.
  - XST_IS_STARTED if the channel is not stopped.
  - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data structures. If this value is returned, the channel should be reset,and the BD ring should be recreated through XAxiDma_BdRingCreate() to avoid data corruption or system instability.

Note
  This function can be used only when DMA is in SG mode

References XAxiDma_BdRing::AllCnt, XAxiDma_BdRing::FirstBdAddr, XAxiDma_BdRing::FirstBdPhysAddr, XAxiDma_BdRing::FreeCnt, XAxiDma_BdRing::FreeHead, XAxiDma_BdRing::HwCnt, XAxiDma_BdRing::HwHead, XAxiDma_BdRing::HwTail, XAxiDma_BdRing::LastBdAddr, XAxiDma_BdRing::PostCnt, XAxiDma_BdRing::PostHead, XAxiDma_BdRing::PreCnt, XAxiDma_BdRing::PreHead, XAxiDma_BdRing::RunState, XAxiDma_BdRing::Separation, XAXIDMA_BD_NDESC_OFFSET, and XAxiDma_BdRead.

int XAxiDma_BdRingClone | ( | XAxiDma_BdRing * | RingPtr,
|  | XAxiDma_Bd * | SrcBdPtr
| ) |  |

Clone the given BD into every BD in the ring.

Only the fields offset from XAXIDMA_BD_START_CLEAR are copied, for XAXIDMA_BD_BYTES_TO_CLEAR bytes. This covers: BufferAddr, Control/Buffer length, status, APP words 0 - 4, and software ID fields.

This function can be called only when all BDs are in the free group such as immediately after creation of the ring. This prevents modification of BDs while they are in use by hardware or the application.

Parameters

  RingPtr | is the BD ring instance to be worked on.
  SrcBdPtr | is the source BD template to be cloned into the list.

Returns
  - XST_SUCCESS if the list was modified.
  - XST_DMA_SG_NO_LIST if a list has not been created.
  - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.
  - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under hardware or application control.

Note
  This function can be used only when DMA is in SG mode

References XAxiDma_BdRing::AllCnt, XAxiDma_BdRing::FirstBdAddr, XAxiDma_BdRing::FreeCnt, XAxiDma_BdRing::RunState, XAxiDma_BdRing::Separation, XAXIDMA_BD_BYTES_TO_CLEAR, XAXIDMA_BD_START_CLEAR, XAXIDMA_BD_STS_COMPLETE_MASK, XAXIDMA_BD_STS_OFFSET, XAxiDma_BdRead, and XAxiDma_BdWrite.

u32 XAxiDma_BdRingCreate | ( | XAxiDma_BdRing * | RingPtr,
|  | UINTPTR | PhysAddr,
|  | UINTPTR | VirtAddr,
|  | u32 | Alignment,
|  | int | BdCount
| ) |  |

Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring.

Parameters

  RingPtr | is the BD ring instance to be worked on.
  PhysAddr | is the physical base address of application memory region.
  VirtAddr | is the virtual base address of the application memory region.If address translation is not being utilized, then VirtAddr should be equivalent to PhysAddr.
  Alignment | governs the byte alignment of individual BDs. This function will enforce a minimum alignment of XAXIDMA_BD_MINIMUM_ALIGNMENT bytes with no maximum as long as it is specified as a power of 2.
  BdCount | is the number of BDs to setup in the application memory region. It is assumed the region is large enough to contain the BDs.Refer to the "SGDMA Ring Creation" section in xaxidma.h for more information. The minimum valid value for this parameter is 1.

Returns
  - XST_SUCCESS if initialization was successful
    - XST_NO_FEATURE if the provided instance is a non SGDMA type of DMA channel.
  - XST_INVALID_PARAM under any of the following conditions: 1) BdCount is not positive

2) PhysAddr and/or VirtAddr are not aligned to the given Alignment parameter;

3) Alignment parameter does not meet minimum requirements or is not a power of 2 value.

- XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans over address 0x00000000 in virtual address space.

Note
  This function can be used only when DMA is in SG mode

References XAxiDma_BdRing::AllCnt, XAxiDma_BdRing::BdaRestart, XAxiDma_BdRing::Cyclic, XAxiDma_BdRing::CyclicBd, XAxiDma_BdRing::FirstBdAddr, XAxiDma_BdRing::FirstBdPhysAddr, XAxiDma_BdRing::FreeCnt, XAxiDma_BdRing::FreeHead, XAxiDma_BdRing::HasStsCntrlStrm, XAxiDma_BdRing::HwCnt, XAxiDma_BdRing::HwHead, XAxiDma_BdRing::HwTail, XAxiDma_BdRing::LastBdAddr, XAxiDma_BdRing::Length, XAxiDma_BdRing::PostCnt, XAxiDma_BdRing::PostHead, XAxiDma_BdRing::PreCnt, XAxiDma_BdRing::PreHead, XAxiDma_BdRing::RunState, XAxiDma_BdRing::Separation, XAXIDMA_BD_HAS_DRE_OFFSET, XAXIDMA_BD_HAS_DRE_SHIFT, XAXIDMA_BD_HAS_STSCNTRL_OFFSET, XAXIDMA_BD_MINIMUM_ALIGNMENT, XAXIDMA_BD_NDESC_MSB_OFFSET, XAXIDMA_BD_NDESC_OFFSET, XAxiDma_BdWrite, and XAXIDMA_DESC_LSB_MASK.

void XAxiDma_BdRingDumpRegs | ( | XAxiDma_BdRing * | RingPtr | ) |

Dump the registers for a channel.

Parameters

  RingPtr | is a pointer to the descriptor ring to be worked on.

Returns
  None

Note
  This function can be used only when DMA is in SG mode

References XAxiDma_BdRing::ChanBase, XAxiDma_BdRing::RingIndex, XAXIDMA_CDESC_OFFSET, XAXIDMA_CR_OFFSET, XAxiDma_ReadReg, XAXIDMA_RX_CDESC0_OFFSET, XAXIDMA_RX_NDESC_OFFSET, XAXIDMA_RX_TDESC0_OFFSET, XAXIDMA_SR_OFFSET, and XAXIDMA_TDESC_OFFSET.

int XAxiDma_BdRingFree | ( | XAxiDma_BdRing * | RingPtr,
|  | int | NumBd,
|  | XAxiDma_Bd * | BdSetPtr
| ) |  |

Frees a set of BDs that had been previously retrieved with XAxiDma_BdRingFromHw().

Parameters

  RingPtr | is a pointer to the descriptor ring instance to be worked on.
  NumBd | is the number of BDs to free.
  BdSetPtr | is the head of a list of BDs returned by XAxiDma_BdRingFromHw().

Returns
  - XST_SUCCESS if the set of BDs was freed.
  - XST_INVALID_PARAM if NumBd is negative
  - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with XAxiDma_BdRingFromHw().

Note
  This function should not be preempted by another XAxiDma function call that modifies the BD space. It is the caller's responsibility to ensure mutual exclusion.

This function can be used only when DMA is in SG mode

References XAxiDma_BdRing::FreeCnt, XAxiDma_BdRing::PostCnt, and XAxiDma_BdRing::PostHead.

int XAxiDma_BdRingFromHw | ( | XAxiDma_BdRing * | RingPtr,
|  | int | BdLimit,
|  | XAxiDma_Bd ** | BdSetPtr
| ) |  |

Returns a set of BD(s) that have been processed by hardware.

The returned BDs may be examined by the application to determine the outcome of the DMA transactions. Once the BDs have been examined, the application must call XAxiDma_BdRingFree() in the same order which they were retrieved here.

Example:

           NumBd = XAxiDma_BdRingFromHw(MyRingPtr, XAXIDMA_ALL_BDS, &MyBdSet);

           if (NumBd == 0)
           {
              // hardware has nothing ready for us yet
           }

           CurBd = MyBdSet;
           for (i=0; i<NumBd; i++)
           {
              // Examine CurBd for post processing.....

              // Onto next BD
              CurBd = XAxiDma_BdRingNext(MyRingPtr, CurBd);
           }

           XAxiDma_BdRingFree(MyRingPtr, NumBd, MyBdSet); // Return the list

A more advanced use of this function may allocate multiple sets of BDs. They must be retrieved from hardware and freed in the correct sequence:

           // Legal
           XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &MySet1);
           XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1);

           // Legal
           XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &MySet1);
           XAxiDma_BdRingFromHw(MyRingPtr, NumBd2, &MySet2);
           XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1);
           XAxiDma_BdRingFree(MyRingPtr, NumBd2, MySet2);

           // Not legal
           XAxiDma_BdRingFromHw(MyRingPtr, NumBd1, &MySet1);
           XAxiDma_BdRingFromHw(MyRingPtr, NumBd2, &MySet2);
           XAxiDma_BdRingFree(MyRingPtr, NumBd2, MySet2);
           XAxiDma_BdRingFree(MyRingPtr, NumBd1, MySet1);

If hardware has partially completed a packet spanning multiple BDs, then none of the BDs for that packet will be included in the results.

Parameters

  RingPtr | is a pointer to the descriptor ring instance to be worked on.
  BdLimit | is the maximum number of BDs to return in the set. Use XAXIDMA_ALL_BDS to return all BDs that have been processed.
  BdSetPtr | is an output parameter, it points to the first BD available for examination.

Returns
  The number of BDs processed by hardware. A value of 0 indicates that no data is available. No more than BdLimit BDs will be returned.

Note
  Treat BDs returned by this function as read-only.

                  This function should not be preempted by another XAxiDma ring
          function call that modifies the BD space. It is the caller's
          responsibility to provide a mutual exclusion mechanism.

          This function can be used only when DMA is in SG mode

References XAxiDma_BdRing::Cyclic, XAxiDma_BdRing::HwCnt, XAxiDma_BdRing::HwHead, XAxiDma_BdRing::HwTail, XAxiDma_BdRing::IsRxChannel, XAxiDma_BdRing::PostCnt, XAXIDMA_BD_CTRL_LEN_OFFSET, XAXIDMA_BD_CTRL_TXEOF_MASK, XAXIDMA_BD_STS_COMPLETE_MASK, XAXIDMA_BD_STS_OFFSET, XAXIDMA_BD_STS_RXEOF_MASK, XAxiDma_BdRead, XAxiDma_BdRingNext, and XAxiDma_BdWrite.

void XAxiDma_BdRingGetCoalesce | ( | XAxiDma_BdRing * | RingPtr,
|  | u32 * | CounterPtr,
|  | u32 * | TimerPtr
| ) |  |

Retrieve current interrupt coalescing parameters from the given descriptor ring channel.

Parameters

  RingPtr | is a pointer to the descriptor ring instance to be worked on.
  CounterPtr | points to a memory location where the current packet counter will be written.
  TimerPtr | points to a memory location where the current waitbound timer will be written.

Returns
  The passed in parameters, CounterPtr and TimerPtr, holds the references to the return values.

Note
  This function can be used only when DMA is in SG mode

References XAxiDma_BdRing::ChanBase, XAXIDMA_COALESCE_MASK, XAXIDMA_CR_OFFSET, XAXIDMA_DELAY_MASK, and XAxiDma_ReadReg.

int XAxiDma_BdRingSetCoalesce | ( | XAxiDma_BdRing * | RingPtr,
|  | u32 | Counter,
|  | u32 | Timer
| ) |  |

Set interrupt coalescing parameters for the given descriptor ring channel.

Parameters

  RingPtr | is a pointer to the descriptor ring instance to be worked on.
  Counter | sets the packet counter on the channel. Valid range is 1..255. XAXIDMA_NO_CHANGE to leave this setting unchanged.
  Timer | sets the waitbound timer on the channel. Valid range is 0..255.

- XAXIDMA_NO_CHANGE to leave this setting unchanged. Each unit depend on hardware building parameter C_DLYTMR_RESOLUTION,which is in the range from 0 to 100,000 clock cycles. A value of 0 disables the delay interrupt.

Returns
  - XST_SUCCESS if interrupt coalescing settings updated
  - XST_FAILURE if Counter or Timer parameters are out of range

Note
  This function can be used only when DMA is in SG mode

References XAxiDma_BdRing::ChanBase, XAXIDMA_COALESCE_MASK, XAXIDMA_CR_OFFSET, XAXIDMA_DELAY_MASK, XAxiDma_ReadReg, and XAxiDma_WriteReg.

int XAxiDma_BdRingStart | ( | XAxiDma_BdRing * | RingPtr | ) |

Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed.

After a DMA channel is started, it is not halted, and it is idle (no active DMA transfers).

Parameters

  RingPtr | is the Channel instance to be worked on

Returns
  - XST_SUCCESS upon success
  - XST_DMA_ERROR if no valid BD available to put into current BD register

Note
  This function can be used only when DMA is in SG mode

References XAxiDma_StartBdRingHw(), and XAxiDma_UpdateBdRingCDesc().

Referenced by XAxiDma_Resume().

int XAxiDma_BdRingToHw | ( | XAxiDma_BdRing * | RingPtr,
|  | int | NumBd,
|  | XAxiDma_Bd * | BdSetPtr
| ) |  |

Enqueue a set of BDs to hardware that were previously allocated by XAxiDma_BdRingAlloc().

Once this function returns, the argument BD set goes under hardware control. Changes to these BDs should be held until they are finished by hardware to avoid data corruption and system instability.

For transmit, the set will be rejected if the last BD of the set does not mark the end of a packet or the first BD does not mark the start of a packet.

Parameters

  RingPtr | is a pointer to the descriptor ring instance to be worked on.
  NumBd | is the number of BDs in the set.
  BdSetPtr | is the first BD of the set to commit to hardware.

Returns
  - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware
  - XST_INVALID_PARAM if passed in NumBd is negative
  - XST_FAILURE if the set of BDs was rejected because the first BD does not have its start-of-packet bit set, or the last BD does not have its end-of-packet bit set, or any one of the BDs has 0 length.
  - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with XAxiDma_BdRingAlloc()

Note
  This function should not be preempted by another XAxiDma ring function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.

This function can be used only when DMA is in SG mode

References XAxiDma_BdRing::ChanBase, XAxiDma_BdRing::Cyclic, XAxiDma_BdRing::CyclicBd, XAxiDma_BdRing::HwCnt, XAxiDma_BdRing::HwTail, XAxiDma_BdRing::IsRxChannel, XAxiDma_BdRing::PreCnt, XAxiDma_BdRing::PreHead, XAxiDma_BdRing::RingIndex, XAxiDma_BdRing::RunState, XAXIDMA_BD_CTRL_LEN_OFFSET, XAXIDMA_BD_CTRL_TXEOF_MASK, XAXIDMA_BD_CTRL_TXSOF_MASK, XAXIDMA_BD_STS_COMPLETE_MASK, XAXIDMA_BD_STS_OFFSET, XAxiDma_BdGetCtrl, XAxiDma_BdGetLength, XAxiDma_BdGetSts, XAxiDma_BdRead, XAxiDma_BdRingNext, XAxiDma_BdWrite, XAXIDMA_DESC_LSB_MASK, XAXIDMA_RX_NDESC_OFFSET, XAXIDMA_RX_TDESC0_MSB_OFFSET, XAXIDMA_RX_TDESC0_OFFSET, XAXIDMA_TDESC_MSB_OFFSET, XAXIDMA_TDESC_OFFSET, and XAxiDma_WriteReg.

int XAxiDma_BdRingUnAlloc | ( | XAxiDma_BdRing * | RingPtr,
|  | int | NumBd,
|  | XAxiDma_Bd * | BdSetPtr
| ) |  |

Fully or partially undo an XAxiDma_BdRingAlloc() operation.

Use this function if all the BDs allocated by XAxiDma_BdRingAlloc() could not be transferred to hardware with XAxiDma_BdRingToHw().

This function releases the BDs after they have been allocated but before they have been given to hardware.

This function is not the same as XAxiDma_BdRingFree(). The Free function returns BDs to the free list after they have been processed by hardware, while UnAlloc returns them before being processed by hardware.

There are two scenarios where this function can be used. Full UnAlloc or Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:

       Status = XAxiDma_BdRingAlloc(MyRingPtr, 10, &BdPtr);
           ...
           ...
       if (Error)
       {
           Status = XAxiDma_BdRingUnAlloc(MyRingPtr, 10, &BdPtr);
       }

A partial UnAlloc means some of the BDs Alloc'd will be returned:

       Status = XAxiDma_BdRingAlloc(MyRingPtr, 10, &BdPtr);
       BdsLeft = 10;
       CurBdPtr = BdPtr;

       while (BdsLeft)
       {
          if (Error)
          {
             Status = XAxiDma_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr);
          }

          CurBdPtr = XAxiDma_BdRingNext(MyRingPtr, CurBdPtr);
          BdsLeft--;
       }

A partial UnAlloc must include the last BD in the list that was Alloc'd.

Parameters

  RingPtr | is a pointer to the descriptor ring instance to be worked on.
  NumBd | is the number of BDs to unallocate
  BdSetPtr | points to the first of the BDs to be returned.

Returns
  - XST_SUCCESS if the BDs were unallocated.
  - XST_INVALID_PARAM if passed in NumBd is negative
  - XST_FAILURE if NumBd parameter was greater that the number of BDs in the preprocessing state.

Note
  This function should not be preempted by another XAxiDma ring function call that modifies the BD space. It is the caller's responsibility to provide a mutual exclusion mechanism.

This function can be used only when DMA is in SG mode

References XAxiDma_BdRing::FreeCnt, XAxiDma_BdRing::FreeHead, and XAxiDma_BdRing::PreCnt.

int XAxiDma_BdSetAppWord | ( | XAxiDma_Bd * | BdPtr,
|  | int | Offset,
|  | u32 | Word
| ) |  |

Set the APP word at the specified APP word offset for a BD.

Parameters

  BdPtr | is the BD to operate on.
  Offset | is the offset inside the APP word, it is valid from 0 to 4
  Word | is the value to set

Returns
  - XST_SUCCESS for success
  - XST_INVALID_PARAM under following error conditions: 1) StsCntrlStrm is not built in hardware 2) Offset is not in valid range

Note
  If the hardware build has C_SG_USE_STSAPP_LENGTH set to 1, then the last APP word, XAXIDMA_LAST_APPWORD, must have non-zero value when AND with 0x7FFFFF. Not doing so will cause the hardware to stall. This function can be used only when DMA is in SG mode

References XAXIDMA_BD_HAS_STSCNTRL_OFFSET, XAXIDMA_BD_USR0_OFFSET, XAxiDma_BdRead, and XAxiDma_BdWrite.

u32 XAxiDma_BdSetBufAddr | ( | XAxiDma_Bd * | BdPtr,
|  | UINTPTR | Addr
| ) |  |

Set the BD's buffer address.

Parameters

  BdPtr | is the BD to operate on
  Addr | is the address to set

Returns
  - XST_SUCCESS if buffer address set successfully
  - XST_INVALID_PARAM if hardware has no DRE and address is not aligned

Note
  This function can be used only when DMA is in SG mode

References XAXIDMA_BD_BUFA_OFFSET, XAXIDMA_BD_HAS_DRE_MASK, XAXIDMA_BD_HAS_DRE_OFFSET, XAXIDMA_BD_WORDLEN_MASK, XAxiDma_BdRead, XAxiDma_BdWrite, and XAxiDma_BdWrite64.

u32 XAxiDma_BdSetBufAddrMicroMode | ( | XAxiDma_Bd * | BdPtr,
|  | UINTPTR | Addr
| ) |  |

Set the BD's buffer address when configured for Micro Mode.

The buffer address should be 4K aligned.

Parameters

  BdPtr | is the BD to operate on
  Addr | is the address to set

Returns
  - XST_SUCCESS if buffer address set successfully
  - XST_INVALID_PARAM if hardware has no DRE and address is not aligned

Note
  This function can be used only when DMA is in SG mode

References XAXIDMA_BD_BUFA_OFFSET, XAxiDma_BdWrite, XAxiDma_BdWrite64, and XAXIDMA_MICROMODE_MIN_BUF_ALIGN.

void XAxiDma_BdSetCtrl | ( | XAxiDma_Bd * | BdPtr,
|  | u32 | Data
| ) |  |

Set the control bits for a BD.

Parameters

  BdPtr | is the BD to operate on.
  Data | is the bit value to set

Returns
  None

Note
  This function can be used only when DMA is in SG mode

References XAXIDMA_BD_CTRL_ALL_MASK, XAXIDMA_BD_CTRL_LEN_OFFSET, XAxiDma_BdRead, and XAxiDma_BdWrite.

int XAxiDma_BdSetLength | ( | XAxiDma_Bd * | BdPtr,
|  | u32 | LenBytes,
|  | u32 | LengthMask
| ) |  |

Set the length field for the given BD.

Length has to be non-zero and less than LengthMask.

For TX channels, the value passed in should be the number of bytes to transmit from the TX buffer associated with the given BD.

For RX channels, the value passed in should be the size of the RX buffer associated with the given BD in bytes. This is to notify the RX channel the capability of the RX buffer to avoid buffer overflow.

The actual receive length can be equal or smaller than the specified length. The actual transfer length will be updated by the hardware in the XAXIDMA_BD_STS_OFFSET word in the BD.

Parameters

  BdPtr | is the BD to operate on.
  LenBytes | is the requested transfer length
  LengthMask | is the maximum transfer length

Returns
  - XST_SUCCESS for success
  - XST_INVALID_PARAM for invalid BD length

Note
  This function can be used only when DMA is in SG mode

References XAXIDMA_BD_CTRL_LEN_OFFSET, XAxiDma_BdRead, and XAxiDma_BdWrite.

u32 XAxiDma_Busy | ( | XAxiDma * | InstancePtr,
|  | int | Direction
| ) |  |

This function checks whether specified DMA channel is busy.

Parameters

  InstancePtr | is the driver instance we are working on
  Direction | is DMA transfer direction, valid values are XAXIDMA_DMA_TO_DEVICE. XAXIDMA_DEVICE_TO_DMA.

Returns
  - TRUE if channel is busy
  - FALSE if channel is idle

Note
  None.

References XAXIDMA_IDLE_MASK, XAxiDma_ReadReg, XAXIDMA_RX_OFFSET, and XAXIDMA_SR_OFFSET.

Referenced by XAxiDma_SimplePollExample(), and XAxiDma_SimpleTransfer().

int XAxiDma_CfgInitialize | ( | XAxiDma * | InstancePtr,
|  | XAxiDma_Config * | Config
| ) |  |

This function initializes a DMA engine.

This function must be called prior to using a DMA engine. Initializing a engine includes setting up the register base address, setting up the instance data, and ensuring the hardware is in a quiescent state.

Parameters

  InstancePtr | is a pointer to the DMA engine instance to be worked on.
  Config | is a pointer to an XAxiDma_Config structure. It contains the information about the hardware build, including base address,and whether status control stream (StsCntrlStrm), MM2S and S2MM are included in the build.

Returns
  - XST_SUCCESS for successful initialization
  - XST_INVALID_PARAM if pointer to the configuration structure is NULL
  - XST_DMA_ERROR if reset operation failed at the end of initialization

Note
  We assume the hardware building tool will check and error out for a hardware build that has no transfer channels.

References XAxiDma::AddrWidth, XAxiDma_Config::AddrWidth, XAxiDma_BdRing::ChanBase, XAxiDma_BdRing::HasStsCntrlStrm, XAxiDma_BdRing::IsRxChannel, XAxiDma_BdRing::RingIndex, XAxiDma_BdRing::RunState, XAxiDma_Reset(), XAxiDma_ResetIsDone(), XAXIDMA_RX_OFFSET, and XAXIDMA_TX_OFFSET.

Referenced by AxiDMASelfTestExample(), main(), and XAxiDma_SimplePollExample().

void XAxiDma_DumpBd | ( | XAxiDma_Bd * | BdPtr | ) |

Dump the fields of a BD.

Parameters

  BdPtr | is the BD to operate on.

Returns
  None

Note
  This function can be used only when DMA is in SG mode

References XAXIDMA_BD_BUFA_OFFSET, XAXIDMA_BD_CTRL_LEN_OFFSET, XAXIDMA_BD_HAS_DRE_OFFSET, XAXIDMA_BD_HAS_STSCNTRL_OFFSET, XAXIDMA_BD_ID_OFFSET, XAXIDMA_BD_MCCTL_OFFSET, XAXIDMA_BD_NDESC_OFFSET, XAXIDMA_BD_STRIDE_VSIZE_OFFSET, XAXIDMA_BD_STS_OFFSET, XAXIDMA_BD_USR0_OFFSET, XAXIDMA_BD_USR1_OFFSET, XAXIDMA_BD_USR2_OFFSET, XAXIDMA_BD_USR3_OFFSET, XAXIDMA_BD_USR4_OFFSET, and XAxiDma_BdRead.

XAxiDma_Config * XAxiDma_LookupConfig | ( | u32 | DeviceId | ) |

Look up the hardware configuration for a device instance.

Parameters

  DeviceId | is the unique device ID of the device to lookup for

Returns
  The configuration structure for the device. If the device ID is not found,a NULL pointer is returned.

Note
  None

Referenced by AxiDMASelfTestExample(), main(), and XAxiDma_SimplePollExample().

XAxiDma_Config * XAxiDma_LookupConfigBaseAddr | ( | UINTPTR | Baseaddr | ) |

Look up the hardware configuration for a device instance based on base address.

Parameters

  Baseaddr | is the base address of the device to lookup for

Returns
  The configuration structure for the device. If the device base address is not found,a NULL pointer is returned.

Note
  None

int XAxiDma_Pause | ( | XAxiDma * | InstancePtr | ) |

Pause DMA transactions on both channels.

If the engine is running and doing transfers, this function does not stop the DMA transactions immediately, because then hardware will throw away our previously queued transfers. All submitted transfers will finish. Transfers submitted after this function will not start until XAxiDma_BdRingStart() or XAxiDma_Resume() is called.

Parameters

  InstancePtr | is a pointer to the DMA engine instance to be worked on.

Returns
  - XST_SUCCESS if successful
  - XST_NOT_SGDMA, if the driver instance is not initialized

Note
  None

References XAxiDma_BdRing::ChanBase, XAxiDma_BdRing::RunState, XAXIDMA_CR_OFFSET, XAXIDMA_CR_RUNSTOP_MASK, XAxiDma_GetRxIndexRing, XAxiDma_GetTxRing, XAxiDma_HasSg, XAxiDma_ReadReg, and XAxiDma_WriteReg.

void XAxiDma_Reset | ( | XAxiDma * | InstancePtr | ) |

Reset both TX and RX channels of a DMA engine.

Reset one channel resets the whole AXI DMA engine.

Any DMA transaction in progress will finish gracefully before engine starts reset. Any other transactions that have been submitted to hardware will be discarded by the hardware.

Parameters

  InstancePtr | is a pointer to the DMA engine instance to be worked on.

Returns
  None

Note
  After the reset:
  - All interrupts are disabled.
  - Engine is halted

References XAxiDma_BdRing::RunState, XAxiDma_BdRingSnapShotCurrBd, XAXIDMA_CR_OFFSET, XAXIDMA_CR_RESET_MASK, XAxiDma_GetRxIndexRing, XAxiDma_GetTxRing, XAxiDma_HasSg, XAXIDMA_RX_OFFSET, XAXIDMA_TX_OFFSET, and XAxiDma_WriteReg.

Referenced by main(), XAxiDma_CfgInitialize(), and XAxiDma_Selftest().

int XAxiDma_ResetIsDone | ( | XAxiDma * | InstancePtr | ) |

Check whether reset is done.

Parameters

  InstancePtr | is a pointer to the DMA engine instance to be worked on.

Returns
  - 1 if reset is done.

- 0 if reset is not done

Note
  None

References XAxiDma_BdRing::ChanBase, XAXIDMA_CR_OFFSET, XAXIDMA_CR_RESET_MASK, XAxiDma_GetRxRing, XAxiDma_GetTxRing, and XAxiDma_ReadReg.

Referenced by XAxiDma_CfgInitialize(), and XAxiDma_Selftest().

int XAxiDma_Resume | ( | XAxiDma * | InstancePtr | ) |

Resume DMA transactions on both channels.

Parameters

  InstancePtr | is a pointer to the DMA engine instance to be worked on.

Returns
  - XST_SUCCESS for success
  - XST_NOT_SGDMA if the driver instance has not been initialized
  - XST_DMA_ERROR if one of the channels fails to start

Note
  None

References XAxiDma_BdRing::RunState, XAxiDma_BdRingStart(), XAxiDma_GetRxIndexRing, XAxiDma_GetTxRing, and XAxiDma_HasSg.

int XAxiDma_SelectCyclicMode | ( | XAxiDma * | InstancePtr,
|  | int | Direction,
|  | int | Select
| ) |  |

This function Enable or Disable Cyclic Mode Feature.

Parameters

  InstancePtr | is the driver instance we are working on
  Direction | is DMA transfer direction, valid values are XAXIDMA_DMA_TO_DEVICE. XAXIDMA_DEVICE_TO_DMA.
  Select | is the option to enable (TRUE) or disable (FALSE).

Returns
  - XST_SUCCESS for success

Note
  None.

References XAXIDMA_CR_CYCLIC_MASK, XAXIDMA_CR_OFFSET, XAxiDma_ReadReg, XAXIDMA_RX_OFFSET, and XAxiDma_WriteReg.

int XAxiDma_SelectKeyHole | ( | XAxiDma * | InstancePtr,
|  | int | Direction,
|  | int | Select
| ) |  |

This function Enable or Disable KeyHole Feature.

Parameters

  InstancePtr | is the driver instance we are working on
  Direction | is DMA transfer direction, valid values are XAXIDMA_DMA_TO_DEVICE. XAXIDMA_DEVICE_TO_DMA.
  Select | is the option to enable (TRUE) or disable (FALSE).

Returns
  - XST_SUCCESS for success

Note
  None.

References XAXIDMA_CR_KEYHOLE_MASK, XAXIDMA_CR_OFFSET, XAxiDma_ReadReg, XAXIDMA_RX_OFFSET, and XAxiDma_WriteReg.

int XAxiDma_Selftest | ( | XAxiDma * | InstancePtr | ) |

Runs a self-test on the driver/device.

This test perform a reset of the DMA device and checks the device is coming out of reset or not

Parameters

  InstancePtr | is a pointer to the XAxiDma instance.

Returns
  - XST_SUCCESS if self-test was successful

- XST_FAILURE if the device is not coming out of reset.

Note
  None.

References XAxiDma_Reset(), and XAxiDma_ResetIsDone().

Referenced by AxiDMASelfTestExample().

u32 XAxiDma_SimpleTransfer | ( | XAxiDma * | InstancePtr,
|  | UINTPTR | BuffAddr,
|  | u32 | Length,
|  | int | Direction
| ) |  |

This function does one simple transfer submission.

It checks in the following sequence:

- if engine is busy, cannot submit
- if engine is in SG mode , cannot submit

Parameters

  InstancePtr | is the pointer to the driver instance
  BuffAddr | is the address of the source/destination buffer
  Length | is the length of the transfer
  Direction | is DMA transfer direction, valid values are XAXIDMA_DMA_TO_DEVICE. XAXIDMA_DEVICE_TO_DMA.

Returns
  - XST_SUCCESS for success of submission
  - XST_FAILURE for submission failure, maybe caused by: Another simple transfer is still going
  - XST_INVALID_PARAM if:Length out of valid range [1:8M] Or, address not aligned when DRE is not built in

Note
  This function is used only when system is configured as Simple mode.

References XAxiDma::AddrWidth, XAxiDma_BdRing::ChanBase, XAXIDMA_BUFFLEN_OFFSET, XAxiDma_Busy(), XAXIDMA_CR_OFFSET, XAXIDMA_CR_RUNSTOP_MASK, XAXIDMA_DESTADDR_MSB_OFFSET, XAXIDMA_DESTADDR_OFFSET, XAXIDMA_HALTED_MASK, XAxiDma_HasSg, XAXIDMA_MICROMODE_MIN_BUF_ALIGN, XAxiDma_ReadReg, XAXIDMA_SR_OFFSET, XAXIDMA_SRCADDR_MSB_OFFSET, XAXIDMA_SRCADDR_OFFSET, and XAxiDma_WriteReg.

Referenced by main(), and XAxiDma_SimplePollExample().

int XAxiDma_StartBdRingHw | ( | XAxiDma_BdRing * | RingPtr | ) |

Start a DMA channel and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed.

After a DMA channel is started, it is not halted, and it is idle (no active DMA transfers).

Parameters

  RingPtr | is the Channel instance to be worked on

Returns
  - XST_SUCCESS upon success
  - XST_DMA_ERROR if no valid BD available to put into current BD register

Note
  This function can be used only when DMA is in SG mode

References XAxiDma_BdRing::ChanBase, XAxiDma_BdRing::Cyclic, XAxiDma_BdRing::CyclicBd, XAxiDma_BdRing::HwCnt, XAxiDma_BdRing::HwTail, XAxiDma_BdRing::IsRxChannel, XAxiDma_BdRing::RingIndex, XAxiDma_BdRing::RunState, XAXIDMA_BD_STS_COMPLETE_MASK, XAXIDMA_BD_STS_OFFSET, XAxiDma_BdRead, XAxiDma_BdRingHwIsStarted, XAXIDMA_CR_OFFSET, XAXIDMA_CR_RUNSTOP_MASK, XAXIDMA_DESC_LSB_MASK, XAxiDma_ReadReg, XAXIDMA_RX_NDESC_OFFSET, XAXIDMA_RX_TDESC0_MSB_OFFSET, XAXIDMA_RX_TDESC0_OFFSET, XAXIDMA_TDESC_MSB_OFFSET, XAXIDMA_TDESC_OFFSET, and XAxiDma_WriteReg.

Referenced by XAxiDma_BdRingStart().

int XAxiDma_UpdateBdRingCDesc | ( | XAxiDma_BdRing * | RingPtr | ) |

Update Current Descriptor.

Parameters

  RingPtr | is the Channel instance to be worked on

Returns
  - XST_SUCCESS upon success
  - XST_DMA_ERROR if no valid BD available to put into current BD register

Note
  This function can be used only when DMA is in SG mode

References XAxiDma_BdRing::AllCnt, XAxiDma_BdRing::BdaRestart, XAxiDma_BdRing::ChanBase, XAxiDma_BdRing::IsRxChannel, XAxiDma_BdRing::RingIndex, XAxiDma_BdRing::RunState, XAxiDma_BdHwCompleted, XAxiDma_BdRingHwIsStarted, XAxiDma_BdRingNext, XAXIDMA_CDESC_MSB_OFFSET, XAXIDMA_CDESC_OFFSET, XAXIDMA_DESC_LSB_MASK, XAXIDMA_RX_CDESC0_MSB_OFFSET, XAXIDMA_RX_CDESC0_OFFSET, XAXIDMA_RX_NDESC_OFFSET, and XAxiDma_WriteReg.

Referenced by XAxiDma_BdRingStart().