scuwdt: xscuwdt_hw.h File Reference

| scuwdt Xilinx SDK Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List
- Examples

Macros
xscuwdt_hw.h File Reference

## Macros
#define | XScuWdt_ReadReg(BaseAddr, RegOffset) Xil_In32((BaseAddr) + ((u32)RegOffset))
| Read the given register. More...
#define | XScuWdt_WriteReg(BaseAddr, RegOffset, Data) Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
| Write the given register. More...
Register Map
Offsets of registers from the start of the device. The WDT registers start at an offset 0x20
#define | XSCUWDT_LOAD_OFFSET 0x00U
| Watchdog Load Register. More...
#define | XSCUWDT_COUNTER_OFFSET 0x04U
| Watchdog Counter Register. More...
#define | XSCUWDT_CONTROL_OFFSET 0x08U
| Watchdog Control Register. More...
#define | XSCUWDT_ISR_OFFSET 0x0CU
| Watchdog Interrupt Status Register. More...
#define | XSCUWDT_RST_STS_OFFSET 0x10U
| Watchdog Reset Status Register. More...
#define | XSCUWDT_DISABLE_OFFSET 0x14U
| Watchdog Disable Register. More...
Watchdog Control register
This register bits control the prescaler, WD/Timer mode, Intr enable, auto-reload, watchdog enable.
#define | XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U
| Prescaler. More...
#define | XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
#define | XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U
| Watchdog/Timer mode. More...
#define | XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U
| Intr enable (in timer mode) More...
#define | XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U
| Auto-reload (in timer mode) More...
#define | XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U
| Watchdog enable. More...
Interrupt Status register
This register indicates the Counter register has reached zero in Counter mode.
#define | XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U
| Event flag. More...
Reset Status register
This register indicates the Counter register has reached zero in Watchdog mode and a reset request is sent.
#define | XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U
| Time out occurred. More...
Disable register
This register is used to switch from watchdog mode to timer mode. The software must write 0x12345678 and 0x87654321 successively to the Watchdog Disable Register so that the watchdog mode bit in the Watchdog Control Register is set to zero.
#define | XSCUWDT_DISABLE_VALUE1 0x12345678U
| Watchdog mode disable value 1. More...
#define | XSCUWDT_DISABLE_VALUE2 0x87654321U
| Watchdog mode disable value 2. More...