iicps: xiicps_hw.h File Reference

| iicps Xilinx SDK Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List
- Examples

Macros | Functions
xiicps_hw.h File Reference

## Macros
#define | XIICPS_POLL_DEFAULT_TIMEOUT_VAL 1000U
| Timeout in us. More...
#define | XIicPs_ReadReg(BaseAddress, RegOffset) XIicPs_In32((BaseAddress) + (u32)(RegOffset))
| Read an IIC register. More...
#define | XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
| Write an IIC register. More...
#define | XIicPs_ReadIER(BaseAddress) XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)
| Read the interrupt enable register. More...
#define | XIicPs_EnableInterrupts(BaseAddress, IntrMask) XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
| Write to the interrupt enable register. More...
#define | XIicPs_DisableAllInterrupts(BaseAddress)
| Disable all interrupts. More...
#define | XIicPs_DisableInterrupts(BaseAddress, IntrMask)
| Disable selected interrupts. More...
Register Map
Register offsets for the IIC.
#define | XIICPS_CR_OFFSET 0x00U
| 32-bit Control More...
#define | XIICPS_SR_OFFSET 0x04U
| Status. More...
#define | XIICPS_ADDR_OFFSET 0x08U
| IIC Address. More...
#define | XIICPS_DATA_OFFSET 0x0CU
| IIC FIFO Data. More...
#define | XIICPS_ISR_OFFSET 0x10U
| Interrupt Status. More...
#define | XIICPS_TRANS_SIZE_OFFSET 0x14U
| Transfer Size. More...
#define | XIICPS_SLV_PAUSE_OFFSET 0x18U
| Slave monitor pause. More...
#define | XIICPS_TIME_OUT_OFFSET 0x1CU
| Time Out. More...
#define | XIICPS_IMR_OFFSET 0x20U
| Interrupt Enabled Mask. More...
#define | XIICPS_IER_OFFSET 0x24U
| Interrupt Enable. More...
#define | XIICPS_IDR_OFFSET 0x28U
| Interrupt Disable. More...
Control Register
This register contains various control bits that affects the operation of the IIC controller. Read/Write.
#define | XIICPS_CR_DIV_A_MASK 0x0000C000U
| Clock Divisor A. More...
#define | XIICPS_CR_DIV_A_SHIFT 14U
| Clock Divisor A shift. More...
#define | XIICPS_DIV_A_MAX 4U
| Maximum value of Divisor A. More...
#define | XIICPS_CR_DIV_B_MASK 0x00003F00U
| Clock Divisor B. More...
#define | XIICPS_CR_DIV_B_SHIFT 8U
| Clock Divisor B shift. More...
#define | XIICPS_CR_CLR_FIFO_MASK 0x00000040U
| Clear FIFO, auto clears. More...
#define | XIICPS_CR_SLVMON_MASK 0x00000020U
| Slave monitor mode. More...
#define | XIICPS_CR_HOLD_MASK 0x00000010U
| Hold bus 1=Hold scl, 0=terminate transfer. More...
#define | XIICPS_CR_ACKEN_MASK 0x00000008U
| Enable TX of ACK when Master receiver. More...
#define | XIICPS_CR_NEA_MASK 0x00000004U
| Addressing Mode 1=7 bit, 0=10 bit. More...
#define | XIICPS_CR_MS_MASK 0x00000002U
| Master mode bit 1=Master, 0=Slave. More...
#define | XIICPS_CR_RD_WR_MASK 0x00000001U
| Read or Write Master transfer 0=Transmitter, 1=Receiver. More...
#define | XIICPS_CR_RESET_VALUE 0U
| Reset value of the Control register. More...
IIC Status Register
This register is used to indicate status of the IIC controller. Read only
#define | XIICPS_SR_BA_MASK 0x00000100U
| Bus Active Mask. More...
#define | XIICPS_SR_RXOVF_MASK 0x00000080U
| Receiver Overflow Mask. More...
#define | XIICPS_SR_TXDV_MASK 0x00000040U
| Transmit Data Valid Mask. More...
#define | XIICPS_SR_RXDV_MASK 0x00000020U
| Receiver Data Valid Mask. More...
#define | XIICPS_SR_RXRW_MASK 0x00000008U
| Receive read/write Mask. More...
IIC Address Register
Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0]. A write access to this register always initiates a transfer if the IIC is in master mode. Read/Write
#define | XIICPS_ADDR_MASK 0x000003FF
| IIC Address Mask. More...
IIC Data Register
When written to, the data register sets data to transmit. When read from, the data register reads the last received byte of data. Read/Write
#define | XIICPS_DATA_MASK 0x000000FF
| IIC Data Mask. More...
IIC Interrupt Registers
IIC Interrupt Status Register This register holds the interrupt status flags for the IIC controller. Some of the flags are level triggered i.e. are set as long as the interrupt condition exists. Other flags are edge triggered, which means they are set one the interrupt condition occurs then remain set until they are cleared by software. The interrupts are cleared by writing a one to the interrupt bit position in the Interrupt Status Register. Read/Write. IIC Interrupt Enable Register This register is used to enable interrupt sources for the IIC controller. Writing a '1' to a bit in this register clears the corresponding bit in the IIC Interrupt Mask register. Write only. IIC Interrupt Disable Register This register is used to disable interrupt sources for the IIC controller. Writing a '1' to a bit in this register sets the corresponding bit in the IIC Interrupt Mask register. Write only. IIC Interrupt Mask Register This register shows the enabled/disabled status of each IIC controller interrupt source. A bit set to 1 will ignore the corresponding interrupt in the status register. A bit set to 0 means the interrupt is enabled. All mask bits are set and all interrupts are disabled after reset. Read only. All four registers have the same bit definitions. They are only defined once for each of the Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, and Interrupt Status Register
#define | XIICPS_IXR_ARB_LOST_MASK 0x00000200U
| Arbitration Lost Interrupt mask. More...
#define | XIICPS_IXR_RX_UNF_MASK 0x00000080U
| FIFO Receive Underflow Interrupt mask. More...
#define | XIICPS_IXR_TX_OVR_MASK 0x00000040U
| Transmit Overflow Interrupt mask. More...
#define | XIICPS_IXR_RX_OVR_MASK 0x00000020U
| Receive Overflow Interrupt mask. More...
#define | XIICPS_IXR_SLV_RDY_MASK 0x00000010U
| Monitored Slave Ready Interrupt mask. More...
#define | XIICPS_IXR_TO_MASK 0x00000008U
| Transfer Time Out Interrupt mask. More...
#define | XIICPS_IXR_NACK_MASK 0x00000004U
| NACK Interrupt mask. More...
#define | XIICPS_IXR_DATA_MASK 0x00000002U
| Data Interrupt mask. More...
#define | XIICPS_IXR_COMP_MASK 0x00000001U
| Transfer Complete Interrupt mask. More...
#define | XIICPS_IXR_DEFAULT_MASK 0x000002FFU
| Default ISR Mask. More...
#define | XIICPS_IXR_ALL_INTR_MASK 0x000002FFU
| All ISR Mask. More...
IIC Transfer Size Register
The register's meaning varies according to the operating mode as follows: Master transmitter mode: number of data bytes still not transmitted minus one Master receiver mode: number of data bytes that are still expected to be received Slave transmitter mode: number of bytes remaining in the FIFO after the master terminates the transfer Slave receiver mode: number of valid data bytes in the FIFO This register is cleared if CLR_FIFO bit in the control register is set. Read/Write
#define | XIICPS_TRANS_SIZE_MASK 0x0000003F
| IIC Transfer Size Mask. More...
#define | XIICPS_FIFO_DEPTH 16
| Number of bytes in the FIFO. More...
#define | XIICPS_DATA_INTR_DEPTH 14
| Number of bytes at DATA intr. More...
IIC Slave Monitor Pause Register
This register is associated with the slave monitor mode of the I2C interface. It is meaningful only when the module is in master mode and bit SLVMON in the control register is set. This register defines the pause interval between consecutive attempts to address the slave once a write to an I2C address register is done by the host. It represents the number of sclk cycles minus one between two attempts. The reset value of the register is 0, which results in the master repeatedly trying to access the slave immediately after unsuccessful attempt. Read/Write
#define | XIICPS_SLV_PAUSE_MASK 0x0000000F
| Slave monitor pause mask. More...
IIC Time Out Register
The value of time out register represents the time out interval in number of sclk cycles minus one. When the accessed slave holds the sclk line low for longer than the time out period, thus prohibiting the I2C interface in master mode to complete the current transfer, an interrupt is generated and TO interrupt flag is set. The reset value of the register is 0x1f. Read/Write
#define | XIICPS_TIME_OUT_MASK 0x000000FFU
| IIC Time Out mask. More...
#define | XIICPS_TO_RESET_VALUE 0x000000FFU
| IIC Time Out reset value. More...

## Functions
void | XIicPs_ResetHw (u32 BaseAddress)
| This function perform the reset sequence to the given I2c interface by configuring the appropriate control bits in the I2c specific registers the i2cps reset sequence involves the following steps Disable all the interuupts Clear the status Clear FIFO's and disable hold bit Clear the line status Update relevant config registers with reset values. More...