csudma: xcsudma_hw.h File Reference

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Macros
xcsudma_hw.h File Reference

## Macros
#define | XCSUDMA_HW_H_
| Prevent circular inclusions by using protection macros. More...
#define | XCsuDma_In32 Xil_In32
| Input operation. More...
#define | XCsuDma_Out32 Xil_Out32
| Output operation. More...
#define | XCsuDma_ReadReg(BaseAddress, RegOffset) XCsuDma_In32((BaseAddress) + (u32)(RegOffset))
| This macro reads the given register. More...
#define | XCsuDma_WriteReg(BaseAddress, RegOffset, Data) XCsuDma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
| This macro writes the value into the given register. More...
Registers offsets
#define | XCSUDMA_ADDR_OFFSET 0x000U
| Address Register Offset. More...
#define | XCSUDMA_SIZE_OFFSET 0x004U
| Size Register Offset. More...
#define | XCSUDMA_STS_OFFSET 0x008U
| Status Register Offset. More...
#define | XCSUDMA_CTRL_OFFSET 0x00CU
| Control Register Offset. More...
#define | XCSUDMA_CRC_OFFSET 0x010U
| CheckSum Register Offset. More...
#define | XCSUDMA_I_STS_OFFSET 0x014U
| Interrupt Status Register Offset. More...
#define | XCSUDMA_I_EN_OFFSET 0x018U
| Interrupt Enable Register Offset. More...
#define | XCSUDMA_I_DIS_OFFSET 0x01CU
| Interrupt Disable Register Offset. More...
#define | XCSUDMA_I_MASK_OFFSET 0x020U
| Interrupt Mask Register Offset. More...
#define | XCSUDMA_CTRL2_OFFSET 0x024U
| Interrupt Control Register 2 Offset. More...
#define | XCSUDMA_ADDR_MSB_OFFSET 0x028U
| Address's MSB Register Offset. More...
#define | XCSUDMA_SAFETY_CHK_OFFSET 0xFF8U
| Safety Check Field Offset. More...
#define | XCSUDMA_FUTURE_ECO_OFFSET 0xFFCU
| Future potential ECO Offset. More...
CSU Base address and CSU_DMA reset offset
#define | XCSU_BASEADDRESS 0xFFCA0000U
| CSU Base Address. More...
#define | XCSU_DMA_RESET_OFFSET 0x0000000CU
| CSU_DMA Reset offset. More...
#define | XPS_CRP_BASEADDRESS 0xF1260000U
CRP PMC_DMA reset offset
#define | XCRP_PMCDMA_RESET_OFFSET 0x00000328U
| PMC_DMA Reset offset. More...
CSU_DMA Reset register bit masks
#define | XCSUDMA_RESET_SET_MASK 0x00000001U
| Reset set mask. More...
#define | XCSUDMA_RESET_UNSET_MASK 0x00000000U
| Reset unset mask. More...
Offset difference for Source and destination
#define | XCSUDMA_OFFSET_DIFF 0x00000800U
| Offset difference for source and destination channels. More...
Address register bit masks
#define | XCSUDMA_ADDR_MASK 0xFFFFFFFCU
| Address mask. More...
#define | XCSUDMA_ADDR_LSB_MASK 0x00000003U
| Address alignment check mask. More...
Size register bit masks and shifts
#define | XCSUDMA_SIZE_MASK 0x1FFFFFFCU
| Mask for size. More...
#define | XCSUDMA_LAST_WORD_MASK 0x00000001U
| Last word check bit mask. More...
#define | XCSUDMA_SIZE_SHIFT 2U
| Shift for size. More...
Status register bit masks and shifts
#define | XCSUDMA_STS_DONE_CNT_MASK 0x0000E000U
| Count done mask. More...
#define | XCSUDMA_STS_FIFO_LEVEL_MASK 0x00001FE0U
| FIFO level mask. More...
#define | XCUSDMA_STS_OUTSTDG_MASK 0x0000001EU
| No.of outstanding read/write commands mask. More...
#define | XCSUDMA_STS_BUSY_MASK 0x00000001U
| Busy mask. More...
#define | XCSUDMA_STS_DONE_CNT_SHIFT 13U
| Shift for Count done. More...
#define | XCSUDMA_STS_FIFO_LEVEL_SHIFT 5U
| Shift for FIFO level. More...
#define | XCUSDMA_STS_OUTSTDG_SHIFT 1U
| Shift for No.of outstanding read/write commands. More...
Control register bit masks and shifts
#define | XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK 0xFE000000U
| SSS FIFO threshold value mask. More...
#define | XCSUDMA_CTRL_APB_ERR_MASK 0x01000000U
| APB register access error mask. More...
#define | XCSUDMA_CTRL_ENDIAN_MASK 0x00800000U
| Endianess mask. More...
#define | XCSUDMA_CTRL_BURST_MASK 0x00400000U
| AXI burst type mask. More...
#define | XCSUDMA_CTRL_TIMEOUT_MASK 0x003FFC00U
| Time out value mask. More...
#define | XCSUDMA_CTRL_FIFO_THRESH_MASK 0x000003FCU
| FIFO threshold mask. More...
#define | XCSUDMA_CTRL_PAUSE_MEM_MASK 0x00000001U
| Memory pause mask. More...
#define | XCSUDMA_CTRL_PAUSE_STRM_MASK 0x00000002U
| Stream pause mask. More...
#define | XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT 25U
| SSS FIFO threshold shift. More...
#define | XCSUDMA_CTRL_APB_ERR_SHIFT 24U
| APB error shift. More...
#define | XCSUDMA_CTRL_ENDIAN_SHIFT 23U
| Endianess shift. More...
#define | XCSUDMA_CTRL_BURST_SHIFT 22U
| AXI burst type shift. More...
#define | XCSUDMA_CTRL_TIMEOUT_SHIFT 10U
| Time out value shift. More...
#define | XCSUDMA_CTRL_FIFO_THRESH_SHIFT 2U
| FIFO thresh shift. More...
CheckSum register bit masks
#define | XCSUDMA_CRC_RESET_MASK 0x00000000U
| Mask to reset value of check sum. More...
Interrupt Enable/Disable/Mask/Status registers bit masks
#define | XCSUDMA_IXR_FIFO_OVERFLOW_MASK 0x00000001U
| FIFO overflow mask, it is valid only to Destination Channel. More...
#define | XCSUDMA_IXR_INVALID_APB_MASK 0x00000040U
| Invalid APB access mask. More...
#define | XCSUDMA_IXR_FIFO_THRESHHIT_MASK 0x00000020U
| FIFO threshold hit indicator mask. More...
#define | XCSUDMA_IXR_TIMEOUT_MEM_MASK 0x00000010U
| Time out counter expired to access memory mask. More...
#define | XCSUDMA_IXR_TIMEOUT_STRM_MASK 0x00000008U
| Time out counter expired to access stream mask. More...
#define | XCSUDMA_IXR_AXI_WRERR_MASK 0x00000004U
| AXI Read/Write error mask. More...
#define | XCSUDMA_IXR_DONE_MASK 0x00000002U
| Done mask. More...
#define | XCSUDMA_IXR_MEM_DONE_MASK 0x00000001U
| Memory done mask, it is valid only for source channel. More...
#define | XCSUDMA_IXR_SRC_MASK 0x0000007FU
     ((XCSUDMA_IXR_INVALID_APB_MASK)|
(XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK) | (XCSUDMA_IXR_MEM_DONE_MASK)) More...
#define | XCSUDMA_IXR_DST_MASK 0x000000FEU
     ((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) |
(XCSUDMA_IXR_INVALID_APB_MASK) | (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK)) More...
Control register 2 bit masks and shifts
#define | XCSUDMA_CTRL2_RESERVED_MASK 0x083F0000U
| Reserved bits mask. More...
#define | XCSUDMA_CTRL2_ACACHE_MASK 0X07000000U
| AXI CACHE mask. More...
#define | XCSUDMA_CTRL2_ROUTE_MASK 0x00800000U
| Route mask. More...
#define | XCSUDMA_CTRL2_TIMEOUT_EN_MASK 0x00400000U
| Time out counters enable mask. More...
#define | XCSUDMA_CTRL2_TIMEOUT_PRE_MASK 0x0000FFF0U
| Time out pre mask. More...
#define | XCSUDMA_CTRL2_MAXCMDS_MASK 0x0000000FU
| Maximum commands mask. More...
#define | XCSUDMA_CTRL2_RESET_MASK 0x0000FFF8U
| Reset mask. More...
#define | XCSUDMA_CTRL2_ACACHE_SHIFT 24U
| Shift for AXI R/W CACHE. More...
#define | XCSUDMA_CTRL2_ROUTE_SHIFT 23U
| Shift for route. More...
#define | XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT 22U
| Shift for Timeout enable feild. More...
#define | XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT 4U
| Shift for Timeout pre feild. More...
MSB Address register bit masks and shifts
#define | XCSUDMA_MSB_ADDR_MASK 0x0001FFFFU
| MSB bits of address mask. More...
#define | XCSUDMA_MSB_ADDR_SHIFT 32U
| Shift for MSB bits of address. More...