zdma: xzdma_hw.h File Reference

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Macros
xzdma_hw.h File Reference

## Macros
#define | XZDMA_HW_H_
| Prevent circular inclusions by using protection macros. More...
#define | XZDma_In32 Xil_In32
| Input operation. More...
#define | XZDma_Out32 Xil_Out32
| Output operation. More...
#define | XZDma_ReadReg(BaseAddress, RegOffset) XZDma_In32((BaseAddress) + (u32)(RegOffset))
| This macro reads the given register. More...
#define | XZDma_WriteReg(BaseAddress, RegOffset, Data) XZDma_Out32(((BaseAddress) + (u32)(RegOffset)), (u32)(Data))
| This macro writes the value into the given register. More...
Registers offsets
#define | XZDMA_ERR_CTRL (0x000U)
#define | XZDMA_CH_ECO (0x004U)
#define | XZDMA_CH_ISR_OFFSET (0x100U)
#define | XZDMA_CH_IMR_OFFSET (0x104U)
#define | XZDMA_CH_IEN_OFFSET (0x108U)
#define | XZDMA_CH_IDS_OFFSET (0x10CU)
#define | XZDMA_CH_CTRL0_OFFSET (0x110U)
#define | XZDMA_CH_CTRL1_OFFSET (0x114U)
#define | XZDMA_CH_PERIF_OFFSET (0x118U)
#define | XZDMA_CH_STS_OFFSET (0x11CU)
#define | XZDMA_CH_DATA_ATTR_OFFSET (0x120U)
#define | XZDMA_CH_DSCR_ATTR_OFFSET (0x124U)
#define | XZDMA_CH_SRC_DSCR_WORD0_OFFSET (0x128U)
#define | XZDMA_CH_SRC_DSCR_WORD1_OFFSET (0x12CU)
#define | XZDMA_CH_SRC_DSCR_WORD2_OFFSET (0x130U)
#define | XZDMA_CH_SRC_DSCR_WORD3_OFFSET (0x134U)
#define | XZDMA_CH_DST_DSCR_WORD0_OFFSET (0x138U)
#define | XZDMA_CH_DST_DSCR_WORD1_OFFSET (0x13CU)
#define | XZDMA_CH_DST_DSCR_WORD2_OFFSET (0x140U)
#define | XZDMA_CH_DST_DSCR_WORD3_OFFSET (0x144U)
#define | XZDMA_CH_WR_ONLY_WORD0_OFFSET (0x148U)
#define | XZDMA_CH_WR_ONLY_WORD1_OFFSET (0x14CU)
#define | XZDMA_CH_WR_ONLY_WORD2_OFFSET (0x150U)
#define | XZDMA_CH_WR_ONLY_WORD3_OFFSET (0x154U)
#define | XZDMA_CH_SRC_START_LSB_OFFSET (0x158U)
#define | XZDMA_CH_SRC_START_MSB_OFFSET (0x15CU)
#define | XZDMA_CH_DST_START_LSB_OFFSET (0x160U)
#define | XZDMA_CH_DST_START_MSB_OFFSET (0x164U)
#define | XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET (0x168U)
#define | XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET (0x16CU)
#define | XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET (0x170U)
#define | XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET (0x174U)
#define | XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET (0x178U)
#define | XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET (0x17CU)
#define | XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET (0x180U)
#define | XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET (0x184U)
#define | XZDMA_CH_TOTAL_BYTE_OFFSET (0x188U)
#define | XZDMA_CH_RATE_CNTL_OFFSET (0x18CU)
#define | XZDMA_CH_IRQ_SRC_ACCT_OFFSET (0x190U)
#define | XZDMA_CH_IRQ_DST_ACCT_OFFSET (0x194U)
#define | XZDMA_CH_CTRL2_OFFSET (0x200U)
Interrupt Enable/Disable/Mask/Status registers bit masks and shifts
#define | XZDMA_IXR_DMA_PAUSE_MASK (0x00000800U)
| IXR pause mask. More...
#define | XZDMA_IXR_DMA_DONE_MASK (0x00000400U)
| IXR done mask. More...
#define | XZDMA_IXR_AXI_WR_DATA_MASK (0x00000200U)
| IXR AXI write data error mask. More...
#define | XZDMA_IXR_AXI_RD_DATA_MASK (0x00000100U)
| IXR AXI read data error mask. More...
#define | XZDMA_IXR_AXI_RD_DST_DSCR_MASK (0x00000080U)
| IXR AXI read descriptor error mask. More...
#define | XZDMA_IXR_AXI_RD_SRC_DSCR_MASK (0x00000040U)
| IXR AXI write descriptor error mask. More...
#define | XZDMA_IXR_DST_ACCT_ERR_MASK (0x00000020U)
| IXR DST interrupt count overflow mask. More...
#define | XZDMA_IXR_SRC_ACCT_ERR_MASK (0x00000010U)
| IXR SRC interrupt count overflow mask. More...
#define | XZDMA_IXR_BYTE_CNT_OVRFL_MASK (0x00000008U)
| IXR byte count over flow mask. More...
#define | XZDMA_IXR_DST_DSCR_DONE_MASK (0x00000004U)
| IXR destination descriptor done mask. More...
#define | XZDMA_IXR_SRC_DSCR_DONE_MASK (0x00000002U)
| IXR source descriptor done mask. More...
#define | XZDMA_IXR_INV_APB_MASK (0x00000001U)
| IXR invalid APB access mask. More...
#define | XZDMA_IXR_ALL_INTR_MASK (0x00000FFFU)
| IXR OR of all the interrupts mask. More...
#define | XZDMA_IXR_DONE_MASK (0x00000400U)
| IXR All done mask. More...
#define | XZDMA_IXR_ERR_MASK (0x00000BF9U)
| IXR all Error mask. More...
Channel Control0 register bit masks and shifts
#define | XZDMA_CTRL0_OVR_FETCH_MASK (0x00000080U)
| Over fetch mask. More...
#define | XZDMA_CTRL0_POINT_TYPE_MASK (0x00000040U)
| Pointer type mask. More...
#define | XZDMA_CTRL0_MODE_MASK (0x00000030U)
| Mode mask. More...
#define | XZDMA_CTRL0_WRONLY_MASK (0x00000010U)
| Write only mask. More...
#define | XZDMA_CTRL0_RDONLY_MASK (0x00000020U)
| Read only mask. More...
#define | XZDMA_CTRL0_RATE_CNTL_MASK (0x00000008U)
| Rate control mask. More...
#define | XZDMA_CTRL0_CONT_ADDR_MASK (0x00000004U)
| Continue address specified mask. More...
#define | XZDMA_CTRL0_CONT_MASK (0x00000002U)
| Continue mask. More...
#define | XZDMA_CTRL0_OVR_FETCH_SHIFT (7U)
| Over fetch shift. More...
#define | XZDMA_CTRL0_POINT_TYPE_SHIFT (6U)
| Pointer type shift. More...
#define | XZDMA_CTRL0_MODE_SHIFT (4U)
| Mode type shift. More...
#define | XZDMA_CTRL0_RESET_VALUE (0x00000080U)
| CTRL0 reset value. More...
Channel Control1 register bit masks and shifts
#define | XZDMA_CTRL1_SRC_ISSUE_MASK (0x0000001FU)
| Source issue mask. More...
#define | XZDMA_CTRL1_RESET_VALUE (0x000003FFU)
| CTRL1 reset value. More...
Channel Peripheral register bit masks and shifts
#define | XZDMA_PERIF_PROG_CELL_CNT_MASK (0x0000003EU)
| Peripheral program cell count. More...
#define | XZDMA_PERIF_SIDE_MASK (0x00000002U)
| Interface attached the side mask. More...
#define | XZDMA_PERIF_EN_MASK (0x00000001U)
| Peripheral flow control mask. More...
Channel Status register bit masks and shifts
#define | XZDMA_STS_DONE_ERR_MASK (0x00000003U)
| Done with errors mask. More...
#define | XZDMA_STS_BUSY_MASK (0x00000002U)
| ZDMA is busy in transfer mask. More...
#define | XZDMA_STS_PAUSE_MASK (0x00000001U)
| ZDMA is in Pause state mask. More...
#define | XZDMA_STS_DONE_MASK (0x00000000U)
| ZDMA done mask. More...
#define | XZDMA_STS_ALL_MASK (0x00000003U)
| ZDMA status mask. More...
Channel Data Attribute register bit masks and shifts
#define | XZDMA_DATA_ATTR_ARBURST_MASK (0x0C000000U)
| Data ArBurst mask. More...
#define | XZDMA_DATA_ATTR_ARCACHE_MASK (0x03C00000U)
| Data ArCache mask. More...
#define | XZDMA_DATA_ATTR_ARQOS_MASK (0x003C0000U)
| Data ARQos masks. More...
#define | XZDMA_DATA_ATTR_ARLEN_MASK (0x0003C000U)
| Data Arlen mask. More...
#define | XZDMA_DATA_ATTR_AWBURST_MASK (0x00003000U)
| Data Awburst mask. More...
#define | XZDMA_DATA_ATTR_AWCACHE_MASK (0x00000F00U)
| Data AwCache mask. More...
#define | XZDMA_DATA_ATTR_AWQOS_MASK (0x000000F0U)
| Data AwQos mask. More...
#define | XZDMA_DATA_ATTR_AWLEN_MASK (0x0000000FU)
| Data Awlen mask. More...
#define | XZDMA_DATA_ATTR_ARBURST_SHIFT (26U)
| Data Arburst shift. More...
#define | XZDMA_DATA_ATTR_ARCACHE_SHIFT (22U)
| Data ArCache shift. More...
#define | XZDMA_DATA_ATTR_ARQOS_SHIFT (18U)
| Data ARQos shift. More...
#define | XZDMA_DATA_ATTR_ARLEN_SHIFT (14U)
| Data Arlen shift. More...
#define | XZDMA_DATA_ATTR_AWBURST_SHIFT (12U)
| Data Awburst shift. More...
#define | XZDMA_DATA_ATTR_AWCACHE_SHIFT (8U)
| Data Awcache shift. More...
#define | XZDMA_DATA_ATTR_AWQOS_SHIFT (4U)
| Data Awqos shift. More...
#define | XZDMA_DATA_ATTR_RESET_VALUE (0x0483D20FU)
| Data Attributes reset value. More...
Channel DSCR Attribute register bit masks and shifts
#define | XZDMA_DSCR_ATTR_AXCOHRNT_MASK (0x00000100U)
| Descriptor coherent mask. More...
#define | XZDMA_DSCR_ATTR_AXCACHE_MASK (0x000000F0U)
| Descriptor cache mask. More...
#define | XZDMA_DSCR_ATTR_AXQOS_MASK (0x0000000FU)
| Descriptor AxQos mask. More...
#define | XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT (8U)
| Descriptor coherent shift. More...
#define | XZDMA_DSCR_ATTR_AXCACHE_SHIFT (4U)
| Descriptor cache shift. More...
#define | XZDMA_DSCR_ATTR_RESET_VALUE (0x00000000U)
| Dscr Attributes reset value. More...
Channel Source/Destination Word0 register bit mask
#define | XZDMA_WORD0_LSB_MASK (0xFFFFFFFFU)
| LSB Address mask. More...
Channel Source/Destination Word1 register bit mask
#define | XZDMA_WORD1_MSB_MASK (0x0001FFFFU)
| MSB Address mask. More...
#define | XZDMA_WORD1_MSB_SHIFT (32U)
| MSB Address shift. More...
Channel Source/Destination Word2 register bit mask
#define | XZDMA_WORD2_SIZE_MASK (0x3FFFFFFFU)
| Size mask. More...
Channel Source/Destination Word3 register bit masks and shifts
#define | XZDMA_WORD3_CMD_MASK (0x00000018U)
| Cmd mask. More...
#define | XZDMA_WORD3_CMD_SHIFT (3U)
| Cmd shift. More...
#define | XZDMA_WORD3_CMD_NXTVALID_MASK (0x00000000U)
| Next Dscr is valid mask. More...
#define | XZDMA_WORD3_CMD_PAUSE_MASK (0x00000008U)
| Pause after this dscr mask. More...
#define | XZDMA_WORD3_CMD_STOP_MASK (0x00000010U)
| Stop after this ..* dscr mask. More...
#define | XZDMA_WORD3_INTR_MASK (0x00000004U)
| Interrupt enable or disable mask. More...
#define | XZDMA_WORD3_INTR_SHIFT (2U)
| Interrupt enable disable shift. More...
#define | XZDMA_WORD3_TYPE_MASK (0x00000002U)
| Type of Descriptor mask. More...
#define | XZDMA_WORD3_TYPE_SHIFT (1U)
| Type of Descriptor Shift. More...
#define | XZDMA_WORD3_COHRNT_MASK (0x00000001U)
| Coherence mask. More...
Channel Source/Destination start address or current payload
MSB register bit mask
#define | XZDMA_START_MSB_ADDR_MASK (0x0001FFFFU)
| Start msb address mask. More...
Channel Rate control count register bit mask
#define | XZDMA_CH_RATE_CNTL_MASK (0x00000FFFU)
| Channel rate control mask. More...
Channel Source/Destination Interrupt account count register bit mask
#define | XZDMA_CH_IRQ_ACCT_MASK (0x000000FFU)
| Interrupt count mask. More...
Channel debug register 0/1 bit mask
#define | XZDMA_CH_DBG_CMN_BUF_MASK (0x000001FFU)
| Common buffer count mask. More...
Channel control2 register bit mask
#define | XZDMA_CH_CTRL2_EN_MASK (0x00000001U)
| Channel enable mask. More...
#define | XZDMA_CH_CTRL2_DIS_MASK (0x00000000U)
| Channel disable mask. More...
#define | XZDMA_WRITE_TO_CLEAR_MASK (0x00000000U)
| Write to clear mask. More...