wdtps: Wdtps_v3_2

| wdtps Xilinx SDK Drivers API Documentation

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Wdtps_v3_2

## Data Structures
struct | XWdtPs_Config
| This typedef contains configuration information for the device. More...
struct | XWdtPs
| The XWdtPs driver instance data. More...

## Macros
#define | XWDTPS_RESET_SIGNAL 0x01U
| Reset signal request. More...
#define | XWDTPS_IRQ_SIGNAL 0x02U
| IRQ signal request. More...
#define | XWDTPS_CLK_PRESCALE 0x01U
| Clock Prescale request. More...
#define | XWDTPS_COUNTER_RESET 0x02U
| Counter Reset request. More...
#define | XWdtPs_IsWdtExpired(InstancePtr)
| Check if the watchdog timer has expired. More...
#define | XWdtPs_RestartWdt(InstancePtr)
| Restart the watchdog timer. More...
#define | XWdtPs_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (u32)(RegOffset))
| Read the given register. More...
#define | XWdtPs_WriteReg(BaseAddress, RegOffset, Data) Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
| Write the given register. More...

## Functions
s32 | XWdtPs_CfgInitialize (XWdtPs *InstancePtr, XWdtPs_Config *ConfigPtr, u32 EffectiveAddress)
| Initialize a specific watchdog timer instance/driver. More...
void | XWdtPs_Start (XWdtPs *InstancePtr)
| Start the watchdog timer of the device. More...
void | XWdtPs_Stop (XWdtPs *InstancePtr)
| Disable the watchdog timer. More...
void | XWdtPs_EnableOutput (XWdtPs *InstancePtr, u8 Signal)
| Enables the indicated signal/output. More...
void | XWdtPs_DisableOutput (XWdtPs *InstancePtr, u8 Signal)
| Disables the indicated signal/output. More...
u32 | XWdtPs_GetControlValue (XWdtPs *InstancePtr, u8 Control)
| Returns the current control setting for the indicated signal/output. More...
void | XWdtPs_SetControlValue (XWdtPs *InstancePtr, u8 Control, u32 Value)
| Updates the current control setting for the indicated signal/output with the provided value. More...
XWdtPs_Config * | XWdtPs_LookupConfig (u16 DeviceId)
| Lookup the device configuration based on the unique device ID. More...
s32 | XWdtPs_SelfTest (XWdtPs *InstancePtr)
| Run a self-test on the timebase. More...

## Variables
XWdtPs_Config | XWdtPs_ConfigTable [XPAR_XWDTPS_NUM_INSTANCES]
| This table contains configuration information for each watchdog timer device in the system. More...
XWdtPs_Config | XWdtPs_ConfigTable [XPAR_XWDTPS_NUM_INSTANCES]
| This table contains configuration information for each watchdog timer device in the system. More...

## Register Map
Offsets of registers from the start of the device
#define | XWDTPS_ZMR_OFFSET 0x00000000U
| Zero Mode Register. More...
#define | XWDTPS_CCR_OFFSET 0x00000004U
| Counter Control Register. More...
#define | XWDTPS_RESTART_OFFSET 0x00000008U
| Restart Register. More...
#define | XWDTPS_SR_OFFSET 0x0000000CU
| Status Register. More...

## Zero Mode Register
This register controls how the time out is indicated and also contains the access code (0xABC) to allow writes to the register
#define | XWDTPS_ZMR_WDEN_MASK 0x00000001U
| enable the WDT More...
#define | XWDTPS_ZMR_RSTEN_MASK 0x00000002U
| enable the reset output More...
#define | XWDTPS_ZMR_IRQEN_MASK 0x00000004U
| enable the IRQ output More...
#define | XWDTPS_ZMR_RSTLN_MASK 0x00000070U
| set length of reset pulse More...
#define | XWDTPS_ZMR_RSTLN_SHIFT 4U
| shift for reset pulse More...
#define | XWDTPS_ZMR_IRQLN_MASK 0x00000180U
| set length of interrupt pulse More...
#define | XWDTPS_ZMR_IRQLN_SHIFT 7U
| shift for interrupt pulse More...
#define | XWDTPS_ZMR_ZKEY_MASK 0x00FFF000U
| mask for writing access key More...
#define | XWDTPS_ZMR_ZKEY_VAL 0x00ABC000U
| access key, 0xABC << 12 More...

## Counter Control register
This register controls how fast the timer runs and the reset value and also contains the access code (0x248) to allow writes to the register
#define | XWDTPS_CCR_CLKSEL_MASK 0x00000003U
| counter clock prescale More...
#define | XWDTPS_CCR_CRV_MASK 0x00003FFCU
| counter reset value More...
#define | XWDTPS_CCR_CRV_SHIFT 2U
| shift for writing value More...
#define | XWDTPS_CCR_CKEY_MASK 0x03FFC000U
| mask for writing access key More...
#define | XWDTPS_CCR_CKEY_VAL 0x00920000U
| access key, 0x248 << 14 More...
#define | XWDTPS_CCR_PSCALE_0008 0x00000000U
| divide clock by 8 More...
#define | XWDTPS_CCR_PSCALE_0064 0x00000001U
| divide clock by 64 More...
#define | XWDTPS_CCR_PSCALE_0512 0x00000002U
| divide clock by 512 More...
#define | XWDTPS_CCR_PSCALE_4096 0x00000003U
| divide clock by 4096 More...

## Restart register
This register resets the timer preventing a timeout. Value is specific 0x1999
#define | XWDTPS_RESTART_KEY_VAL 0x00001999U
| valid key More...

## Status register
This register indicates timer reached zero count.
#define | XWDTPS_SR_WDZ_MASK 0x00000001U
| time out occurred More...

## Macro Definition Documentation

#define XWDTPS_CCR_CKEY_MASK 0x03FFC000U

mask for writing access key

#define XWDTPS_CCR_CKEY_VAL 0x00920000U

access key, 0x248 << 14

Referenced by XWdtPs_SetControlValue().

#define XWDTPS_CCR_CLKSEL_MASK 0x00000003U

counter clock prescale

Referenced by XWdtPs_GetControlValue(), and XWdtPs_SetControlValue().

#define XWDTPS_CCR_CRV_MASK 0x00003FFCU

counter reset value

Referenced by XWdtPs_GetControlValue(), and XWdtPs_SetControlValue().

#define XWDTPS_CCR_CRV_SHIFT 2U

shift for writing value

Referenced by XWdtPs_GetControlValue(), and XWdtPs_SetControlValue().

#define XWDTPS_CCR_OFFSET 0x00000004U

Counter Control Register.

Referenced by XWdtPs_GetControlValue(), and XWdtPs_SetControlValue().

#define XWDTPS_CCR_PSCALE_0008 0x00000000U

divide clock by 8

Referenced by WdtPsIntrExample(), and WdtPsPolledExample().

#define XWDTPS_CCR_PSCALE_0064 0x00000001U

divide clock by 64

#define XWDTPS_CCR_PSCALE_0512 0x00000002U

divide clock by 512

#define XWDTPS_CCR_PSCALE_4096 0x00000003U

divide clock by 4096

#define XWDTPS_CLK_PRESCALE 0x01U

Clock Prescale request.

Referenced by WdtPsIntrExample(), WdtPsPolledExample(), XWdtPs_GetControlValue(), and XWdtPs_SetControlValue().

#define XWDTPS_COUNTER_RESET 0x02U

Counter Reset request.

Referenced by WdtPsIntrExample(), WdtPsPolledExample(), XWdtPs_GetControlValue(), and XWdtPs_SetControlValue().

#define XWDTPS_IRQ_SIGNAL 0x02U

IRQ signal request.

Referenced by WdtPsIntrExample(), XWdtPs_DisableOutput(), and XWdtPs_EnableOutput().

#define XWdtPs_IsWdtExpired | ( |  | InstancePtr | ) |

Value:
((XWdtPs_ReadReg((InstancePtr)->Config.BaseAddress, XWDTPS_SR_OFFSET) & \
XWDTPS_SR_WDZ_MASK) == XWDTPS_SR_WDZ_MASK)
XWDTPS_SR_OFFSET
#define XWDTPS_SR_OFFSET
Status Register.
Definition: xwdtps_hw.h:70
XWDTPS_SR_WDZ_MASK
#define XWDTPS_SR_WDZ_MASK
time out occurred
Definition: xwdtps_hw.h:132
XWdtPs_ReadReg
#define XWdtPs_ReadReg(BaseAddress, RegOffset)
Read the given register.
Definition: xwdtps_hw.h:155

Check if the watchdog timer has expired.

This function is used for polled mode and it is also used to check if the last reset was caused by the watchdog timer.

Parameters

  InstancePtr | is a pointer to the XWdtPs instance.

Returns
  - TRUE if the watchdog has expired.
  - FALSE if the watchdog has not expired.

Note
  C-style signature: int XWdtPs_IsWdtExpired(XWdtPs *InstancePtr)

Referenced by WdtPsIntrExample(), and WdtPsPolledExample().

#define XWdtPs_ReadReg | ( |  | BaseAddress,
|  |  | RegOffset
| ) |  | Xil_In32((BaseAddress) + (u32)(RegOffset))

Read the given register.

Parameters

  BaseAddress | is the base address of the device
  RegOffset | is the register offset to be read

Returns
  The 32-bit value of the register

Note
  C-style signature: u32 XWdtPs_ReadReg(u32 BaseAddress, u32 RegOffset)

Referenced by XWdtPs_DisableOutput(), XWdtPs_EnableOutput(), XWdtPs_GetControlValue(), XWdtPs_SelfTest(), XWdtPs_SetControlValue(), XWdtPs_Start(), and XWdtPs_Stop().

#define XWDTPS_RESET_SIGNAL 0x01U

Reset signal request.

Referenced by WdtPsIntrExample(), WdtPsPolledExample(), XWdtPs_DisableOutput(), and XWdtPs_EnableOutput().

#define XWDTPS_RESTART_KEY_VAL 0x00001999U

valid key

#define XWDTPS_RESTART_OFFSET 0x00000008U

Restart Register.

#define XWdtPs_RestartWdt | ( |  | InstancePtr | ) |

Value:
XWdtPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XWDTPS_RESTART_OFFSET, XWDTPS_RESTART_KEY_VAL)
XWDTPS_RESTART_KEY_VAL
#define XWDTPS_RESTART_KEY_VAL
valid key
Definition: xwdtps_hw.h:124
XWdtPs_WriteReg
#define XWdtPs_WriteReg(BaseAddress, RegOffset, Data)
Write the given register.
Definition: xwdtps_hw.h:173
XWDTPS_RESTART_OFFSET
#define XWDTPS_RESTART_OFFSET
Restart Register.
Definition: xwdtps_hw.h:69

Restart the watchdog timer.

An application needs to call this function periodically to keep the timer from asserting the enabled output.

Parameters

  InstancePtr | is a pointer to the XWdtPs instance.

Returns
  None.

Note
  C-style signature: void XWdtPs_RestartWdt(XWdtPs *InstancePtr)

Referenced by WdtPsIntrExample(), and WdtPsPolledExample().

#define XWDTPS_SR_OFFSET 0x0000000CU

Status Register.

#define XWDTPS_SR_WDZ_MASK 0x00000001U

time out occurred

#define XWdtPs_WriteReg | ( |  | BaseAddress,
|  |  | RegOffset,
|  |  | Data
| ) |  | Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))

Write the given register.

Parameters

  BaseAddress | is the base address of the device
  RegOffset | is the register offset to be written
  Data | is the 32-bit value to write to the register

Returns
  None.

Note
  C-style signature: void XWdtPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XWdtPs_DisableOutput(), XWdtPs_EnableOutput(), XWdtPs_SelfTest(), XWdtPs_SetControlValue(), XWdtPs_Start(), and XWdtPs_Stop().

#define XWDTPS_ZMR_IRQEN_MASK 0x00000004U

enable the IRQ output

Referenced by XWdtPs_DisableOutput(), and XWdtPs_EnableOutput().

#define XWDTPS_ZMR_IRQLN_MASK 0x00000180U

set length of interrupt pulse

#define XWDTPS_ZMR_IRQLN_SHIFT 7U

shift for interrupt pulse

#define XWDTPS_ZMR_OFFSET 0x00000000U

Zero Mode Register.

Referenced by XWdtPs_DisableOutput(), XWdtPs_EnableOutput(), XWdtPs_SelfTest(), XWdtPs_Start(), and XWdtPs_Stop().

#define XWDTPS_ZMR_RSTEN_MASK 0x00000002U

enable the reset output

Referenced by XWdtPs_DisableOutput(), and XWdtPs_EnableOutput().

#define XWDTPS_ZMR_RSTLN_MASK 0x00000070U

set length of reset pulse

Referenced by XWdtPs_SelfTest().

#define XWDTPS_ZMR_RSTLN_SHIFT 4U

shift for reset pulse

#define XWDTPS_ZMR_WDEN_MASK 0x00000001U

enable the WDT

Referenced by XWdtPs_Start(), and XWdtPs_Stop().

#define XWDTPS_ZMR_ZKEY_MASK 0x00FFF000U

mask for writing access key

#define XWDTPS_ZMR_ZKEY_VAL 0x00ABC000U

access key, 0xABC << 12

Referenced by XWdtPs_DisableOutput(), XWdtPs_EnableOutput(), XWdtPs_SelfTest(), XWdtPs_Start(), and XWdtPs_Stop().

## Function Documentation

s32 XWdtPs_CfgInitialize | ( | XWdtPs * | InstancePtr,
|  | XWdtPs_Config * | ConfigPtr,
|  | u32 | EffectiveAddress
| ) |  |

Initialize a specific watchdog timer instance/driver.

This function must be called before other functions of the driver are called.

Parameters

  InstancePtr | is a pointer to the XWdtPs instance.
  ConfigPtr | is the config structure.
  EffectiveAddress | is the base address for the device. It could be a virtual address if address translation is supported in the system, otherwise it is the physical address.

Returns
  - XST_SUCCESS if initialization was successful.
  - XST_DEVICE_IS_STARTED if the device has already been started.

Note
  None.

References XWdtPs_Config::BaseAddress, XWdtPs::Config, XWdtPs_Config::DeviceId, XWdtPs::IsReady, and XWdtPs::IsStarted.

Referenced by WdtPsIntrExample(), WdtPsPolledExample(), and WdtPsSelfTestExample().

void XWdtPs_DisableOutput | ( | XWdtPs * | InstancePtr,
|  | u8 | Signal
| ) |  |

Disables the indicated signal/output.

Performs a read/modify/write cycle to update the value correctly.

Parameters

  InstancePtr | is a pointer to the XWdtPs instance.
  Signal | is the desired signal/output. Valid Signal Values are XWDTPS_RESET_SIGNAL and XWDTPS_IRQ_SIGNAL Only one of them can be specified at a time.

Returns
  None.

Note
  None.

References XWdtPs_Config::BaseAddress, XWdtPs::Config, XWdtPs::IsReady, XWDTPS_IRQ_SIGNAL, XWdtPs_ReadReg, XWDTPS_RESET_SIGNAL, XWdtPs_WriteReg, XWDTPS_ZMR_IRQEN_MASK, XWDTPS_ZMR_OFFSET, XWDTPS_ZMR_RSTEN_MASK, and XWDTPS_ZMR_ZKEY_VAL.

Referenced by WdtPsIntrExample(), and WdtPsPolledExample().

void XWdtPs_EnableOutput | ( | XWdtPs * | InstancePtr,
|  | u8 | Signal
| ) |  |

Enables the indicated signal/output.

Performs a read/modify/write cycle to update the value correctly.

Parameters

  InstancePtr | is a pointer to the XWdtPs instance.
  Signal | is the desired signal/output. Valid Signal Values are XWDTPS_RESET_SIGNAL and XWDTPS_IRQ_SIGNAL. Only one of them can be specified at a time.

Returns
  None.

Note
  None.

References XWdtPs_Config::BaseAddress, XWdtPs::Config, XWdtPs::IsReady, XWDTPS_IRQ_SIGNAL, XWdtPs_ReadReg, XWDTPS_RESET_SIGNAL, XWdtPs_WriteReg, XWDTPS_ZMR_IRQEN_MASK, XWDTPS_ZMR_OFFSET, XWDTPS_ZMR_RSTEN_MASK, and XWDTPS_ZMR_ZKEY_VAL.

Referenced by WdtPsIntrExample().

u32 XWdtPs_GetControlValue | ( | XWdtPs * | InstancePtr,
|  | u8 | Control
| ) |  |

Returns the current control setting for the indicated signal/output.

The register referenced is the Counter Control Register (XWDTPS_CCR_OFFSET)

Parameters

  InstancePtr | is a pointer to the XWdtPs instance.
  Control | is the desired signal/output. Valid Control Values are XWDTPS_CLK_PRESCALE and XWDTPS_COUNTER_RESET. Only one of them can be specified at a time.

Returns
  The contents of the requested control field in the Counter Control Register (XWDTPS_CCR_OFFSET). If the Control is XWDTPS_CLK_PRESCALE then use the definitions XWDTEPB_CCR_PSCALE_XXXX. If the Control is XWDTPS_COUNTER_RESET then the values are 0x0 to 0xFFF. This is the Counter Restart value in the CCR register.

Note
  None.

References XWdtPs_Config::BaseAddress, XWdtPs::Config, XWdtPs::IsReady, XWDTPS_CCR_CLKSEL_MASK, XWDTPS_CCR_CRV_MASK, XWDTPS_CCR_CRV_SHIFT, XWDTPS_CCR_OFFSET, XWDTPS_CLK_PRESCALE, XWDTPS_COUNTER_RESET, and XWdtPs_ReadReg.

XWdtPs_Config * XWdtPs_LookupConfig | ( | u16 | DeviceId | ) |

Lookup the device configuration based on the unique device ID.

The table contains the configuration info for each device in the system.

Parameters

  DeviceId | is the unique device ID of the device being looked up.

Returns
  A pointer to the configuration table entry corresponding to the given device ID, or NULL if no match is found.

Note
  None.

Referenced by WdtPsIntrExample(), WdtPsPolledExample(), and WdtPsSelfTestExample().

s32 XWdtPs_SelfTest | ( | XWdtPs * | InstancePtr | ) |

Run a self-test on the timebase.

This test verifies that the register access locking functions. This is tested by trying to alter a register without setting the key value and verifying that the register contents did not change.

Parameters

  InstancePtr | is a pointer to the XWdtPs instance.

Returns
  - XST_SUCCESS if self-test was successful.
  - XST_FAILURE if self-test was not successful.

Note
  None.

References XWdtPs_Config::BaseAddress, XWdtPs::Config, XWdtPs::IsReady, XWdtPs_ReadReg, XWdtPs_WriteReg, XWDTPS_ZMR_OFFSET, XWDTPS_ZMR_RSTLN_MASK, and XWDTPS_ZMR_ZKEY_VAL.

Referenced by WdtPsIntrExample(), and WdtPsSelfTestExample().

void XWdtPs_SetControlValue | ( | XWdtPs * | InstancePtr,
|  | u8 | Control,
|  | u32 | Value
| ) |  |

Updates the current control setting for the indicated signal/output with the provided value.

Performs a read/modify/write cycle to update the value correctly. The register referenced is the Counter Control Register (XWDTPS_CCR_OFFSET)

Parameters

  InstancePtr | is a pointer to the XWdtPs instance.
  Control | is the desired signal/output. Valid Control Values are XWDTPS_CLK_PRESCALE and XWDTPS_COUNTER_RESET. Only one of them can be specified at a time.
  Value | is the desired control value. If the Control is XWDTPS_CLK_PRESCALE then use the definitions XWDTEPB_CCR_PSCALE_XXXX. If the Control is XWDTPS_COUNTER_RESET then the valid values are 0x0 to 0xFFF, this sets the counter restart value of the CCR register.

Returns
  None.

Note
  None.

References XWdtPs_Config::BaseAddress, XWdtPs::Config, XWdtPs::IsReady, XWDTPS_CCR_CKEY_VAL, XWDTPS_CCR_CLKSEL_MASK, XWDTPS_CCR_CRV_MASK, XWDTPS_CCR_CRV_SHIFT, XWDTPS_CCR_OFFSET, XWDTPS_CLK_PRESCALE, XWDTPS_COUNTER_RESET, XWdtPs_ReadReg, and XWdtPs_WriteReg.

Referenced by WdtPsIntrExample(), and WdtPsPolledExample().

void XWdtPs_Start | ( | XWdtPs * | InstancePtr | ) |

Start the watchdog timer of the device.

Parameters

  InstancePtr | is a pointer to the XWdtPs instance.

Returns
  None.

Note
  None.

References XWdtPs_Config::BaseAddress, XWdtPs::Config, XWdtPs::IsReady, XWdtPs::IsStarted, XWdtPs_ReadReg, XWdtPs_WriteReg, XWDTPS_ZMR_OFFSET, XWDTPS_ZMR_WDEN_MASK, and XWDTPS_ZMR_ZKEY_VAL.

Referenced by WdtPsIntrExample(), and WdtPsPolledExample().

void XWdtPs_Stop | ( | XWdtPs * | InstancePtr | ) |

Disable the watchdog timer.

It is the caller's responsibility to disconnect the interrupt handler of the watchdog timer from the interrupt source, typically an interrupt controller, and disable the interrupt in the interrupt controller.

Parameters

  InstancePtr | is a pointer to the XWdtPs instance.

Returns
  None.

Note
  None.

References XWdtPs_Config::BaseAddress, XWdtPs::Config, XWdtPs::IsReady, XWdtPs::IsStarted, XWdtPs_ReadReg, XWdtPs_WriteReg, XWDTPS_ZMR_OFFSET, XWDTPS_ZMR_WDEN_MASK, and XWDTPS_ZMR_ZKEY_VAL.

Referenced by WdtPsIntrExample().

## Variable Documentation

XWdtPs_Config XWdtPs_ConfigTable[XPAR_XWDTPS_NUM_INSTANCES]

This table contains configuration information for each watchdog timer device in the system.

XWdtPs_Config XWdtPs_ConfigTable[XPAR_XWDTPS_NUM_INSTANCES]

Initial value:
= {
{
(u16)XPAR_XWDTPS_0_DEVICE_ID,
(u32)XPAR_XWDTPS_0_BASEADDR
},
{
(u16)XPAR_XWDTPS_1_DEVICE_ID,
(u32)XPAR_XWDTPS_1_BASEADDR
}
}

This table contains configuration information for each watchdog timer device in the system.