axiethernet: xavb_hw.h File Reference

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xavb_hw.h File Reference

## Overview

This header file contains the identifiers and basic driver functions (or macros) that can be used to access the device.

Other driver functions are defined in xavb.h.

    MODIFICATION HISTORY:

    Ver   Who  Date     Changes

    1.00a mbr  09/19/08 First release
    1.01a mbr  06/24/09 PTP frame format updates for IEEE802.1 AS draft 5-0
    2_02a mbr  09/16/09 Updates for programmable PTP timers
    2_04a kag  07/23/10 PTP frame format updates for IEEE802.1 AS draft 6-7
    3_01a kag  08/29/11 Added new APIs to update the RX Filter Control Reg.
                  Fix for CR:572539. Updated bit map for Rx Filter
                  control reg.
    3_01a asa  04/10/12 The AVB core is now brought inside the AxiEthernet
                  core. Because of this there are changes in the
                  register map.

## Data Structures
struct | XAvb_RtcFormat
| This typedef defines the format for the Real Time Clock (RTC). More...
struct | XAvb_Uint64
| This typedef describes a 64-bit un-signed integer in terms of 2 u32s. More...

## Macros
#define | XAvb_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (RegOffset))
| This macro reads from the given AVB core register. More...
#define | XAvb_WriteReg(BaseAddress, RegOffset, Data) Xil_Out32((BaseAddress) + (RegOffset), (Data))
| This macro writes to the given AVB core register. More...
#define | XAvb_ReadPtpBuffer(BaseAddress, PtpPacketBaseAddress, PtpPacketOffset) Xil_In32(BaseAddress + PtpPacketBaseAddress + PtpPacketOffset)
| This macro reads from the given PTP frame buffer. More...
#define | XAvb_WritePtpBuffer(BaseAddress, PtpPacketBaseAddress, PtpPacketOffset, Data) Xil_Out32(BaseAddress + PtpPacketBaseAddress + PtpPacketOffset, (Data))
| This macro writes to the given PTP frame buffer. More...
#define | XAvbMac_ReadConfig(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (RegOffset))
| This macro reads from the given TEMAC Configuration Register. More...
#define | XAvbMac_WriteConfig(BaseAddress, RegOffset, Data) Xil_Out32((BaseAddress) + (RegOffset), (Data))
| This macro writes to the given TEMAC Configuration Register. More...
#define | XAvbMac_ReadMdio(BaseAddress, Phyad, Regad)
| This macro reads from the given MDIO Register using the TEMAC. More...
#define | XAvbMac_WriteMdio(BaseAddress, Phyad, Regad, Data)
| This macro writes to the given MDIO Register using the TEMAC. More...
Register offsets for the Tri-Mode Ethernet MAC. Each register is 32
bits. The MAC is addressable through the Ethernet AVB Endpoint core.
#define | XAVB_MAC_RX_REG0_OFFSET 0x00000400
| MAC Rx Config Register 0. More...
#define | XAVB_MAC_RX_REG1_OFFSET 0x00000404
| MAC Rx Config Register 1. More...
#define | XAVB_MAC_TX_REG_OFFSET 0x00000408
| MAC Tx Config Register. More...
#define | XAVB_MAC_FC_REG_OFFSET 0x0000040c
| MAC Flow Control Register. More...
#define | XAVB_MAC_SPD_REG_OFFSET 0x00000410
| MAC Speed Control Register. More...
Register offsets for the Ethernet Audio Video Endpoint. Each register
is 32 bits.
#define | XAVB_PTP_TX_CONTROL_OFFSET 0x00012000
| Tx PTP Control Reg. More...
#define | XAVB_PTP_RX_CONTROL_OFFSET 0x00012004
| Rx PTP Control Reg. More...
#define | XAVB_RX_FILTER_CONTROL 0x00012008
| Rx Filter Control Reg. More...
#define | XAVB_TX_SENDSLOPE 0x0001200C
| Tx rate sendSlope Reg. More...
#define | XAVB_TX_IDLESLOPE 0x00012010
| Tx rate idleSlope Reg. More...
#define | XAVB_TX_HILIMIT 0x00012014
| Tx rate hiLimit Reg. More...
#define | XAVB_TX_LOLIMIT 0x00012018
| Tx rate loLimit Reg. More...
#define | XAVB_RTC_NANOSEC_OFFSET 0x00012800
| RTC ns offset Reg. More...
#define | XAVB_RTC_SEC_LOWER_OFFSET 0x00012808
| RTC sec[31:0] offset. More...
#define | XAVB_RTC_SEC_UPPER_OFFSET 0x0001280C
| RTC sec[47:32] offset. More...
#define | XAVB_RTC_INCREMENT_OFFSET 0x00012810
| RTC Increment Reg. More...
#define | XAVB_RTC_NANOSEC_VALUE_OFFSET 0x00012814
| RTC ns value Reg. More...
#define | XAVB_RTC_SEC_LOWER_VALUE_OFFSET 0x00012818
| RTC sec[31:0] value. More...
#define | XAVB_RTC_SEC_UPPER_VALUE_OFFSET 0x0001281C
| RTC sec[47:32] value. More...
#define | XAVB_RTC_CLEAR_INT_OFFSET 0x00012820
| RTC Interrupt Clear. More...
#define | XAVB_RTC_8K_OFFSET_OFFSET 0x00012824
| RTC 8k phase offset. More...
#define | XAVB_SW_RESET_OFFSET 0x00012828
| S/W Reset Reg. More...
Packet base address offsets for the Ethernet Audio Video Endpoint Tx
Precise Timing Protocol (PTP) frame buffer. Each PTP frames is stored in 256-byte chunks of BRAM. This BRAM can store 8 PTP frames of which only 6 are currently in use.
#define | XAVB_PTP_TX_SYNC_OFFSET 0x00011000
#define | XAVB_PTP_TX_FOLLOW_UP_OFFSET 0x00011100
#define | XAVB_PTP_TX_PDELAYREQ_OFFSET 0x00011200
#define | XAVB_PTP_TX_PDELAYRESP_OFFSET 0x00011300
#define | XAVB_PTP_TX_PDELAYRESP_FOLLOW_UP_OFFSET 0x00011400
#define | XAVB_PTP_TX_ANNOUNCE_OFFSET 0x00011500
Base address offset for the Ethernet Audio Video Endpoint Rx
Precise Timing Protocol (PTP) frame buffer. These PTP frames are stored in 256-byte chunks of BRAM. This BRAM can store 16 PTP frames.
#define | XAVB_PTP_RX_BASE_OFFSET 0x00010000
AVB Tx PTP Control Register
#define | XAVB_PTP_TX_SEND_SYNC_FRAME_MASK 0x00000001
#define | XAVB_PTP_TX_SEND_FOLLOWUP_FRAME_MASK 0x00000002
#define | XAVB_PTP_TX_SEND_PDELAYREQ_FRAME_MASK 0x00000004
#define | XAVB_PTP_TX_SEND_PDELAYRESP_FRAME_MASK 0x00000008
#define | XAVB_PTP_TX_SEND_PDELAYRESPFOLLOWUP_FRAME_MASK 0x00000010
#define | XAVB_PTP_TX_SEND_ANNOUNCE_FRAME_MASK 0x00000020
#define | XAVB_PTP_TX_SEND_FRAME6_BIT_MASK 0x00000040
#define | XAVB_PTP_TX_SEND_FRAME7_BIT_MASK 0x00000080
#define | XAVB_PTP_TX_WAIT_SYNC_FRAME_MASK 0x00000100
#define | XAVB_PTP_TX_WAIT_FOLLOWUP_FRAME_MASK 0x00000200
#define | XAVB_PTP_TX_WAIT_PDELAYREQ_FRAME_MASK 0x00000400
#define | XAVB_PTP_TX_WAIT_PDELAYRESP_FRAME_MASK 0x00000800
#define | XAVB_PTP_TX_WAIT_PDELAYRESPFOLLOWUP_FRAME_MASK 0x00001000
#define | XAVB_PTP_TX_WAIT_ANNOUNCE_FRAME_MASK 0x00002000
#define | XAVB_PTP_TX_WAIT_FRAME6_BIT_MASK 0x00004000
#define | XAVB_PTP_TX_WAIT_FRAME7_BIT_MASK 0x00008000
#define | XAVB_PTP_TX_WAIT_ALL_FRAMES_MASK 0x0000FF00
#define | XAVB_PTP_TX_PACKET_FIELD_MASK 0x00070000
AVB Rx PTP Control Register
#define | XAVB_PTP_RX_CLEAR_BIT_MASK 0x00000001
#define | XAVB_PTP_RX_PACKET_FIELD_MASK 0x00000F00
AVB Rx Filter Control Register
#define | XAVB_RX_AV_VLAN_PRIORITY_A_MASK 0x00000007
#define | XAVB_RX_AV_VLAN_VID_A_MASK 0x00007FF8
#define | XAVB_RX_AV_VLAN_MATCH_MODE_MASK 0x00008000
#define | XAVB_RX_AV_VLAN_PRIORITY_B_MASK 0x00070000
#define | XAVB_RX_AV_VLAN_VID_B_MASK 0x7FF80000
#define | XAVB_RX_LEGACY_PROMISCUOUS_MODE_MASK 0x80000000
AVB Tx rate control sendSlope
#define | XAVB_TX_SENDSLOPE_MASK 0X000FFFFF
AVB Tx rate control idleSlope
#define | XAVB_TX_IDLESLOPE_MASK 0X000FFFFF
AVB Tx rate control hiLimit
#define | XAVB_TX_HILIMIT_MASK 0X01FFFFFF
AVB Tx rate control loLimit
#define | XAVB_TX_LOLIMIT_MASK 0X01FFFFFF
RTC field Registers
#define | XAVB_RTC_NS_MASK 0x3FFFFFFF
#define | XAVB_RTC_SEC_LOWER_MASK 0xFFFFFFFF
#define | XAVB_RTC_SEC_UPPER_MASK 0x0000FFFF
RTC Interrupt Clear Register
#define | XAVB_RTC_INCREMENT_VALUE_MASK 0x03FFFFFF
#define | XAVB_RTC_CLEAR_INT_MASK 0x00000000
RTC Increment Register
#define | XAVB_RTC_INCREMENT_NOMINAL_RATE 0x00800000
| This value assumes a 125MHz rtc_clock. More...
#define | XAVB_RTC_400PPM_OFFSET 0x00004189
| Add some rails so that recovery is possible after a string of bad pDelay values. More...
RTC 8k phase offset Register
#define | XAVB_RTC_8K_PHASE_OFFSET_MASK 0x3FFFFFFF
S/W Reset Register
#define | XAVB_SW_RESET_TX_AND_RX_PATHS 0x00000003
AVB MAC MDIO register address space.
#define | XAVB_MAC_MDIO_BASE_OFFSET 0x00006000
MDIO valid data mask (MDIO registers are all 16-bits).
#define | XAVB_MAC_MDIO_DATA_MASK 0x0000FFFF
MAC Statistic Counter names and CounterID.
#define | XAVB_STATS_BYTES_TRANSMITTED 0x00000000
#define | XAVB_STATS_BYTES_RECEIVED 0x00000001
#define | XAVB_STATS_UNDERSIZED_FRAMES_RECEIVED 0x00000002
#define | XAVB_STATS_FRAGMENT_FRAMES_RECEIVED 0x00000003
#define | XAVB_STATS_64_BYTE_FRAMES_RECEIVED_OK 0x00000004
#define | XAVB_STATS_65_TO_127_BYTE_FRAMES_RECEIVED_OK 0x00000005
#define | XAVB_STATS_128_TO_255_BYTE_FRAMES_RECEIVED_OK 0x00000006
#define | XAVB_STATS_256_TO_511_BYTE_FRAMES_RECEIVED_OK 0x00000007
#define | XAVB_STATS_512_TO_1023_BYTE_FRAMES_RECEIVED_OK 0x00000008
#define | XAVB_STATS_1024_TO_1518_BYTE_FRAMES_RECEIVED_OK 0x00000009
#define | XAVB_STATS_OVERSIZED_FRAMES_RECEIVED_OK 0x0000000A
#define | XAVB_STATS_64_BYTE_FRAMES_TRANSMITTED_OK 0x0000000B
#define | XAVB_STATS_65_TO_127_BYTE_FRAMES_TRANSMITTED_OK 0x0000000C
#define | XAVB_STATS_128_TO_255_BYTE_FRAMES_TRANSMITTED_OK 0x0000000D
#define | XAVB_STATS_256_TO_511_BYTE_FRAMES_TRANSMITTED_OK 0x0000000E
#define | XAVB_STATS_512_TO_1023_BYTE_FRAMES_TRANSMITTED_OK 0x0000000F
#define | XAVB_STATS_1024_TO_1518_BYTE_FRAMES_TRANSMITTED_OK 0x00000010
#define | XAVB_STATS_OVERSIZE_FRAMES_TRANSMITTED_OK 0x00000011
#define | XAVB_STATS_FRAMES_RECEIVED_OK 0x00000012
#define | XAVB_STATS_FCS_ERRORS 0x00000013
#define | XAVB_STATS_BROADCAST_FRAMES_RECEIVED_OK 0x00000014
#define | XAVB_STATS_MULTICAST_FRAMES_RECEIVED_OK 0x00000015
#define | XAVB_STATS_CONTROL_FRAMES_RECEIVED_OK 0x00000016
#define | XAVB_STATS_LENGTH_TYPE_OUT_OF_RANGE 0x00000017
#define | XAVB_STATS_VLAN_TAGGED_FRAMES_RECEIVED_OK 0x00000018
#define | XAVB_STATS_PAUSE_FRAMES_RECEIVED_OK 0x00000019
#define | XAVB_STATS_CONTROL_FRAMES_WITH_UNSUPPORTED_OPCODE 0x0000001A
#define | XAVB_STATS_FRAMES_TRANSMITTED 0x0000001B
#define | XAVB_STATS_BROADCAST_FRAMES_TRANSMITTED 0x0000001C
#define | XAVB_STATS_MULTICAST_FRAMES_TRANSMITTED 0x0000001D
#define | XAVB_STATS_UNDERRUN_ERRORS 0x0000001E
#define | XAVB_STATS_CONTROL_FRAMES_TRANSMITTED_OK 0x0000001F
#define | XAVB_STATS_VLAN_TAGGED_FRAMES_TRANSMITTED_OK 0x00000020
#define | XAVB_STATS_PAUSE_FRAMES_TRANSMITTED_OK 0x00000021
#define | XAVB_STATS_SINGLE_COLLISION_FRAMES 0x00000022
#define | XAVB_STATS_MULTI_COLLISION_FRAMES 0x00000023
#define | XAVB_STATS_DEFERRAL_FRAMES 0x00000024
#define | XAVB_STATS_LATE_COLLISION_FRAMES 0x00000025
#define | XAVB_STATS_EXCESS_COLLISION_FRAMES 0x00000026
#define | XAVB_STATS_EXCESS_DEFERRAL_FRAMES 0x00000027
#define | XAVB_STATS_CARRIER_SENSE_ERRORS 0x00000028
#define | XAVB_STATS_ALIGNMENT_ERRORS 0x00000029

## Functions
void | XAvbMac_ReadStats (u32 BaseAddress, u32 CounterId, XAvb_Uint64 *Value)
| This function reads the given Ethernet Statistic Register. More...
void | XAvb_ReadRtc (u32 BaseAddress, XAvb_RtcFormat *RtcValue)
| This function reads the current Real Time Counter (RTC) value. More...
void | XAvb_WriteRtcOffset (u32 BaseAddress, XAvb_RtcFormat *RtcValue)
| This function writes to the Real Time Counter (RTC) Offset Registers. More...

## Macro Definition Documentation

#define XAVB_MAC_FC_REG_OFFSET 0x0000040c

MAC Flow Control Register.

#define XAVB_MAC_RX_REG0_OFFSET 0x00000400

MAC Rx Config Register 0.

#define XAVB_MAC_RX_REG1_OFFSET 0x00000404

MAC Rx Config Register 1.

#define XAVB_MAC_SPD_REG_OFFSET 0x00000410

MAC Speed Control Register.

#define XAVB_MAC_TX_REG_OFFSET 0x00000408

MAC Tx Config Register.

#define XAVB_PTP_RX_CONTROL_OFFSET 0x00012004

Rx PTP Control Reg.

Referenced by XAvb_PtpRxInterruptHandler().

#define XAVB_PTP_TX_CONTROL_OFFSET 0x00012000

Tx PTP Control Reg.

Referenced by XAvb_MasterSendAnnounce(), XAvb_MasterSendFollowUp(), XAvb_MasterSendSync(), XAvb_SendPDelayReq(), XAvb_SendPDelayResp(), XAvb_SendPDelayRespFollowUp(), and XAvb_WaitOnTxPtpQueue().

#define XAvb_ReadPtpBuffer | ( |  | BaseAddress,
|  |  | PtpPacketBaseAddress,
|  |  | PtpPacketOffset
| ) |  | Xil_In32(BaseAddress + PtpPacketBaseAddress + PtpPacketOffset)

This macro reads from the given PTP frame buffer.

Parameters

  BaseAddress | is the base address of the device
  PtpPacketBaseAddress | is the base address of the frame in the PTP BRAM packet buffer
  PtpPacketOffset | is the offset address within the PTP frame

Returns
  The 32-bit value of the register

Note
  None.

Referenced by XAvb_CalcRtcOffset(), XAvb_CaptureNanoSec(), XAvb_DecodeRxFollowUp(), XAvb_DecodeRxPDelayResp(), XAvb_DecodeRxPDelayRespFollowUp(), XAvb_DecodeRxSignaling(), XAvb_DecodeRxSync(), XAvb_GetPortIdentity(), XAvb_IncSequenceId(), XAvb_IsRxFramePTP(), XAvb_MasterSendFollowUp(), XAvb_MasterSendSync(), XAvb_PtpRxInterruptHandler(), XAvb_ReadAnnounceFrame(), XAvb_ReadAnnounceReceiptTimeout(), XAvb_SendPDelayReq(), XAvb_SendPDelayResp(), XAvb_SendPDelayRespFollowUp(), XAvb_SetupSourcePortIdentity(), XAvb_UpdateLogMeanMessageInterval(), and XAvb_WriteToMultipleTxPtpFrames().

#define XAvb_ReadReg | ( |  | BaseAddress,
|  |  | RegOffset
| ) |  | Xil_In32((BaseAddress) + (RegOffset))

This macro reads from the given AVB core register.

Parameters

  BaseAddress | is the base address of the device
  RegOffset | is the register offset to be read

Returns
  The 32-bit value of the register

Note
  None.

Referenced by XAvb_Adjust8kClock(), XAvb_CalcRtcOffset(), XAvb_MasterSendAnnounce(), XAvb_MasterSendFollowUp(), XAvb_MasterSendSync(), XAvb_PtpRxInterruptHandler(), XAvb_SendPDelayResp(), XAvb_SetupRxFilterControlMatchMode(), XAvb_SetupRxFilterControlPcp(), XAvb_SetupRxFilterControlVid(), XAvb_UpdateRtcIncrement(), and XAvb_WaitOnTxPtpQueue().

#define XAVB_RTC_400PPM_OFFSET 0x00004189

Add some rails so that recovery is possible after a string of bad pDelay values.

The RTC should be able to lock to within 100ppm of the slowest allowable clock (25 MHz). This equates to +/-4ps. Let's arbitrarily set the rails to 400ppm (+/-16ps) just in case someone decides to use a particularly bad oscillator. The lowest 20 bits of NewIncrement are fractions of a nanosecond, which equates to +/- 0x04189

Referenced by XAvb_UpdateRtcIncrement().

#define XAVB_RTC_8K_OFFSET_OFFSET 0x00012824

RTC 8k phase offset.

Referenced by XAvb_Adjust8kClock().

#define XAVB_RTC_CLEAR_INT_OFFSET 0x00012820

RTC Interrupt Clear.

Referenced by XAvb_PtpTimerInterruptHandler().

#define XAVB_RTC_INCREMENT_NOMINAL_RATE 0x00800000

This value assumes a 125MHz rtc_clock.

Referenced by XAvb_BecomeRtcMaster(), and XAvb_UpdateRtcIncrement().

#define XAVB_RTC_INCREMENT_OFFSET 0x00012810

RTC Increment Reg.

Referenced by XAvb_BecomeRtcMaster(), and XAvb_UpdateRtcIncrement().

#define XAVB_RTC_NANOSEC_OFFSET 0x00012800

RTC ns offset Reg.

Referenced by XAvb_Adjust8kClock(), XAvb_CalcRtcOffset(), XAvb_MasterSendFollowUp(), XAvb_SendPDelayResp(), and XAvb_WriteRtcOffset().

#define XAVB_RTC_NANOSEC_VALUE_OFFSET 0x00012814

RTC ns value Reg.

Referenced by XAvb_MasterSendAnnounce(), XAvb_MasterSendSync(), XAvb_ReadRtc(), and XAvb_SendPDelayResp().

#define XAVB_RTC_SEC_LOWER_OFFSET 0x00012808

RTC sec[31:0] offset.

Referenced by XAvb_WriteRtcOffset().

#define XAVB_RTC_SEC_LOWER_VALUE_OFFSET 0x00012818

RTC sec[31:0] value.

Referenced by XAvb_CalcRtcOffset(), XAvb_MasterSendAnnounce(), XAvb_MasterSendSync(), XAvb_ReadRtc(), and XAvb_SendPDelayResp().

#define XAVB_RTC_SEC_UPPER_OFFSET 0x0001280C

RTC sec[47:32] offset.

Referenced by XAvb_WriteRtcOffset().

#define XAVB_RTC_SEC_UPPER_VALUE_OFFSET 0x0001281C

RTC sec[47:32] value.

Referenced by XAvb_MasterSendSync(), XAvb_ReadRtc(), and XAvb_SendPDelayResp().

#define XAVB_RX_FILTER_CONTROL 0x00012008

Rx Filter Control Reg.

Referenced by XAvb_SetupRxFilterControlMatchMode(), XAvb_SetupRxFilterControlPcp(), and XAvb_SetupRxFilterControlVid().

#define XAVB_SW_RESET_OFFSET 0x00012828

S/W Reset Reg.

Referenced by XAvb_Reset().

#define XAVB_TX_HILIMIT 0x00012014

Tx rate hiLimit Reg.

#define XAVB_TX_IDLESLOPE 0x00012010

Tx rate idleSlope Reg.

#define XAVB_TX_LOLIMIT 0x00012018

Tx rate loLimit Reg.

#define XAVB_TX_SENDSLOPE 0x0001200C

Tx rate sendSlope Reg.

#define XAvb_WritePtpBuffer | ( |  | BaseAddress,
|  |  | PtpPacketBaseAddress,
|  |  | PtpPacketOffset,
|  |  | Data
| ) |  | Xil_Out32(BaseAddress + PtpPacketBaseAddress + PtpPacketOffset, (Data))

This macro writes to the given PTP frame buffer.

Parameters

  BaseAddress | is the base address of the device
  PtpPacketBaseAddress | is the base address of the frame in the PTP packet buffer
  PtpPacketOffset | is the offset address within the PTP frame
  Data | is the 32-bit value to write to the register

Returns
  None.

Note
  None.

Referenced by XAvb_IncSequenceId(), XAvb_MasterSendFollowUp(), XAvb_MasterSendSync(), XAvb_SendPDelayResp(), XAvb_SendPDelayRespFollowUp(), XAvb_SetupSourcePortIdentity(), XAvb_UpdateLogMeanMessageInterval(), and XAvb_WriteToMultipleTxPtpFrames().

#define XAvb_WriteReg | ( |  | BaseAddress,
|  |  | RegOffset,
|  |  | Data
| ) |  | Xil_Out32((BaseAddress) + (RegOffset), (Data))

This macro writes to the given AVB core register.

Parameters

  BaseAddress | is the base address of the device
  RegOffset | is the register offset to be written
  Data | is the 32-bit value to write to the register

Returns
  None.

Note
  None.

Referenced by XAvb_Adjust8kClock(), XAvb_BecomeRtcMaster(), XAvb_MasterSendAnnounce(), XAvb_MasterSendFollowUp(), XAvb_MasterSendSync(), XAvb_PtpTimerInterruptHandler(), XAvb_Reset(), XAvb_SendPDelayReq(), XAvb_SendPDelayResp(), XAvb_SendPDelayRespFollowUp(), XAvb_SetupRxFilterControlMatchMode(), XAvb_SetupRxFilterControlPcp(), XAvb_SetupRxFilterControlVid(), and XAvb_UpdateRtcIncrement().

#define XAvbMac_ReadConfig | ( |  | BaseAddress,
|  |  | RegOffset
| ) |  | Xil_In32((BaseAddress) + (RegOffset))

This macro reads from the given TEMAC Configuration Register.

Parameters

  BaseAddress | is the base address of the device
  RegOffset | is the register offset to be read

Returns
  The 32-bit value of the register

Note
  None.

#define XAvbMac_ReadMdio | ( |  | BaseAddress,
|  |  | Phyad,
|  |  | Regad
| ) |  |

Value:
Xil_In32((BaseAddress) + XAVB_MAC_MDIO_BASE_OFFSET \
+ (((Phyad) & 0x1F) << 8) \
+ (((Regad) & 0x1F) << 3))

This macro reads from the given MDIO Register using the TEMAC.

Parameters

  BaseAddress | is the base address of the device
  Phyad | is the Physical Address of the PHY
  Regad | is the Address of the MDIO register within the addressed PHY

Returns
  The 32-bit value of the register (upper 16-bits will be all 0's)

Note
  None.

#define XAvbMac_WriteConfig | ( |  | BaseAddress,
|  |  | RegOffset,
|  |  | Data
| ) |  | Xil_Out32((BaseAddress) + (RegOffset), (Data))

This macro writes to the given TEMAC Configuration Register.

Parameters

  BaseAddress | is the base address of the device
  RegOffset | is the register offset to be written
  Data | is the 32-bit value to write to the register

Returns
  None.

Note
  None.

#define XAvbMac_WriteMdio | ( |  | BaseAddress,
|  |  | Phyad,
|  |  | Regad,
|  |  | Data
| ) |  |

Value:
Xil_Out32(BaseAddress + XAVB_MAC_MDIO_BASE_OFFSET \
+ (((Phyad) & 0x1F) << 8) \
+ (((Regad) & 0x1F) << 3), \
(Data & XAVB_MAC_MDIO_DATA_MASK))

This macro writes to the given MDIO Register using the TEMAC.

Parameters

  BaseAddress | is the base address of the device
  Phyad | is the Physical Address of the PHY
  Regad | is the Address of the MDIO register within the addressed PHY
  Data | is the 32-bit value to write

Returns
  None.

Note
  None.

## Function Documentation

void XAvb_ReadRtc | ( | u32 | BaseAddress,
|  | XAvb_RtcFormat * | RtcValue
| ) |  |

This function reads the current Real Time Counter (RTC) value.

Parameters

  BaseAddress | is the base address of the device
  RtcValue | is a pointer to a struct in which to store the value read from the RTC (The RTC 48-bit seconds field and the 32-bit ns field of this struct are updated).

Returns
  None

Note
  This is provided as a basic function since the ns field MUST be read before the seconds/epoch registers (reading the ns samples the entire RTC in hardware).

References XAvb_RtcFormat::NanoSeconds, XAvb_RtcFormat::SecondsLower, XAvb_RtcFormat::SecondsUpper, XAVB_RTC_NANOSEC_VALUE_OFFSET, XAVB_RTC_SEC_LOWER_VALUE_OFFSET, and XAVB_RTC_SEC_UPPER_VALUE_OFFSET.

Referenced by XAvb_CalcRtcOffset(), and XAvb_SendPDelayRespFollowUp().

void XAvb_WriteRtcOffset | ( | u32 | BaseAddress,
|  | XAvb_RtcFormat * | RtcValue
| ) |  |

This function writes to the Real Time Counter (RTC) Offset Registers.

Parameters

  BaseAddress | is the base address of the device
  RtcValue | is the nanoseconds and seconds offset values that should be written to the RTC.

Returns
  None

Note
  This is provided as a basic function since the ns field MUST be written after the seconds/epoch offset registers (writing to the ns offset registers samples the entire RTC offset in hardware).

References XAvb_RtcFormat::NanoSeconds, XAvb_RtcFormat::SecondsLower, XAvb_RtcFormat::SecondsUpper, XAVB_RTC_NANOSEC_OFFSET, XAVB_RTC_SEC_LOWER_OFFSET, and XAVB_RTC_SEC_UPPER_OFFSET.

Referenced by XAvb_CalcRtcOffset().

void XAvbMac_ReadStats | ( | u32 | BaseAddress,
|  | u32 | CounterId,
|  | XAvb_Uint64 * | Value
| ) |  |

This function reads the given Ethernet Statistic Register.

Parameters

  BaseAddress | is the base address of the device
  CounterID | is the Statistic Counter to be read
  Value | a pointer to the read value of the 64-bit value of the counter and it is updated by this function

Returns
  None.

Note
  The CounterID's defined here are the same as the Statistic Counter Addresses as used with the TEMAC core. Since each counter is 8-bytes wide, we must multiply these Counter ID's by 8 (or a left shift of 3) when mapping this into the PLB memory map. The 64-bit counter value is read as two separate 32-bit accesses.

References XAvb_Uint64::Lower, and XAvb_Uint64::Upper.