dsitxss: XDsiTxSs_Config Struct Reference

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XDsiTxSs_Config Struct Reference
Dsitxss_v1_1

MIPI DSI Tx Subsystem configuration structure. More...

## Data Fields
u32 | DeviceId
| DeviceId is the unique ID of the device. More...
UINTPTR | BaseAddr
        BaseAddress is the physical
base address of the subsystem address range More...
UINTPTR | HighAddr
        HighAddress is the physical
MAX address of the subsystem address range More...
u8 | DsiLanes
| DSI supported lanes 1, 2, 3, 4. More...
u8 | DataType
| RGB type. More...
u32 | DsiByteFifo
| 128, 256, 512, 1024, 2048, 4096, 8192, 16384 More...
u8 | CrcGen
| CRC Generation enable or not. More...
u8 | DsiPixel
| Pixels per beat received on input stream. More...
u32 | DphyLinerate
| DPHY line rate. More...
u32 | IsDphyRegIntfcPresent
    Flag for DPHY register
interface presence More...
DsiTxSsSubCore | DphyInfo
| Sub-core instance configuration. More...
DsiTxSsSubCore | DsiInfo
| Sub-core instance configuration. More...

## Detailed Description

MIPI DSI Tx Subsystem configuration structure.

Each subsystem device should have a configuration structure associated that defines the MAX supported sub-cores within subsystem

## Field Documentation

UINTPTR XDsiTxSs_Config::BaseAddr

        BaseAddress is the physical

base address of the subsystem address range

Referenced by DsiTxSs_IntrExample(), DsiTxSs_SelfTestExample(), DsiTxSs_VideoTestExample(), and XDsiTxSs_CfgInitialize().

u8 XDsiTxSs_Config::CrcGen

CRC Generation enable or not.

u8 XDsiTxSs_Config::DataType

RGB type.

u32 XDsiTxSs_Config::DeviceId

DeviceId is the unique ID of the device.

DsiTxSsSubCore XDsiTxSs_Config::DphyInfo

Sub-core instance configuration.

Referenced by XDsiTxSs_ReportCoreInfo(), and XDsiTxSs_SelfTest().

u32 XDsiTxSs_Config::DphyLinerate

DPHY line rate.

u32 XDsiTxSs_Config::DsiByteFifo

128, 256, 512, 1024, 2048, 4096, 8192, 16384

DsiTxSsSubCore XDsiTxSs_Config::DsiInfo

Sub-core instance configuration.

u8 XDsiTxSs_Config::DsiLanes

DSI supported lanes 1, 2, 3, 4.

u8 XDsiTxSs_Config::DsiPixel

Pixels per beat received on input stream.

UINTPTR XDsiTxSs_Config::HighAddr

        HighAddress is the physical

MAX address of the subsystem address range

u32 XDsiTxSs_Config::IsDphyRegIntfcPresent

    Flag for DPHY register

interface presence

Referenced by XDsiTxSs_Activate(), and XDsiTxSs_Reset().