dphy: Xdphy_v1_0

| dphy Xilinx SDK Drivers API Documentation

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Xdphy_v1_0

## Macros
#define | XDPHY_HW_H_
| Prevent circular inclusions by using protection macros. More...

## Device registers
Register sets of MIPI DPHY
#define | XDPHY_CTRL_REG_OFFSET 0x00000000
| Control Register. More...
#define | XDPHY_HSEXIT_IDELAY_REG_OFFSET 0x00000004
| IDelay Tap per lane for Rx Register. More...
#define | XDPHY_INIT_REG_OFFSET 0x00000008
| Initialization Timer Register. More...
#define | XDPHY_WAKEUP_REG_OFFSET 0x0000000C
| Wakeup Timer for ULPS exit Register. More...
#define | XDPHY_HSTIMEOUT_REG_OFFSET 0x00000010
| Watchdog timeout in HS mode Register. More...
#define | XDPHY_ESCTIMEOUT_REG_OFFSET 0x00000014
| Goto Stop state on timeout timer Register. More...
#define | XDPHY_CLSTATUS_REG_OFFSET 0x00000018
| Clk lane PHY error Status Register. More...
#define | XDPHY_DL0STATUS_REG_OFFSET 0x0000001C
| Data lane 0 PHY error Status Register. More...
#define | XDPHY_DL1STATUS_REG_OFFSET 0x00000020
| Data lane 1 PHY error Status Register. More...
#define | XDPHY_DL2STATUS_REG_OFFSET 0x00000024
| Data lane 2 PHY error Status Register. More...
#define | XDPHY_DL3STATUS_REG_OFFSET 0x00000028
| Data lane 3 PHY error Status Register. More...
#define | XDPHY_HSSETTLE_REG_OFFSET 0x00000030
| HS Settle Register L0. More...
#define | XDPHY_IDELAY58_REG_OFFSET 0x00000034
| IDelay Tap per lane for Rx 4-7 Register. More...
#define | XDPHY_HSSETTLE1_REG_OFFSET 0x00000048
| HS Settle Register L1. More...
#define | XDPHY_HSSETTLE2_REG_OFFSET 0x0000004C
| HS Settle Register L2. More...
#define | XDPHY_HSSETTLE3_REG_OFFSET 0x00000050
| HS Settle Register L3. More...
#define | XDPHY_HSSETTLE4_REG_OFFSET 0x00000054
| HS Settle Register L4. More...
#define | XDPHY_HSSETTLE5_REG_OFFSET 0x00000058
| HS Settle Register L5. More...
#define | XDPHY_HSSETTLE6_REG_OFFSET 0x0000005C
| HS Settle Register L6. More...
#define | XDPHY_HSSETTLE7_REG_OFFSET 0x00000060
| HS Settle Register L7. More...
#define | XDPHY_DL4STATUS_REG_OFFSET 0x00000064
| Data lane 0 PHY error Status Register. More...
#define | XDPHY_DL5STATUS_REG_OFFSET 0x00000068
| Data lane 1 PHY error Status Register. More...
#define | XDPHY_DL6STATUS_REG_OFFSET 0x0000006C
| Data lane 2 PHY error Status Register. More...
#define | XDPHY_DL7STATUS_REG_OFFSET 0x00000070
| Data lane 3 PHY error Status Register. More...

## Bitmasks and offsets of XDPHY_CTRL_REG_OFFSET register
This register is used for the enabling/disabling and resetting the DPHY
#define | XDPHY_CTRL_REG_SOFTRESET_MASK 0x00000001
| Soft Reset. More...
#define | XDPHY_CTRL_REG_DPHYEN_MASK 0x00000002
| Enable/Disable controller. More...
#define | XDPHY_CTRL_REG_SOFTRESET_OFFSET 0
| Bit offset for Soft Reset. More...
#define | XDPHY_CTRL_REG_DPHYEN_OFFSET 1
| Bit offset for DPHY Enable. More...

## Bitmasks and offsets of XDPHY_HSEXIT_IDELAY_REG_OFFSET register
This register in RX mode acts like IDELAY. In IDELAY mode, it is used to calibrate input delay per lane
#define | XDPHY_HSEXIT_IDELAY_REG_TAP_MASK 0x1F1F1F1F
| used to set the IDELAY TAP value for all lanes More...

## Bitmasks and offsets of XDPHY_INIT_REG_OFFSET register
This register is used for lane Initialization. Recommended to use 1ms or longer in for TX mode and 200us-500us for RX mode
#define | XDPHY_INIT_REG_VAL_MASK 0xFFFFFFFF
| Init Timer value in ns. More...
#define | XDPHY_INIT_REG_VAL_OFFSET 0
| Bit offset for Init Timer. More...

## Bitmask and offset of XDPHY_WAKEUP_REG_OFFSET register
Wakeup time delay for ULPS exit.
#define | XDPHY_WAKEUP_REG_VAL_MASK 0xFFFFFFFF
| Wakeup timer value. More...
#define | XDPHY_WAKEUP_REG_VAL_OFFSET 0
| Bit offset for Wakeup value. More...

## Bitmask and offset of XDPHY_HSTIMEOUT_REG_OFFSET register
This register is used to program watchdog timer in high speed mode. Default value is 65541. Valid range 1000-65541.
#define | XDPHY_HSTIMEOUT_REG_TIMEOUT_MASK 0xFFFFFFFF
| HS_T/RX_TIMEOUT Received. More...
#define | XDPHY_HSTIMEOUT_REG_TIMEOUT_OFFSET 0
| Bit offset for Timeout. More...

## Bitmask and offset of XDPHY_ESCTIMEOUT_REG_OFFSET register
This register contains Rx Data Lanes timeout for watchdog timer in escape mode.
#define | XDPHY_ESCTIMEOUT_REG_VAL_MASK 0xFFFFFFFF
| Escape Timout Value. More...
#define | XDPHY_ESCTIMEOUT_REG_VAL_OFFSET 0
| Bit offset for Escape Timeout. More...

## Bitmask and offset of XDPHY_CLSTATUS_REG_OFFSET register
This register contains the clock lane status and state machine control.
#define | XDPHY_CLSTATUS_REG_ERRCTRL_MASK 0x00000020
| Clock lane control error. More...
#define | XDPHY_CLSTATUS_REG_STOPSTATE_MASK 0x00000010
| Clock lane stop state. More...
#define | XDPHY_CLSTATUS_REG_INITDONE_MASK 0x00000008
| Initialization done bit. More...
#define | XDPHY_CLSTATUS_REG_ULPS_MASK 0x00000004
| Set in ULPS mode. More...
#define | XDPHY_CLSTATUS_REG_MODE_MASK 0x00000003
| Low, High, Esc mode. More...
#define | XDPHY_CLSTATUS_ALLMASK
#define | XDPHY_CLSTATUS_REG_ERRCTRL_OFFSET 5
| Bit offset for Control Error on Clock. More...
#define | XDPHY_CLSTATUS_REG_STOPSTATE_OFFSET 4
| Bit offset for Stop State on Clock. More...
#define | XDPHY_CLSTATUS_REG_INITDONE_OFFSET 3
| Bit offset for Initialization Done. More...
#define | XDPHY_CLSTATUS_REG_ULPS_OFFSET 2
| Bit offset for ULPS. More...
#define | XDPHY_CLSTATUS_REG_MODE_OFFSET 0
| Bit offset for Mode bits. More...

## Bitmasks and offsets of XDPHY_DLxSTATUS_REG_OFFSET register
This register contains the data lanes status
#define | XDPHY_DLXSTATUS_REG_PACKETCOUNT_MASK 0xFFFF0000
| Packet Count. More...
#define | XDPHY_DLXSTATUS_REG_CALIB_STATUS_MASK 0x00000100
| Calib status. More...
#define | XDPHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK 0x00000080
| Calib complete. More...
#define | XDPHY_DLXSTATUS_REG_STOP_MASK 0x00000040
| Stop State on data lane. More...
#define | XDPHY_DLXSTATUS_REG_ESCABRT_MASK 0x00000020
| Set on Data Lane Esc timeout occurs. More...
#define | XDPHY_DLXSTATUS_REG_HSABRT_MASK 0x00000010
| Set on Data Lane HS timeout. More...
#define | XDPHY_DLXSTATUS_REG_INITDONE_MASK 0x00000008
| Set after initialization. More...
#define | XDPHY_DLXSTATUS_REG_ULPS_MASK 0x00000004
| Set when DPHY in ULPS mode. More...
#define | XDPHY_DLXSTATUS_REG_MODE_MASK 0x00000003
| Control Mode (Esc, Low, High) of Data Lane. More...
#define | XDPHY_DLXSTATUS_ALLMASK
#define | XDPHY_DLXSTATUS_REG_PACKCOUNT_OFFSET 16
| Bit offset packet count. More...
#define | XDPHY_DLXSTATUS_REG_CALIB_STATUS_OFFSET 8
| Bit offset calib status. More...
#define | XDPHY_DLXSTATUS_REG_CALIB_COMPLETE_OFFSET 7
| Bit offset Calib complete. More...
#define | XDPHY_DLXSTATUS_REG_STOP_OFFSET 6
| Bit offset for Stop State. More...
#define | XDPHY_DLXSTATUS_REG_ESCABRT_OFFSET 5
| Bit offset for Escape Abort. More...
#define | XDPHY_DLXSTATUS_REG_HSABRT_OFFSET 4
| Bit offset for High Speed Abort. More...
#define | XDPHY_DLXSTATUS_REG_INITDONE_OFFSET 3
| Bit offset for Initialization done. More...
#define | XDPHY_DLXSTATUS_REG_ULPS_OFFSET 2
| Bit offset for ULPS. More...
#define | XDPHY_DLXSTATUS_REG_MODE_OFFSET 0
| Bit offset for Modes. More...

## Bitmask and offset of XDPHY_HSSETTLE_REG_OFFSET register
This register is used to program the HS SETTLE register. Default value is 135 + 10UI.
#define | XDPHY_HSSETTLE_REG_TIMEOUT_MASK 0x1FF
| HS_SETTLE value. More...
#define | XDPHY_HSSETTLE_REG_TIMEOUT_OFFSET 0
| Bit offset for HS_SETTLE. More...

## Macro Definition Documentation

#define XDPHY_CLSTATUS_REG_ERRCTRL_MASK 0x00000020

Clock lane control error.

Only for RX

#define XDPHY_CLSTATUS_REG_ERRCTRL_OFFSET 5

Bit offset for Control Error on Clock.

#define XDPHY_CLSTATUS_REG_INITDONE_MASK 0x00000008

Initialization done bit.

#define XDPHY_CLSTATUS_REG_INITDONE_OFFSET 3

Bit offset for Initialization Done.

#define XDPHY_CLSTATUS_REG_MODE_MASK 0x00000003

Low, High, Esc mode.

Referenced by XDphy_GetClkLaneMode().

#define XDPHY_CLSTATUS_REG_MODE_OFFSET 0

Bit offset for Mode bits.

#define XDPHY_CLSTATUS_REG_OFFSET 0x00000018

Clk lane PHY error Status Register.

Referenced by XDphy_GetClkLaneStatus(), and XDphy_GetInfo().

#define XDPHY_CLSTATUS_REG_STOPSTATE_MASK 0x00000010

Clock lane stop state.

#define XDPHY_CLSTATUS_REG_STOPSTATE_OFFSET 4

Bit offset for Stop State on Clock.

#define XDPHY_CLSTATUS_REG_ULPS_MASK 0x00000004

Set in ULPS mode.

#define XDPHY_CLSTATUS_REG_ULPS_OFFSET 2

Bit offset for ULPS.

#define XDPHY_CTRL_REG_DPHYEN_MASK 0x00000002

Enable/Disable controller.

Referenced by XDphy_Activate().

#define XDPHY_CTRL_REG_DPHYEN_OFFSET 1

Bit offset for DPHY Enable.

#define XDPHY_CTRL_REG_OFFSET 0x00000000

Control Register.

Referenced by XDphy_Activate(), and XDphy_Reset().

#define XDPHY_CTRL_REG_SOFTRESET_MASK 0x00000001

Soft Reset.

Referenced by XDphy_Reset().

#define XDPHY_CTRL_REG_SOFTRESET_OFFSET 0

Bit offset for Soft Reset.

#define XDPHY_DL0STATUS_REG_OFFSET 0x0000001C

Data lane 0 PHY error Status Register.

Referenced by XDphy_ClearDataLane(), XDphy_GetDataLaneStatus(), XDphy_GetDLCalibStatus(), XDphy_GetInfo(), and XDphy_GetPacketCount().

#define XDPHY_DL1STATUS_REG_OFFSET 0x00000020

Data lane 1 PHY error Status Register.

Referenced by XDphy_GetInfo().

#define XDPHY_DL2STATUS_REG_OFFSET 0x00000024

Data lane 2 PHY error Status Register.

Referenced by XDphy_GetInfo().

#define XDPHY_DL3STATUS_REG_OFFSET 0x00000028

Data lane 3 PHY error Status Register.

Referenced by XDphy_GetInfo().

#define XDPHY_DL4STATUS_REG_OFFSET 0x00000064

Data lane 0 PHY error Status Register.

Referenced by XDphy_GetInfo().

#define XDPHY_DL5STATUS_REG_OFFSET 0x00000068

Data lane 1 PHY error Status Register.

Referenced by XDphy_GetInfo().

#define XDPHY_DL6STATUS_REG_OFFSET 0x0000006C

Data lane 2 PHY error Status Register.

Referenced by XDphy_GetInfo().

#define XDPHY_DL7STATUS_REG_OFFSET 0x00000070

Data lane 3 PHY error Status Register.

Referenced by XDphy_GetInfo().

#define XDPHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK 0x00000080

Calib complete.

Referenced by XDphy_GetDLCalibStatus().

#define XDPHY_DLXSTATUS_REG_CALIB_COMPLETE_OFFSET 7

Bit offset Calib complete.

#define XDPHY_DLXSTATUS_REG_CALIB_STATUS_MASK 0x00000100

Calib status.

Referenced by XDphy_GetDLCalibStatus().

#define XDPHY_DLXSTATUS_REG_CALIB_STATUS_OFFSET 8

Bit offset calib status.

#define XDPHY_DLXSTATUS_REG_ESCABRT_MASK 0x00000020

Set on Data Lane Esc timeout occurs.

Referenced by XDphy_ClearDataLane().

#define XDPHY_DLXSTATUS_REG_ESCABRT_OFFSET 5

Bit offset for Escape Abort.

#define XDPHY_DLXSTATUS_REG_HSABRT_MASK 0x00000010

Set on Data Lane HS timeout.

Referenced by XDphy_ClearDataLane().

#define XDPHY_DLXSTATUS_REG_HSABRT_OFFSET 4

Bit offset for High Speed Abort.

#define XDPHY_DLXSTATUS_REG_INITDONE_MASK 0x00000008

Set after initialization.

#define XDPHY_DLXSTATUS_REG_INITDONE_OFFSET 3

Bit offset for Initialization done.

#define XDPHY_DLXSTATUS_REG_MODE_MASK 0x00000003

Control Mode (Esc, Low, High) of Data Lane.

Referenced by XDphy_GetDataLaneMode().

#define XDPHY_DLXSTATUS_REG_MODE_OFFSET 0

Bit offset for Modes.

#define XDPHY_DLXSTATUS_REG_PACKCOUNT_OFFSET 16

Bit offset packet count.

Referenced by XDphy_GetPacketCount().

#define XDPHY_DLXSTATUS_REG_PACKETCOUNT_MASK 0xFFFF0000

Packet Count.

Referenced by XDphy_GetPacketCount().

#define XDPHY_DLXSTATUS_REG_STOP_MASK 0x00000040

Stop State on data lane.

#define XDPHY_DLXSTATUS_REG_STOP_OFFSET 6

Bit offset for Stop State.

#define XDPHY_DLXSTATUS_REG_ULPS_MASK 0x00000004

Set when DPHY in ULPS mode.

#define XDPHY_DLXSTATUS_REG_ULPS_OFFSET 2

Bit offset for ULPS.

#define XDPHY_ESCTIMEOUT_REG_OFFSET 0x00000014

Goto Stop state on timeout timer Register.

Referenced by XDphy_Configure(), and XDphy_GetInfo().

#define XDPHY_ESCTIMEOUT_REG_VAL_MASK 0xFFFFFFFF

Escape Timout Value.

#define XDPHY_ESCTIMEOUT_REG_VAL_OFFSET 0

Bit offset for Escape Timeout.

#define XDPHY_HSEXIT_IDELAY_REG_OFFSET 0x00000004

IDelay Tap per lane for Rx Register.

Referenced by XDphy_Configure(), and XDphy_GetInfo().

#define XDPHY_HSEXIT_IDELAY_REG_TAP_MASK 0x1F1F1F1F

used to set the IDELAY TAP value for all lanes

Referenced by XDphy_Configure().

#define XDPHY_HSSETTLE1_REG_OFFSET 0x00000048

HS Settle Register L1.

Referenced by XDphy_Configure(), and XDphy_GetInfo().

#define XDPHY_HSSETTLE2_REG_OFFSET 0x0000004C

HS Settle Register L2.

Referenced by XDphy_Configure(), and XDphy_GetInfo().

#define XDPHY_HSSETTLE3_REG_OFFSET 0x00000050

HS Settle Register L3.

Referenced by XDphy_Configure(), and XDphy_GetInfo().

#define XDPHY_HSSETTLE4_REG_OFFSET 0x00000054

HS Settle Register L4.

Referenced by XDphy_Configure(), and XDphy_GetInfo().

#define XDPHY_HSSETTLE5_REG_OFFSET 0x00000058

HS Settle Register L5.

Referenced by XDphy_Configure(), and XDphy_GetInfo().

#define XDPHY_HSSETTLE6_REG_OFFSET 0x0000005C

HS Settle Register L6.

Referenced by XDphy_Configure(), and XDphy_GetInfo().

#define XDPHY_HSSETTLE7_REG_OFFSET 0x00000060

HS Settle Register L7.

Referenced by XDphy_Configure(), and XDphy_GetInfo().

#define XDPHY_HSSETTLE_REG_OFFSET 0x00000030

HS Settle Register L0.

Referenced by XDphy_Configure(), and XDphy_GetInfo().

#define XDPHY_HSSETTLE_REG_TIMEOUT_MASK 0x1FF

HS_SETTLE value.

#define XDPHY_HSSETTLE_REG_TIMEOUT_OFFSET 0

Bit offset for HS_SETTLE.

#define XDPHY_HSTIMEOUT_REG_OFFSET 0x00000010

Watchdog timeout in HS mode Register.

Referenced by XDphy_Configure(), and XDphy_GetInfo().

#define XDPHY_HSTIMEOUT_REG_TIMEOUT_MASK 0xFFFFFFFF

HS_T/RX_TIMEOUT Received.

#define XDPHY_HSTIMEOUT_REG_TIMEOUT_OFFSET 0

Bit offset for Timeout.

#define XDPHY_HW_H_

Prevent circular inclusions by using protection macros.

#define XDPHY_IDELAY58_REG_OFFSET 0x00000034

IDelay Tap per lane for Rx 4-7 Register.

Referenced by XDphy_Configure().

#define XDPHY_INIT_REG_OFFSET 0x00000008

Initialization Timer Register.

Referenced by XDphy_Configure(), and XDphy_GetInfo().

#define XDPHY_INIT_REG_VAL_MASK 0xFFFFFFFF

Init Timer value in ns.

#define XDPHY_INIT_REG_VAL_OFFSET 0

Bit offset for Init Timer.

#define XDPHY_WAKEUP_REG_OFFSET 0x0000000C

Wakeup Timer for ULPS exit Register.

Referenced by XDphy_Configure(), and XDphy_GetInfo().

#define XDPHY_WAKEUP_REG_VAL_MASK 0xFFFFFFFF

Wakeup timer value.

#define XDPHY_WAKEUP_REG_VAL_OFFSET 0

Bit offset for Wakeup value.