sysmon: Sysmon_v7_5

| sysmon Xilinx SDK Drivers API Documentation

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Data Structures | Macros | Functions | Variables
Sysmon_v7_5

## Data Structures
struct | XSysMon_Config
| This typedef contains configuration information for the System Monitor/ADC device. More...
struct | XSysMon
| The driver's instance data. More...

## Macros
#define | XSysMon_IsEventSamplingModeSet(InstancePtr)
| This macro checks if the SysMonitor/ADC device is in Event Sampling mode. More...
#define | XSysMon_IsDrpBusy(InstancePtr)
| This macro checks if the Dynamic Reconfiguration Port (DRP) transaction from the JTAG is in progress. More...
#define | XSysMon_IsDrpLocked(InstancePtr)
| This macro checks if the Dynamic Reconfiguration Port (DRP) is locked by the JTAG. More...
#define | XSysMon_RawToTemperature(AdcData) ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
| This macro converts System Monitor/ADC Raw Data to Temperature(centigrades). More...
#define | XSysMon_RawToVoltage(AdcData) ((((float)(AdcData))* (3.0f))/65536.0f)
| This macro converts System Monitor/ADC Raw Data to Voltage(volts). More...
#define | XSysMon_TemperatureToRaw(Temperature) ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
| This macro converts Temperature in centigrades to System Monitor/ADC Raw Data. More...
#define | XSysMon_VoltageToRaw(Voltage) ((int)((Voltage)*65536.0f/3.0f))
| This macro converts Voltage in Volts to System Monitor/ADC Raw Data. More...
#define | XSysMon_ReadReg(BaseAddress, RegOffset) (Xil_In32((BaseAddress) + (RegOffset)))
| Read a register of the System Monitor/ADC device. More...
#define | XSysMon_WriteReg(BaseAddress, RegOffset, Data) (Xil_Out32((BaseAddress) + (RegOffset), (Data)))
| Write a register of the System Monitor/ADC device. More...

## Functions
int | XSysMon_CfgInitialize (XSysMon *InstancePtr, XSysMon_Config *ConfigPtr, UINTPTR EffectiveAddr)
| This function initializes a specific XSysMon device/instance. More...
void | XSysMon_Reset (XSysMon *InstancePtr)
| This function forces the software reset of the complete SystemMonitor/ADC Hard Macro and the SYSMON ADC Core Logic. More...
u32 | XSysMon_GetStatus (XSysMon *InstancePtr)
| The functions reads the contents of the Status Register. More...
u32 | XSysMon_GetAlarmOutputStatus (XSysMon *InstancePtr)
| This function reads the contents of Alarm Output Register. More...
void | XSysMon_StartAdcConversion (XSysMon *InstancePtr)
| This function starts the ADC conversion in the Single Channel event driven sampling mode. More...
void | XSysMon_ResetAdc (XSysMon *InstancePtr)
| This function resets the SystemMonitor/ADC Hard Macro in the device. More...
u16 | XSysMon_GetAdcData (XSysMon *InstancePtr, u8 Channel)
| Get the ADC converted data for the specified channel. More...
u16 | XSysMon_GetCalibCoefficient (XSysMon *InstancePtr, u8 CoeffType)
| This function gets the calibration coefficient data for the specified parameter. More...
u16 | XSysMon_GetMinMaxMeasurement (XSysMon *InstancePtr, u8 MeasurementType)
| This function reads the Minimum/Maximum measurement for one of the following parameters : More...
void | XSysMon_SetAvg (XSysMon *InstancePtr, u8 Average)
| This function sets the number of samples of averaging that is to be done for all the channels in both the single channel mode and sequence mode of operations. More...
u8 | XSysMon_GetAvg (XSysMon *InstancePtr)
| This function returns the number of samples of averaging configured for all the channels in the Configuration Register 0. More...
int | XSysMon_SetSingleChParams (XSysMon *InstancePtr, u8 Channel, int IncreaseAcqCycles, int IsEventMode, int IsDifferentialMode)
| The function sets the given parameters in the Configuration Register 0 in the single channel mode. More...
void | XSysMon_SetAlarmEnables (XSysMon *InstancePtr, u32 AlmEnableMask)
| This function enables the alarm outputs for the specified alarms in the Configuration Registers 1 and 3: More...
u32 | XSysMon_GetAlarmEnables (XSysMon *InstancePtr)
| This function gets the status of the alarm output enables in the Configuration Register 1. More...
void | XSysMon_SetCalibEnables (XSysMon *InstancePtr, u16 Calibration)
| This function enables the specified calibration in the Configuration Register 1 : More...
u16 | XSysMon_GetCalibEnables (XSysMon *InstancePtr)
| This function reads the value of the calibration enables from the Configuration Register 1. More...
void | XSysMon_SetSequencerMode (XSysMon *InstancePtr, u8 SequencerMode)
| This function sets the specified Channel Sequencer Mode in the Configuration Register 1 : More...
u8 | XSysMon_GetSequencerMode (XSysMon *InstancePtr)
| This function gets the channel sequencer mode from the Configuration Register 1. More...
void | XSysMon_SetSequencerEvent (XSysMon *InstancePtr, int IsEventMode)
| The function enables the Event mode or Continuous mode in the sequencer mode. More...
void | XSysMon_SetExtenalMux (XSysMon *InstancePtr, u8 Channel)
| The function enables the external mux and connects a channel to the mux. More...
void | XSysMon_SetAdcClkDivisor (XSysMon *InstancePtr, u8 Divisor)
| The function sets the frequency of the ADCCLK by configuring the DCLK to ADCCLK ratio in the Configuration Register #2. More...
u8 | XSysMon_GetAdcClkDivisor (XSysMon *InstancePtr)
| The function gets the ADCCLK divisor from the Configuration Register 2. More...
int | XSysMon_SetSeqChEnables (XSysMon *InstancePtr, u64 ChEnableMask)
| This function enables the specified channels in the ADC Channel Selection Sequencer Registers. More...
u64 | XSysMon_GetSeqChEnables (XSysMon *InstancePtr)
| This function gets the channel enable bits status from the ADC Channel Selection Sequencer Registers. More...
int | XSysMon_SetSeqAvgEnables (XSysMon *InstancePtr, u64 AvgEnableChMask)
| This function enables the averaging for the specified channels in the ADC Channel Averaging Enable Sequencer Registers. More...
u64 | XSysMon_GetSeqAvgEnables (XSysMon *InstancePtr)
| This function returns the channels for which the averaging has been enabled in the ADC Channel Averaging Enables Sequencer Registers. More...
int | XSysMon_SetSeqInputMode (XSysMon *InstancePtr, u32 InputModeChMask)
| This function sets the Analog input mode for the specified channels in the ADC Channel Analog-Input Mode Sequencer Registers. More...
u32 | XSysMon_GetSeqInputMode (XSysMon *InstancePtr)
| This function gets the Analog input mode for all the channels from the ADC Channel Analog-Input Mode Sequencer Registers. More...
int | XSysMon_SetSeqAcqTime (XSysMon *InstancePtr, u32 AcqCyclesChMask)
| This function sets the number of Acquisition cycles in the ADC Channel Acquisition Time Sequencer Registers. More...
u32 | XSysMon_GetSeqAcqTime (XSysMon *InstancePtr)
| This function gets the status of acquisition from the ADC Channel Acquisition Time Sequencer Registers. More...
void | XSysMon_SetAlarmThreshold (XSysMon *InstancePtr, u8 AlarmThrReg, u16 Value)
| This functions sets the contents of the given Alarm Threshold Register. More...
u16 | XSysMon_GetAlarmThreshold (XSysMon *InstancePtr, u8 AlarmThrReg)
| This function returns the contents of the specified Alarm Threshold Register. More...
void | XSysMon_SetOverTemp (XSysMon *InstancePtr, u16 Value)
| This function sets the powerdown temperature for the OverTemp signal in the OT Powerdown register. More...
u16 | XSysMon_GetOverTemp (XSysMon *InstancePtr)
| This function returns the powerdown temperature of the OverTemp signal in the OT Powerdown register. More...
void | XSysMon_EnableUserOverTemp (XSysMon *InstancePtr)
| This function enables programming of the powerdown temperature for the OverTemp signal in the OT Powerdown register. More...
void | XSysMon_DisableUserOverTemp (XSysMon *InstancePtr)
| This function disables programming of the powerdown temperature for the OverTemp signal in the OT Powerdown register. More...
void | XSysMon_EnableTempUpdate (XSysMon *InstancePtr)
| This function enables the Temperature updation logic so that temperature can be sent over TEMP_OUT port. More...
void | XSysMon_DisableTempUpdate (XSysMon *InstancePtr)
| This function disables the Temperature updation logic for TEMP_OUT port. More...
void | XSysMon_SetTempWaitCycles (XSysMon *InstancePtr, u16 WaitCycles)
| This function sets the number of Wait Cycles for Temperature updation logic. More...
XSysMon_Config * | XSysMon_LookupConfig (u16 DeviceId)
| Functions in xsysmon_sinit.c. More...
int | XSysMon_SelfTest (XSysMon *InstancePtr)
| Functions in xsysmon_selftest.c. More...
void | XSysMon_IntrGlobalEnable (XSysMon *InstancePtr)
| Functions in xsysmon_intr.c. More...
void | XSysMon_IntrGlobalDisable (XSysMon *InstancePtr)
| This function disables the global interrupt in the Global Interrupt Enable Register (GIER) so that the interrupt output from the System Monitor/ADC device is disabled. More...
void | XSysMon_IntrEnable (XSysMon *InstancePtr, u32 Mask)
| This function enables the specified interrupts in the device. More...
void | XSysMon_IntrDisable (XSysMon *InstancePtr, u32 Mask)
| This function disables the specified interrupts in the device. More...
u32 | XSysMon_IntrGetEnabled (XSysMon *InstancePtr)
| This function returns the enabled interrupts read from the Interrupt Enable Register (IPIER). More...
u32 | XSysMon_IntrGetStatus (XSysMon *InstancePtr)
| This function returns the interrupt status read from Interrupt Status Register(IPISR). More...
void | XSysMon_IntrClear (XSysMon *InstancePtr, u32 Mask)
| This function clears the specified interrupts in the Interrupt Status Register (IPISR). More...

## Variables
XSysMon_Config | XSysMon_ConfigTable [XPAR_XSYSMON_NUM_INSTANCES]
| This table contains configuration information for each System Monitor/ADC device in the system. More...
XSysMon_Config | XSysMon_ConfigTable []
| This table contains configuration information for each System Monitor/ADC device in the system. More...

## Indexes for the different channels.
#define | XSM_CH_TEMP 0x0
| On Chip Temperature. More...
#define | XSM_CH_VCCINT 0x1
| VCCINT. More...
#define | XSM_CH_VCCAUX 0x2
| VCCAUX. More...
#define | XSM_CH_VPVN 0x3
| VP/VN Dedicated analog inputs. More...
#define | XSM_CH_VREFP 0x4
| VREFP. More...
#define | XSM_CH_VREFN 0x5
| VREFN. More...
#define | XSM_CH_VBRAM 0x6
| VBRAM - 7 Series and Zynq. More...
#define | XSM_CH_SUPPLY_CALIB 0x07
| Supply Calib Data Reg. More...
#define | XSM_CH_ADC_CALIB 0x08
| ADC Offset Channel Reg. More...
#define | XSM_CH_GAINERR_CALIB 0x09
| Gain Error Channel Reg. More...
#define | XSM_CH_VCCPINT 0x0D
| On-chip PS VCCPINT Channel, Zynq. More...
#define | XSM_CH_VCCPAUX 0x0E
| On-chip PS VCCPAUX Channel, Zynq. More...
#define | XSM_CH_VCCPDRO 0x0F
| On-chip PS VCCPDRO Channel, Zynq. More...
#define | XSM_CH_AUX_MIN 16
| Channel number for 1st Aux Channel. More...
#define | XSM_CH_AUX_MAX 31
| Channel number for Last Aux channel. More...
#define | XSM_CH_VUSR0 32
| VUSER0 Supply - UltraScale. More...
#define | XSM_CH_VUSR1 33
| VUSER1 Supply - UltraScale. More...
#define | XSM_CH_VUSR2 34
| VUSER2 Supply - UltraScale. More...
#define | XSM_CH_VUSR3 35
| VUSER3 Supply - UltraScale. More...

## Indexes for reading the Calibration Coefficient Data.
#define | XSM_CALIB_SUPPLY_OFFSET_COEFF 0
| Supply Offset Calib Coefficient. More...
#define | XSM_CALIB_ADC_OFFSET_COEFF 1
| ADC Offset Calib Coefficient. More...
#define | XSM_CALIB_GAIN_ERROR_COEFF 2
| Gain Error Calib Coefficient. More...

## Indexes for reading the Minimum/Maximum Measurement Data.
#define | XSM_MAX_TEMP 0
| Maximum Temperature Data. More...
#define | XSM_MAX_VCCINT 1
| Maximum VCCINT Data. More...
#define | XSM_MAX_VCCAUX 2
| Maximum VCCAUX Data. More...
#define | XSM_MAX_VCCBRAM 3
| Maximum VCCBRAM Data, 7 Series/Zynq. More...
#define | XSM_MIN_TEMP 4
| Minimum Temperature Data. More...
#define | XSM_MIN_VCCINT 5
| Minimum VCCINT Data. More...
#define | XSM_MIN_VCCAUX 6
| Minimum VCCAUX Data. More...
#define | XSM_MIN_VCCBRAM 7
| Minimum VCCBRAM Data, 7 Series/Zynq. More...
#define | XSM_MAX_VCCPINT 8
| Maximum VCCPINT Data, Zynq. More...
#define | XSM_MAX_VCCPAUX 9
| Maximum VCCPAUX Data, Zynq. More...
#define | XSM_MAX_VCCPDRO 0xA
| Maximum VCCPDRO Data, Zynq. More...
#define | XSM_MIN_VCCPINT 0xC
| Minimum VCCPINT Data, Zynq. More...
#define | XSM_MIN_VCCPAUX 0xD
| Minimum VCCPAUX Data, Zynq. More...
#define | XSM_MIN_VCCPDRO 0xE
| Minimum VCCPDRO Data, Zynq. More...
#define | XSM_MAX_VUSR0 0x80
| Maximum VUSR0 Data, Ultrascale. More...
#define | XSM_MAX_VUSR1 0x81
| Maximum VUSR1 Data, Ultrascale. More...
#define | XSM_MAX_VUSR2 0x82
| Maximum VUSR2 Data, Ultrascale. More...
#define | XSM_MAX_VUSR3 0x83
| Maximum VUSR3 Data, Ultrascale. More...
#define | XSM_MIN_VUSR0 0x88
| Minimum VUSR0 Data, Ultrascale. More...
#define | XSM_MIN_VUSR1 0x89
| Minimum VUSR1 Data, Ultrascale. More...
#define | XSM_MIN_VUSR2 0x8A
| Minimum VUSR2 Data, Ultrascale. More...
#define | XSM_MIN_VUSR3 0x8B
| Minimum VUSR3 Data, Ultrascale. More...

## Alarm Threshold(Limit) Register (ATR) indexes.
#define | XSM_ATR_TEMP_UPPER 0
| High user Temperature. More...
#define | XSM_ATR_VCCINT_UPPER 1
| VCCINT high voltage limit. More...
#define | XSM_ATR_VCCAUX_UPPER 2
| VCCAUX high voltage limit. More...
#define | XSM_ATR_OT_UPPER 3
| Lower Over Temperature limit. More...
#define | XSM_ATR_TEMP_LOWER 4
| Low user Temperature. More...
#define | XSM_ATR_VCCINT_LOWER 5
| VCCINT low voltage limit. More...
#define | XSM_ATR_VCCAUX_LOWER 6
| VCCAUX low voltage limit. More...
#define | XSM_ATR_OT_LOWER 7
| Lower Over Temperature limit. More...
#define | XSM_ATR_VBRAM_UPPER 8
| VBRAM high voltage limit. More...
#define | XSM_ATR_VCCPINT_UPPER 9
| VCCPINT Upper Alarm, Zynq. More...
#define | XSM_ATR_VCCPAUX_UPPER 0xA
| VCCPAUX Upper Alarm, Zynq. More...
#define | XSM_ATR_VCCPDRO_UPPER 0xB
| VCCPDRO Upper Alarm, Zynq. More...
#define | XSM_ATR_VBRAM_LOWER 0xC
| VRBAM Lower Alarm, 7 Series and Zynq. More...
#define | XSM_ATR_VCCPINT_LOWER 0xD
| VCCPINT Lower Alarm, Zynq. More...
#define | XSM_ATR_VCCPAUX_LOWER 0xE
| VCCPAUX Lower Alarm, Zynq. More...
#define | XSM_ATR_VCCPDRO_LOWER 0xF
| VCCPDRO Lower Alarm, Zynq. More...
#define | XSM_ATR_VUSR0_UPPER 0x10
| VUSER0 Upper Alarm, Ultrascale. More...
#define | XSM_ATR_VUSR1_UPPER 0x11
| VUSER1 Upper Alarm, Ultrascale. More...
#define | XSM_ATR_VUSR2_UPPER 0x12
| VUSER2 Upper Alarm, Ultrascale. More...
#define | XSM_ATR_VUSR3_UPPER 0x13
| VUSER3 Upper Alarm, Ultrascale. More...
#define | XSM_ATR_VUSR0_LOWER 0x18
| VUSER0 Lower Alarm, Ultrascale. More...
#define | XSM_ATR_VUSR1_LOWER 0x19
| VUSER1 Lower Alarm, Ultrascale. More...
#define | XSM_ATR_VUSR2_LOWER 0x1A
| VUSER2 Lower Alarm, Ultrascale. More...
#define | XSM_ATR_VUSR3_LOWER 0x1B
| VUSER3 Lower Alarm, Ultrascale. More...

## Averaging to be done for the channels.
#define | XSM_AVG_0_SAMPLES 0
| No Averaging. More...
#define | XSM_AVG_16_SAMPLES 1
| Average 16 samples. More...
#define | XSM_AVG_64_SAMPLES 2
| Average 64 samples. More...
#define | XSM_AVG_256_SAMPLES 3
| Average 256 samples. More...

## Channel Sequencer Modes of operation.
#define | XSM_SEQ_MODE_SAFE 0
| Default Safe Mode. More...
#define | XSM_SEQ_MODE_ONEPASS 1
| Onepass through Sequencer. More...
#define | XSM_SEQ_MODE_CONTINPASS 2
| Continuous Cycling Seqquencer. More...
#define | XSM_SEQ_MODE_SINGCHAN 3
| Single channel - No Sequencing. More...
#define | XSM_SEQ_MODE_SIMUL 4
| Simultaneous Cycling Sequencer, 7 Series and Zynq XADC only. More...
#define | XSM_SEQ_MODE_INDEPENDENT 8
| Independent ADC Sequencer, 7 Series and Zynq XADC only. More...

## Register offsets
The following constants provide access to each of the registers of the System Monitor/ADC device.
#define | XSM_SRR_OFFSET 0x00
| Software Reset Register. More...
#define | XSM_SR_OFFSET 0x04
| Status Register. More...
#define | XSM_AOR_OFFSET 0x08
| Alarm Output Register. More...
#define | XSM_CONVST_OFFSET 0x0C
| ADC Convert Start Register. More...
#define | XSM_ARR_OFFSET 0x10
| ADC Reset Register. More...
#define | XSM_GIER_OFFSET 0x5C
| Global Interrupt Enable. More...
#define | XSM_IPISR_OFFSET 0x60
| Interrupt Status Register. More...
#define | XSM_IPIER_OFFSET 0x68
| Interrupt Enable register. More...
#define | XSM_TEMP_OFFSET (XSM_IP_OFFSET + 0x200)
| On-chip Temperature Reg. More...
#define | XSM_VCCINT_OFFSET (XSM_IP_OFFSET + 0x204)
| On-chip VCCINT Data Reg. More...
#define | XSM_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x208)
| On-chip VCCAUX Data Reg. More...
#define | XSM_VPVN_OFFSET (XSM_IP_OFFSET + 0x20C)
| ADC out of VP/VN. More...
#define | XSM_VREFP_OFFSET (XSM_IP_OFFSET + 0x210)
| On-chip VREFP Data Reg. More...
#define | XSM_VREFN_OFFSET (XSM_IP_OFFSET + 0x214)
| On-chip VREFN Data Reg. More...
#define | XSM_VBRAM_OFFSET (XSM_IP_OFFSET + 0x218)
| On-chip VBRAM Data,7-series/Zynq. More...
#define | XSM_SUPPLY_CALIB_OFFSET (XSM_IP_OFFSET + 0x220)
| Supply Offset Data Reg. More...
#define | XSM_ADC_CALIB_OFFSET (XSM_IP_OFFSET + 0x224)
| ADC Offset Data Reg. More...
#define | XSM_GAINERR_CALIB_OFFSET (XSM_IP_OFFSET + 0x228)
| Gain Error Data Reg. More...
#define | XSM_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x22C)
| PS VCCPINT Data Reg - Zynq. More...
#define | XSM_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x230)
| PS VCCPAUX Data Reg - Zynq. More...
#define | XSM_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x234)
| PS VCCPDRO Data Reg - Zynq. More...
#define | XSM_VUSR0_OFFSET (XSM_IP_OFFSET + 0x400)
| VUSER0 Supply - Ultrascale. More...
#define | XSM_VUSR1_OFFSET (XSM_IP_OFFSET + 0x404)
| VUSER0 Supply - Ultrascale. More...
#define | XSM_VUSR2_OFFSET (XSM_IP_OFFSET + 0x408)
| VUSER0 Supply - Ultrascale. More...
#define | XSM_VUSR3_OFFSET (XSM_IP_OFFSET + 0x40C)
| VUSER0 Supply - Ultrascale. More...
#define | XSM_AUX00_OFFSET (XSM_IP_OFFSET + 0x240)
| ADC out of VAUXP0/VAUXN0. More...
#define | XSM_AUX01_OFFSET (XSM_IP_OFFSET + 0x244)
| ADC out of VAUXP1/VAUXN1. More...
#define | XSM_AUX02_OFFSET (XSM_IP_OFFSET + 0x248)
| ADC out of VAUXP2/VAUXN2. More...
#define | XSM_AUX03_OFFSET (XSM_IP_OFFSET + 0x24C)
| ADC out of VAUXP3/VAUXN3. More...
#define | XSM_AUX04_OFFSET (XSM_IP_OFFSET + 0x250)
| ADC out of VAUXP4/VAUXN4. More...
#define | XSM_AUX05_OFFSET (XSM_IP_OFFSET + 0x254)
| ADC out of VAUXP5/VAUXN5. More...
#define | XSM_AUX06_OFFSET (XSM_IP_OFFSET + 0x258)
| ADC out of VAUXP6/VAUXN6. More...
#define | XSM_AUX07_OFFSET (XSM_IP_OFFSET + 0x25C)
| ADC out of VAUXP7/VAUXN7. More...
#define | XSM_AUX08_OFFSET (XSM_IP_OFFSET + 0x260)
| ADC out of VAUXP8/VAUXN8. More...
#define | XSM_AUX09_OFFSET (XSM_IP_OFFSET + 0x264)
| ADC out of VAUXP9/VAUXN9. More...
#define | XSM_AUX10_OFFSET (XSM_IP_OFFSET + 0x268)
| ADC out of VAUXP10/VAUXN10. More...
#define | XSM_AUX11_OFFSET (XSM_IP_OFFSET + 0x26C)
| ADC out of VAUXP11/VAUXN11. More...
#define | XSM_AUX12_OFFSET (XSM_IP_OFFSET + 0x270)
| ADC out of VAUXP12/VAUXN12. More...
#define | XSM_AUX13_OFFSET (XSM_IP_OFFSET + 0x274)
| ADC out of VAUXP13/VAUXN13. More...
#define | XSM_AUX14_OFFSET (XSM_IP_OFFSET + 0x278)
| ADC out of VAUXP14/VAUXN14. More...
#define | XSM_AUX15_OFFSET (XSM_IP_OFFSET + 0x27C)
| ADC out of VAUXP15/VAUXN15. More...
#define | XSM_MAX_TEMP_OFFSET (XSM_IP_OFFSET + 0x280)
| Maximum Temperature Reg. More...
#define | XSM_MAX_VCCINT_OFFSET (XSM_IP_OFFSET + 0x284)
| Maximum VCCINT Register. More...
#define | XSM_MAX_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x288)
| Maximum VCCAUX Register. More...
#define | XSM_MAX_VBRAM_OFFSET (XSM_IP_OFFSET + 0x28C)
| Maximum VBRAM Reg, 7 Series/Zynq. More...
#define | XSM_MIN_TEMP_OFFSET (XSM_IP_OFFSET + 0x290)
| Minimum Temperature Reg. More...
#define | XSM_MIN_VCCINT_OFFSET (XSM_IP_OFFSET + 0x294)
| Minimum VCCINT Register. More...
#define | XSM_MIN_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x298)
| Minimum VCCAUX Register. More...
#define | XSM_MIN_VBRAM_OFFSET (XSM_IP_OFFSET + 0x29C)
| Maximum VBRAM Reg, 7 Series/Zynq. More...
#define | XSM_MAX_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x2A0)
| Max VCCPINT Register, Zynq. More...
#define | XSM_MAX_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x2A4)
| Max VCCPAUX Register, Zynq. More...
#define | XSM_MAX_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x2A8)
| Max VCCPDRO Register, Zynq. More...
#define | XSM_MIN_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x2AC)
| Min VCCPINT Register, Zynq. More...
#define | XSM_MIN_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x2B0)
| Min VCCPAUX Register, Zynq. More...
#define | XSM_MIN_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x2B4)
| Min VCCPDRO Register, Zynq. More...
#define | XSM_MAX_VUSR0_OFFSET (XSM_IP_OFFSET + 0x480)
| Maximum VUSER0 Supply Reg. More...
#define | XSM_MAX_VUSR1_OFFSET (XSM_IP_OFFSET + 0x484)
| Maximum VUSER1 Supply Reg. More...
#define | XSM_MAX_VUSR2_OFFSET (XSM_IP_OFFSET + 0x488)
| Maximum VUSER2 Supply Reg. More...
#define | XSM_MAX_VUSR3_OFFSET (XSM_IP_OFFSET + 0x48C)
| Maximum VUSER3 Supply Reg. More...
#define | XSM_MIN_VUSR0_OFFSET (XSM_IP_OFFSET + 0x4A0)
| Minimum VUSER0 Supply Reg. More...
#define | XSM_MIN_VUSR1_OFFSET (XSM_IP_OFFSET + 0x4A4)
| Minimum VUSER1 Supply Reg. More...
#define | XSM_MIN_VUSR2_OFFSET (XSM_IP_OFFSET + 0x4A8)
| Minimum VUSER2 Supply Reg. More...
#define | XSM_MIN_VUSR3_OFFSET (XSM_IP_OFFSET + 0x4AC)
| Minimum VUSER3 Supply Reg. More...
#define | XSM_FLAG_REG_OFFSET (XSM_IP_OFFSET + 0x2FC)
| General Status. More...
#define | XSM_CFR0_OFFSET (XSM_IP_OFFSET + 0x300)
| Configuration Register 0. More...
#define | XSM_CFR1_OFFSET (XSM_IP_OFFSET + 0x304)
| Configuration Register 1. More...
#define | XSM_CFR2_OFFSET (XSM_IP_OFFSET + 0x308)
| Configuration Register 2. More...
#define | XSM_SEQ00_OFFSET (XSM_IP_OFFSET + 0x320)
| Seq Reg 00 Adc Channel Selection. More...
#define | XSM_SEQ01_OFFSET (XSM_IP_OFFSET + 0x324)
| Seq Reg 01 Adc Channel Selection. More...
#define | XSM_SEQ02_OFFSET (XSM_IP_OFFSET + 0x328)
| Seq Reg 02 Adc Average Enable. More...
#define | XSM_SEQ03_OFFSET (XSM_IP_OFFSET + 0x32C)
| Seq Reg 03 Adc Average Enable. More...
#define | XSM_SEQ04_OFFSET (XSM_IP_OFFSET + 0x330)
| Seq Reg 04 Adc Input Mode Select. More...
#define | XSM_SEQ05_OFFSET (XSM_IP_OFFSET + 0x334)
| Seq Reg 05 Adc Input Mode Select. More...
#define | XSM_SEQ06_OFFSET (XSM_IP_OFFSET + 0x338)
| Seq Reg 06 Adc Acquisition Select. More...
#define | XSM_SEQ07_OFFSET (XSM_IP_OFFSET + 0x33C)
| Seq Reg 07 Adc Acquisition Select. More...
#define | XSM_SEQ08_OFFSET (XSM_IP_OFFSET + 0x318)
| Seq Reg 08 Adc Channel Selection. More...
#define | XSM_SEQ09_OFFSET (XSM_IP_OFFSET + 0x31C)
| Seq Reg 09 Adc Average Enable. More...
#define | XSM_ATR_TEMP_UPPER_OFFSET (XSM_IP_OFFSET + 0x340)
| Temp Upper Alarm Register. More...
#define | XSM_ATR_VCCINT_UPPER_OFFSET (XSM_IP_OFFSET + 0x344)
| VCCINT Upper Alarm Reg. More...
#define | XSM_ATR_VCCAUX_UPPER_OFFSET (XSM_IP_OFFSET + 0x348)
| VCCAUX Upper Alarm Reg. More...
#define | XSM_ATR_OT_UPPER_OFFSET (XSM_IP_OFFSET + 0x34C)
| Over Temp Upper Alarm Reg. More...
#define | XSM_ATR_TEMP_LOWER_OFFSET (XSM_IP_OFFSET + 0x350)
| Temp Lower Alarm Register. More...
#define | XSM_ATR_VCCINT_LOWER_OFFSET (XSM_IP_OFFSET + 0x354)
| VCCINT Lower Alarm Reg. More...
#define | XSM_ATR_VCCAUX_LOWER_OFFSET (XSM_IP_OFFSET + 0x358)
| VCCAUX Lower Alarm Reg. More...
#define | XSM_ATR_OT_LOWER_OFFSET (XSM_IP_OFFSET + 0x35C)
| Over Temp Lower Alarm Reg. More...
#define | XSM_ATR_VBRAM_UPPER_OFFSET (XSM_IP_OFFSET + 0x360)
| VBBAM Upper Alarm,7 Series. More...
#define | XSM_ATR_VCCPINT_UPPER_OFFSET (XSM_IP_OFFSET + 0x364)
| VCCPINT Upper Alarm, Zynq. More...
#define | XSM_ATR_VCCPAUX_UPPER_OFFSET (XSM_IP_OFFSET + 0x368)
| VCCPAUX Upper Alarm, Zynq. More...
#define | XSM_ATR_VCCPDRO_UPPER_OFFSET (XSM_IP_OFFSET + 0x36C)
| VCCPDRO Upper Alarm, Zynq. More...
#define | XSM_ATR_VBRAM_LOWER_OFFSET (XSM_IP_OFFSET + 0x370)
| VRBAM Lower Alarm, 7 Series. More...
#define | XSM_ATR_VCCPINT_LOWER_OFFSET (XSM_IP_OFFSET + 0x374)
| VCCPINT Lower Alarm, Zynq. More...
#define | XSM_ATR_VCCPAUX_LOWER_OFFSET (XSM_IP_OFFSET + 0x378)
| VCCPAUX Lower Alarm, Zynq. More...
#define | XSM_ATR_VCCPDRO_LOWER_OFFSET (XSM_IP_OFFSET + 0x37C)
| VCCPDRO Lower Alarm, Zynq. More...
#define | XSM_ATR_VUSR0_UPPER_OFFSET (XSM_IP_OFFSET + 0x380)
| VUSER0 Upper Alarm Reg. More...
#define | XSM_ATR_VUSR1_UPPER_OFFSET (XSM_IP_OFFSET + 0x384)
| VUSER1 Upper Alarm Reg. More...
#define | XSM_ATR_VUSR2_UPPER_OFFSET (XSM_IP_OFFSET + 0x388)
| VUSER2 Upper Alarm Reg. More...
#define | XSM_ATR_VUSR3_UPPER_OFFSET (XSM_IP_OFFSET + 0x38C)
| VUSER3 Upper Alarm Reg. More...
#define | XSM_ATR_VUSR0_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A0)
| VUSER0 Lower Alarm Reg. More...
#define | XSM_ATR_VUSR1_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A4)
| VUSER1 Lower Alarm Reg. More...
#define | XSM_ATR_VUSR2_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A8)
| VUSER2 Lower Alarm Reg. More...
#define | XSM_ATR_VUSR3_LOWER_OFFSET (XSM_IP_OFFSET + 0x3AC)
| VUSER3 Lower Alarm Reg. More...

## System Monitor/ADC Software Reset Register (SRR) mask(s)
#define | XSM_SRR_IPRST_MASK 0x0000000A
| Device Reset Mask. More...

## System Monitor/ADC Status Register (SR) mask(s)
#define | XSM_SR_JTAG_BUSY_MASK 0x00000400
| JTAG is busy. More...
#define | XSM_SR_JTAG_MODIFIED_MASK 0x00000200
| JTAG Write has occurred. More...
#define | XSM_SR_JTAG_LOCKED_MASK 0x00000100
| JTAG is locked. More...
#define | XSM_SR_BUSY_MASK 0x00000080
| ADC is busy in conversion. More...
#define | XSM_SR_EOS_MASK 0x00000040
| End of Sequence. More...
#define | XSM_SR_EOC_MASK 0x00000020
| End of Conversion. More...
#define | XSM_SR_CH_MASK 0x0000001F
| Input ADC channel. More...

## System Monitor/ADC Alarm Output Register (AOR) mask(s)
#define | XSM_AOR_ALARM_ALL_MASK 0x00001FFF
| Mask for all Alarms. More...
#define | XSM_AOR_VUSR3_MASK 0x00001000
| ALM11 - VUSER3 Alarm Mask. More...
#define | XSM_AOR_VUSR2_MASK 0x00000800
| ALM10 - VUSER2 Alarm Mask. More...
#define | XSM_AOR_VUSR1_MASK 0x00000400
| ALM9 - VUSER1 Alarm Mask. More...
#define | XSM_AOR_VUSR0_MASK 0x00000200
| ALM8 - VUSER0 Alarm Mask. More...
#define | XSM_AOR_ALL_MASK 0x00000100
| ALM7 - All Alarms 0 to 6. More...
#define | XSM_AOR_VCCPDRO_MASK 0x00000080
| ALM6 - VCCPDRO Mask, Zynq. More...
#define | XSM_AOR_VCCPAUX_MASK 0x00000040
| ALM5 - VCCPAUX Mask, Zynq. More...
#define | XSM_AOR_VCCPINT_MASK 0x00000020
| ALM4 - VCCPINT Mask, Zynq. More...
#define | XSM_AOR_VBRAM_MASK 0x00000010
| ALM3 - VBRAM Output Mask. More...
#define | XSM_AOR_VCCAUX_MASK 0x00000008
| ALM2 - VCCAUX Output Mask. More...
#define | XSM_AOR_VCCINT_MASK 0x00000004
| ALM1 - VCCINT Alarm Mask. More...
#define | XSM_AOR_TEMP_MASK 0x00000002
| ALM0 - Temp sensor Alarm Mask. More...
#define | XSM_AOR_OT_MASK 0x00000001
| Over Temp Alarm Output. More...

## System Monitor/ADC CONVST Register (CONVST) mask(s)
#define | XSM_CONVST_CONVST_MASK 0x00000001
| Conversion Start Mask. More...
#define | XSM_CONVST_TEMPUPDT_MASK 0x00000002
| Temperature Update Enable Mask. More...
#define | XSM_CONVST_WAITCYCLES_SHIFT 2
| Wait Cycles Shift. More...
#define | XSM_CONVST_WAITCYCLES_MASK 0x0003FFFC
| Wait Cycles Mask. More...
#define | XSM_CONVST_WAITCYCLES_DEFAULT 0x03E8
| Wait Cycles default value. More...

## System Monitor/ADC Reset Register (ARR) mask(s)
#define | XSM_ARR_RST_MASK 0x00000001
| ADC Reset bit mask. More...

## Global Interrupt Enable Register (GIER) mask(s)
#define | XSM_GIER_GIE_MASK 0x80000000
| Global interrupt enable. More...

## System Monitor/ADC device Interrupt Status/Enable Registers
Interrupt Status Register (IPISR) This register holds the interrupt status flags for the device. Interrupt Enable Register (IPIER) This register is used to enable interrupt sources for the device. Writing a '1' to a bit in this register enables the corresponding Interrupt. Writing a '0' to a bit in this register disables the corresponding Interrupt IPISR/IPIER registers have the same bit definitions and are only defined once.
#define | XSM_IPIXR_VBRAM_MASK 0x00000400
| ALM3 - VBRAM Output Mask. More...
#define | XSM_IPIXR_TEMP_DEACTIVE_MASK 0x00000200
| Alarm 0 DEACTIVE. More...
#define | XSM_IPIXR_OT_DEACTIVE_MASK 0x00000100
| Over Temp DEACTIVE. More...
#define | XSM_IPIXR_JTAG_MODIFIED_MASK 0x00000080
| JTAG Modified. More...
#define | XSM_IPIXR_JTAG_LOCKED_MASK 0x00000040
| JTAG Locked. More...
#define | XSM_IPIXR_EOC_MASK 0x00000020
| End Of Conversion. More...
#define | XSM_IPIXR_EOS_MASK 0x00000010
| End Of Sequence. More...
#define | XSM_IPIXR_VCCAUX_MASK 0x00000008
| Alarm 2 - VCCAUX. More...
#define | XSM_IPIXR_VCCINT_MASK 0x00000004
| Alarm 1 - VCCINT. More...
#define | XSM_IPIXR_TEMP_MASK 0x00000002
| Alarm 0 - Temp ACTIVE. More...
#define | XSM_IPIXR_OT_MASK 0x00000001
| Over Temperature ACTIVE. More...
#define | XSM_IPIXR_VUSR0_MASK 0x00004000
| Alarm 8 VUSER0. More...
#define | XSM_IPIXR_VUSR1_MASK 0x00008000
| Alarm 9 VUSER1. More...
#define | XSM_IPIXR_VUSR2_MASK 0x00010000
| Alarm 10 VUSER2. More...
#define | XSM_IPIXR_VUSR3_MASK 0x00020000
| Alarm 11 VUSER3. More...
#define | XSM_IPIXR_ALL_MASK 0x0003C7FF
| Mask of all interrupts. More...

## Mask for all ADC converted data including Minimum/Maximum Measurements
      and Threshold data.
#define | XSM_ADCDATA_MAX_MASK 0x03FF

## Configuration Register 0 (CFR0) mask(s)
#define | XSM_CFR0_CAL_AVG_MASK 0x8000
| Averaging enable Mask. More...
#define | XSM_CFR0_AVG_VALID_MASK 0x3000
| Averaging bit Mask. More...
#define | XSM_CFR0_AVG1_MASK 0x0000
| No Averaging. More...
#define | XSM_CFR0_AVG16_MASK 0x1000
| Average 16 samples. More...
#define | XSM_CFR0_AVG64_MASK 0x2000
| Average 64 samples. More...
#define | XSM_CFR0_AVG256_MASK 0x3000
| Average 256 samples. More...
#define | XSM_CFR0_AVG_SHIFT 12
| Shift for the Averaging bits. More...
#define | XSM_CFR0_MUX_MASK 0x0800
| External Mux Mask Enable. More...
#define | XSM_CFR0_DU_MASK 0x0400
| Bipolar/Unipolar mode. More...
#define | XSM_CFR0_EC_MASK 0x0200
| Event driven/Continuous mode. More...
#define | XSM_CFR0_ACQ_MASK 0x0100
| Add acquisition by 6 ADCCLK. More...
#define | XSM_CFR0_CHANNEL_MASK 0x003F
| Channel number bit Mask. More...

## Configuration Register 1 (CFR1) mask(s)
#define | XSM_CFR1_SEQ_VALID_MASK 0xF000
| Sequence bit Mask. More...
#define | XSM_CFR1_SEQ_SAFEMODE_MASK 0x0000
| Default Safe Mode. More...
#define | XSM_CFR1_SEQ_ONEPASS_MASK 0x1000
| Onepass through Seq. More...
#define | XSM_CFR1_SEQ_CONTINPASS_MASK 0x2000
| Continuous Cycling Seq. More...
#define | XSM_CFR1_SEQ_SINGCHAN_MASK 0x3000
| Single channel - No Seq. More...
#define | XSM_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000
| Simultaneous Sampling Mask. More...
#define | XSM_CFR1_SEQ_INDEPENDENT_MASK 0x8000
| Independent Mode. More...
#define | XSM_CFR1_SEQ_SHIFT 12
| Sequence bit shift. More...
#define | XSM_CFR1_ALM_VCCPDRO_MASK 0x0800
| Alarm 6 - VCCPDRO, Zynq. More...
#define | XSM_CFR1_ALM_VCCPAUX_MASK 0x0400
| Alarm 5 - VCCPAUX, Zynq. More...
#define | XSM_CFR1_ALM_VCCPINT_MASK 0x0200
| Alarm 4 - VCCPINT, Zynq. More...
#define | XSM_CFR1_ALM_VBRAM_MASK 0x0100
| Alarm 3 - VBRAM Enable 7 Series and Zynq. More...
#define | XSM_CFR1_CAL_VALID_MASK 0x00F0
| Valid Calibration Mask. More...
#define | XSM_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080
| Calibration 3 -Power Supply Gain/Offset Enable. More...
#define | XSM_CFR1_CAL_PS_OFFSET_MASK 0x0040
| Calibration 2 -Power Supply Offset Enable. More...
#define | XSM_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020
| Calibration 1 -ADC Gain Offset Enable. More...
#define | XSM_CFR1_CAL_ADC_OFFSET_MASK 0x0010
| Calibration 0 -ADC Offset Enable. More...
#define | XSM_CFR1_CAL_DISABLE_MASK 0x0000
| No Calibration. More...
#define | XSM_CFR1_ALM_ALL_MASK 0x0F0F
| Mask for all alarms. More...
#define | XSM_CFR1_ALM_VCCAUX_MASK 0x0008
| Alarm 2 - VCCAUX Enable. More...
#define | XSM_CFR1_ALM_VCCINT_MASK 0x0004
| Alarm 1 - VCCINT Enable. More...
#define | XSM_CFR1_ALM_TEMP_MASK 0x0002
| Alarm 0 - Temperature. More...
#define | XSM_CFR1_OT_MASK 0x0001
| Over Temperature Enable. More...

## Configuration Register 2 (CFR2) mask(s)
#define | XSM_CFR2_CD_VALID_MASK 0xFF00
| Clock Divisor bit Mask. More...
#define | XSM_CFR2_CD_SHIFT 8
| Num of shift on division. More...
#define | XSM_CFR2_CD_MIN 8
| Minimum value of divisor. More...
#define | XSM_CFR2_CD_MAX 255
| Maximum value of divisor. More...
#define | XSM_CFR2_PD_MASK 0x0030
| Power Down Mask. More...
#define | XSM_CFR2_PD_XADC_MASK 0x0030
| Power Down XADC Mask. More...
#define | XSM_CFR2_PD_ADC1_MASK 0x0020
| Power Down XADC Mask. More...
#define | XSM_CFR2_PD_SHIFT 4
| Power Down Shift. More...

## Configuration Register 3 (CFR3) mask(s)
#define | XSM_CFR3_ALM_ALL_MASK 0x000F
| Mask for all alarms. More...
#define | XSM_CFR3_ALM_VUSR3_MASK 0x0008
| VUSER 0 Supply. More...
#define | XSM_CFR3_ALM_VUSR2_MASK 0x0004
| VUSER 1 Supply. More...
#define | XSM_CFR3_ALM_VUSR1_MASK 0x0002
| VUSER 2 Supply. More...
#define | XSM_CFR3_ALM_VUSR0_MASK 0x0001
| VUSER 3 Supply. More...
#define | XSM_CFR_ALM_ALL_MASK 0xF0F0F

## Alarm masks for channels in Configuration registers 1 and 3
#define | XSM_CFR_ALM_VUSR3_MASK 0x00080000
| VUSER 0 Supply. More...
#define | XSM_CFR_ALM_VUSR2_MASK 0x00040000
| VUSER 1 Supply. More...
#define | XSM_CFR_ALM_VUSR1_MASK 0x00020000
| VUSER 2 Supply. More...
#define | XSM_CFR_ALM_VUSR0_MASK 0x00010000
| VUSER 3 Supply. More...
#define | XSM_CFR_ALM_VCCPDRO_MASK 0x0800
| Alarm 6 - VCCPDRO, Zynq. More...
#define | XSM_CFR_ALM_VCCPAUX_MASK 0x0400
| Alarm 5 - VCCPAUX, Zynq. More...
#define | XSM_CFR_ALM_VCCPINT_MASK 0x0200
| Alarm 4 - VCCPINT, Zynq. More...
#define | XSM_CFR_ALM_VBRAM_MASK 0x0100
| Alarm 3 - VBRAM Enable 7 Series and Zynq. More...
#define | XSM_CFR_ALM_VCCAUX_MASK 0x0008
| Alarm 2 - VCCAUX Enable. More...
#define | XSM_CFR_ALM_VCCINT_MASK 0x0004
| Alarm 1 - VCCINT Enable. More...
#define | XSM_CFR_ALM_TEMP_MASK 0x0002
| Alarm 0 - Temperature. More...
#define | XSM_CFR_OT_MASK 0x0001
| Over Temperature Enable. More...

## Sequence Register (SEQ) Bit Definitions
#define | XSM_SEQ_CH_CALIB 0x00000001
| ADC Calibration Channel. More...
#define | XSM_SEQ_CH_VCCPINT 0x00000020
| VCCPINT, Zynq Only. More...
#define | XSM_SEQ_CH_VCCPAUX 0x00000040
| VCCPAUX, Zynq Only. More...
#define | XSM_SEQ_CH_VCCPDRO 0x00000080
| VCCPDRO, Zynq Only. More...
#define | XSM_SEQ_CH_TEMP 0x00000100
| On Chip Temperature Channel. More...
#define | XSM_SEQ_CH_VCCINT 0x00000200
| VCCINT Channel. More...
#define | XSM_SEQ_CH_VCCAUX 0x00000400
| VCCAUX Channel. More...
#define | XSM_SEQ_CH_VPVN 0x00000800
| VP/VN analog inputs Channel. More...
#define | XSM_SEQ_CH_VREFP 0x00001000
| VREFP Channel. More...
#define | XSM_SEQ_CH_VREFN 0x00002000
| VREFN Channel. More...
#define | XSM_SEQ_CH_VBRAM 0x00004000
| VBRAM Channel, 7 series/Zynq. More...
#define | XSM_SEQ_CH_AUX00 0x00010000
| 1st Aux Channel More...
#define | XSM_SEQ_CH_AUX01 0x00020000
| 2nd Aux Channel More...
#define | XSM_SEQ_CH_AUX02 0x00040000
| 3rd Aux Channel More...
#define | XSM_SEQ_CH_AUX03 0x00080000
| 4th Aux Channel More...
#define | XSM_SEQ_CH_AUX04 0x00100000
| 5th Aux Channel More...
#define | XSM_SEQ_CH_AUX05 0x00200000
| 6th Aux Channel More...
#define | XSM_SEQ_CH_AUX06 0x00400000
| 7th Aux Channel More...
#define | XSM_SEQ_CH_AUX07 0x00800000
| 8th Aux Channel More...
#define | XSM_SEQ_CH_AUX08 0x01000000
| 9th Aux Channel More...
#define | XSM_SEQ_CH_AUX09 0x02000000
| 10th Aux Channel More...
#define | XSM_SEQ_CH_AUX10 0x04000000
| 11th Aux Channel More...
#define | XSM_SEQ_CH_AUX11 0x08000000
| 12th Aux Channel More...
#define | XSM_SEQ_CH_AUX12 0x10000000
| 13th Aux Channel More...
#define | XSM_SEQ_CH_AUX13 0x20000000
| 14th Aux Channel More...
#define | XSM_SEQ_CH_AUX14 0x40000000
| 15th Aux Channel More...
#define | XSM_SEQ_CH_AUX15 0x80000000
| 16th Aux Channel More...
#define | XSM_SEQ_CH_VUSR0 0x100000000
| VUSER0 Channel. More...
#define | XSM_SEQ_CH_VUSR1 0x200000000
| VUSER1 Channel. More...
#define | XSM_SEQ_CH_VUSR2 0x400000000
| VUSER2 Channel. More...
#define | XSM_SEQ_CH_VUSR3 0x800000000
| VUSER3 Channel. More...
#define | XSM_SEQ00_CH_VALID_MASK 0x7FE1
| Mask for the valid channels. More...
#define | XSM_SEQ01_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XSM_SEQ02_CH_VALID_MASK 0x7FE0
| Mask for the valid channels. More...
#define | XSM_SEQ03_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XSM_SEQ04_CH_VALID_MASK 0x0800
| Mask for the valid channels. More...
#define | XSM_SEQ05_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XSM_SEQ06_CH_VALID_MASK 0x0800
| Mask for the valid channels. More...
#define | XSM_SEQ07_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XSM_SEQ08_CH_VALID_MASK 0x000F
| Mask for the valid channels. More...
#define | XSM_SEQ09_CH_VALID_MASK 0x000F
| Mask for the valid channels. More...
#define | XSM_SEQ_CH_AUX_SHIFT 16
| Shift for the Aux Channel. More...
#define | XSM_SEQ_CH_VUSR_SHIFT 32
| Shift for the Aux Channel. More...

## OT Upper Alarm Threshold Register Bit Definitions
#define | XSM_ATR_OT_UPPER_ENB_MASK 0x000F
| Mask for OT enable. More...
#define | XSM_ATR_OT_UPPER_VAL_MASK 0xFFF0
| Mask for OT value. More...
#define | XSM_ATR_OT_UPPER_VAL_SHIFT 4
| Shift for OT value. More...
#define | XSM_ATR_OT_UPPER_ENB_VAL 0x0003
| Value for OT enable. More...
#define | XSM_ATR_OT_UPPER_VAL_MAX 0x0FFF
| Max OT value. More...

## Macro Definition Documentation

#define XSM_ADC_CALIB_OFFSET (XSM_IP_OFFSET + 0x224)

ADC Offset Data Reg.

#define XSM_AOR_ALARM_ALL_MASK 0x00001FFF

Mask for all Alarms.

Referenced by XSysMon_GetAlarmOutputStatus().

#define XSM_AOR_ALL_MASK 0x00000100

ALM7 - All Alarms 0 to 6.

#define XSM_AOR_OFFSET 0x08

Alarm Output Register.

Referenced by SysMonLowLevelExample(), and XSysMon_GetAlarmOutputStatus().

#define XSM_AOR_OT_MASK 0x00000001

Over Temp Alarm Output.

#define XSM_AOR_TEMP_MASK 0x00000002

ALM0 - Temp sensor Alarm Mask.

Referenced by SysMonLowLevelExample(), and SysMonPolledExample().

#define XSM_AOR_VBRAM_MASK 0x00000010

ALM3 - VBRAM Output Mask.

- 7 Series and Zynq

#define XSM_AOR_VCCAUX_MASK 0x00000008

ALM2 - VCCAUX Output Mask.

Referenced by SysMonLowLevelExample(), and SysMonPolledExample().

#define XSM_AOR_VCCINT_MASK 0x00000004

ALM1 - VCCINT Alarm Mask.

#define XSM_AOR_VCCPAUX_MASK 0x00000040

ALM5 - VCCPAUX Mask, Zynq.

#define XSM_AOR_VCCPDRO_MASK 0x00000080

ALM6 - VCCPDRO Mask, Zynq.

#define XSM_AOR_VCCPINT_MASK 0x00000020

ALM4 - VCCPINT Mask, Zynq.

#define XSM_AOR_VUSR0_MASK 0x00000200

ALM8 - VUSER0 Alarm Mask.

#define XSM_AOR_VUSR1_MASK 0x00000400

ALM9 - VUSER1 Alarm Mask.

#define XSM_AOR_VUSR2_MASK 0x00000800

ALM10 - VUSER2 Alarm Mask.

#define XSM_AOR_VUSR3_MASK 0x00001000

ALM11 - VUSER3 Alarm Mask.

#define XSM_ARR_OFFSET 0x10

ADC Reset Register.

Referenced by XSysMon_ResetAdc().

#define XSM_ARR_RST_MASK 0x00000001

ADC Reset bit mask.

Referenced by XSysMon_ResetAdc().

#define XSM_ATR_OT_LOWER 7

Lower Over Temperature limit.

#define XSM_ATR_OT_LOWER_OFFSET (XSM_IP_OFFSET + 0x35C)

Over Temp Lower Alarm Reg.

#define XSM_ATR_OT_UPPER 3

Lower Over Temperature limit.

#define XSM_ATR_OT_UPPER_ENB_MASK 0x000F

Mask for OT enable.

Referenced by XSysMon_DisableUserOverTemp(), and XSysMon_EnableUserOverTemp().

#define XSM_ATR_OT_UPPER_ENB_VAL 0x0003

Value for OT enable.

Referenced by XSysMon_EnableUserOverTemp().

#define XSM_ATR_OT_UPPER_OFFSET (XSM_IP_OFFSET + 0x34C)

Over Temp Upper Alarm Reg.

Referenced by XSysMon_DisableUserOverTemp(), XSysMon_EnableUserOverTemp(), XSysMon_GetOverTemp(), and XSysMon_SetOverTemp().

#define XSM_ATR_OT_UPPER_VAL_MASK 0xFFF0

Mask for OT value.

Referenced by XSysMon_SetOverTemp().

#define XSM_ATR_OT_UPPER_VAL_MAX 0x0FFF

Max OT value.

Referenced by XSysMon_SetOverTemp().

#define XSM_ATR_OT_UPPER_VAL_SHIFT 4

Shift for OT value.

Referenced by XSysMon_GetOverTemp(), and XSysMon_SetOverTemp().

#define XSM_ATR_TEMP_LOWER 4

Low user Temperature.

Referenced by SysMonIntrExample(), and SysMonPolledExample().

#define XSM_ATR_TEMP_LOWER_OFFSET (XSM_IP_OFFSET + 0x350)

Temp Lower Alarm Register.

#define XSM_ATR_TEMP_UPPER 0

High user Temperature.

Referenced by SysMonIntrExample(), and SysMonPolledExample().

#define XSM_ATR_TEMP_UPPER_OFFSET (XSM_IP_OFFSET + 0x340)

Temp Upper Alarm Register.

Referenced by SysMonLowLevelExample(), XSysMon_GetAlarmThreshold(), and XSysMon_SetAlarmThreshold().

#define XSM_ATR_VBRAM_LOWER 0xC

VRBAM Lower Alarm, 7 Series and Zynq.

#define XSM_ATR_VBRAM_LOWER_OFFSET (XSM_IP_OFFSET + 0x370)

VRBAM Lower Alarm, 7 Series.

#define XSM_ATR_VBRAM_UPPER 8

VBRAM high voltage limit.

#define XSM_ATR_VBRAM_UPPER_OFFSET (XSM_IP_OFFSET + 0x360)

VBBAM Upper Alarm,7 Series.

#define XSM_ATR_VCCAUX_LOWER 6

VCCAUX low voltage limit.

Referenced by SysMonIntrExample(), and SysMonPolledExample().

#define XSM_ATR_VCCAUX_LOWER_OFFSET (XSM_IP_OFFSET + 0x358)

VCCAUX Lower Alarm Reg.

Referenced by SysMonLowLevelExample().

#define XSM_ATR_VCCAUX_UPPER 2

VCCAUX high voltage limit.

Referenced by SysMonIntrExample(), and SysMonPolledExample().

#define XSM_ATR_VCCAUX_UPPER_OFFSET (XSM_IP_OFFSET + 0x348)

VCCAUX Upper Alarm Reg.

Referenced by SysMonLowLevelExample().

#define XSM_ATR_VCCINT_LOWER 5

VCCINT low voltage limit.

Referenced by SysMonSingleChannelIntrExample().

#define XSM_ATR_VCCINT_LOWER_OFFSET (XSM_IP_OFFSET + 0x354)

VCCINT Lower Alarm Reg.

#define XSM_ATR_VCCINT_UPPER 1

VCCINT high voltage limit.

Referenced by SysMonSingleChannelIntrExample(), and XSysMon_SelfTest().

#define XSM_ATR_VCCINT_UPPER_OFFSET (XSM_IP_OFFSET + 0x344)

VCCINT Upper Alarm Reg.

#define XSM_ATR_VCCPAUX_LOWER 0xE

VCCPAUX Lower Alarm, Zynq.

#define XSM_ATR_VCCPAUX_LOWER_OFFSET (XSM_IP_OFFSET + 0x378)

VCCPAUX Lower Alarm, Zynq.

#define XSM_ATR_VCCPAUX_UPPER 0xA

VCCPAUX Upper Alarm, Zynq.

#define XSM_ATR_VCCPAUX_UPPER_OFFSET (XSM_IP_OFFSET + 0x368)

VCCPAUX Upper Alarm, Zynq.

#define XSM_ATR_VCCPDRO_LOWER 0xF

VCCPDRO Lower Alarm, Zynq.

#define XSM_ATR_VCCPDRO_LOWER_OFFSET (XSM_IP_OFFSET + 0x37C)

VCCPDRO Lower Alarm, Zynq.

#define XSM_ATR_VCCPDRO_UPPER 0xB

VCCPDRO Upper Alarm, Zynq.

#define XSM_ATR_VCCPDRO_UPPER_OFFSET (XSM_IP_OFFSET + 0x36C)

VCCPDRO Upper Alarm, Zynq.

#define XSM_ATR_VCCPINT_LOWER 0xD

VCCPINT Lower Alarm, Zynq.

#define XSM_ATR_VCCPINT_LOWER_OFFSET (XSM_IP_OFFSET + 0x374)

VCCPINT Lower Alarm, Zynq.

#define XSM_ATR_VCCPINT_UPPER 9

VCCPINT Upper Alarm, Zynq.

#define XSM_ATR_VCCPINT_UPPER_OFFSET (XSM_IP_OFFSET + 0x364)

VCCPINT Upper Alarm, Zynq.

#define XSM_ATR_VUSR0_LOWER 0x18

VUSER0 Lower Alarm, Ultrascale.

Referenced by XSysMon_GetAlarmThreshold(), and XSysMon_SetAlarmThreshold().

#define XSM_ATR_VUSR0_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A0)

VUSER0 Lower Alarm Reg.

#define XSM_ATR_VUSR0_UPPER 0x10

VUSER0 Upper Alarm, Ultrascale.

#define XSM_ATR_VUSR0_UPPER_OFFSET (XSM_IP_OFFSET + 0x380)

VUSER0 Upper Alarm Reg.

#define XSM_ATR_VUSR1_LOWER 0x19

VUSER1 Lower Alarm, Ultrascale.

#define XSM_ATR_VUSR1_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A4)

VUSER1 Lower Alarm Reg.

#define XSM_ATR_VUSR1_UPPER 0x11

VUSER1 Upper Alarm, Ultrascale.

#define XSM_ATR_VUSR1_UPPER_OFFSET (XSM_IP_OFFSET + 0x384)

VUSER1 Upper Alarm Reg.

#define XSM_ATR_VUSR2_LOWER 0x1A

VUSER2 Lower Alarm, Ultrascale.

#define XSM_ATR_VUSR2_LOWER_OFFSET (XSM_IP_OFFSET + 0x3A8)

VUSER2 Lower Alarm Reg.

#define XSM_ATR_VUSR2_UPPER 0x12

VUSER2 Upper Alarm, Ultrascale.

#define XSM_ATR_VUSR2_UPPER_OFFSET (XSM_IP_OFFSET + 0x388)

VUSER2 Upper Alarm Reg.

#define XSM_ATR_VUSR3_LOWER 0x1B

VUSER3 Lower Alarm, Ultrascale.

Referenced by XSysMon_GetAlarmThreshold(), and XSysMon_SetAlarmThreshold().

#define XSM_ATR_VUSR3_LOWER_OFFSET (XSM_IP_OFFSET + 0x3AC)

VUSER3 Lower Alarm Reg.

#define XSM_ATR_VUSR3_UPPER 0x13

VUSER3 Upper Alarm, Ultrascale.

Referenced by XSysMon_GetAlarmThreshold(), and XSysMon_SetAlarmThreshold().

#define XSM_ATR_VUSR3_UPPER_OFFSET (XSM_IP_OFFSET + 0x38C)

VUSER3 Upper Alarm Reg.

#define XSM_AUX00_OFFSET (XSM_IP_OFFSET + 0x240)

ADC out of VAUXP0/VAUXN0.

#define XSM_AUX01_OFFSET (XSM_IP_OFFSET + 0x244)

ADC out of VAUXP1/VAUXN1.

#define XSM_AUX02_OFFSET (XSM_IP_OFFSET + 0x248)

ADC out of VAUXP2/VAUXN2.

#define XSM_AUX03_OFFSET (XSM_IP_OFFSET + 0x24C)

ADC out of VAUXP3/VAUXN3.

#define XSM_AUX04_OFFSET (XSM_IP_OFFSET + 0x250)

ADC out of VAUXP4/VAUXN4.

#define XSM_AUX05_OFFSET (XSM_IP_OFFSET + 0x254)

ADC out of VAUXP5/VAUXN5.

#define XSM_AUX06_OFFSET (XSM_IP_OFFSET + 0x258)

ADC out of VAUXP6/VAUXN6.

#define XSM_AUX07_OFFSET (XSM_IP_OFFSET + 0x25C)

ADC out of VAUXP7/VAUXN7.

#define XSM_AUX08_OFFSET (XSM_IP_OFFSET + 0x260)

ADC out of VAUXP8/VAUXN8.

#define XSM_AUX09_OFFSET (XSM_IP_OFFSET + 0x264)

ADC out of VAUXP9/VAUXN9.

#define XSM_AUX10_OFFSET (XSM_IP_OFFSET + 0x268)

ADC out of VAUXP10/VAUXN10.

#define XSM_AUX11_OFFSET (XSM_IP_OFFSET + 0x26C)

ADC out of VAUXP11/VAUXN11.

#define XSM_AUX12_OFFSET (XSM_IP_OFFSET + 0x270)

ADC out of VAUXP12/VAUXN12.

#define XSM_AUX13_OFFSET (XSM_IP_OFFSET + 0x274)

ADC out of VAUXP13/VAUXN13.

#define XSM_AUX14_OFFSET (XSM_IP_OFFSET + 0x278)

ADC out of VAUXP14/VAUXN14.

#define XSM_AUX15_OFFSET (XSM_IP_OFFSET + 0x27C)

ADC out of VAUXP15/VAUXN15.

#define XSM_AVG_0_SAMPLES 0

No Averaging.

#define XSM_AVG_16_SAMPLES 1

Average 16 samples.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), and SysMonPolledExample().

#define XSM_AVG_256_SAMPLES 3

Average 256 samples.

Referenced by XSysMon_SetAvg().

#define XSM_AVG_64_SAMPLES 2

Average 64 samples.

#define XSM_CALIB_ADC_OFFSET_COEFF 1

ADC Offset Calib Coefficient.

#define XSM_CALIB_GAIN_ERROR_COEFF 2

Gain Error Calib Coefficient.

Referenced by XSysMon_GetCalibCoefficient().

#define XSM_CALIB_SUPPLY_OFFSET_COEFF 0

Supply Offset Calib Coefficient.

#define XSM_CFR0_ACQ_MASK 0x0100

Add acquisition by 6 ADCCLK.

Referenced by XSysMon_SetSingleChParams().

#define XSM_CFR0_AVG16_MASK 0x1000

Average 16 samples.

Referenced by SysMonLowLevelExample().

#define XSM_CFR0_AVG1_MASK 0x0000

No Averaging.

#define XSM_CFR0_AVG256_MASK 0x3000

Average 256 samples.

#define XSM_CFR0_AVG64_MASK 0x2000

Average 64 samples.

#define XSM_CFR0_AVG_SHIFT 12

Shift for the Averaging bits.

Referenced by XSysMon_GetAvg(), and XSysMon_SetAvg().

#define XSM_CFR0_AVG_VALID_MASK 0x3000

Averaging bit Mask.

Referenced by SysMonLowLevelExample(), XSysMon_GetAvg(), XSysMon_SetAvg(), and XSysMon_SetSingleChParams().

#define XSM_CFR0_CAL_AVG_MASK 0x8000

Averaging enable Mask.

#define XSM_CFR0_CHANNEL_MASK 0x003F

Channel number bit Mask.

Referenced by XSysMon_SetExtenalMux(), and XSysMon_SetSingleChParams().

#define XSM_CFR0_DU_MASK 0x0400

Bipolar/Unipolar mode.

Referenced by XSysMon_SetSingleChParams().

#define XSM_CFR0_EC_MASK 0x0200

Event driven/Continuous mode.

Referenced by XSysMon_SetSequencerEvent(), and XSysMon_SetSingleChParams().

#define XSM_CFR0_MUX_MASK 0x0800

External Mux Mask Enable.

- 7 Series and Zynq

Referenced by XSysMon_SetExtenalMux().

#define XSM_CFR0_OFFSET (XSM_IP_OFFSET + 0x300)

Configuration Register 0.

Referenced by SysMonLowLevelExample(), XSysMon_GetAvg(), XSysMon_SetAvg(), XSysMon_SetExtenalMux(), XSysMon_SetSequencerEvent(), and XSysMon_SetSingleChParams().

#define XSM_CFR1_ALM_ALL_MASK 0x0F0F

Mask for all alarms.

Referenced by SysMonLowLevelExample(), XSysMon_GetAlarmEnables(), and XSysMon_SetAlarmEnables().

#define XSM_CFR1_ALM_TEMP_MASK 0x0002

Alarm 0 - Temperature.

Referenced by SysMonIntrExample(), SysMonLowLevelExample(), and SysMonPolledExample().

#define XSM_CFR1_ALM_VBRAM_MASK 0x0100

Alarm 3 - VBRAM Enable 7 Series and Zynq.

#define XSM_CFR1_ALM_VCCAUX_MASK 0x0008

Alarm 2 - VCCAUX Enable.

Referenced by SysMonIntrExample(), SysMonLowLevelExample(), and SysMonPolledExample().

#define XSM_CFR1_ALM_VCCINT_MASK 0x0004

Alarm 1 - VCCINT Enable.

Referenced by SysMonSingleChannelIntrExample().

#define XSM_CFR1_ALM_VCCPAUX_MASK 0x0400

Alarm 5 - VCCPAUX, Zynq.

#define XSM_CFR1_ALM_VCCPDRO_MASK 0x0800

Alarm 6 - VCCPDRO, Zynq.

#define XSM_CFR1_ALM_VCCPINT_MASK 0x0200

Alarm 4 - VCCPINT, Zynq.

#define XSM_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020

Calibration 1 -ADC Gain Offset Enable.

#define XSM_CFR1_CAL_ADC_OFFSET_MASK 0x0010

Calibration 0 -ADC Offset Enable.

Referenced by XSysMon_SetCalibEnables().

#define XSM_CFR1_CAL_DISABLE_MASK 0x0000

No Calibration.

Referenced by XSysMon_SetCalibEnables().

#define XSM_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080

Calibration 3 -Power Supply Gain/Offset Enable.

#define XSM_CFR1_CAL_PS_OFFSET_MASK 0x0040

Calibration 2 -Power Supply Offset Enable.

#define XSM_CFR1_CAL_VALID_MASK 0x00F0

Valid Calibration Mask.

Referenced by XSysMon_GetCalibEnables(), and XSysMon_SetCalibEnables().

#define XSM_CFR1_OFFSET (XSM_IP_OFFSET + 0x304)

Configuration Register 1.

Referenced by SysMonLowLevelExample(), XSysMon_GetAlarmEnables(), XSysMon_GetCalibEnables(), XSysMon_GetSequencerMode(), XSysMon_SetAlarmEnables(), XSysMon_SetCalibEnables(), and XSysMon_SetSequencerMode().

#define XSM_CFR1_OT_MASK 0x0001

Over Temperature Enable.

#define XSM_CFR1_SEQ_CONTINPASS_MASK 0x2000

Continuous Cycling Seq.

Referenced by SysMonLowLevelExample().

#define XSM_CFR1_SEQ_INDEPENDENT_MASK 0x8000

Independent Mode.

#define XSM_CFR1_SEQ_ONEPASS_MASK 0x1000

Onepass through Seq.

#define XSM_CFR1_SEQ_SAFEMODE_MASK 0x0000

Default Safe Mode.

Referenced by SysMonLowLevelExample().

#define XSM_CFR1_SEQ_SHIFT 12

Sequence bit shift.

Referenced by XSysMon_GetSequencerMode(), and XSysMon_SetSequencerMode().

#define XSM_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000

Simultaneous Sampling Mask.

#define XSM_CFR1_SEQ_SINGCHAN_MASK 0x3000

Single channel - No Seq.

#define XSM_CFR1_SEQ_VALID_MASK 0xF000

Sequence bit Mask.

Referenced by SysMonLowLevelExample(), XSysMon_GetSequencerMode(), and XSysMon_SetSequencerMode().

#define XSM_CFR2_CD_MAX 255

Maximum value of divisor.

#define XSM_CFR2_CD_MIN 8

Minimum value of divisor.

#define XSM_CFR2_CD_SHIFT 8

Num of shift on division.

Referenced by SysMonLowLevelExample(), XSysMon_GetAdcClkDivisor(), and XSysMon_SetAdcClkDivisor().

#define XSM_CFR2_CD_VALID_MASK 0xFF00

Clock Divisor bit Mask.

#define XSM_CFR2_OFFSET (XSM_IP_OFFSET + 0x308)

Configuration Register 2.

Referenced by SysMonLowLevelExample(), XSysMon_GetAdcClkDivisor(), and XSysMon_SetAdcClkDivisor().

#define XSM_CFR2_PD_ADC1_MASK 0x0020

Power Down XADC Mask.

#define XSM_CFR2_PD_MASK 0x0030

Power Down Mask.

#define XSM_CFR2_PD_SHIFT 4

Power Down Shift.

#define XSM_CFR2_PD_XADC_MASK 0x0030

Power Down XADC Mask.

#define XSM_CFR3_ALM_ALL_MASK 0x000F

Mask for all alarms.

Referenced by XSysMon_GetAlarmEnables(), and XSysMon_SetAlarmEnables().

#define XSM_CFR3_ALM_VUSR0_MASK 0x0001

VUSER 3 Supply.

#define XSM_CFR3_ALM_VUSR1_MASK 0x0002

VUSER 2 Supply.

#define XSM_CFR3_ALM_VUSR2_MASK 0x0004

VUSER 1 Supply.

#define XSM_CFR3_ALM_VUSR3_MASK 0x0008

VUSER 0 Supply.

#define XSM_CFR_ALM_TEMP_MASK 0x0002

Alarm 0 - Temperature.

#define XSM_CFR_ALM_VBRAM_MASK 0x0100

Alarm 3 - VBRAM Enable 7 Series and Zynq.

#define XSM_CFR_ALM_VCCAUX_MASK 0x0008

Alarm 2 - VCCAUX Enable.

#define XSM_CFR_ALM_VCCINT_MASK 0x0004

Alarm 1 - VCCINT Enable.

#define XSM_CFR_ALM_VCCPAUX_MASK 0x0400

Alarm 5 - VCCPAUX, Zynq.

#define XSM_CFR_ALM_VCCPDRO_MASK 0x0800

Alarm 6 - VCCPDRO, Zynq.

#define XSM_CFR_ALM_VCCPINT_MASK 0x0200

Alarm 4 - VCCPINT, Zynq.

#define XSM_CFR_ALM_VUSR0_MASK 0x00010000

VUSER 3 Supply.

#define XSM_CFR_ALM_VUSR1_MASK 0x00020000

VUSER 2 Supply.

#define XSM_CFR_ALM_VUSR2_MASK 0x00040000

VUSER 1 Supply.

#define XSM_CFR_ALM_VUSR3_MASK 0x00080000

VUSER 0 Supply.

#define XSM_CFR_OT_MASK 0x0001

Over Temperature Enable.

#define XSM_CH_ADC_CALIB 0x08

ADC Offset Channel Reg.

#define XSM_CH_AUX_MAX 31

Channel number for Last Aux channel.

Referenced by XSysMon_GetAdcData(), XSysMon_SetExtenalMux(), and XSysMon_SetSingleChParams().

#define XSM_CH_AUX_MIN 16

Channel number for 1st Aux Channel.

Referenced by SysMonAuxPolledExample(), XSysMon_SetExtenalMux(), and XSysMon_SetSingleChParams().

#define XSM_CH_GAINERR_CALIB 0x09

Gain Error Channel Reg.

#define XSM_CH_SUPPLY_CALIB 0x07

Supply Calib Data Reg.

#define XSM_CH_TEMP 0x0

On Chip Temperature.

Referenced by SysMonIntrExample(), and SysMonPolledExample().

#define XSM_CH_VBRAM 0x6

VBRAM - 7 Series and Zynq.

Referenced by XSysMon_GetAdcData().

#define XSM_CH_VCCAUX 0x2

VCCAUX.

Referenced by SysMonIntrExample(), and SysMonPolledExample().

#define XSM_CH_VCCINT 0x1

VCCINT.

Referenced by SysMonSingleChannelIntrExample().

#define XSM_CH_VCCPAUX 0x0E

On-chip PS VCCPAUX Channel, Zynq.

#define XSM_CH_VCCPDRO 0x0F

On-chip PS VCCPDRO Channel, Zynq.

#define XSM_CH_VCCPINT 0x0D

On-chip PS VCCPINT Channel, Zynq.

Referenced by XSysMon_GetAdcData().

#define XSM_CH_VPVN 0x3

VP/VN Dedicated analog inputs.

Referenced by XSysMon_SetSingleChParams().

#define XSM_CH_VREFN 0x5

VREFN.

Referenced by XSysMon_SetExtenalMux(), and XSysMon_SetSingleChParams().

#define XSM_CH_VREFP 0x4

VREFP.

#define XSM_CH_VUSR0 32

VUSER0 Supply - UltraScale.

Referenced by XSysMon_GetAdcData(), and XSysMon_SetSingleChParams().

#define XSM_CH_VUSR1 33

VUSER1 Supply - UltraScale.

#define XSM_CH_VUSR2 34

VUSER2 Supply - UltraScale.

#define XSM_CH_VUSR3 35

VUSER3 Supply - UltraScale.

Referenced by XSysMon_GetAdcData(), and XSysMon_SetSingleChParams().

#define XSM_CONVST_CONVST_MASK 0x00000001

Conversion Start Mask.

Referenced by XSysMon_StartAdcConversion().

#define XSM_CONVST_OFFSET 0x0C

ADC Convert Start Register.

Referenced by XSysMon_DisableTempUpdate(), XSysMon_EnableTempUpdate(), XSysMon_SetTempWaitCycles(), and XSysMon_StartAdcConversion().

#define XSM_CONVST_TEMPUPDT_MASK 0x00000002

Temperature Update Enable Mask.

Referenced by XSysMon_DisableTempUpdate(), and XSysMon_EnableTempUpdate().

#define XSM_CONVST_WAITCYCLES_DEFAULT 0x03E8

Wait Cycles default value.

Referenced by XSysMon_CfgInitialize().

#define XSM_CONVST_WAITCYCLES_MASK 0x0003FFFC

Wait Cycles Mask.

Referenced by XSysMon_SetTempWaitCycles().

#define XSM_CONVST_WAITCYCLES_SHIFT 2

Wait Cycles Shift.

Referenced by XSysMon_CfgInitialize(), and XSysMon_SetTempWaitCycles().

#define XSM_FLAG_REG_OFFSET (XSM_IP_OFFSET + 0x2FC)

General Status.

#define XSM_GAINERR_CALIB_OFFSET (XSM_IP_OFFSET + 0x228)

Gain Error Data Reg.

#define XSM_GIER_GIE_MASK 0x80000000

Global interrupt enable.

Referenced by XSysMon_IntrGlobalEnable().

#define XSM_GIER_OFFSET 0x5C

Global Interrupt Enable.

Referenced by XSysMon_IntrGlobalDisable(), and XSysMon_IntrGlobalEnable().

#define XSM_IPIER_OFFSET 0x68

Interrupt Enable register.

Referenced by XSysMon_IntrDisable(), XSysMon_IntrEnable(), and XSysMon_IntrGetEnabled().

#define XSM_IPISR_OFFSET 0x60

Interrupt Status Register.

Referenced by XSysMon_IntrClear(), and XSysMon_IntrGetStatus().

#define XSM_IPIXR_ALL_MASK 0x0003C7FF

Mask of all interrupts.

Referenced by XSysMon_IntrClear(), XSysMon_IntrDisable(), XSysMon_IntrEnable(), XSysMon_IntrGetEnabled(), and XSysMon_IntrGetStatus().

#define XSM_IPIXR_EOC_MASK 0x00000020

End Of Conversion.

Referenced by SysMonSingleChannelIntrExample().

#define XSM_IPIXR_EOS_MASK 0x00000010

End Of Sequence.

#define XSM_IPIXR_JTAG_LOCKED_MASK 0x00000040

JTAG Locked.

#define XSM_IPIXR_JTAG_MODIFIED_MASK 0x00000080

JTAG Modified.

#define XSM_IPIXR_OT_DEACTIVE_MASK 0x00000100

Over Temp DEACTIVE.

#define XSM_IPIXR_OT_MASK 0x00000001

Over Temperature ACTIVE.

#define XSM_IPIXR_TEMP_DEACTIVE_MASK 0x00000200

Alarm 0 DEACTIVE.

#define XSM_IPIXR_TEMP_MASK 0x00000002

Alarm 0 - Temp ACTIVE.

Referenced by SysMonIntrExample().

#define XSM_IPIXR_VBRAM_MASK 0x00000400

ALM3 - VBRAM Output Mask.

- 7 Series and Zynq

#define XSM_IPIXR_VCCAUX_MASK 0x00000008

Alarm 2 - VCCAUX.

Referenced by SysMonIntrExample().

#define XSM_IPIXR_VCCINT_MASK 0x00000004

Alarm 1 - VCCINT.

Referenced by SysMonSingleChannelIntrExample().

#define XSM_IPIXR_VUSR0_MASK 0x00004000

Alarm 8 VUSER0.

#define XSM_IPIXR_VUSR1_MASK 0x00008000

Alarm 9 VUSER1.

#define XSM_IPIXR_VUSR2_MASK 0x00010000

Alarm 10 VUSER2.

#define XSM_IPIXR_VUSR3_MASK 0x00020000

Alarm 11 VUSER3.

#define XSM_MAX_TEMP 0

Maximum Temperature Data.

Referenced by SysMonPolledExample().

#define XSM_MAX_TEMP_OFFSET (XSM_IP_OFFSET + 0x280)

Maximum Temperature Reg.

Referenced by SysMonLowLevelExample(), and XSysMon_GetMinMaxMeasurement().

#define XSM_MAX_VBRAM_OFFSET (XSM_IP_OFFSET + 0x28C)

Maximum VBRAM Reg, 7 Series/Zynq.

#define XSM_MAX_VCCAUX 2

Maximum VCCAUX Data.

Referenced by SysMonPolledExample().

#define XSM_MAX_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x288)

Maximum VCCAUX Register.

Referenced by SysMonLowLevelExample().

#define XSM_MAX_VCCBRAM 3

Maximum VCCBRAM Data, 7 Series/Zynq.

#define XSM_MAX_VCCINT 1

Maximum VCCINT Data.

#define XSM_MAX_VCCINT_OFFSET (XSM_IP_OFFSET + 0x284)

Maximum VCCINT Register.

#define XSM_MAX_VCCPAUX 9

Maximum VCCPAUX Data, Zynq.

#define XSM_MAX_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x2A4)

Max VCCPAUX Register, Zynq.

#define XSM_MAX_VCCPDRO 0xA

Maximum VCCPDRO Data, Zynq.

Referenced by XSysMon_GetMinMaxMeasurement().

#define XSM_MAX_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x2A8)

Max VCCPDRO Register, Zynq.

#define XSM_MAX_VCCPINT 8

Maximum VCCPINT Data, Zynq.

#define XSM_MAX_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x2A0)

Max VCCPINT Register, Zynq.

#define XSM_MAX_VUSR0 0x80

Maximum VUSR0 Data, Ultrascale.

Referenced by XSysMon_GetMinMaxMeasurement().

#define XSM_MAX_VUSR0_OFFSET (XSM_IP_OFFSET + 0x480)

Maximum VUSER0 Supply Reg.

#define XSM_MAX_VUSR1 0x81

Maximum VUSR1 Data, Ultrascale.

#define XSM_MAX_VUSR1_OFFSET (XSM_IP_OFFSET + 0x484)

Maximum VUSER1 Supply Reg.

#define XSM_MAX_VUSR2 0x82

Maximum VUSR2 Data, Ultrascale.

#define XSM_MAX_VUSR2_OFFSET (XSM_IP_OFFSET + 0x488)

Maximum VUSER2 Supply Reg.

#define XSM_MAX_VUSR3 0x83

Maximum VUSR3 Data, Ultrascale.

Referenced by XSysMon_GetMinMaxMeasurement().

#define XSM_MAX_VUSR3_OFFSET (XSM_IP_OFFSET + 0x48C)

Maximum VUSER3 Supply Reg.

#define XSM_MIN_TEMP 4

Minimum Temperature Data.

Referenced by SysMonPolledExample().

#define XSM_MIN_TEMP_OFFSET (XSM_IP_OFFSET + 0x290)

Minimum Temperature Reg.

Referenced by SysMonLowLevelExample().

#define XSM_MIN_VBRAM_OFFSET (XSM_IP_OFFSET + 0x29C)

Maximum VBRAM Reg, 7 Series/Zynq.

#define XSM_MIN_VCCAUX 6

Minimum VCCAUX Data.

Referenced by SysMonPolledExample().

#define XSM_MIN_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x298)

Minimum VCCAUX Register.

Referenced by SysMonLowLevelExample().

#define XSM_MIN_VCCBRAM 7

Minimum VCCBRAM Data, 7 Series/Zynq.

#define XSM_MIN_VCCINT 5

Minimum VCCINT Data.

#define XSM_MIN_VCCINT_OFFSET (XSM_IP_OFFSET + 0x294)

Minimum VCCINT Register.

#define XSM_MIN_VCCPAUX 0xD

Minimum VCCPAUX Data, Zynq.

#define XSM_MIN_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x2B0)

Min VCCPAUX Register, Zynq.

#define XSM_MIN_VCCPDRO 0xE

Minimum VCCPDRO Data, Zynq.

Referenced by XSysMon_GetMinMaxMeasurement().

#define XSM_MIN_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x2B4)

Min VCCPDRO Register, Zynq.

#define XSM_MIN_VCCPINT 0xC

Minimum VCCPINT Data, Zynq.

Referenced by XSysMon_GetMinMaxMeasurement().

#define XSM_MIN_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x2AC)

Min VCCPINT Register, Zynq.

#define XSM_MIN_VUSR0 0x88

Minimum VUSR0 Data, Ultrascale.

Referenced by XSysMon_GetMinMaxMeasurement().

#define XSM_MIN_VUSR0_OFFSET (XSM_IP_OFFSET + 0x4A0)

Minimum VUSER0 Supply Reg.

#define XSM_MIN_VUSR1 0x89

Minimum VUSR1 Data, Ultrascale.

#define XSM_MIN_VUSR1_OFFSET (XSM_IP_OFFSET + 0x4A4)

Minimum VUSER1 Supply Reg.

#define XSM_MIN_VUSR2 0x8A

Minimum VUSR2 Data, Ultrascale.

#define XSM_MIN_VUSR2_OFFSET (XSM_IP_OFFSET + 0x4A8)

Minimum VUSER2 Supply Reg.

#define XSM_MIN_VUSR3 0x8B

Minimum VUSR3 Data, Ultrascale.

Referenced by XSysMon_GetMinMaxMeasurement().

#define XSM_MIN_VUSR3_OFFSET (XSM_IP_OFFSET + 0x4AC)

Minimum VUSER3 Supply Reg.

#define XSM_SEQ00_CH_VALID_MASK 0x7FE1

Mask for the valid channels.

Referenced by XSysMon_GetSeqChEnables(), and XSysMon_SetSeqChEnables().

#define XSM_SEQ00_OFFSET (XSM_IP_OFFSET + 0x320)

Seq Reg 00 Adc Channel Selection.

Referenced by SysMonLowLevelExample(), XSysMon_GetSeqChEnables(), and XSysMon_SetSeqChEnables().

#define XSM_SEQ01_CH_VALID_MASK 0xFFFF

Mask for the valid channels.

Referenced by XSysMon_GetSeqChEnables(), and XSysMon_SetSeqChEnables().

#define XSM_SEQ01_OFFSET (XSM_IP_OFFSET + 0x324)

Seq Reg 01 Adc Channel Selection.

Referenced by SysMonLowLevelExample(), XSysMon_GetSeqChEnables(), and XSysMon_SetSeqChEnables().

#define XSM_SEQ02_CH_VALID_MASK 0x7FE0

Mask for the valid channels.

Referenced by XSysMon_GetSeqAvgEnables(), and XSysMon_SetSeqAvgEnables().

#define XSM_SEQ02_OFFSET (XSM_IP_OFFSET + 0x328)

Seq Reg 02 Adc Average Enable.

Referenced by SysMonLowLevelExample(), XSysMon_GetSeqAvgEnables(), and XSysMon_SetSeqAvgEnables().

#define XSM_SEQ03_CH_VALID_MASK 0xFFFF

Mask for the valid channels.

Referenced by XSysMon_GetSeqAvgEnables(), and XSysMon_SetSeqAvgEnables().

#define XSM_SEQ03_OFFSET (XSM_IP_OFFSET + 0x32C)

Seq Reg 03 Adc Average Enable.

Referenced by SysMonLowLevelExample(), XSysMon_GetSeqAvgEnables(), and XSysMon_SetSeqAvgEnables().

#define XSM_SEQ04_CH_VALID_MASK 0x0800

Mask for the valid channels.

Referenced by XSysMon_GetSeqInputMode(), and XSysMon_SetSeqInputMode().

#define XSM_SEQ04_OFFSET (XSM_IP_OFFSET + 0x330)

Seq Reg 04 Adc Input Mode Select.

Referenced by XSysMon_GetSeqInputMode(), and XSysMon_SetSeqInputMode().

#define XSM_SEQ05_CH_VALID_MASK 0xFFFF

Mask for the valid channels.

Referenced by XSysMon_GetSeqInputMode(), and XSysMon_SetSeqInputMode().

#define XSM_SEQ05_OFFSET (XSM_IP_OFFSET + 0x334)

Seq Reg 05 Adc Input Mode Select.

Referenced by SysMonLowLevelExample(), XSysMon_GetSeqInputMode(), and XSysMon_SetSeqInputMode().

#define XSM_SEQ06_CH_VALID_MASK 0x0800

Mask for the valid channels.

Referenced by XSysMon_GetSeqAcqTime(), and XSysMon_SetSeqAcqTime().

#define XSM_SEQ06_OFFSET (XSM_IP_OFFSET + 0x338)

Seq Reg 06 Adc Acquisition Select.

Referenced by XSysMon_GetSeqAcqTime(), and XSysMon_SetSeqAcqTime().

#define XSM_SEQ07_CH_VALID_MASK 0xFFFF

Mask for the valid channels.

Referenced by XSysMon_GetSeqAcqTime(), and XSysMon_SetSeqAcqTime().

#define XSM_SEQ07_OFFSET (XSM_IP_OFFSET + 0x33C)

Seq Reg 07 Adc Acquisition Select.

Referenced by SysMonLowLevelExample(), XSysMon_GetSeqAcqTime(), and XSysMon_SetSeqAcqTime().

#define XSM_SEQ08_CH_VALID_MASK 0x000F

Mask for the valid channels.

Referenced by XSysMon_GetSeqChEnables(), and XSysMon_SetSeqChEnables().

#define XSM_SEQ08_OFFSET (XSM_IP_OFFSET + 0x318)

Seq Reg 08 Adc Channel Selection.

Referenced by XSysMon_GetSeqChEnables(), and XSysMon_SetSeqChEnables().

#define XSM_SEQ09_CH_VALID_MASK 0x000F

Mask for the valid channels.

Referenced by XSysMon_GetSeqAvgEnables(), and XSysMon_SetSeqAvgEnables().

#define XSM_SEQ09_OFFSET (XSM_IP_OFFSET + 0x31C)

Seq Reg 09 Adc Average Enable.

Referenced by XSysMon_GetSeqAvgEnables(), and XSysMon_SetSeqAvgEnables().

#define XSM_SEQ_CH_AUX00 0x00010000

1st Aux Channel

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), SysMonLowLevelExample(), and SysMonPolledExample().

#define XSM_SEQ_CH_AUX01 0x00020000

2nd Aux Channel

#define XSM_SEQ_CH_AUX02 0x00040000

3rd Aux Channel

#define XSM_SEQ_CH_AUX03 0x00080000

4th Aux Channel

#define XSM_SEQ_CH_AUX04 0x00100000

5th Aux Channel

#define XSM_SEQ_CH_AUX05 0x00200000

6th Aux Channel

#define XSM_SEQ_CH_AUX06 0x00400000

7th Aux Channel

#define XSM_SEQ_CH_AUX07 0x00800000

8th Aux Channel

#define XSM_SEQ_CH_AUX08 0x01000000

9th Aux Channel

#define XSM_SEQ_CH_AUX09 0x02000000

10th Aux Channel

#define XSM_SEQ_CH_AUX10 0x04000000

11th Aux Channel

#define XSM_SEQ_CH_AUX11 0x08000000

12th Aux Channel

#define XSM_SEQ_CH_AUX12 0x10000000

13th Aux Channel

#define XSM_SEQ_CH_AUX13 0x20000000

14th Aux Channel

#define XSM_SEQ_CH_AUX14 0x40000000

15th Aux Channel

#define XSM_SEQ_CH_AUX15 0x80000000

16th Aux Channel

Referenced by SysMonIntrExample(), SysMonLowLevelExample(), and SysMonPolledExample().

#define XSM_SEQ_CH_AUX_SHIFT 16

Shift for the Aux Channel.

Referenced by SysMonLowLevelExample(), XSysMon_GetSeqAcqTime(), XSysMon_GetSeqAvgEnables(), XSysMon_GetSeqChEnables(), XSysMon_GetSeqInputMode(), XSysMon_SetSeqAcqTime(), XSysMon_SetSeqAvgEnables(), XSysMon_SetSeqChEnables(), and XSysMon_SetSeqInputMode().

#define XSM_SEQ_CH_CALIB 0x00000001

ADC Calibration Channel.

#define XSM_SEQ_CH_TEMP 0x00000100

On Chip Temperature Channel.

Referenced by SysMonIntrExample(), SysMonLowLevelExample(), and SysMonPolledExample().

#define XSM_SEQ_CH_VBRAM 0x00004000

VBRAM Channel, 7 series/Zynq.

#define XSM_SEQ_CH_VCCAUX 0x00000400

VCCAUX Channel.

Referenced by SysMonIntrExample(), SysMonLowLevelExample(), and SysMonPolledExample().

#define XSM_SEQ_CH_VCCINT 0x00000200

VCCINT Channel.

#define XSM_SEQ_CH_VCCPAUX 0x00000040

VCCPAUX, Zynq Only.

#define XSM_SEQ_CH_VCCPDRO 0x00000080

VCCPDRO, Zynq Only.

#define XSM_SEQ_CH_VCCPINT 0x00000020

VCCPINT, Zynq Only.

#define XSM_SEQ_CH_VPVN 0x00000800

VP/VN analog inputs Channel.

#define XSM_SEQ_CH_VREFN 0x00002000

VREFN Channel.

#define XSM_SEQ_CH_VREFP 0x00001000

VREFP Channel.

#define XSM_SEQ_CH_VUSR0 0x100000000

VUSER0 Channel.

#define XSM_SEQ_CH_VUSR1 0x200000000

VUSER1 Channel.

#define XSM_SEQ_CH_VUSR2 0x400000000

VUSER2 Channel.

#define XSM_SEQ_CH_VUSR3 0x800000000

VUSER3 Channel.

#define XSM_SEQ_CH_VUSR_SHIFT 32

Shift for the Aux Channel.

Referenced by XSysMon_GetSeqAvgEnables(), XSysMon_GetSeqChEnables(), XSysMon_SetSeqAvgEnables(), and XSysMon_SetSeqChEnables().

#define XSM_SEQ_MODE_CONTINPASS 2

Continuous Cycling Seqquencer.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), and SysMonPolledExample().

#define XSM_SEQ_MODE_INDEPENDENT 8

Independent ADC Sequencer, 7 Series and Zynq XADC only.

Referenced by XSysMon_SetSequencerMode().

#define XSM_SEQ_MODE_ONEPASS 1

Onepass through Sequencer.

#define XSM_SEQ_MODE_SAFE 0

Default Safe Mode.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), SysMonPolledExample(), XSysMon_SetSeqAcqTime(), XSysMon_SetSeqAvgEnables(), XSysMon_SetSeqChEnables(), and XSysMon_SetSeqInputMode().

#define XSM_SEQ_MODE_SIMUL 4

Simultaneous Cycling Sequencer, 7 Series and Zynq XADC only.

Referenced by XSysMon_SetSequencerMode().

#define XSM_SEQ_MODE_SINGCHAN 3

Single channel - No Sequencing.

Referenced by SysMonSingleChannelIntrExample(), and XSysMon_SetSingleChParams().

#define XSM_SR_BUSY_MASK 0x00000080

ADC is busy in conversion.

#define XSM_SR_CH_MASK 0x0000001F

Input ADC channel.

#define XSM_SR_EOC_MASK 0x00000020

End of Conversion.

#define XSM_SR_EOS_MASK 0x00000040

End of Sequence.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), SysMonLowLevelExample(), and SysMonPolledExample().

#define XSM_SR_JTAG_BUSY_MASK 0x00000400

JTAG is busy.

#define XSM_SR_JTAG_LOCKED_MASK 0x00000100

JTAG is locked.

#define XSM_SR_JTAG_MODIFIED_MASK 0x00000200

JTAG Write has occurred.

#define XSM_SR_OFFSET 0x04

Status Register.

Referenced by SysMonLowLevelExample(), and XSysMon_GetStatus().

#define XSM_SRR_IPRST_MASK 0x0000000A

Device Reset Mask.

Referenced by SysMonLowLevelExample(), and XSysMon_Reset().

#define XSM_SRR_OFFSET 0x00

Software Reset Register.

Referenced by SysMonLowLevelExample(), and XSysMon_Reset().

#define XSM_SUPPLY_CALIB_OFFSET (XSM_IP_OFFSET + 0x220)

Supply Offset Data Reg.

Referenced by XSysMon_GetCalibCoefficient().

#define XSM_TEMP_OFFSET (XSM_IP_OFFSET + 0x200)

On-chip Temperature Reg.

Referenced by SysMonLowLevelExample(), and XSysMon_GetAdcData().

#define XSM_VBRAM_OFFSET (XSM_IP_OFFSET + 0x218)

On-chip VBRAM Data,7-series/Zynq.

#define XSM_VCCAUX_OFFSET (XSM_IP_OFFSET + 0x208)

On-chip VCCAUX Data Reg.

Referenced by SysMonLowLevelExample().

#define XSM_VCCINT_OFFSET (XSM_IP_OFFSET + 0x204)

On-chip VCCINT Data Reg.

#define XSM_VCCPAUX_OFFSET (XSM_IP_OFFSET + 0x230)

PS VCCPAUX Data Reg - Zynq.

#define XSM_VCCPDRO_OFFSET (XSM_IP_OFFSET + 0x234)

PS VCCPDRO Data Reg - Zynq.

#define XSM_VCCPINT_OFFSET (XSM_IP_OFFSET + 0x22C)

PS VCCPINT Data Reg - Zynq.

#define XSM_VPVN_OFFSET (XSM_IP_OFFSET + 0x20C)

ADC out of VP/VN.

#define XSM_VREFN_OFFSET (XSM_IP_OFFSET + 0x214)

On-chip VREFN Data Reg.

#define XSM_VREFP_OFFSET (XSM_IP_OFFSET + 0x210)

On-chip VREFP Data Reg.

#define XSM_VUSR0_OFFSET (XSM_IP_OFFSET + 0x400)

VUSER0 Supply - Ultrascale.

Referenced by XSysMon_GetAdcData().

#define XSM_VUSR1_OFFSET (XSM_IP_OFFSET + 0x404)

VUSER0 Supply - Ultrascale.

#define XSM_VUSR2_OFFSET (XSM_IP_OFFSET + 0x408)

VUSER0 Supply - Ultrascale.

#define XSM_VUSR3_OFFSET (XSM_IP_OFFSET + 0x40C)

VUSER0 Supply - Ultrascale.

#define XSysMon_IsDrpBusy | ( |  | InstancePtr | ) |

Value:
((XSysMon_ReadReg((InstancePtr)->Config.BaseAddress, \
XSM_SR_OFFSET) & XSM_SR_JTAG_BUSY_MASK) ? \
TRUE : FALSE)
XSM_SR_OFFSET
#define XSM_SR_OFFSET
Status Register.
Definition: xsysmon_hw.h:107
XSM_SR_JTAG_BUSY_MASK
#define XSM_SR_JTAG_BUSY_MASK
JTAG is busy.
Definition: xsysmon_hw.h:349
XSysMon_ReadReg
#define XSysMon_ReadReg(BaseAddress, RegOffset)
Read a register of the System Monitor/ADC device.
Definition: xsysmon_hw.h:666

This macro checks if the Dynamic Reconfiguration Port (DRP) transaction from the JTAG is in progress.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  - TRUE if the DRP transaction from JTAG is in Progress.
  - FALSE if there is no DRP transaction from the JTAG.

Note
  C-Style signature: int XSysMon_IsDrpBusy(XSysMon *InstancePtr);

#define XSysMon_IsDrpLocked | ( |  | InstancePtr | ) |

Value:
(((XSysMon_ReadReg((InstancePtr)->Config.BaseAddress, \
XSM_SR_OFFSET) & XSM_SR_JTAG_LOCKED_MASK) ? \
TRUE : FALSE))
XSM_SR_JTAG_LOCKED_MASK
#define XSM_SR_JTAG_LOCKED_MASK
JTAG is locked.
Definition: xsysmon_hw.h:351
XSM_SR_OFFSET
#define XSM_SR_OFFSET
Status Register.
Definition: xsysmon_hw.h:107
XSysMon_ReadReg
#define XSysMon_ReadReg(BaseAddress, RegOffset)
Read a register of the System Monitor/ADC device.
Definition: xsysmon_hw.h:666

This macro checks if the Dynamic Reconfiguration Port (DRP) is locked by the JTAG.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  - TRUE if the DRP is locked by the JTAG.
  - FALSE if the DRP is not locked by the JTAG.

Note
  C-Style signature: int XSysMon_IsDrpLocked(XSysMon *InstancePtr);

#define XSysMon_IsEventSamplingModeSet | ( |  | InstancePtr | ) |

Value:
(((XSysMon_ReadReg((InstancePtr)->Config.BaseAddress, \
XSM_CFR0_OFFSET) & XSM_CFR0_EC_MASK) ? \
TRUE : FALSE))
XSM_CFR0_EC_MASK
#define XSM_CFR0_EC_MASK
Event driven/Continuous mode.
Definition: xsysmon_hw.h:476
XSM_CFR0_OFFSET
#define XSM_CFR0_OFFSET
Configuration Register 0.
Definition: xsysmon_hw.h:248
XSysMon_ReadReg
#define XSysMon_ReadReg(BaseAddress, RegOffset)
Read a register of the System Monitor/ADC device.
Definition: xsysmon_hw.h:666

This macro checks if the SysMonitor/ADC device is in Event Sampling mode.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  - TRUE if the device is in Event Sampling Mode.
  - FALSE if the device is in Continuous Sampling Mode.

Note
  C-Style signature: int XSysMon_IsEventSamplingMode(XSysMon *InstancePtr);

#define XSysMon_RawToTemperature | ( |  | AdcData | ) | ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)

This macro converts System Monitor/ADC Raw Data to Temperature(centigrades).

Parameters

  AdcData | is the SysMon Raw ADC Data.

Returns
  The Temperature in centigrades.

Note
  C-Style signature: float XSysMon_RawToTemperature(u32 AdcData);

Referenced by SysMonIntrExample(), and SysMonPolledExample().

#define XSysMon_RawToVoltage | ( |  | AdcData | ) | ((((float)(AdcData))* (3.0f))/65536.0f)

This macro converts System Monitor/ADC Raw Data to Voltage(volts).

Parameters

  AdcData | is the System Monitor/ADC Raw Data.

Returns
  The Voltage in volts.

Note
  C-Style signature: float XSysMon_RawToVoltage(u32 AdcData);

Referenced by SysMonAuxPolledExample().

#define XSysMon_ReadReg | ( |  | BaseAddress,
|  |  | RegOffset
| ) |  | (Xil_In32((BaseAddress) + (RegOffset)))

Read a register of the System Monitor/ADC device.

This macro provides register access to all registers using the register offsets defined above.

Parameters

  BaseAddress | contains the base address of the device.
  RegOffset | is the offset of the register to read.

Returns
  The contents of the register.

Note
  C-style Signature: u32 XSysMon_ReadReg(u32 BaseAddress, u32 RegOffset);

Referenced by SysMonLowLevelExample(), XSysMon_DisableUserOverTemp(), XSysMon_EnableUserOverTemp(), XSysMon_GetAdcClkDivisor(), XSysMon_GetAdcData(), XSysMon_GetAlarmEnables(), XSysMon_GetAlarmOutputStatus(), XSysMon_GetAlarmThreshold(), XSysMon_GetAvg(), XSysMon_GetCalibCoefficient(), XSysMon_GetCalibEnables(), XSysMon_GetMinMaxMeasurement(), XSysMon_GetOverTemp(), XSysMon_GetSeqAcqTime(), XSysMon_GetSeqAvgEnables(), XSysMon_GetSeqChEnables(), XSysMon_GetSeqInputMode(), XSysMon_GetSequencerMode(), XSysMon_GetStatus(), XSysMon_IntrClear(), XSysMon_IntrDisable(), XSysMon_IntrEnable(), XSysMon_IntrGetEnabled(), XSysMon_IntrGetStatus(), XSysMon_SetAlarmEnables(), XSysMon_SetAvg(), XSysMon_SetCalibEnables(), XSysMon_SetExtenalMux(), XSysMon_SetOverTemp(), XSysMon_SetSequencerEvent(), XSysMon_SetSequencerMode(), and XSysMon_SetSingleChParams().

#define XSysMon_TemperatureToRaw | ( |  | Temperature | ) | ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))

This macro converts Temperature in centigrades to System Monitor/ADC Raw Data.

Parameters

  Temperature | is the Temperature in centigrades to be converted to System Monitor/ADC Raw Data.

Returns
  The System Monitor/ADC Raw Data.

Note
  C-Style signature: int XSysMon_TemperatureToRaw(float Temperature);

#define XSysMon_VoltageToRaw | ( |  | Voltage | ) | ((int)((Voltage)*65536.0f/3.0f))

This macro converts Voltage in Volts to System Monitor/ADC Raw Data.

Parameters

  Voltage | is the Voltage in volts to be converted to System Monitor/ADC Raw Data.

Returns
  The System Monitor/ADC Raw Data.

Note
  C-Style signature: int XSysMon_VoltageToRaw(float Voltage);

#define XSysMon_WriteReg | ( |  | BaseAddress,
|  |  | RegOffset,
|  |  | Data
| ) |  | (Xil_Out32((BaseAddress) + (RegOffset), (Data)))

Write a register of the System Monitor/ADC device.

This macro provides register access to all registers using the register offsets defined above.

Parameters

  BaseAddress | contains the base address of the device.
  RegOffset | is the offset of the register to write.
  Data | is the value to write to the register.

Returns
  None.

Note
  C-style Signature: void XSysMon_WriteReg(u32 BaseAddress, u32 RegOffset,u32 Data)

Referenced by SysMonLowLevelExample(), XSysMon_DisableTempUpdate(), XSysMon_DisableUserOverTemp(), XSysMon_EnableTempUpdate(), XSysMon_EnableUserOverTemp(), XSysMon_IntrClear(), XSysMon_IntrDisable(), XSysMon_IntrEnable(), XSysMon_IntrGlobalDisable(), XSysMon_IntrGlobalEnable(), XSysMon_Reset(), XSysMon_ResetAdc(), XSysMon_SetAdcClkDivisor(), XSysMon_SetAlarmEnables(), XSysMon_SetAlarmThreshold(), XSysMon_SetAvg(), XSysMon_SetCalibEnables(), XSysMon_SetExtenalMux(), XSysMon_SetOverTemp(), XSysMon_SetSeqAcqTime(), XSysMon_SetSeqAvgEnables(), XSysMon_SetSeqChEnables(), XSysMon_SetSeqInputMode(), XSysMon_SetSequencerEvent(), XSysMon_SetSequencerMode(), XSysMon_SetSingleChParams(), XSysMon_SetTempWaitCycles(), and XSysMon_StartAdcConversion().

## Function Documentation

int XSysMon_CfgInitialize | ( | XSysMon * | InstancePtr,
|  | XSysMon_Config * | ConfigPtr,
|  | UINTPTR | EffectiveAddr
| ) |  |

This function initializes a specific XSysMon device/instance.

Functions in xsysmon.c.

This function must be called prior to using the System Monitor/ADC device.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  ConfigPtr | points to the XSysMon device configuration structure.
  EffectiveAddr | is the device base address in the virtual memory address space. If the address translation is not used then the physical address is passed. Unexpected errors may occur if the address mapping is changed after this function is invoked.

Returns
  - XST_SUCCESS if successful.

Note
  The user needs to first call the XSysMon_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XSysMon_CfgInitialize() API.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon_Config::DeviceId, XSysMon_Config::IncludeInterrupt, XSysMon::IsReady, XSysMon::Mask, XSM_CONVST_WAITCYCLES_DEFAULT, XSM_CONVST_WAITCYCLES_SHIFT, and XSysMon_Reset().

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), SysMonPolledExample(), and SysMonSingleChannelIntrExample().

void XSysMon_DisableTempUpdate | ( | XSysMon * | InstancePtr | ) |

This function disables the Temperature updation logic for TEMP_OUT port.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  None.

Note
  None

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSysMon::Mask, XSM_CONVST_OFFSET, XSM_CONVST_TEMPUPDT_MASK, and XSysMon_WriteReg.

void XSysMon_DisableUserOverTemp | ( | XSysMon * | InstancePtr | ) |

This function disables programming of the powerdown temperature for the OverTemp signal in the OT Powerdown register.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  None.

Note
  This API should be used only with V6 SysMon/7 Series and Zynq XADC since the upper threshold of OverTemp is programmable in only V6 SysMon/7 Series and Zynq XADC.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_ATR_OT_UPPER_ENB_MASK, XSM_ATR_OT_UPPER_OFFSET, XSysMon_ReadReg, and XSysMon_WriteReg.

void XSysMon_EnableTempUpdate | ( | XSysMon * | InstancePtr | ) |

This function enables the Temperature updation logic so that temperature can be sent over TEMP_OUT port.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  None.

Note
  None

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSysMon::Mask, XSM_CONVST_OFFSET, XSM_CONVST_TEMPUPDT_MASK, and XSysMon_WriteReg.

void XSysMon_EnableUserOverTemp | ( | XSysMon * | InstancePtr | ) |

This function enables programming of the powerdown temperature for the OverTemp signal in the OT Powerdown register.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  None.

Note
  This API should be used only with V6/7 Series since the upper threshold of OverTemp is programmable in only V6 SysMon/7 Series and Zynq XADC.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_ATR_OT_UPPER_ENB_MASK, XSM_ATR_OT_UPPER_ENB_VAL, XSM_ATR_OT_UPPER_OFFSET, XSysMon_ReadReg, and XSysMon_WriteReg.

u8 XSysMon_GetAdcClkDivisor | ( | XSysMon * | InstancePtr | ) |

The function gets the ADCCLK divisor from the Configuration Register 2.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  The divisor read from the Configuration Register 2.

Note
  The ADCCLK is an internal clock used by the ADC and is synchronized to the DCLK clock. The ADCCLK is equal to DCLK divided by the user selection in the Configuration Register 2.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_CFR2_CD_SHIFT, XSM_CFR2_OFFSET, and XSysMon_ReadReg.

u16 XSysMon_GetAdcData | ( | XSysMon * | InstancePtr,
|  | u8 | Channel
| ) |  |

Get the ADC converted data for the specified channel.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  Channel | is the channel number. Use the XSM_CH_* defined in the file xsysmon.h. The valid channels are 0 to 5 and 16 to 31 for all the device families. Channel 6 is valid for 7 Series and Zynq. Channel 13, 14, 15 are valid for Zynq. 32 to 35 are valid for Ultrascale.

Returns
  A 16-bit value representing the ADC converted data for the specified channel. The System Monitor/ADC device guarantees a 10 bit resolution for the ADC converted data and data is the 10 MSB bits of the 16 data read from the device.

Note
  The channels 7,8,9 are used for calibration of the device and hence there is no associated data with this channel. Please make sure that the proper channel number is passed.

References XSysMon::IsReady, XSM_CH_AUX_MAX, XSM_CH_VBRAM, XSM_CH_VCCPINT, XSM_CH_VUSR0, XSM_CH_VUSR3, XSM_TEMP_OFFSET, XSM_VUSR0_OFFSET, and XSysMon_ReadReg.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), SysMonPolledExample(), and SysMonSingleChannelIntrExample().

u32 XSysMon_GetAlarmEnables | ( | XSysMon * | InstancePtr | ) |

This function gets the status of the alarm output enables in the Configuration Register 1.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  This is the bit-mask of the enabled alarm outputs in the Configuration Register 1. Use the masks XSM_CFR_ALM_*, XSM_CFR_ALM*_* and XSM_CFR_OT_MASK defined in xsysmon_hw.h to interpret the returned value.

Bit positions of 1 indicate that the alarm output is enabled. Bit positions of 0 indicate that the alarm output is disabled.

Note
  The implementation of the alarm enables in the Configuration register 1 is such that alarms for the bit positions of 1 will be disabled and alarms for bit positions of 0 will be enabled. The enabled alarm outputs returned by this function is the negated value of the the data read from the Configuration Register 1.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_CFR1_ALM_ALL_MASK, XSM_CFR1_OFFSET, XSM_CFR3_ALM_ALL_MASK, and XSysMon_ReadReg.

u32 XSysMon_GetAlarmOutputStatus | ( | XSysMon * | InstancePtr | ) |

This function reads the contents of Alarm Output Register.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  A 32-bit value read from the Alarm Output Register. Use the XSM_AOR_*_MASK constants defined in xsysmon_hw.h to interpret the value.

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_AOR_ALARM_ALL_MASK, XSM_AOR_OFFSET, and XSysMon_ReadReg.

Referenced by SysMonPolledExample().

u16 XSysMon_GetAlarmThreshold | ( | XSysMon * | InstancePtr,
|  | u8 | AlarmThrReg
| ) |  |

This function returns the contents of the specified Alarm Threshold Register.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  AlarmThrReg | is the index of an Alarm Threshold Register to be read. Use XSM_ATR_* constants defined in xsysmon.h to specify the index.

Returns
  A 16-bit value representing the contents of the selected Alarm Threshold Register.

Note
  Over Temperature upper threshold is programmable only in V6 and 7 Series XADC BRAM high and low voltage threshold registers are available only in 7 Series and Zynq XADC. All the remaining Alarm Threshold registers specified by the constants XSM_ATR_*, are available in all the families of the Sysmon.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_ATR_TEMP_UPPER_OFFSET, XSM_ATR_VUSR0_LOWER, XSM_ATR_VUSR3_LOWER, XSM_ATR_VUSR3_UPPER, and XSysMon_ReadReg.

Referenced by XSysMon_SelfTest().

u8 XSysMon_GetAvg | ( | XSysMon * | InstancePtr | ) |

This function returns the number of samples of averaging configured for all the channels in the Configuration Register 0.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  The averaging read from the Configuration Register 0 is returned. Use the XSM_AVG_* bit definitions defined in xsysmon.h file to interpret the returned value :
  - XSM_AVG_0_SAMPLES means no averaging
  - XSM_AVG_16_SAMPLES means 16 samples of averaging
  - XSM_AVG_64_SAMPLES means 64 samples of averaging
  - XSM_AVG_256_SAMPLES means 256 samples of averaging

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_CFR0_AVG_SHIFT, XSM_CFR0_AVG_VALID_MASK, XSM_CFR0_OFFSET, and XSysMon_ReadReg.

u16 XSysMon_GetCalibCoefficient | ( | XSysMon * | InstancePtr,
|  | u8 | CoeffType
| ) |  |

This function gets the calibration coefficient data for the specified parameter.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  CoeffType | specifies the calibration coefficient to be read. Use XSM_CALIB_* constants defined in xsysmon.h to specify the calibration coefficient to be read.

Returns
  A 16-bit value representing the calibration coefficient. The System Monitor/ADC device guarantees a 10 bit resolution for the ADC converted data and data is the 10 MSB bits of the 16 data read from the device.

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_CALIB_GAIN_ERROR_COEFF, XSM_SUPPLY_CALIB_OFFSET, and XSysMon_ReadReg.

u16 XSysMon_GetCalibEnables | ( | XSysMon * | InstancePtr | ) |

This function reads the value of the calibration enables from the Configuration Register 1.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  The value of the calibration enables in the Configuration Register 1 :
  - XSM_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction
  - XSM_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset correction
  - XSM_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset correction
  - XSM_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor gain and offset correction
  - XSM_CFR1_CAL_DISABLE_MASK : No Calibration

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_CFR1_CAL_VALID_MASK, XSM_CFR1_OFFSET, and XSysMon_ReadReg.

u16 XSysMon_GetMinMaxMeasurement | ( | XSysMon * | InstancePtr,
|  | u8 | MeasurementType
| ) |  |

This function reads the Minimum/Maximum measurement for one of the following parameters :

        - Minimum Temperature (XSM_MIN_TEMP) - All families
        - Minimum VCCINT (XSM_MIN_VCCINT) - All families
        - Minimum VCCAUX (XSM_MIN_VCCAUX) - All families
        - Maximum Temperature (XSM_MAX_TEMP) - All families
        - Maximum VCCINT (XSM_MAX_VCCINT) - All families
        - Maximum VCCAUX (XSM_MAX_VCCAUX) - All families
        - Maximum VCCBRAM (XSM_MAX_VCCBRAM) - 7 series and Zynq only
        - Minimum VCCBRAM (XSM_MIN_VCCBRAM) - 7 series and Zynq only
                - Maximum VCCPINT (XSM_MAX_VCCPINT) - Zynq only
                - Maximum VCCPAUX (XSM_MAX_VCCPAUX) - Zynq only
                - Maximum VCCPDRO (XSM_MAX_VCCPDRO) - Zynq only
                - Minimum VCCPINT (XSM_MIN_VCCPINT) - Zynq only
                - Minimum VCCPAUX (XSM_MIN_VCCPAUX) - Zynq only
                - Minimum VCCPDRO (XSM_MIN_VCCPDRO) - Zynq only
        - Maximum VUSER0 (XSM_MAX_VUSR0) - Ultrascale
        - Maximum VUSER1 (XSM_MAX_VUSR1) - Ultrascale
        - Maximum VUSER2 (XSM_MAX_VUSR2) - Ultrascale
        - Maximum VUSER3 (XSM_MAX_VUSR3) - Ultrascale
        - Minimum VUSER0 (XSM_MIN_VUSR0) - Ultrascale
        - Minimum VUSER1 (XSM_MIN_VUSR1) - Ultrascale
        - Minimum VUSER2 (XSM_MIN_VUSR2) - Ultrascale
        - Minimum VUSER3 (XSM_MIN_VUSR3) - Ultrascale

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  MeasurementType | specifies the parameter for which the Minimum/Maximum measurement has to be read. Use XSM_MAX_* and XSM_MIN_* constants defined in xsysmon.h to specify the data to be read.

Returns
  A 16-bit value representing the maximum/minimum measurement for specified parameter. The System Monitor/ADC device guarantees a 10 bit resolution for the ADC converted data and data is the 10 MSB bits of 16 bit data read from the device.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_MAX_TEMP_OFFSET, XSM_MAX_VCCPDRO, XSM_MAX_VUSR0, XSM_MAX_VUSR3, XSM_MIN_VCCPDRO, XSM_MIN_VCCPINT, XSM_MIN_VUSR0, XSM_MIN_VUSR3, and XSysMon_ReadReg.

Referenced by SysMonPolledExample().

u16 XSysMon_GetOverTemp | ( | XSysMon * | InstancePtr | ) |

This function returns the powerdown temperature of the OverTemp signal in the OT Powerdown register.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  A 12-bit OT Upper Alarm Register powerdown value.

Note
  This API has been deprecated. Use XSysMon_GetAlarmThreshold(), instead. This API should be used only with V6/7 Series since the upper threshold of OverTemp is programmable in only V6 SysMon/7 Series and Zynq XADC.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_ATR_OT_UPPER_OFFSET, XSM_ATR_OT_UPPER_VAL_SHIFT, and XSysMon_ReadReg.

u32 XSysMon_GetSeqAcqTime | ( | XSysMon * | InstancePtr | ) |

This function gets the status of acquisition from the ADC Channel Acquisition Time Sequencer Registers.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  The acquisition time for all the channels. Use XSM_SEQ_CH__* defined in xsysmon_hw.h to interpret the Channel numbers. Bit masks of 1 are the channels for which acquisition cycles are extended and bit mask of 0 are the channels for which acquisition cycles are not extended.

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_SEQ06_CH_VALID_MASK, XSM_SEQ06_OFFSET, XSM_SEQ07_CH_VALID_MASK, XSM_SEQ07_OFFSET, XSM_SEQ_CH_AUX_SHIFT, and XSysMon_ReadReg.

u64 XSysMon_GetSeqAvgEnables | ( | XSysMon * | InstancePtr | ) |

This function returns the channels for which the averaging has been enabled in the ADC Channel Averaging Enables Sequencer Registers.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  The status of averaging (enabled/disabled) for all the channels. Use XSM_SEQ_CH__* defined in xsysmon_hw.h to interpret the Channel numbers. Bit masks of 1 are the channels for which averaging is enabled and bit mask of 0 are the channels for averaging is disabled.

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_SEQ02_CH_VALID_MASK, XSM_SEQ02_OFFSET, XSM_SEQ03_CH_VALID_MASK, XSM_SEQ03_OFFSET, XSM_SEQ09_CH_VALID_MASK, XSM_SEQ09_OFFSET, XSM_SEQ_CH_AUX_SHIFT, XSM_SEQ_CH_VUSR_SHIFT, and XSysMon_ReadReg.

u64 XSysMon_GetSeqChEnables | ( | XSysMon * | InstancePtr | ) |

This function gets the channel enable bits status from the ADC Channel Selection Sequencer Registers.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  Gets the channel enable bits. Use XSM_SEQ_CH_* defined in xsysmon_hw.h to interpret the Channel numbers. Bit masks of 1 are the channels that are enabled and bit mask of 0 are the channels that are disabled.
  None.

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_SEQ00_CH_VALID_MASK, XSM_SEQ00_OFFSET, XSM_SEQ01_CH_VALID_MASK, XSM_SEQ01_OFFSET, XSM_SEQ08_CH_VALID_MASK, XSM_SEQ08_OFFSET, XSM_SEQ_CH_AUX_SHIFT, XSM_SEQ_CH_VUSR_SHIFT, and XSysMon_ReadReg.

u32 XSysMon_GetSeqInputMode | ( | XSysMon * | InstancePtr | ) |

This function gets the Analog input mode for all the channels from the ADC Channel Analog-Input Mode Sequencer Registers.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  The input mode for all the channels. Use XSM_SEQ_CH_* defined in xsysmon_hw.h to interpret the Channel numbers. Bit masks of 1 are the channels for which input mode is differential and bit mask of 0 are the channels for which input mode is unipolar.

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_SEQ04_CH_VALID_MASK, XSM_SEQ04_OFFSET, XSM_SEQ05_CH_VALID_MASK, XSM_SEQ05_OFFSET, XSM_SEQ_CH_AUX_SHIFT, and XSysMon_ReadReg.

u8 XSysMon_GetSequencerMode | ( | XSysMon * | InstancePtr | ) |

This function gets the channel sequencer mode from the Configuration Register 1.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  The channel sequencer mode :
  - XSM_SEQ_MODE_SAFE : Default safe mode
  - XSM_SEQ_MODE_ONEPASS : One pass through sequence
  - XSM_SEQ_MODE_CONTINPASS : Continuous channel sequencing
  - XSM_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
  - XSM_SEQ_MODE_SIMUL : Simultaneous sampling mode
  - XSM_SEQ_MODE_INDEPENDENT : Independent mode

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_CFR1_OFFSET, XSM_CFR1_SEQ_SHIFT, XSM_CFR1_SEQ_VALID_MASK, and XSysMon_ReadReg.

Referenced by XSysMon_SetSeqAcqTime(), XSysMon_SetSeqAvgEnables(), XSysMon_SetSeqChEnables(), XSysMon_SetSeqInputMode(), and XSysMon_SetSingleChParams().

u32 XSysMon_GetStatus | ( | XSysMon * | InstancePtr | ) |

The functions reads the contents of the Status Register.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  A 32-bit value representing the contents of the Status Register. Use the XSM_SR_*_MASK constants defined in xsysmon_hw.h to interpret the returned value.

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_SR_OFFSET, and XSysMon_ReadReg.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), and SysMonPolledExample().

void XSysMon_IntrClear | ( | XSysMon * | InstancePtr,
|  | u32 | Mask
| ) |  |

This function clears the specified interrupts in the Interrupt Status Register (IPISR).

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  Mask | is the bit-mask of the interrupts to be cleared. Bit positions of 1 will be cleared. Bit positions of 0 will not change the previous interrupt status. This mask is formed by OR'ing XSM_IPIXR_* bits which are defined in xsysmon_hw.h.

Returns
  None.

Note
  The device must be configured at hardware build time to include interrupt component for this function to work.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon_Config::IncludeInterrupt, XSysMon::IsReady, XSM_IPISR_OFFSET, XSM_IPIXR_ALL_MASK, XSysMon_ReadReg, and XSysMon_WriteReg.

Referenced by SysMonIntrExample(), and SysMonSingleChannelIntrExample().

void XSysMon_IntrDisable | ( | XSysMon * | InstancePtr,
|  | u32 | Mask
| ) |  |

This function disables the specified interrupts in the device.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  Mask | is the bit-mask of the interrupts to be disabled. Bit positions of 1 will be disabled. Bit positions of 0 will keep the previous setting. This mask is formed by OR'ing XSM_IPIXR_* bits defined in xsysmon_hw.h.

Returns
  None.

Note
  The device must be configured at hardware build time to include interrupt component for this function to work.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon_Config::IncludeInterrupt, XSysMon::IsReady, XSM_IPIER_OFFSET, XSM_IPIXR_ALL_MASK, XSysMon_ReadReg, and XSysMon_WriteReg.

void XSysMon_IntrEnable | ( | XSysMon * | InstancePtr,
|  | u32 | Mask
| ) |  |

This function enables the specified interrupts in the device.

Interrupts enabled using this function will not occur until the global interrupt enable bit is set by using the XSysMon_IntrGlobalEnable()function.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  Mask | is the bit-mask of the interrupts to be enabled. Bit positions of 1 will be enabled. Bit positions of 0 will keep the previous setting. This mask is formed by OR'ing XSM_IPIXR_* bits defined in xsysmon_hw.h.

Returns
  None.

Note
  The device must be configured at hardware build time to include interrupt component for this function to work.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon_Config::IncludeInterrupt, XSysMon::IsReady, XSM_IPIER_OFFSET, XSM_IPIXR_ALL_MASK, XSysMon_ReadReg, and XSysMon_WriteReg.

Referenced by SysMonIntrExample(), and SysMonSingleChannelIntrExample().

u32 XSysMon_IntrGetEnabled | ( | XSysMon * | InstancePtr | ) |

This function returns the enabled interrupts read from the Interrupt Enable Register (IPIER).

Use the XSM_IPIXR_* constants defined in xsysmon_hw.h to interpret the returned value.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  A 32-bit value representing the contents of the IPIER.

Note
  The device must be configured at hardware build time to include interrupt component for this function to work.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon_Config::IncludeInterrupt, XSysMon::IsReady, XSM_IPIER_OFFSET, XSM_IPIXR_ALL_MASK, and XSysMon_ReadReg.

u32 XSysMon_IntrGetStatus | ( | XSysMon * | InstancePtr | ) |

This function returns the interrupt status read from Interrupt Status Register(IPISR).

Use the XSM_IPIXR_* constants defined in xsysmon_hw.h to interpret the returned value.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  A 32-bit value representing the contents of the IPISR.

Note
  The device must be configured at hardware build time to include interrupt component for this function to work.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon_Config::IncludeInterrupt, XSysMon::IsReady, XSM_IPISR_OFFSET, XSM_IPIXR_ALL_MASK, and XSysMon_ReadReg.

Referenced by SysMonIntrExample(), and SysMonSingleChannelIntrExample().

void XSysMon_IntrGlobalDisable | ( | XSysMon * | InstancePtr | ) |

This function disables the global interrupt in the Global Interrupt Enable Register (GIER) so that the interrupt output from the System Monitor/ADC device is disabled.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  None.

Note
  The device must be configured at hardware build time to include interrupt component for this function to work.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon_Config::IncludeInterrupt, XSysMon::IsReady, XSM_GIER_OFFSET, and XSysMon_WriteReg.

Referenced by SysMonIntrExample(), and SysMonSingleChannelIntrExample().

void XSysMon_IntrGlobalEnable | ( | XSysMon * | InstancePtr | ) |

Functions in xsysmon_intr.c.

This function enables the global interrupt in the Global Interrupt Enable Register (GIER) so that the interrupt output from the System Monitor/ADC device is enabled.

Interrupts enabled using XSysMon_IntrEnable() will not occur until the global interrupt enable bit is set by using this function.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  None.

Note
  The device must be configured at hardware build time to include interrupt component for this function to work.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon_Config::IncludeInterrupt, XSysMon::IsReady, XSM_GIER_GIE_MASK, XSM_GIER_OFFSET, and XSysMon_WriteReg.

Referenced by SysMonIntrExample(), and SysMonSingleChannelIntrExample().

XSysMon_Config * XSysMon_LookupConfig | ( | u16 | DeviceId | ) |

Functions in xsysmon_sinit.c.

This function looks up the device configuration based on the unique device ID.

The table XSysMon_ConfigTable contains the configuration info for each device in the system.

Parameters

  DeviceId | contains the ID of the device for which the device configuration pointer is to be returned.

Returns
  - A pointer to the configuration found.
  - NULL if the specified device ID was not found.

Note
  None.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), SysMonPolledExample(), and SysMonSingleChannelIntrExample().

void XSysMon_Reset | ( | XSysMon * | InstancePtr | ) |

This function forces the software reset of the complete SystemMonitor/ADC Hard Macro and the SYSMON ADC Core Logic.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  None.

Note
  The Control registers in the SystemMonitor/ADC Hard Macro are not affected by this reset, only the Status registers are reset. Refer to the device data sheet for the device status and register values after the reset. Use the XSysMon_ResetAdc() to reset only the SystemMonitor/ADC Hard Macro.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_SRR_IPRST_MASK, XSM_SRR_OFFSET, and XSysMon_WriteReg.

Referenced by XSysMon_CfgInitialize(), and XSysMon_SelfTest().

void XSysMon_ResetAdc | ( | XSysMon * | InstancePtr | ) |

This function resets the SystemMonitor/ADC Hard Macro in the device.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  None.

Note
  The Control registers in the SystemMonitor/ADC Hard Macro are not affected by this reset, only the Status registers are reset. This reset causes the ADC to begin with a new conversion. Refer to the device data sheet for the device status and register values after the reset. Use the XSysMon_Reset() API to reset both the SystemMonitor/ADC Hard Macro and the SYSMON ADC Core Logic.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_ARR_OFFSET, XSM_ARR_RST_MASK, and XSysMon_WriteReg.

int XSysMon_SelfTest | ( | XSysMon * | InstancePtr | ) |

Functions in xsysmon_selftest.c.

Run a self-test on the driver/device.

The test

- Resets the device,
- Writes a value into the Alarm Threshold register and reads it back for comparison.
- Resets the device again.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  - XST_SUCCESS if the value read from the Alarm Threshold register is the same as the value written.
  - XST_FAILURE Otherwise

Note
  This is a destructive test in that resets of the device are performed. Refer to the device specification for the device status after the reset operation.

References XSysMon::IsReady, XSM_ATR_VCCINT_UPPER, XSysMon_GetAlarmThreshold(), XSysMon_Reset(), and XSysMon_SetAlarmThreshold().

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), SysMonPolledExample(), and SysMonSingleChannelIntrExample().

void XSysMon_SetAdcClkDivisor | ( | XSysMon * | InstancePtr,
|  | u8 | Divisor
| ) |  |

The function sets the frequency of the ADCCLK by configuring the DCLK to ADCCLK ratio in the Configuration Register #2.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  Divisor | is clock divisor used to derive ADCCLK from DCLK. Valid values of the divisor are 8 to 255 for V5 SysMon. 0 to 255 for V6/7 Series and Zynq XADC. Values 0, 1, 2 are all mapped to 2. Refer to the device specification for more details.

Returns
  None.

Note
  - The ADCCLK is an internal clock used by the ADC and is synchronized to the DCLK clock. The ADCCLK is equal to DCLK divided by the user selection in the Configuration Register 2.
  - There is no Assert on the minimum value of the Divisor. Users must take care such that the minimum value of Divisor used is 8, in case of V5 SysMon.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_CFR2_CD_SHIFT, XSM_CFR2_OFFSET, and XSysMon_WriteReg.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), SysMonPolledExample(), and SysMonSingleChannelIntrExample().

void XSysMon_SetAlarmEnables | ( | XSysMon * | InstancePtr,
|  | u32 | AlmEnableMask
| ) |  |

This function enables the alarm outputs for the specified alarms in the Configuration Registers 1 and 3:

        - OT for Over Temperature (XSM_CFR_OT_MASK)
        - ALM0 for On board Temperature (XSM_CFR_ALM_TEMP_MASK)
        - ALM1 for VCCINT (XSM_CFR_ALM_VCCINT_MASK)
        - ALM2 for VCCAUX (XSM_CFR_ALM_VCCAUX_MASK)
                - ALM3 for VBRAM (XSM_CFR_ALM_VBRAM_MASK)for 7 Series and Zynq
                - ALM4 for VCCPINT (XSM_CFR_ALM_VCCPINT_MASK) for Zynq
        - ALM5 for VCCPAUX (XSM_CFR_ALM_VCCPAUX_MASK) for Zynq
                - ALM6 for VCCPDRO (XSM_CFR_ALM_VCCPDRO_MASK) for Zynq
                - ALM8 for VUSER0 (XSM_CFR_ALM_VUSR0_MASK) for Ultrascale
                - ALM9 for VUSER1 (XSM_CFR_ALM_VUSR1_MASK) for Ultrascale
                - ALM10 for VUSER2 (XSM_CFR_ALM_VUSR2_MASK) for Ultrascale
                - ALM11 for VUSER3 (XSM_CFR_ALM_VUSR3_MASK) for Ultrascale

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  AlmEnableMask | is the bit-mask of the alarm outputs to be enabled in the Configuration Register 1. Bit positions of 1 will be enabled. Bit positions of 0 will be disabled. This mask is formed by OR'ing XSM_CFR_ALM_*_MASK, XSM_CFR_ALM_*_MASK and XSM_CFR_OT_MASK masks defined in xsysmon_hw.h.

Returns
  None.

Note
  The implementation of the alarm enables in the Configuration register 1 is such that the alarms for bit positions of 1 will be disabled and alarms for bit positions of 0 will be enabled. The alarm outputs specified by the AlmEnableMask are negated before writing to the Configuration Register 1.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_CFR1_ALM_ALL_MASK, XSM_CFR1_OFFSET, XSM_CFR3_ALM_ALL_MASK, XSysMon_ReadReg, and XSysMon_WriteReg.

Referenced by SysMonIntrExample(), SysMonPolledExample(), and SysMonSingleChannelIntrExample().

void XSysMon_SetAlarmThreshold | ( | XSysMon * | InstancePtr,
|  | u8 | AlarmThrReg,
|  | u16 | Value
| ) |  |

This functions sets the contents of the given Alarm Threshold Register.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  AlarmThrReg | is the index of an Alarm Threshold Register to be set. Use XSM_ATR_* constants defined in xsysmon.h to specify the index.
  Value | is the 16-bit threshold value to write into the register.

Returns
  None.

Note
  Over Temperature upper threshold is programmable only in V6, 7 Series/Zynq XADC and UltraScale. BRAM high and low voltage threshold registers are available only in 7 Series XADC and UltraScale. VUSER0 to VUSER3 threshold registers are available only in UltraScale. All the remaining Alarm Threshold registers specified by the constants XSM_ATR_*, are available in all the families of the Sysmon.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_ATR_TEMP_UPPER_OFFSET, XSM_ATR_VUSR0_LOWER, XSM_ATR_VUSR3_LOWER, XSM_ATR_VUSR3_UPPER, and XSysMon_WriteReg.

Referenced by SysMonIntrExample(), SysMonPolledExample(), SysMonSingleChannelIntrExample(), and XSysMon_SelfTest().

void XSysMon_SetAvg | ( | XSysMon * | InstancePtr,
|  | u8 | Average
| ) |  |

This function sets the number of samples of averaging that is to be done for all the channels in both the single channel mode and sequence mode of operations.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  Average | is the number of samples of averaging programmed to the Configuration Register 0. Use the XSM_AVG_* definitions defined in xsysmon.h file : XSM_AVG_0_SAMPLES for no averaging XSM_AVG_16_SAMPLES for 16 samples of averaging XSM_AVG_64_SAMPLES for 64 samples of averaging XSM_AVG_256_SAMPLES for 256 samples of averaging

Returns
  None.

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_AVG_256_SAMPLES, XSM_CFR0_AVG_SHIFT, XSM_CFR0_AVG_VALID_MASK, XSM_CFR0_OFFSET, XSysMon_ReadReg, and XSysMon_WriteReg.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), and SysMonPolledExample().

void XSysMon_SetCalibEnables | ( | XSysMon * | InstancePtr,
|  | u16 | Calibration
| ) |  |

This function enables the specified calibration in the Configuration Register 1 :

      - XSM_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction
      - XSM_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset
      correction
      - XSM_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor
      offset correction
      - XSM_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor
      gain and offset correction
      - XSM_CFR1_CAL_DISABLE_MASK : No Calibration

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  Calibration | is the Calibration to be applied. Use XSM_CFR1_CAL*_* bits defined in xsysmon_hw.h. Multiple calibrations can be enabled at a time by oring the XSM_CFR1_CAL_ADC_* and XSM_CFR1_CAL_PS_* bits. Calibration can be disabled by specifying XSM_CFR1_CAL_DISABLE_MASK;

Returns
  None.

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_CFR1_CAL_ADC_OFFSET_MASK, XSM_CFR1_CAL_DISABLE_MASK, XSM_CFR1_CAL_VALID_MASK, XSM_CFR1_OFFSET, XSysMon_ReadReg, and XSysMon_WriteReg.

void XSysMon_SetExtenalMux | ( | XSysMon * | InstancePtr,
|  | u8 | Channel
| ) |  |

The function enables the external mux and connects a channel to the mux.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  Channel | is the channel number used to connect to the external Mux. The valid channels are 0 to 6, 8, and 16 to 31.

Returns
  - XST_SUCCESS if the given values were written successfully to the Configuration Register 0.
  - XST_FAILURE if the channel sequencer is enabled or the input parameters are not valid for the selected channel.

Note
  The External Mux is only available in 7 Series and Zynq XADC. This API should be used only with 7 Series and Zynq XADC.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_CFR0_CHANNEL_MASK, XSM_CFR0_MUX_MASK, XSM_CFR0_OFFSET, XSM_CH_AUX_MAX, XSM_CH_AUX_MIN, XSM_CH_VREFN, XSysMon_ReadReg, and XSysMon_WriteReg.

Referenced by SysMonAuxPolledExample().

void XSysMon_SetOverTemp | ( | XSysMon * | InstancePtr,
|  | u16 | Value
| ) |  |

This function sets the powerdown temperature for the OverTemp signal in the OT Powerdown register.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  Value | is the 16-bit OT Upper Alarm Register powerdown value. Valid values are 0 to 0x0FFF.

Returns
  None.

Note
  This API has been deprecated. Use XSysMon_SetAlarmThreshold(), instead. This API should be used only with V6/7 Series since the upper threshold of OverTemp is programmable in in only V6 SysMon/7 Series and Zynq XADC.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_ATR_OT_UPPER_OFFSET, XSM_ATR_OT_UPPER_VAL_MASK, XSM_ATR_OT_UPPER_VAL_MAX, XSM_ATR_OT_UPPER_VAL_SHIFT, XSysMon_ReadReg, and XSysMon_WriteReg.

int XSysMon_SetSeqAcqTime | ( | XSysMon * | InstancePtr,
|  | u32 | AcqCyclesChMask
| ) |  |

This function sets the number of Acquisition cycles in the ADC Channel Acquisition Time Sequencer Registers.

The sequencer must be in the Safe Mode before writing to these registers.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  AcqCyclesChMask | is the bit mask of all the channels for which the number of acquisition cycles is to be extended. Use XSM_SEQ_CH__* defined in xsysmon_hw.h to specify the Channel numbers. Acquisition cycles will be extended to 10 ADCCLK cycles for bit masks of 1 and will be the default 4 ADCCLK cycles for bit masks of 0. The AcqCyclesChMask is a 32 bit mask that is written to the two 16 bit ADC Channel Acquisition Time Sequencer Registers.

Returns
  - XST_SUCCESS if the given values were written successfully to the Channel Sequencer Registers.
  - XST_FAILURE if the channel sequencer is enabled.

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_SEQ06_CH_VALID_MASK, XSM_SEQ06_OFFSET, XSM_SEQ07_CH_VALID_MASK, XSM_SEQ07_OFFSET, XSM_SEQ_CH_AUX_SHIFT, XSM_SEQ_MODE_SAFE, XSysMon_GetSequencerMode(), and XSysMon_WriteReg.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), and SysMonPolledExample().

int XSysMon_SetSeqAvgEnables | ( | XSysMon * | InstancePtr,
|  | u64 | AvgEnableChMask
| ) |  |

This function enables the averaging for the specified channels in the ADC Channel Averaging Enable Sequencer Registers.

The sequencer must be in the Safe Mode before writing to these registers.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  AvgEnableChMask | is the bit mask of all the channels for which averaging is to be enabled. Use XSM_SEQ_CH__* defined in xsysmon_hw.h to specify the Channel numbers. Averaging will be enabled for bit masks of 1 and disabled for bit mask of 0. The AvgEnableChMask is a 64 bit mask that is written to the three 16 bit ADC Channel Averaging Enable Sequencer Registers.

Returns
  - XST_SUCCESS if the given values were written successfully to the ADC Channel Averaging Enables Sequencer Registers.
  - XST_FAILURE if the channel sequencer is enabled.

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_SEQ02_CH_VALID_MASK, XSM_SEQ02_OFFSET, XSM_SEQ03_CH_VALID_MASK, XSM_SEQ03_OFFSET, XSM_SEQ09_CH_VALID_MASK, XSM_SEQ09_OFFSET, XSM_SEQ_CH_AUX_SHIFT, XSM_SEQ_CH_VUSR_SHIFT, XSM_SEQ_MODE_SAFE, XSysMon_GetSequencerMode(), and XSysMon_WriteReg.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), and SysMonPolledExample().

int XSysMon_SetSeqChEnables | ( | XSysMon * | InstancePtr,
|  | u64 | ChEnableMask
| ) |  |

This function enables the specified channels in the ADC Channel Selection Sequencer Registers.

The sequencer must be in the Safe Mode before writing to these registers.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  ChEnableMask | is the bit mask of all the channels to be enabled. Use XSM_SEQ_CH_* defined in xsysmon_hw.h to specify the Channel numbers. Bit masks of 1 will be enabled and bit mask of 0 will be disabled. The ChEnableMask is a 64 bit mask that is written to the three 16 bit ADC Channel Selection Sequencer Registers.

Returns
  - XST_SUCCESS if the given values were written successfully to the ADC Channel Selection Sequencer Registers.
  - XST_FAILURE if the channel sequencer is enabled.

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_SEQ00_CH_VALID_MASK, XSM_SEQ00_OFFSET, XSM_SEQ01_CH_VALID_MASK, XSM_SEQ01_OFFSET, XSM_SEQ08_CH_VALID_MASK, XSM_SEQ08_OFFSET, XSM_SEQ_CH_AUX_SHIFT, XSM_SEQ_CH_VUSR_SHIFT, XSM_SEQ_MODE_SAFE, XSysMon_GetSequencerMode(), and XSysMon_WriteReg.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), and SysMonPolledExample().

int XSysMon_SetSeqInputMode | ( | XSysMon * | InstancePtr,
|  | u32 | InputModeChMask
| ) |  |

This function sets the Analog input mode for the specified channels in the ADC Channel Analog-Input Mode Sequencer Registers.

The sequencer must be in the Safe Mode before writing to these registers.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  InputModeChMask | is the bit mask of all the channels for which the input mode is differential mode. Use XSM_SEQ_CH__* defined in xsysmon_hw.h to specify the channel numbers. Differential input mode will be set for bit masks of 1 and unipolar input mode for bit masks of 0. The InputModeChMask is a 32 bit mask that is written to the two 16 bit ADC Channel Analog-Input Mode Sequencer Registers.

Returns
  - XST_SUCCESS if the given values were written successfully to the ADC Channel Analog-Input Mode Sequencer Registers.
  - XST_FAILURE if the channel sequencer is enabled.

Note
  None.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_SEQ04_CH_VALID_MASK, XSM_SEQ04_OFFSET, XSM_SEQ05_CH_VALID_MASK, XSM_SEQ05_OFFSET, XSM_SEQ_CH_AUX_SHIFT, XSM_SEQ_MODE_SAFE, XSysMon_GetSequencerMode(), and XSysMon_WriteReg.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), and SysMonPolledExample().

void XSysMon_SetSequencerEvent | ( | XSysMon * | InstancePtr,
|  | int | IsEventMode
| ) |  |

The function enables the Event mode or Continuous mode in the sequencer mode.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  IsEventMode | is a boolean parameter that specifies continuous sampling (specify FALSE) or event driven sampling mode (specify TRUE) for the given channel.

Returns
  None.

Note
  The Event mode is only available in 7 Series XADC and Zynq. This API should be used only with 7 Series XADC and Zynq .

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_CFR0_EC_MASK, XSM_CFR0_OFFSET, XSysMon_ReadReg, and XSysMon_WriteReg.

void XSysMon_SetSequencerMode | ( | XSysMon * | InstancePtr,
|  | u8 | SequencerMode
| ) |  |

This function sets the specified Channel Sequencer Mode in the Configuration Register 1 :

        - Default safe mode (XSM_SEQ_MODE_SAFE)
        - One pass through sequence (XSM_SEQ_MODE_ONEPASS)
        - Continuous channel sequencing (XSM_SEQ_MODE_CONTINPASS)
        - Single Channel/Sequencer off (XSM_SEQ_MODE_SINGCHAN)
        - Simultaneous sampling mode (XSM_SEQ_MODE_SIMUL)
        - Independent mode (XSM_SEQ_MODE_INDEPENDENT)

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  SequencerMode | is the sequencer mode to be set. Use XSM_SEQ_MODE_* bits defined in xsysmon.h.

Returns
  None.

Note
  Only one of the modes can be enabled at a time.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_CFR1_OFFSET, XSM_CFR1_SEQ_SHIFT, XSM_CFR1_SEQ_VALID_MASK, XSM_SEQ_MODE_INDEPENDENT, XSM_SEQ_MODE_SIMUL, XSysMon_ReadReg, and XSysMon_WriteReg.

Referenced by SysMonAuxPolledExample(), SysMonIntrExample(), SysMonPolledExample(), and SysMonSingleChannelIntrExample().

int XSysMon_SetSingleChParams | ( | XSysMon * | InstancePtr,
|  | u8 | Channel,
|  | int | IncreaseAcqCycles,
|  | int | IsEventMode,
|  | int | IsDifferentialMode
| ) |  |

The function sets the given parameters in the Configuration Register 0 in the single channel mode.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  Channel | is the channel number for conversion. The valid channels are 0 to 5, 8, and 16 to 31. Channel 6 is valid for 7 series and Zynq XADC. Channel 32 to 35 are valid for Ultrascale.
  IncreaseAcqCycles | is a boolean parameter which specifies whether the Acquisition time for the external channels has to be increased to 10 ADCCLK cycles (specify TRUE) or remain at the default 4 ADCCLK cycles (specify FALSE). This parameter is only valid for the external channels.
  IsEventMode | is a boolean parameter that specifies continuous sampling (specify FALSE) or event driven sampling mode (specify TRUE) for the given channel.
  IsDifferentialMode | is a boolean parameter which specifies unipolar(specify FALSE) or differential mode (specify TRUE) for the analog inputs. The input mode is only valid for the external channels.

Returns
  - XST_SUCCESS if the given values were written successfully to the Configuration Register 0.
  - XST_FAILURE if the channel sequencer is enabled or the input parameters are not valid for the selected channel.

Note
  - The number of samples for the averaging for all the channels is set by using the function XSysMon_SetAvg.
  - The calibration of the device is done by doing a ADC conversion on the calibration channel(channel 8). The input parameters IncreaseAcqCycles, IsDifferentialMode and IsEventMode are not valid for this channel.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSM_CFR0_ACQ_MASK, XSM_CFR0_AVG_VALID_MASK, XSM_CFR0_CHANNEL_MASK, XSM_CFR0_DU_MASK, XSM_CFR0_EC_MASK, XSM_CFR0_OFFSET, XSM_CH_AUX_MAX, XSM_CH_AUX_MIN, XSM_CH_VPVN, XSM_CH_VREFN, XSM_CH_VUSR0, XSM_CH_VUSR3, XSM_SEQ_MODE_SINGCHAN, XSysMon_GetSequencerMode(), XSysMon_ReadReg, and XSysMon_WriteReg.

Referenced by SysMonSingleChannelIntrExample().

void XSysMon_SetTempWaitCycles | ( | XSysMon * | InstancePtr,
|  | u16 | WaitCycles
| ) |  |

This function sets the number of Wait Cycles for Temperature updation logic.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.
  WaitCycles | is number of wait cycles

Returns
  None.

Note
  The default number of wait cycles are 1000(0x3E8).

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSysMon::Mask, XSM_CONVST_OFFSET, XSM_CONVST_WAITCYCLES_MASK, XSM_CONVST_WAITCYCLES_SHIFT, and XSysMon_WriteReg.

void XSysMon_StartAdcConversion | ( | XSysMon * | InstancePtr | ) |

This function starts the ADC conversion in the Single Channel event driven sampling mode.

The EOC bit in Status Register will be set once the conversion is finished. Refer to the device specification for more details.

Parameters

  InstancePtr | is a pointer to the XSysMon instance.

Returns
  None.

Note
  The default state of the CONVST bit is a logic 0. The conversion is started when the CONVST bit is set to 1 from 0. This bit is cleared in this function so that the next conversion can be started by setting this bit.

References XSysMon_Config::BaseAddress, XSysMon::Config, XSysMon::IsReady, XSysMon::Mask, XSM_CONVST_CONVST_MASK, XSM_CONVST_OFFSET, and XSysMon_WriteReg.

## Variable Documentation

XSysMon_Config XSysMon_ConfigTable[]

This table contains configuration information for each System Monitor/ADC device in the system.

XSysMon_Config XSysMon_ConfigTable[XPAR_XSYSMON_NUM_INSTANCES]

Initial value:
=
{
{
XPAR_SYSMON_0_DEVICE_ID,
XPAR_SYSMON_0_BASEADDR,
XPAR_SYSMON_0_INCLUDE_INTR
}
}

This table contains configuration information for each System Monitor/ADC device in the system.