canps: xcanps_hw.h File Reference

| canps Xilinx SDK Drivers API Documentation

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Macros | Functions
xcanps_hw.h File Reference

## Macros
#define | XCanPs_ReadReg(BaseAddr, RegOffset) Xil_In32((BaseAddr) + (u32)(RegOffset))
| This macro reads the given register. More...
#define | XCanPs_WriteReg(BaseAddr, RegOffset, Data) Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
| This macro writes the given register. More...
Register offsets for the CAN. Each register is 32 bits.
#define | XCANPS_SRR_OFFSET 0x00000000U
| Software Reset Register. More...
#define | XCANPS_MSR_OFFSET 0x00000004U
| Mode Select Register. More...
#define | XCANPS_BRPR_OFFSET 0x00000008U
| Baud Rate Prescaler. More...
#define | XCANPS_BTR_OFFSET 0x0000000CU
| Bit Timing Register. More...
#define | XCANPS_ECR_OFFSET 0x00000010U
| Error Counter Register. More...
#define | XCANPS_ESR_OFFSET 0x00000014U
| Error Status Register. More...
#define | XCANPS_SR_OFFSET 0x00000018U
| Status Register. More...
#define | XCANPS_ISR_OFFSET 0x0000001CU
| Interrupt Status Register. More...
#define | XCANPS_IER_OFFSET 0x00000020U
| Interrupt Enable Register. More...
#define | XCANPS_ICR_OFFSET 0x00000024U
| Interrupt Clear Register. More...
#define | XCANPS_TCR_OFFSET 0x00000028U
| Timestamp Control Register. More...
#define | XCANPS_WIR_OFFSET 0x0000002CU
| Watermark Interrupt Reg. More...
#define | XCANPS_TXFIFO_ID_OFFSET 0x00000030U
| TX FIFO ID. More...
#define | XCANPS_TXFIFO_DLC_OFFSET 0x00000034U
| TX FIFO DLC. More...
#define | XCANPS_TXFIFO_DW1_OFFSET 0x00000038U
| TX FIFO Data Word 1. More...
#define | XCANPS_TXFIFO_DW2_OFFSET 0x0000003CU
| TX FIFO Data Word 2. More...
#define | XCANPS_TXHPB_ID_OFFSET 0x00000040U
| TX High Priority Buffer ID. More...
#define | XCANPS_TXHPB_DLC_OFFSET 0x00000044U
| TX High Priority Buffer DLC. More...
#define | XCANPS_TXHPB_DW1_OFFSET 0x00000048U
| TX High Priority Buf Data 1. More...
#define | XCANPS_TXHPB_DW2_OFFSET 0x0000004CU
| TX High Priority Buf Data Word 2. More...
#define | XCANPS_RXFIFO_ID_OFFSET 0x00000050U
| RX FIFO ID. More...
#define | XCANPS_RXFIFO_DLC_OFFSET 0x00000054U
| RX FIFO DLC. More...
#define | XCANPS_RXFIFO_DW1_OFFSET 0x00000058U
| RX FIFO Data Word 1. More...
#define | XCANPS_RXFIFO_DW2_OFFSET 0x0000005CU
| RX FIFO Data Word 2. More...
#define | XCANPS_AFR_OFFSET 0x00000060U
| Acceptance Filter Register. More...
#define | XCANPS_AFMR1_OFFSET 0x00000064U
| Acceptance Filter Mask 1. More...
#define | XCANPS_AFIR1_OFFSET 0x00000068U
| Acceptance Filter ID 1. More...
#define | XCANPS_AFMR2_OFFSET 0x0000006CU
| Acceptance Filter Mask 2. More...
#define | XCANPS_AFIR2_OFFSET 0x00000070U
| Acceptance Filter ID 2. More...
#define | XCANPS_AFMR3_OFFSET 0x00000074U
| Acceptance Filter Mask 3. More...
#define | XCANPS_AFIR3_OFFSET 0x00000078U
| Acceptance Filter ID 3. More...
#define | XCANPS_AFMR4_OFFSET 0x0000007CU
| Acceptance Filter Mask 4. More...
#define | XCANPS_AFIR4_OFFSET 0x00000080U
| Acceptance Filter ID 4. More...
Software Reset Register (SRR) Bit Definitions and Masks
#define | XCANPS_SRR_CEN_MASK 0x00000002U
| Can Enable. More...
#define | XCANPS_SRR_SRST_MASK 0x00000001U
| Reset. More...
Mode Select Register (MSR) Bit Definitions and Masks
#define | XCANPS_MSR_SNOOP_MASK 0x00000004U
| Snoop Mode Select. More...
#define | XCANPS_MSR_LBACK_MASK 0x00000002U
| Loop Back Mode Select. More...
#define | XCANPS_MSR_SLEEP_MASK 0x00000001U
| Sleep Mode Select. More...
Baud Rate Prescaler register (BRPR) Bit Definitions and Masks
#define | XCANPS_BRPR_BRP_MASK 0x000000FFU
| Baud Rate Prescaler. More...
Bit Timing Register (BTR) Bit Definitions and Masks
#define | XCANPS_BTR_SJW_MASK 0x00000180U
| Synchronization Jump Width. More...
#define | XCANPS_BTR_SJW_SHIFT 7U
#define | XCANPS_BTR_TS2_MASK 0x00000070U
| Time Segment 2. More...
#define | XCANPS_BTR_TS2_SHIFT 4U
#define | XCANPS_BTR_TS1_MASK 0x0000000FU
| Time Segment 1. More...
Error Counter Register (ECR) Bit Definitions and Masks
#define | XCANPS_ECR_REC_MASK 0x0000FF00U
| Receive Error Counter. More...
#define | XCANPS_ECR_REC_SHIFT 8U
#define | XCANPS_ECR_TEC_MASK 0x000000FFU
| Transmit Error Counter. More...
Error Status Register (ESR) Bit Definitions and Masks
#define | XCANPS_ESR_ACKER_MASK 0x00000010U
| ACK Error. More...
#define | XCANPS_ESR_BERR_MASK 0x00000008U
| Bit Error. More...
#define | XCANPS_ESR_STER_MASK 0x00000004U
| Stuff Error. More...
#define | XCANPS_ESR_FMER_MASK 0x00000002U
| Form Error. More...
#define | XCANPS_ESR_CRCER_MASK 0x00000001U
| CRC Error. More...
Status Register (SR) Bit Definitions and Masks
#define | XCANPS_SR_SNOOP_MASK 0x00001000U
| Snoop Mask. More...
#define | XCANPS_SR_ACFBSY_MASK 0x00000800U
| Acceptance Filter busy. More...
#define | XCANPS_SR_TXFLL_MASK 0x00000400U
| TX FIFO is full. More...
#define | XCANPS_SR_TXBFLL_MASK 0x00000200U
| TX High Priority Buffer full. More...
#define | XCANPS_SR_ESTAT_MASK 0x00000180U
| Error Status. More...
#define | XCANPS_SR_ESTAT_SHIFT 7U
#define | XCANPS_SR_ERRWRN_MASK 0x00000040U
| Error Warning. More...
#define | XCANPS_SR_BBSY_MASK 0x00000020U
| Bus Busy. More...
#define | XCANPS_SR_BIDLE_MASK 0x00000010U
| Bus Idle. More...
#define | XCANPS_SR_NORMAL_MASK 0x00000008U
| Normal Mode. More...
#define | XCANPS_SR_SLEEP_MASK 0x00000004U
| Sleep Mode. More...
#define | XCANPS_SR_LBACK_MASK 0x00000002U
| Loop Back Mode. More...
#define | XCANPS_SR_CONFIG_MASK 0x00000001U
| Configuration Mode. More...
Interrupt Status/Enable/Clear Register Bit Definitions and Masks
#define | XCANPS_IXR_TXFEMP_MASK 0x00004000U
| Tx Fifo Empty Interrupt. More...
#define | XCANPS_IXR_TXFWMEMP_MASK 0x00002000U
| Tx Fifo Watermark Empty. More...
#define | XCANPS_IXR_RXFWMFLL_MASK 0x00001000U
| Rx FIFO Watermark Full. More...
#define | XCANPS_IXR_WKUP_MASK 0x00000800U
| Wake up Interrupt. More...
#define | XCANPS_IXR_SLP_MASK 0x00000400U
| Sleep Interrupt. More...
#define | XCANPS_IXR_BSOFF_MASK 0x00000200U
| Bus Off Interrupt. More...
#define | XCANPS_IXR_ERROR_MASK 0x00000100U
| Error Interrupt. More...
#define | XCANPS_IXR_RXNEMP_MASK 0x00000080U
| RX FIFO Not Empty Interrupt. More...
#define | XCANPS_IXR_RXOFLW_MASK 0x00000040U
| RX FIFO Overflow Interrupt. More...
#define | XCANPS_IXR_RXUFLW_MASK 0x00000020U
| RX FIFO Underflow Interrupt. More...
#define | XCANPS_IXR_RXOK_MASK 0x00000010U
| New Message Received Intr. More...
#define | XCANPS_IXR_TXBFLL_MASK 0x00000008U
| TX High Priority Buf Full. More...
#define | XCANPS_IXR_TXFLL_MASK 0x00000004U
| TX FIFO Full Interrupt. More...
#define | XCANPS_IXR_TXOK_MASK 0x00000002U
| TX Successful Interrupt. More...
#define | XCANPS_IXR_ARBLST_MASK 0x00000001U
| Arbitration Lost Interrupt. More...
#define | XCANPS_IXR_ALL
CAN Timestamp Control Register (TCR) Bit Definitions and Masks
#define | XCANPS_TCR_CTS_MASK 0x00000001U
| Clear Timestamp counter mask. More...
CAN Watermark Register (WIR) Bit Definitions and Masks
#define | XCANPS_WIR_FW_MASK 0x0000003FU
| Rx Full Threshold mask. More...
#define | XCANPS_WIR_EW_MASK 0x00003F00U
| Tx Empty Threshold mask. More...
#define | XCANPS_WIR_EW_SHIFT 0x00000008U
| Tx Empty Threshold shift. More...
CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter
Mask/Acceptance Filter ID)
#define | XCANPS_IDR_ID1_MASK 0xFFE00000U
| Standard Messg Identifier. More...
#define | XCANPS_IDR_ID1_SHIFT 21U
#define | XCANPS_IDR_SRR_MASK 0x00100000U
| Substitute Remote TX Req. More...
#define | XCANPS_IDR_SRR_SHIFT 20U
#define | XCANPS_IDR_IDE_MASK 0x00080000U
| Identifier Extension. More...
#define | XCANPS_IDR_IDE_SHIFT 19U
#define | XCANPS_IDR_ID2_MASK 0x0007FFFEU
| Extended Message Ident. More...
#define | XCANPS_IDR_ID2_SHIFT 1U
#define | XCANPS_IDR_RTR_MASK 0x00000001U
| Remote TX Request. More...
CAN Frame Data Length Code (TX High Priority Buffer/TX/RX)
#define | XCANPS_DLCR_DLC_MASK 0xF0000000U
| Data Length Code. More...
#define | XCANPS_DLCR_DLC_SHIFT 28U
#define | XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFFU
| Timestamp Mask (Rx only) More...
CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX)
#define | XCANPS_DW1R_DB0_MASK 0xFF000000U
| Data Byte 0. More...
#define | XCANPS_DW1R_DB0_SHIFT 24U
#define | XCANPS_DW1R_DB1_MASK 0x00FF0000U
| Data Byte 1. More...
#define | XCANPS_DW1R_DB1_SHIFT 16U
#define | XCANPS_DW1R_DB2_MASK 0x0000FF00U
| Data Byte 2. More...
#define | XCANPS_DW1R_DB2_SHIFT 8U
#define | XCANPS_DW1R_DB3_MASK 0x000000FFU
| Data Byte 3. More...
CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX)
#define | XCANPS_DW2R_DB4_MASK 0xFF000000U
| Data Byte 4. More...
#define | XCANPS_DW2R_DB4_SHIFT 24U
#define | XCANPS_DW2R_DB5_MASK 0x00FF0000U
| Data Byte 5. More...
#define | XCANPS_DW2R_DB5_SHIFT 16U
#define | XCANPS_DW2R_DB6_MASK 0x0000FF00U
| Data Byte 6. More...
#define | XCANPS_DW2R_DB6_SHIFT 8U
#define | XCANPS_DW2R_DB7_MASK 0x000000FFU
| Data Byte 7. More...
Acceptance Filter Register (AFR) Bit Definitions and Masks
#define | XCANPS_AFR_UAF4_MASK 0x00000008U
| Use Acceptance Filter No.4. More...
#define | XCANPS_AFR_UAF3_MASK 0x00000004U
| Use Acceptance Filter No.3. More...
#define | XCANPS_AFR_UAF2_MASK 0x00000002U
| Use Acceptance Filter No.2. More...
#define | XCANPS_AFR_UAF1_MASK 0x00000001U
| Use Acceptance Filter No.1. More...
#define | XCANPS_AFR_UAF_ALL_MASK
CAN frame length constants
#define | XCANPS_MAX_FRAME_SIZE sizeof(u32)*16U
| Maximum CAN frame length in bytes. More...

## Functions
void | XCanPs_ResetHw (u32 BaseAddr)
| This function resets the CAN device. More...