gpiops: xgpiops_hw.h File Reference

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xgpiops_hw.h File Reference

## Macros
#define | XGpioPs_ReadReg(BaseAddr, RegOffset) Xil_In32((BaseAddr) + (u32)(RegOffset))
| This macro reads the given register. More...
#define | XGpioPs_WriteReg(BaseAddr, RegOffset, Data) Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
| This macro writes to the given register. More...
Register offsets for the GPIO. Each register is 32 bits.
#define | XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
#define | XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
#define | XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
#define | XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
#define | XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
#define | XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
#define | XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
#define | XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
#define | XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
#define | XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
#define | XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
#define | XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
#define | XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
Register offsets for each Bank.
#define | XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
#define | XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
#define | XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
Interrupt type reset values for each bank
#define | XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
#define | XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
#define | XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
#define | XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
#define | XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
#define | XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU