rfdc: APIs

| rfdc Xilinx SDK Drivers API Documentation

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### - x -

- XRFDC_ADC0_SUBDRP_ADDR_OFFSET : xrfdc_hw.h
- XRFDC_ADC0_SUBDRP_DAT_OFFSET : xrfdc_hw.h
- XRFDC_ADC1_SUBDRP_ADDR_OFFSET : xrfdc_hw.h
- XRFDC_ADC1_SUBDRP_DAT_OFFSET : xrfdc_hw.h
- XRFDC_ADC2_SUBDRP_ADDR_OFFSET : xrfdc_hw.h
- XRFDC_ADC2_SUBDRP_DAT_OFFSET : xrfdc_hw.h
- XRFDC_ADC3_SUBDRP_ADDR_OFFSET : xrfdc_hw.h
- XRFDC_ADC3_SUBDRP_DAT_OFFSET : xrfdc_hw.h
- XRFDC_ADC_CRSE_DLY_CFG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_CRSE_DLY_UPDT_OFFSET : xrfdc_hw.h
- XRFDC_ADC_DAC_MC_CFG0_OFFSET : xrfdc_hw.h
- XRFDC_ADC_DAC_MC_CFG1_OFFSET : xrfdc_hw.h
- XRFDC_ADC_DAC_MC_CFG2_OFFSET : xrfdc_hw.h
- XRFDC_ADC_DAT_IMR_MASK : xrfdc_hw.h
- XRFDC_ADC_DAT_PATH_ISR_MASK : xrfdc_hw.h
- XRFDC_ADC_DAT_SCAL_CFG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_DEBUG_RST_OFFSET : xrfdc_hw.h
- XRFDC_ADC_DEC_IMR_OFFSET : xrfdc_hw.h
- XRFDC_ADC_DEC_ISR_OFFSET : xrfdc_hw.h
- XRFDC_ADC_DECI_CONFIG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_DECI_MODE_OFFSET : xrfdc_hw.h
- XRFDC_ADC_FAB_RATE_RD_MASK : xrfdc_hw.h
- XRFDC_ADC_FAB_RATE_WR_MASK : xrfdc_hw.h
- XRFDC_ADC_FABRIC_DBG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_FABRIC_IMR_OFFSET : xrfdc_hw.h
- XRFDC_ADC_FABRIC_ISR_OFFSET : xrfdc_hw.h
- XRFDC_ADC_FABRIC_OFFSET : xrfdc_hw.h
- XRFDC_ADC_FABRIC_RATE_OFFSET : xrfdc_hw.h
- XRFDC_ADC_FEND_DAT_CRL_OFFSET : xrfdc_hw.h
- XRFDC_ADC_FIFO_LTNC_CRL_OFFSET : xrfdc_hw.h
- XRFDC_ADC_FIFO_LTNCY_LB_OFFSET : xrfdc_hw.h
- XRFDC_ADC_FIFO_LTNCY_MB_OFFSET : xrfdc_hw.h
- XRFDC_ADC_MXR_CFG0_OFFSET : xrfdc_hw.h
- XRFDC_ADC_MXR_CFG1_OFFSET : xrfdc_hw.h
- XRFDC_ADC_NCO_FQWD_LOW_OFFSET : xrfdc_hw.h
- XRFDC_ADC_NCO_FQWD_MID_OFFSET : xrfdc_hw.h
- XRFDC_ADC_NCO_FQWD_UPP_OFFSET : xrfdc_hw.h
- XRFDC_ADC_NCO_PHASE_MOD_OFFSET : xrfdc_hw.h
- XRFDC_ADC_RX_MC_PWRDWN_OFFSET : xrfdc_hw.h
- XRFDC_ADC_RXPR_MC_CFG0_OFFSET : xrfdc_hw.h
- XRFDC_ADC_RXPR_MC_CFG1_OFFSET : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_CTRL_OFFSET : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_FLUSH_MASK : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_FLUSH_SHIFT : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_HYST_MASK : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_HYST_SHIFT : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_INTG_MASK : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_INTG_SHIFT : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_MAGN_OFFSET : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_MASK : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_MODE_MASK : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_MODE_READ_SHIFT : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_MODE_WRITE_SHIFT : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_TCONST_MASK : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_TCONST_SHIFT : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_THRESH_MASK : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_OFF_OFFSET : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_ON_OFFSET : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_THRESHOLD0_LEVEL_OFFSET : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_OFF_OFFSET : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_ON_OFFSET : xrfdc_hw.h
- XRFDC_ADC_SIG_DETECT_THRESHOLD1_LEVEL_OFFSET : xrfdc_hw.h
- XRFDC_ADC_SWITCH_MATRX_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCB_CRL0_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCB_CRL1_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCB_CRL2_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCB_CRL3_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS0_BG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS0_FG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS1_BG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS1_FG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS2_BG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS2_FG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS3_BG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS3_FG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS4_LB_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS4_MB_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS5_LB_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS5_MB_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS6_LB_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS6_MB_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS7_LB_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_DCBSTS7_MB_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_TISK_CRL0_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_TISK_CRL1_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_TISK_CRL2_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_TISK_CRL3_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_TISK_CRL4_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_TISK_DAC0_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_TISK_DAC1_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_TISK_DAC2_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_TISK_DAC3_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_TISK_DACP0_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_TISK_DACP1_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_TISK_DACP2_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TI_TISK_DACP3_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TRSHD0_AVG_LO_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TRSHD0_AVG_UP_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TRSHD0_CFG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TRSHD0_OVER_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TRSHD0_UNDER_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TRSHD1_AVG_LO_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TRSHD1_AVG_UP_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TRSHD1_CFG_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TRSHD1_OVER_OFFSET : xrfdc_hw.h
- XRFDC_ADC_TRSHD1_UNDER_OFFSET : xrfdc_hw.h
- XRFDC_ADC_UPDATE_DYN_OFFSET : xrfdc_hw.h
- XRFDC_ADC_UPDT_CRSE_DLY_MASK : xrfdc_hw.h
- XRFDC_CAL_FREEZE_CAL_MASK : xrfdc_hw.h
- XRFDC_CAL_FREEZE_CAL_SHIFT : xrfdc_hw.h
- XRFDC_CAL_FREEZE_PIN_MASK : xrfdc_hw.h
- XRFDC_CAL_FREEZE_PIN_SHIFT : xrfdc_hw.h
- XRFDC_CAL_FREEZE_STS_MASK : xrfdc_hw.h
- XRFDC_CAL_FREEZE_STS_SHIFT : xrfdc_hw.h
- XRFDC_CAL_GCB_ACEN_MASK : xrfdc_hw.h
- XRFDC_CAL_GCB_ACEN_SHIFT : xrfdc_hw.h
- XRFDC_CAL_GCB_EN_MASK : xrfdc_hw.h
- XRFDC_CAL_GCB_EN_SHIFT : xrfdc_hw.h
- XRFDC_CAL_GCB_ENFL_MASK : xrfdc_hw.h
- XRFDC_CAL_GCB_FAB_MASK : xrfdc_hw.h
- XRFDC_CAL_GCB_FLSH_MASK : xrfdc_hw.h
- XRFDC_CAL_GCB_FLSH_SHIFT : xrfdc_hw.h
- XRFDC_CAL_GCB_MASK : xrfdc_hw.h
- XRFDC_CAL_GCB_OFFSET_COEFF0 : xrfdc_hw.h
- XRFDC_CAL_GCB_OFFSET_COEFF0_ALT : xrfdc_hw.h
- XRFDC_CAL_GCB_OFFSET_COEFF1 : xrfdc_hw.h
- XRFDC_CAL_GCB_OFFSET_COEFF1_ALT : xrfdc_hw.h
- XRFDC_CAL_GCB_OFFSET_COEFF2 : xrfdc_hw.h
- XRFDC_CAL_GCB_OFFSET_COEFF2_ALT : xrfdc_hw.h
- XRFDC_CAL_GCB_OFFSET_COEFF3 : xrfdc_hw.h
- XRFDC_CAL_GCB_OFFSET_COEFF3_ALT : xrfdc_hw.h
- XRFDC_CAL_OCB1_OFFSET_COEFF0 : xrfdc_hw.h
- XRFDC_CAL_OCB1_OFFSET_COEFF1 : xrfdc_hw.h
- XRFDC_CAL_OCB1_OFFSET_COEFF2 : xrfdc_hw.h
- XRFDC_CAL_OCB1_OFFSET_COEFF3 : xrfdc_hw.h
- XRFDC_CAL_OCB2_OFFSET_COEFF0 : xrfdc_hw.h
- XRFDC_CAL_OCB2_OFFSET_COEFF1 : xrfdc_hw.h
- XRFDC_CAL_OCB2_OFFSET_COEFF2 : xrfdc_hw.h
- XRFDC_CAL_OCB2_OFFSET_COEFF3 : xrfdc_hw.h
- XRFDC_CAL_OCB_EN_MASK : xrfdc_hw.h
- XRFDC_CAL_OCB_EN_SHIFT : xrfdc_hw.h
- XRFDC_CAL_OCB_MASK : xrfdc_hw.h
- XRFDC_CAL_SLICE_SHIFT : xrfdc_hw.h
- XRFDC_CAL_TSCB_EN_MASK : xrfdc_hw.h
- XRFDC_CAL_TSCB_EN_SHIFT : xrfdc_hw.h
- XRFDC_CAL_TSCB_MASK : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF0 : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF0_ALT : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF1 : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF1_ALT : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF2 : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF2_ALT : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF3 : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF3_ALT : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF4 : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF4_ALT : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF5 : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF5_ALT : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF6 : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF6_ALT : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF7 : xrfdc_hw.h
- XRFDC_CAL_TSCB_OFFSET_COEFF7_ALT : xrfdc_hw.h
- XRFDC_CLK_EN_CAL_MASK : xrfdc_hw.h
- XRFDC_CLK_EN_DIG_MASK : xrfdc_hw.h
- XRFDC_CLK_EN_DP_MASK : xrfdc_hw.h
- XRFDC_CLK_EN_FAB_MASK : xrfdc_hw.h
- XRFDC_CLK_EN_LM_MASK : xrfdc_hw.h
- XRFDC_CLK_EN_OFFSET : xrfdc_hw.h
- XRFDC_CLK_NETWORK_CTRL0 : xrfdc_hw.h
- XRFDC_CLK_NETWORK_CTRL1 : xrfdc_hw.h
- XRFDC_CLK_NETWORK_CTRL1_USE_PLL_MASK : xrfdc_hw.h
- XRFDC_CLOCK_DETECT_MASK : xrfdc_hw.h
- XRFDC_CLOCK_DETECT_OFFSET : xrfdc_hw.h
- XRFDC_COMMON_INTR_ENABLE : xrfdc_hw.h
- XRFDC_COMMON_INTR_STS : xrfdc_hw.h
- XRFDC_CRSE_DLY_CFG_MASK : xrfdc_hw.h
- XRFDC_CRSE_DLY_CFG_MASK_EXT : xrfdc_hw.h
- XRFDC_CRSEDLY_UPDT_DLY_MASK : xrfdc_hw.h
- XRFDC_CRSEDLY_UPDT_MODE_FABRIC : xrfdc_hw.h
- XRFDC_CRSEDLY_UPDT_MODE_GRP : xrfdc_hw.h
- XRFDC_CRSEDLY_UPDT_MODE_MARKER : xrfdc_hw.h
- XRFDC_CRSEDLY_UPDT_MODE_MASK : xrfdc_hw.h
- XRFDC_CRSEDLY_UPDT_MODE_SLICE : xrfdc_hw.h
- XRFDC_CRSEDLY_UPDT_MODE_SYSREF : xrfdc_hw.h
- XRFDC_CRSEDLY_UPDT_MODE_TILE : xrfdc_hw.h
- XRFDC_CURRENT_STATE_OFFSET : xrfdc_hw.h
- XRFDC_DAC_CRSE_DLY_CFG_OFFSET : xrfdc_hw.h
- XRFDC_DAC_CRSE_DLY_UPDT_OFFSET : xrfdc_hw.h
- XRFDC_DAC_DAT_IMR_MASK : xrfdc_hw.h
- XRFDC_DAC_DAT_ISR_INVSINC_MASK : xrfdc_hw.h
- XRFDC_DAC_DAT_PATH_ISR_MASK : xrfdc_hw.h
- XRFDC_DAC_DATAPATH_OFFSET : xrfdc_hw.h
- XRFDC_DAC_DECODER_CLK_OFFSET : xrfdc_hw.h
- XRFDC_DAC_DECODER_CTRL_OFFSET : xrfdc_hw.h
- XRFDC_DAC_FAB_RATE_RD_MASK : xrfdc_hw.h
- XRFDC_DAC_FAB_RATE_WR_MASK : xrfdc_hw.h
- XRFDC_DAC_FABRIC_IMR_OFFSET : xrfdc_hw.h
- XRFDC_DAC_FABRIC_ISR_OFFSET : xrfdc_hw.h
- XRFDC_DAC_INTERP_CTRL_OFFSET : xrfdc_hw.h
- XRFDC_DAC_INTERP_DATA_MASK : xrfdc_hw.h
- XRFDC_DAC_INVSINC_OFFSET : xrfdc_hw.h
- XRFDC_DAC_ITERP_DATA_OFFSET : xrfdc_hw.h
- XRFDC_DAC_MB_CFG_OFFSET : xrfdc_hw.h
- XRFDC_DAC_MC_CFG0_OFFSET : xrfdc_hw.h
- XRFDC_DAC_MC_CFG3_OFFSET : xrfdc_hw.h
- XRFDC_DAC_UPDATE_DYN_OFFSET : xrfdc_hw.h
- XRFDC_DAC_UPDT_CRSE_DLY_MASK : xrfdc_hw.h
- XRFDC_DAC_VOP_CTRL_OFFSET : xrfdc_hw.h
- XRFDC_DAT_CLK_EN_MASK : xrfdc_hw.h
- XRFDC_DAT_IMR_DECI_IPATH_MASK : xrfdc_hw.h
- XRFDC_DAT_IMR_INTR_QPATH_MASK : xrfdc_hw.h
- XRFDC_DAT_IMR_QMC_GAIN_MASK : xrfdc_hw.h
- XRFDC_DAT_IMR_QMC_OFFST_MASK : xrfdc_hw.h
- XRFDC_DAT_ISR_DECI_IPATH_MASK : xrfdc_hw.h
- XRFDC_DAT_ISR_INTR_QPATH_MASK : xrfdc_hw.h
- XRFDC_DAT_ISR_QMC_GAIN_MASK : xrfdc_hw.h
- XRFDC_DAT_ISR_QMC_OFFST_MASK : xrfdc_hw.h
- XRFDC_DAT_SCALE_CFG_MASK : xrfdc_hw.h
- XRFDC_DATAPATH_IMR_MASK : xrfdc_hw.h
- XRFDC_DATAPATH_LATENCY_MASK : xrfdc_hw.h
- XRFDC_DATAPATH_MODE_MASK : xrfdc_hw.h
- XRFDC_DATPATH_IMR_OFFSET : xrfdc_hw.h
- XRFDC_DATPATH_ISR_OFFSET : xrfdc_hw.h
- XRFDC_DBG_RST_CAL_MASK : xrfdc_hw.h
- XRFDC_DBG_RST_DIG_MASK : xrfdc_hw.h
- XRFDC_DBG_RST_DP_MASK : xrfdc_hw.h
- XRFDC_DBG_RST_DRP_CAL_MASK : xrfdc_hw.h
- XRFDC_DBG_RST_FAB_MASK : xrfdc_hw.h
- XRFDC_DBG_RST_LM_MASK : xrfdc_hw.h
- XRFDC_DEC_CFG_4GSPS_MASK : xrfdc_hw.h
- XRFDC_DEC_CFG_CHA_MASK : xrfdc_hw.h
- XRFDC_DEC_CFG_CHB_MASK : xrfdc_hw.h
- XRFDC_DEC_CFG_IQ_MASK : xrfdc_hw.h
- XRFDC_DEC_CFG_MASK : xrfdc_hw.h
- XRFDC_DEC_CTRL_MODE_MASK : xrfdc_hw.h
- XRFDC_DEC_IMR_SUBADC0_OVR_MASK : xrfdc_hw.h
- XRFDC_DEC_IMR_SUBADC0_UND_MASK : xrfdc_hw.h
- XRFDC_DEC_IMR_SUBADC1_OVR_MASK : xrfdc_hw.h
- XRFDC_DEC_IMR_SUBADC1_UND_MASK : xrfdc_hw.h
- XRFDC_DEC_IMR_SUBADC2_OVR_MASK : xrfdc_hw.h
- XRFDC_DEC_IMR_SUBADC2_UND_MASK : xrfdc_hw.h
- XRFDC_DEC_IMR_SUBADC3_OVR_MASK : xrfdc_hw.h
- XRFDC_DEC_IMR_SUBADC3_UND_MASK : xrfdc_hw.h
- XRFDC_DEC_ISR_SUBADC0_OVR_MASK : xrfdc_hw.h
- XRFDC_DEC_ISR_SUBADC0_UND_MASK : xrfdc_hw.h
- XRFDC_DEC_ISR_SUBADC1_OVR_MASK : xrfdc_hw.h
- XRFDC_DEC_ISR_SUBADC1_UND_MASK : xrfdc_hw.h
- XRFDC_DEC_ISR_SUBADC2_OVR_MASK : xrfdc_hw.h
- XRFDC_DEC_ISR_SUBADC2_UND_MASK : xrfdc_hw.h
- XRFDC_DEC_ISR_SUBADC3_OVR_MASK : xrfdc_hw.h
- XRFDC_DEC_ISR_SUBADC3_UND_MASK : xrfdc_hw.h
- XRFDC_DEC_ISR_SUBADC_MASK : xrfdc_hw.h
- XRFDC_DEC_MOD_MASK : xrfdc_hw.h
- XRFDC_DEC_MOD_MASK_EXT : xrfdc_hw.h
- XRFDC_DIGI_ANALOG_SHIFT4 : xrfdc_hw.h
- XRFDC_DSA_UPDT_OFFSET : xrfdc_hw.h
- XRFDC_EN_I_IQ_MASK : xrfdc_hw.h
- XRFDC_EN_INTR_ADC_TILE0_MASK : xrfdc_hw.h
- XRFDC_EN_INTR_ADC_TILE1_MASK : xrfdc_hw.h
- XRFDC_EN_INTR_ADC_TILE2_MASK : xrfdc_hw.h
- XRFDC_EN_INTR_ADC_TILE3_MASK : xrfdc_hw.h
- XRFDC_EN_INTR_DAC_TILE0_MASK : xrfdc_hw.h
- XRFDC_EN_INTR_DAC_TILE1_MASK : xrfdc_hw.h
- XRFDC_EN_INTR_DAC_TILE2_MASK : xrfdc_hw.h
- XRFDC_EN_INTR_DAC_TILE3_MASK : xrfdc_hw.h
- XRFDC_EN_INTR_SLICE0_MASK : xrfdc_hw.h
- XRFDC_EN_INTR_SLICE1_MASK : xrfdc_hw.h
- XRFDC_EN_INTR_SLICE2_MASK : xrfdc_hw.h
- XRFDC_EN_INTR_SLICE3_MASK : xrfdc_hw.h
- XRFDC_EN_INTR_SLICE_MASK : xrfdc_hw.h
- XRFDC_EN_INVSINC_MASK : xrfdc_hw.h
- XRFDC_EN_MB_MASK : xrfdc_hw.h
- XRFDC_EN_Q_IQ_MASK : xrfdc_hw.h
- XRFDC_FAB_CLK_DIV_CAL_MASK : xrfdc_hw.h
- XRFDC_FAB_CLK_DIV_MASK : xrfdc_hw.h
- XRFDC_FAB_IMR_MARGIND_OVR_MASK : xrfdc_hw.h
- XRFDC_FAB_IMR_MARGIND_UND_MASK : xrfdc_hw.h
- XRFDC_FAB_IMR_USRDAT_MASK : xrfdc_hw.h
- XRFDC_FAB_IMR_USRDAT_OVR_MASK : xrfdc_hw.h
- XRFDC_FAB_IMR_USRDAT_UND_MASK : xrfdc_hw.h
- XRFDC_FAB_ISR_MARGIND_OVR_MASK : xrfdc_hw.h
- XRFDC_FAB_ISR_MARGIND_UND_MASK : xrfdc_hw.h
- XRFDC_FAB_ISR_USRDAT_MASK : xrfdc_hw.h
- XRFDC_FAB_ISR_USRDAT_OVR_MASK : xrfdc_hw.h
- XRFDC_FAB_ISR_USRDAT_UND_MASK : xrfdc_hw.h
- XRFDC_FAB_RATE_RD_SHIFT : xrfdc_hw.h
- XRFDC_FAB_RD_PTR_OFFST_MASK : xrfdc_hw.h
- XRFDC_FEND_DAT_CTRL_MASK : xrfdc_hw.h
- XRFDC_FIFO_EN_MASK : xrfdc_hw.h
- XRFDC_FIFO_ENABLE : xrfdc_hw.h
- XRFDC_FIFO_LTNCY_DIS_MASK : xrfdc_hw.h
- XRFDC_FIFO_LTNCY_DONE_MASK : xrfdc_hw.h
- XRFDC_FIFO_LTNCY_KEY_MASK : xrfdc_hw.h
- XRFDC_FIFO_LTNCY_PRD_MASK : xrfdc_hw.h
- XRFDC_FIFO_LTNCY_RES_MASK : xrfdc_hw.h
- XRFDC_FIFO_LTNCY_RESTRT_MASK : xrfdc_hw.h
- XRFDC_FINE_MIX_SCALE_MASK : xrfdc_hw.h
- XRFDC_HSCOM_CLK_DIV_OFFSET : xrfdc_hw.h
- XRFDC_HSCOM_CLK_DSTR_MASK : xrfdc_hw.h
- XRFDC_HSCOM_CLK_DSTR_MASK_ALT : xrfdc_hw.h
- XRFDC_HSCOM_CLK_DSTR_OFFSET : xrfdc_hw.h
- XRFDC_HSCOM_NETWORK_CTRL1_MASK : xrfdc_hw.h
- XRFDC_HSCOM_PWR_OFFSET : xrfdc_hw.h
- XRFDC_HSCOM_PWR_STATE_MASK : xrfdc_hw.h
- XRFDC_HSCOM_PWR_STATE_OFFSET : xrfdc_hw.h
- XRFDC_HSCOM_UPDT_DYN_OFFSET : xrfdc_hw.h
- XRFDC_I_IQ_COS_MINSIN : xrfdc_hw.h
- XRFDC_INTERP_MODE_I_MASK : xrfdc_hw.h
- XRFDC_INTERP_MODE_I_MASK_EXT : xrfdc_hw.h
- XRFDC_INTERP_MODE_MASK : xrfdc_hw.h
- XRFDC_INTERP_MODE_MASK_EXT : xrfdc_hw.h
- XRFDC_INTERP_MODE_Q_SHIFT : xrfdc_hw.h
- XRFDC_INTERP_MODE_Q_SHIFT_EXT : xrfdc_hw.h
- XRFDC_INTR_CMODE_OVR_MASK : xrfdc_hw.h
- XRFDC_INTR_CMODE_UNDR_MASK : xrfdc_hw.h
- XRFDC_INTR_COMMON_MASK : xrfdc_hw.h
- XRFDC_INTR_DAT_OVR_MASK : xrfdc_hw.h
- XRFDC_INTR_ENABLE : xrfdc_hw.h
- XRFDC_INTR_FIFO_OVR_MASK : xrfdc_hw.h
- XRFDC_INTR_OVR_RANGE_MASK : xrfdc_hw.h
- XRFDC_INTR_OVR_VOLTAGE_MASK : xrfdc_hw.h
- XRFDC_INTR_STS : xrfdc_hw.h
- XRFDC_MB_CFG_MASK : xrfdc_hw.h
- XRFDC_MB_EN_4X_MASK : xrfdc_hw.h
- XRFDC_MC_CFG0_MIX_MODE_MASK : xrfdc_hw.h
- XRFDC_MC_CFG0_MIX_MODE_SHIFT : xrfdc_hw.h
- XRFDC_MIX_CFG0_MASK : xrfdc_hw.h
- XRFDC_MIX_CFG1_MASK : xrfdc_hw.h
- XRFDC_MIX_I_DAT_WRD0_MASK : xrfdc_hw.h
- XRFDC_MIX_I_DAT_WRD1_MASK : xrfdc_hw.h
- XRFDC_MIX_I_DAT_WRD2_MASK : xrfdc_hw.h
- XRFDC_MIX_I_DAT_WRD3_MASK : xrfdc_hw.h
- XRFDC_MIX_Q_DAT_WRD0_MASK : xrfdc_hw.h
- XRFDC_MIX_Q_DAT_WRD1_MASK : xrfdc_hw.h
- XRFDC_MIX_Q_DAT_WRD2_MASK : xrfdc_hw.h
- XRFDC_MIX_Q_DAT_WRD3_MASK : xrfdc_hw.h
- XRFDC_MIXER_MODE_C2C_MASK : xrfdc_hw.h
- XRFDC_MIXER_MODE_C2R_MASK : xrfdc_hw.h
- XRFDC_MIXER_MODE_OFF_MASK : xrfdc_hw.h
- XRFDC_MIXER_MODE_R2C_MASK : xrfdc_hw.h
- XRFDC_MODE_INVSINC_MASK : xrfdc_hw.h
- XRFDC_MXR_MODE_OFFSET : xrfdc_hw.h
- XRFDC_NCO_FQWD_LOW_MASK : xrfdc_hw.h
- XRFDC_NCO_FQWD_MASK : xrfdc_hw.h
- XRFDC_NCO_FQWD_MID_MASK : xrfdc_hw.h
- XRFDC_NCO_FQWD_MID_SHIFT : xrfdc_hw.h
- XRFDC_NCO_FQWD_UPP_MASK : xrfdc_hw.h
- XRFDC_NCO_FQWD_UPP_SHIFT : xrfdc_hw.h
- XRFDC_NCO_PHASE_LOW_MASK : xrfdc_hw.h
- XRFDC_NCO_PHASE_LOW_OFFSET : xrfdc_hw.h
- XRFDC_NCO_PHASE_MASK : xrfdc_hw.h
- XRFDC_NCO_PHASE_MOD_4PHASE : xrfdc_hw.h
- XRFDC_NCO_PHASE_MOD_EVEN : xrfdc_hw.h
- XRFDC_NCO_PHASE_MOD_MASK : xrfdc_hw.h
- XRFDC_NCO_PHASE_MODE_ODD : xrfdc_hw.h
- XRFDC_NCO_PHASE_RST_MASK : xrfdc_hw.h
- XRFDC_NCO_PHASE_UPP_MASK : xrfdc_hw.h
- XRFDC_NCO_PHASE_UPP_OFFSET : xrfdc_hw.h
- XRFDC_NCO_PHASE_UPP_SHIFT : xrfdc_hw.h
- XRFDC_NCO_RST_OFFSET : xrfdc_hw.h
- XRFDC_NCO_UPDT_DLY_MASK : xrfdc_hw.h
- XRFDC_NCO_UPDT_MODE_FABRIC : xrfdc_hw.h
- XRFDC_NCO_UPDT_MODE_GRP : xrfdc_hw.h
- XRFDC_NCO_UPDT_MODE_MARKER : xrfdc_hw.h
- XRFDC_NCO_UPDT_MODE_MASK : xrfdc_hw.h
- XRFDC_NCO_UPDT_MODE_SLICE : xrfdc_hw.h
- XRFDC_NCO_UPDT_MODE_SYSREF : xrfdc_hw.h
- XRFDC_NCO_UPDT_MODE_TILE : xrfdc_hw.h
- XRFDC_NCO_UPDT_OFFSET : xrfdc_hw.h
- XRFDC_NCO_UPDT_RST_DLY_MASK : xrfdc_hw.h
- XRFDC_PLL_CHARGEPUMP : xrfdc_hw.h
- XRFDC_PLL_CRS1 : xrfdc_hw.h
- XRFDC_PLL_CRS1_VCO_SEL_MASK : xrfdc_hw.h
- XRFDC_PLL_CRS2 : xrfdc_hw.h
- XRFDC_PLL_DIVIDER0 : xrfdc_hw.h
- XRFDC_PLL_DIVIDER0_ALT_MASK : xrfdc_hw.h
- XRFDC_PLL_DIVIDER0_BYPDIV_MASK : xrfdc_hw.h
- XRFDC_PLL_DIVIDER0_BYPPLL_MASK : xrfdc_hw.h
- XRFDC_PLL_DIVIDER1 : xrfdc_hw.h
- XRFDC_PLL_FPDIV : xrfdc_hw.h
- XRFDC_PLL_FREQ : xrfdc_hw.h
- XRFDC_PLL_FS : xrfdc_hw.h
- XRFDC_PLL_LOCKED_MASK : xrfdc_hw.h
- XRFDC_PLL_LOCKED_SHIFT : xrfdc_hw.h
- XRFDC_PLL_LPF0 : xrfdc_hw.h
- XRFDC_PLL_LPF1 : xrfdc_hw.h
- XRFDC_PLL_REFDIV : xrfdc_hw.h
- XRFDC_PLL_REFDIV_MASK : xrfdc_hw.h
- XRFDC_PLL_SDM_CFG0 : xrfdc_hw.h
- XRFDC_PLL_SDM_SEED0 : xrfdc_hw.h
- XRFDC_PLL_SDM_SEED1 : xrfdc_hw.h
- XRFDC_PLL_SPARE0 : xrfdc_hw.h
- XRFDC_PLL_SPARE1 : xrfdc_hw.h
- XRFDC_PLL_VCO0 : xrfdc_hw.h
- XRFDC_PLL_VCO1 : xrfdc_hw.h
- XRFDC_PLL_VCO_SEL_AUTO_MASK : xrfdc_hw.h
- XRFDC_PLL_VREG : xrfdc_hw.h
- XRFDC_PWR_STATE_MASK : xrfdc_hw.h
- XRFDC_PWR_UP_STAT_MASK : xrfdc_hw.h
- XRFDC_PWR_UP_STAT_SHIFT : xrfdc_hw.h
- XRFDC_Q_IQ_SIN_COS : xrfdc_hw.h
- XRFDC_QMC_CFG_EN_GAIN_MASK : xrfdc_hw.h
- XRFDC_QMC_CFG_EN_PHASE_MASK : xrfdc_hw.h
- XRFDC_QMC_CFG_OFFSET : xrfdc_hw.h
- XRFDC_QMC_CFG_PHASE_SHIFT : xrfdc_hw.h
- XRFDC_QMC_GAIN_CRCTN_MASK : xrfdc_hw.h
- XRFDC_QMC_GAIN_OFFSET : xrfdc_hw.h
- XRFDC_QMC_OFF_OFFSET : xrfdc_hw.h
- XRFDC_QMC_OFFST_CRCTN_MASK : xrfdc_hw.h
- XRFDC_QMC_PHASE_CRCTN_MASK : xrfdc_hw.h
- XRFDC_QMC_PHASE_OFFSET : xrfdc_hw.h
- XRFDC_QMC_UPDT_DLY_MASK : xrfdc_hw.h
- XRFDC_QMC_UPDT_MODE_FABRIC : xrfdc_hw.h
- XRFDC_QMC_UPDT_MODE_GRP : xrfdc_hw.h
- XRFDC_QMC_UPDT_MODE_MARKER : xrfdc_hw.h
- XRFDC_QMC_UPDT_MODE_MASK : xrfdc_hw.h
- XRFDC_QMC_UPDT_MODE_SLICE : xrfdc_hw.h
- XRFDC_QMC_UPDT_MODE_SYSREF : xrfdc_hw.h
- XRFDC_QMC_UPDT_MODE_TILE : xrfdc_hw.h
- XRFDC_QMC_UPDT_OFFSET : xrfdc_hw.h
- XRFdc_ReadReg : xrfdc_hw.h
- XRFdc_ReadReg16 : xrfdc_hw.h
- XRFdc_ReadReg64 : xrfdc_hw.h
- XRFdc_ReadReg8 : xrfdc_hw.h
- XRFDC_REFCLK_DIV_1_MASK : xrfdc_hw.h
- XRFDC_REFCLK_DIV_2_MASK : xrfdc_hw.h
- XRFDC_REFCLK_DIV_3_MASK : xrfdc_hw.h
- XRFDC_REFCLK_DIV_4_MASK : xrfdc_hw.h
- XRFDC_RESET_OFFSET : xrfdc_hw.h
- XRFDC_RESTART_MASK : xrfdc_hw.h
- XRFDC_RESTART_OFFSET : xrfdc_hw.h
- XRFDC_RESTART_STATE_OFFSET : xrfdc_hw.h
- XRFDC_RSR_START_SHIFT : xrfdc_hw.h
- XRFDC_RX_MC_CFG0_CM_MASK : xrfdc_hw.h
- XRFDC_RX_MC_CFG0_IM3_DITH_MASK : xrfdc_hw.h
- XRFDC_RX_MC_CFG0_IM3_DITH_SHIFT : xrfdc_hw.h
- XRFDC_RX_MC_CFG0_MASK : xrfdc_hw.h
- XRFDC_RX_MC_CFG1_MASK : xrfdc_hw.h
- XRFDC_RX_MC_CFG2_MASK : xrfdc_hw.h
- XRFDC_RX_MC_PWRDWN_MASK : xrfdc_hw.h
- XRFDC_RX_PR_MC_CFG0_MASK : xrfdc_hw.h
- XRFDC_RX_PR_MC_CFG1_MASK : xrfdc_hw.h
- XRFDC_SEL_CB_TO_DECI_MASK : xrfdc_hw.h
- XRFDC_SEL_CB_TO_MIX0_MASK : xrfdc_hw.h
- XRFDC_SEL_CB_TO_MIX0_SHIFT : xrfdc_hw.h
- XRFDC_SEL_CB_TO_MIX1_MASK : xrfdc_hw.h
- XRFDC_SEL_CB_TO_QMC_MASK : xrfdc_hw.h
- XRFDC_SEL_I_IQ_MASK : xrfdc_hw.h
- XRFDC_SEL_Q_IQ_MASK : xrfdc_hw.h
- XRFDC_STATUS_OFFSET : xrfdc_hw.h
- XRFDC_SUBDRP_ADC0_ADDR_MASK : xrfdc_hw.h
- XRFDC_SUBDRP_ADC0_DAT_MASK : xrfdc_hw.h
- XRFDC_SUBDRP_ADC1_ADDR_MASK : xrfdc_hw.h
- XRFDC_SUBDRP_ADC1_DAT_MASK : xrfdc_hw.h
- XRFDC_SUBDRP_ADC2_ADDR_MASK : xrfdc_hw.h
- XRFDC_SUBDRP_ADC2_DAT_MASK : xrfdc_hw.h
- XRFDC_SUBDRP_ADC3_ADDR_MASK : xrfdc_hw.h
- XRFDC_SUBDRP_ADC3_DAT_MASK : xrfdc_hw.h
- XRFDC_SWITCH_MTRX_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_CTRL0_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_CTRL1_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_CTRL2_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_MODE_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS0_BG_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS0_FG_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS1_BG_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS1_FG_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS2_BG_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS2_FG_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS3_BG_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS3_FG_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS4_LSB_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS4_MSB_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS5_LSB_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS5_MSB_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS6_LSB_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS6_MSB_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS7_LSB_MASK : xrfdc_hw.h
- XRFDC_TI_DCB_STS7_MSB_MASK : xrfdc_hw.h
- XRFDC_TI_TISK_CHOP_EN_MASK : xrfdc_hw.h
- XRFDC_TI_TISK_DBG_CTRL_MASK : xrfdc_hw.h
- XRFDC_TI_TISK_DBG_UPDT_RT_MASK : xrfdc_hw.h
- XRFDC_TI_TISK_DITH_DLY_MASK : xrfdc_hw.h
- XRFDC_TI_TISK_EN_MASK : xrfdc_hw.h
- XRFDC_TI_TISK_MODE_MASK : xrfdc_hw.h
- XRFDC_TI_TISK_MU_CM_MASK : xrfdc_hw.h
- XRFDC_TI_TISK_MU_DF_MASK : xrfdc_hw.h
- XRFDC_TI_TISK_ZONE_MASK : xrfdc_hw.h
- XRFDC_TILE_RESET_MASK : xrfdc_hw.h
- XRFDC_TISK_BYPASS0_MASK : xrfdc_hw.h
- XRFDC_TISK_BYPASS1_MASK : xrfdc_hw.h
- XRFDC_TISK_CHOP_EN_MASK : xrfdc_hw.h
- XRFDC_TISK_DAC0_CODE_MASK : xrfdc_hw.h
- XRFDC_TISK_DAC0_OVRID_EN_MASK : xrfdc_hw.h
- XRFDC_TISK_DAC1_CODE_MASK : xrfdc_hw.h
- XRFDC_TISK_DAC1_OVRID_EN_MASK : xrfdc_hw.h
- XRFDC_TISK_DAC2_CODE_MASK : xrfdc_hw.h
- XRFDC_TISK_DAC2_OVRID_EN_MASK : xrfdc_hw.h
- XRFDC_TISK_DAC3_CODE_MASK : xrfdc_hw.h
- XRFDC_TISK_DAC3_OVRID_EN_MASK : xrfdc_hw.h
- XRFDC_TISK_DACP0_CODE_MASK : xrfdc_hw.h
- XRFDC_TISK_DACP0_OVRID_EN_MASK : xrfdc_hw.h
- XRFDC_TISK_DACP1_CODE_MASK : xrfdc_hw.h
- XRFDC_TISK_DACP1_OVRID_EN_MASK : xrfdc_hw.h
- XRFDC_TISK_DACP2_CODE_MASK : xrfdc_hw.h
- XRFDC_TISK_DACP2_OVRID_EN_MASK : xrfdc_hw.h
- XRFDC_TISK_DACP3_CODE_MASK : xrfdc_hw.h
- XRFDC_TISK_DACP3_OVRID_EN_MASK : xrfdc_hw.h
- XRFDC_TISK_DBG_CTRL_MASK : xrfdc_hw.h
- XRFDC_TISK_DBG_UPDT_RT_MASK : xrfdc_hw.h
- XRFDC_TISK_DITH_DLY_MASK : xrfdc_hw.h
- XRFDC_TISK_DZ_MAX_VAL_MASK : xrfdc_hw.h
- XRFDC_TISK_DZ_MIN_VAL_MASK : xrfdc_hw.h
- XRFDC_TISK_EN_MASK : xrfdc_hw.h
- XRFDC_TISK_MODE_MASK : xrfdc_hw.h
- XRFDC_TISK_MU0_MASK : xrfdc_hw.h
- XRFDC_TISK_MU1_MASK : xrfdc_hw.h
- XRFDC_TISK_MU_CM_MASK : xrfdc_hw.h
- XRFDC_TISK_MU_DF_MASK : xrfdc_hw.h
- XRFDC_TISK_SETTLE_MASK : xrfdc_hw.h
- XRFDC_TISK_ZONE_MASK : xrfdc_hw.h
- XRFDC_TISK_ZONE_SHIFT : xrfdc_hw.h
- XRFDC_TRSHD0_AVG_LOW_MASK : xrfdc_hw.h
- XRFDC_TRSHD0_AVG_UPP_MASK : xrfdc_hw.h
- XRFDC_TRSHD0_AVG_UPP_SHIFT : xrfdc_hw.h
- XRFDC_TRSHD0_CLR_MOD_MASK : xrfdc_hw.h
- XRFDC_TRSHD0_EN_MOD_MASK : xrfdc_hw.h
- XRFDC_TRSHD0_OVER_MASK : xrfdc_hw.h
- XRFDC_TRSHD0_STIKY_CLR_MASK : xrfdc_hw.h
- XRFDC_TRSHD0_UNDER_MASK : xrfdc_hw.h
- XRFDC_TRSHD1_AVG_LOW_MASK : xrfdc_hw.h
- XRFDC_TRSHD1_AVG_UPP_MASK : xrfdc_hw.h
- XRFDC_TRSHD1_AVG_UPP_SHIFT : xrfdc_hw.h
- XRFDC_TRSHD1_CLR_MOD_MASK : xrfdc_hw.h
- XRFDC_TRSHD1_EN_MOD_MASK : xrfdc_hw.h
- XRFDC_TRSHD1_OVER_MASK : xrfdc_hw.h
- XRFDC_TRSHD1_STIKY_CLR_MASK : xrfdc_hw.h
- XRFDC_TRSHD1_UNDER_MASK : xrfdc_hw.h
- XRFDC_UPDT_EVNT_MASK : xrfdc_hw.h
- XRFDC_UPDT_EVNT_NCO_MASK : xrfdc_hw.h
- XRFDC_UPDT_EVNT_QMC_MASK : xrfdc_hw.h
- XRFDC_UPDT_EVNT_SLICE_MASK : xrfdc_hw.h
- XRFdc_WriteReg : xrfdc_hw.h
- XRFdc_WriteReg16 : xrfdc_hw.h
- XRFdc_WriteReg64 : xrfdc_hw.h
- XRFdc_WriteReg8 : xrfdc_hw.h