tmrctr: xtmrctr_l.h File Reference

| tmrctr Xilinx SDK Drivers API Documentation

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Macros
xtmrctr_l.h File Reference

## Macros
#define | XTC_DEVICE_TIMER_COUNT 2
| Defines the number of timer counters within a single hardware device. More...
#define | XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset)
| Read one of the timer counter registers. More...
#define | XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)
| Write a specified value to a register of a timer counter. More...
#define | XTmrCtr_SetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)
| Set the Control Status Register of a timer counter to the specified value. More...
#define | XTmrCtr_GetControlStatusReg(BaseAddress, TmrCtrNumber) XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
| Get the Control Status Register of a timer counter. More...
#define | XTmrCtr_GetTimerCounterReg(BaseAddress, TmrCtrNumber) XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCR_OFFSET) \
| Get the Timer Counter Register of a timer counter. More...
#define | XTmrCtr_SetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue)
| Set the Load Register of a timer counter to the specified value. More...
#define | XTmrCtr_GetLoadReg(BaseAddress, TmrCtrNumber) XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET)
| Get the Load Register of a timer counter. More...
#define | XTmrCtr_Enable(BaseAddress, TmrCtrNumber)
| Enable a timer counter such that it starts running. More...
#define | XTmrCtr_Disable(BaseAddress, TmrCtrNumber)
| Disable a timer counter such that it stops running. More...
#define | XTmrCtr_EnableIntr(BaseAddress, TmrCtrNumber)
| Enable the interrupt for a timer counter. More...
#define | XTmrCtr_DisableIntr(BaseAddress, TmrCtrNumber)
| Disable the interrupt for a timer counter. More...
#define | XTmrCtr_LoadTimerCounterReg(BaseAddress, TmrCtrNumber)
| Cause the timer counter to load it's Timer Counter Register with the value in the Load Register. More...
#define | XTmrCtr_HasEventOccurred(BaseAddress, TmrCtrNumber)
| Determine if a timer counter event has occurred. More...
Register Offset Definitions
Register offsets within a timer counter, there are multiple timer counters within a single device
#define | XTC_TCSR_OFFSET 0
| Control/Status register. More...
#define | XTC_TLR_OFFSET 4
| Load register. More...
#define | XTC_TCR_OFFSET 8
| Timer counter register. More...
Control Status Register Bit Definitions
Control Status Register bit masks Used to configure the timer counter device.
#define | XTC_CSR_CASC_MASK 0x00000800
| Cascade Mode. More...
#define | XTC_CSR_ENABLE_ALL_MASK 0x00000400
| Enables all timer counters. More...
#define | XTC_CSR_ENABLE_PWM_MASK 0x00000200
| Enables the Pulse Width Modulation. More...
#define | XTC_CSR_INT_OCCURED_MASK 0x00000100
| If bit is set, an interrupt has occured. More...
#define | XTC_CSR_ENABLE_TMR_MASK 0x00000080
| Enables only the specific timer. More...
#define | XTC_CSR_ENABLE_INT_MASK 0x00000040
| Enables the interrupt output. More...
#define | XTC_CSR_LOAD_MASK 0x00000020
| Loads the timer using the load value provided earlier in the Load Register, XTC_TLR_OFFSET. More...
#define | XTC_CSR_AUTO_RELOAD_MASK 0x00000010
| In compare mode, configures the timer counter to reload from the Load Register. More...
#define | XTC_CSR_EXT_CAPTURE_MASK 0x00000008
| Enables the external input to the timer counter. More...
#define | XTC_CSR_EXT_GENERATE_MASK 0x00000004
| Enables the external generate output for the timer. More...
#define | XTC_CSR_DOWN_COUNT_MASK 0x00000002
| Configures the timer counter to count down from start value, the default is to count up. More...
#define | XTC_CSR_CAPTURE_MODE_MASK 0x00000001
| Enables the timer to capture the timer counter value when the external capture line is asserted. More...