devcfg: xdevcfg_hw.h File Reference

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Macros | Functions
xdevcfg_hw.h File Reference

## Macros
#define | XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF
| Invalid DMA address. More...
#define | XDCFG_UNLOCK_DATA 0x757BDF0D
| First APB access data. More...
#define | XDCFG_BASE_ADDRESS 0xF8007000
| Device Config base address. More...
#define | XDCFG_CONFIG_RESET_VALUE 0x508
| Config reg reset value. More...
#define | XDcfg_ReadReg(BaseAddr, RegOffset) Xil_In32((BaseAddr) + (RegOffset))
| Read the given register. More...
#define | XDcfg_WriteReg(BaseAddr, RegOffset, Data) Xil_Out32((BaseAddr) + (RegOffset), (Data))
| Write to the given register. More...
Register Map
Offsets of registers from the start of the device
#define | XDCFG_CTRL_OFFSET 0x00
| Control Register. More...
#define | XDCFG_LOCK_OFFSET 0x04
| Lock Register. More...
#define | XDCFG_CFG_OFFSET 0x08
| Configuration Register. More...
#define | XDCFG_INT_STS_OFFSET 0x0C
| Interrupt Status Register. More...
#define | XDCFG_INT_MASK_OFFSET 0x10
| Interrupt Mask Register. More...
#define | XDCFG_STATUS_OFFSET 0x14
| Status Register. More...
#define | XDCFG_DMA_SRC_ADDR_OFFSET 0x18
| DMA Source Address Register. More...
#define | XDCFG_DMA_DEST_ADDR_OFFSET 0x1C
| DMA Destination Address Reg. More...
#define | XDCFG_DMA_SRC_LEN_OFFSET 0x20
| DMA Source Transfer Length. More...
#define | XDCFG_DMA_DEST_LEN_OFFSET 0x24
| DMA Destination Transfer. More...
#define | XDCFG_ROM_SHADOW_OFFSET 0x28
| DMA ROM Shadow Register. More...
#define | XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C
| Multi BootAddress Pointer. More...
#define | XDCFG_SW_ID_OFFSET 0x30
| Software ID Register. More...
#define | XDCFG_UNLOCK_OFFSET 0x34
| Unlock Register. More...
#define | XDCFG_MCTRL_OFFSET 0x80
| Miscellaneous Control Reg. More...
Control Register Bit definitions
#define | XDCFG_CTRL_FORCE_RST_MASK 0x80000000
| Force into Secure Reset. More...
#define | XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000
| Program signal to Reset FPGA. More...
#define | XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000
| Control PL POR timer. More...
#define | XDCFG_CTRL_PCAP_PR_MASK 0x08000000
| Enable PCAP for PR. More...
#define | XDCFG_CTRL_PCAP_MODE_MASK 0x04000000
| Enable PCAP. More...
#define | XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
| Enable PCAP send data to FPGA every 4 PCAP cycles. More...
#define | XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000
| Multiboot Enable. More...
#define | XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000
| JTAG Chain Disable. More...
#define | XDCFG_CTRL_USER_MODE_MASK 0x00008000
| User Mode Mask. More...
#define | XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000
| AES key source. More...
#define | XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00
| AES Enable Mask. More...
#define | XDCFG_CTRL_SEU_EN_MASK 0x00000100
| SEU Enable Mask. More...
#define | XDCFG_CTRL_SEC_EN_MASK 0x00000080
| Secure/Non Secure Status mask. More...
#define | XDCFG_CTRL_SPNIDEN_MASK 0x00000040
| Secure Non Invasive Debug Enable. More...
#define | XDCFG_CTRL_SPIDEN_MASK 0x00000020
| Secure Invasive Debug Enable. More...
#define | XDCFG_CTRL_NIDEN_MASK 0x00000010
| Non-Invasive Debug Enable. More...
#define | XDCFG_CTRL_DBGEN_MASK 0x00000008
| Invasive Debug Enable. More...
#define | XDCFG_CTRL_DAP_EN_MASK 0x00000007
| DAP Enable Mask. More...
Lock register bit definitions
#define | XDCFG_LOCK_AES_EFUSE_MASK 0x00000010
| Lock AES Efuse bit. More...
#define | XDCFG_LOCK_AES_EN_MASK 0x00000008
| Lock AES_EN update. More...
#define | XDCFG_LOCK_SEU_MASK 0x00000004
| Lock SEU_En update. More...
#define | XDCFG_LOCK_SEC_MASK 0x00000002
| Lock SEC_EN and USER_MODE. More...
#define | XDCFG_LOCK_DBG_MASK 0x00000001
| This bit locks security config including: DAP_En, DBGEN,, NIDEN, SPNIEN. More...
Config Register Bit definitions
#define | XDCFG_CFG_RFIFO_TH_MASK 0x00000C00
| Read FIFO Threshold Mask. More...
#define | XDCFG_CFG_WFIFO_TH_MASK 0x00000300
| Write FIFO Threshold Mask. More...
#define | XDCFG_CFG_RCLK_EDGE_MASK 0x00000080
| Read data active clock edge. More...
#define | XDCFG_CFG_WCLK_EDGE_MASK 0x00000040
| Write data active clock edge. More...
#define | XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020
| Disable Source address increment mask. More...
#define | XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010
| Disable Destination address increment mask. More...
Interrupt Status/Mask Register Bit definitions
#define | XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000
| Tri-state IO during HIZ. More...
#define | XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000
| First configuration done. More...
#define | XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000
| Global power down. More...
#define | XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000
| Tri-state IO during configuration. More...
#define | XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000
| PL configuration reset. More...
#define | XDCFG_IXR_AXI_WTO_MASK 0x00800000
| AXI Write Address or Data or response timeout. More...
#define | XDCFG_IXR_AXI_WERR_MASK 0x00400000
| AXI Write response error. More...
#define | XDCFG_IXR_AXI_RTO_MASK 0x00200000
| AXI Read Address or response timeout. More...
#define | XDCFG_IXR_AXI_RERR_MASK 0x00100000
| AXI Read response error. More...
#define | XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000
| Rx FIFO Overflow. More...
#define | XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000
| Tx FIFO less than threshold. More...
#define | XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000
| Rx FIFO greater than threshold. More...
#define | XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000
| Illegal DMA command. More...
#define | XDCFG_IXR_DMA_Q_OV_MASK 0x00004000
| DMA command queue overflow. More...
#define | XDCFG_IXR_DMA_DONE_MASK 0x00002000
| DMA Command Done. More...
#define | XDCFG_IXR_D_P_DONE_MASK 0x00001000
| DMA and PCAP transfers Done. More...
#define | XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800
| PCAP to DMA transfer length error. More...
#define | XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040
| HMAC error mask. More...
#define | XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020
| SEU Error mask. More...
#define | XDCFG_IXR_PCFG_POR_B_MASK 0x00000010
| FPGA POR mask. More...
#define | XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008
| FPGA Reset mask. More...
#define | XDCFG_IXR_PCFG_DONE_MASK 0x00000004
| Done Signal Mask. More...
#define | XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002
| Detect Positive edge of Init Signal. More...
#define | XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001
| Detect Negative edge of Init Signal. More...
#define | XDCFG_IXR_ERROR_FLAGS_MASK
#define | XDCFG_IXR_ALL_MASK 0x00F7F8EF
Status Register Bit definitions
#define | XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000
| DMA command Queue full. More...
#define | XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000
| DMA command Queue empty. More...
#define | XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
| Number of completed DMA transfers. More...
#define | XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000
| Rx FIFO level. More...
#define | XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000
| Tx FIFO level. More...
#define | XDCFG_STATUS_PSS_GTS_USR_B 0x00000800
| Tri-state IO during HIZ. More...
#define | XDCFG_STATUS_PSS_FST_CFG_B 0x00000400
| First PL config done. More...
#define | XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200
| Global power down. More...
#define | XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100
| Tri-state IO during config. More...
#define | XDCFG_STATUS_SECURE_RST_MASK 0x00000080
| Secure Reset POR Status. More...
#define | XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040
| Illegal APB access. More...
#define | XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020
| PL config reset status. More...
#define | XDCFG_STATUS_PCFG_INIT_MASK 0x00000010
| FPGA Init Status. More...
#define | XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
| BBRAM key disable. More...
#define | XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004
| Efuse Security Enable Status. More...
#define | XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002
| EFuse JTAG Disable status. More...
DMA Source/Destination Transfer Length Register Bit definitions
#define | XDCFG_DMA_LEN_MASK 0x7FFFFFF
| Length Mask. More...
Miscellaneous Control Register Bit definitions
#define | XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000
| PS Version Mask. More...
#define | XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28
| PS Version Shift. More...
#define | XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010
| PCAP loopback mask. More...
FIFO Threshold Bit definitions
#define | XDCFG_CFG_FIFO_QUARTER 0x0
| Quarter empty. More...
#define | XDCFG_CFG_FIFO_HALF 0x1
| Half empty. More...
#define | XDCFG_CFG_FIFO_3QUARTER 0x2
| 3/4 empty More...
#define | XDCFG_CFG_FIFO_EMPTY 0x4
| Empty. More...

## Functions
void | XDcfg_ResetHw (u32 BaseAddr)
| This function perform the reset sequence to the given devcfg interface by configuring the appropriate control bits in the devcfg specifc registers the devcfg reset squence involves the following steps Disable all the interuupts Clear the status Update relevant config registers with reset values Disbale the looopback mode and pcap rate enable. More...