enhance: xenhance_hw.h File Reference

| enhance Xilinx SDK Drivers API Documentation

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Macros
xenhance_hw.h File Reference

## Macros
#define | XENHANCE_HW_H_
| Prevent circular inclusions by using protection macros. More...
#define | XEnhance_In32 Xil_In32
| Enhance Input Operation. More...
#define | XEnhance_Out32 Xil_Out32
| Enhance Output Operation. More...
#define | XEnhance_ReadReg(BaseAddress, RegOffset) XEnhance_In32((BaseAddress) + (u32)(RegOffset))
| This function macro reads the given register. More...
#define | XEnhance_WriteReg(BaseAddress, RegOffset, Data) XEnhance_Out32((BaseAddress) + (u32)(RegOffset), (Data))
| This function macro writes the given register. More...
Control Registers
#define | XENH_CONTROL_OFFSET 0x0000
| Control Offset. More...
#define | XENH_STATUS_OFFSET 0x0004
| Status Offset. More...
#define | XENH_ERROR_OFFSET 0x0008
| Error Offset. More...
#define | XENH_IRQ_EN_OFFSET 0x000C
| IRQ Enable Offset. More...
#define | XENH_VERSION_OFFSET 0x0010
| Version Offset. More...
#define | XENH_SYSDEBUG0_OFFSET 0x0014
| System Debug 0 Offset. More...
#define | XENH_SYSDEBUG1_OFFSET 0x0018
| System Debug 1 Offset. More...
#define | XENH_SYSDEBUG2_OFFSET 0x001C
| System Debug 2 Offset. More...
Timing Control Registers
#define | XENH_ACTIVE_SIZE_OFFSET 0x0020
| Horizontal and Vertical Active Frame Size Offset. More...
Core Specific Registers
#define | XENH_NOISE_THRESHOLD_OFFSET 0x0100
| Noise Reduction Control Active. More...
#define | XENH_ENHANCE_STRENGTH_OFFSET 0x0104
| Edge Enhancement Control Active. More...
#define | XENH_HALO_SUPPRESS_OFFSET 0x0108
| Halo Suppression Control Active. More...
Enhance Control Register Bit Masks
#define | XENH_CTL_SW_EN_MASK 0x00000001
| Enable Mask. More...
#define | XENH_CTL_RUE_MASK 0x00000002
| Register Update Enable Mask. More...
#define | XENH_CTL_BPE_MASK 0x00000010
| Bypass Mask. More...
#define | XENH_CTL_TPE_MASK 0x00000020
| Test Pattern Mask. More...
#define | XENH_CTL_AUTORESET_MASK 0x40000000
| Software Reset - Auto-synchronize to SOF Mask. More...
#define | XENH_CTL_RESET_MASK 0x80000000
| Software Reset - Instantaneous Mask. More...
Interrupt Register Bit Masks. It is applicable for
Status and Irq_Enable Registers
#define | XENH_IXR_PROCS_STARTED_MASK 0x00000001
| Process started Mask. More...
#define | XENH_IXR_EOF_MASK 0x00000002
| End-Of-Frame Mask. More...
#define | XENH_IXR_SE_MASK 0x00010000
| Slave Error Mask. More...
#define | XENH_IXR_ALLINTR_MASK 0x00010003
| OR'ing of all Mask. More...
Enhance Error Register Bit Masks
#define | XENH_ERR_EOL_EARLY_MASK 0x00000001
| Frame EOL early Mask. More...
#define | XENH_ERR_EOL_LATE_MASK 0x00000002
| Frame EOL late Mask. More...
#define | XENH_ERR_SOF_EARLY_MASK 0x00000004
| Frame SOF early Mask. More...
#define | XENH_ERR_SOF_LATE_MASK 0x00000008
| Frame SOF late Mask. More...
Enhance Version Register bit definition
#define | XENH_VER_REV_NUM_MASK 0x000000FF
| Revision Number Mask. More...
#define | XENH_VER_PID_MASK 0x00000F00
| Patch ID Mask. More...
#define | XENH_VER_MINOR_MASK 0x00FF0000
| Version Minor Mask. More...
#define | XENH_VER_MAJOR_MASK 0xFF000000
| Version Major Mask. More...
#define | XENH_VER_REV_MASK 0x0000F000
| VersionRevision Mask. More...
#define | XENH_VER_INTERNAL_SHIFT 8
| Version Internal Shift. More...
#define | XENH_VER_REV_SHIFT 12
| Version Revision Shift. More...
#define | XENH_VER_MINOR_SHIFT 16
| Version Minor Shift. More...
#define | XENH_VER_MAJOR_SHIFT 24
| Version Major Shift. More...
Enhance ActiveSize register Masks and Shifts
#define | XENH_ACTSIZE_NUM_PIXEL_MASK 0x00001FFF
| Active size Mask. More...
#define | XENH_ACTSIZE_NUM_LINE_MASK 0x1FFF0000
| Number of Active lines per Frame (Vertical) Mask. More...
#define | XENH_ACTSIZE_NUM_LINE_SHIFT 16
| Active size Shift. More...
Enhance Noise Threshold Register Bit Masks
#define | XENH_NOISE_THRESHOLD_MASK 0x0000FFFF
| Noise Threshold Mask. More...
Enhance Strength Register Bit Masks
#define | XENH_STRENGTH_MASK 0x0000FFFF
| Enhance Strength Mask. More...
Enhance Halo Suppress Register Bit Masks
#define | XENH_HALO_SUPPRESS_MASK 0x0000FFFF
| Halo Suppress Mask. More...
Backward compatibility macros
#define | ENHANCE_CONTROL XENH_CONTROL_OFFSET
#define | ENHANCE_STATUS XENH_STATUS_OFFSET
#define | ENHANCE_ERROR XENH_ERROR_OFFSET
#define | ENHANCE_IRQ_ENABLE XENH_IRQ_EN_OFFSET
#define | ENHANCE_VERSION XENH_VERSION_OFFSET
#define | ENHANCE_SYSDEBUG0 XENH_SYSDEBUG0_OFFSET
#define | ENHANCE_SYSDEBUG1 XENH_SYSDEBUG1_OFFSET
#define | ENHANCE_SYSDEBUG2 XENH_SYSDEBUG2_OFFSET
#define | ENHANCE_ACTIVE_SIZE XENH_ACTIVE_SIZE_OFFSET
#define | ENHANCE_NOISE_THRESHOLD XENH_NOISE_THRESHOLD_OFFSET
#define | ENHANCE_ENHANCE_STRENGTH XENH_ENHANCE_STRENGTH_OFFSET
#define | ENHANCE_HALO_SUPPRESS XENH_HALO_SUPPRESS_OFFSET
#define | ENHANCE_CTL_EN_MASK XENH_CTL_SW_EN_MASK
#define | ENHANCE_CTL_RU_MASK XENH_CTL_RUE_MASK
#define | ENHANCE_CTL_RESET XENH_CTL_RESET_MASK
#define | ENHANCE_CTL_AUTORESET XENH_CTL_AUTORESET_MASK
#define | ENHANCE_In32 XEnhance_In32
#define | ENHANCE_Out32 XEnhance_Out32
#define | ENHANCE_ReadReg XEnhance_ReadReg
#define | ENHANCE_WriteReg XEnhance_WriteReg
Interrupt Registers
#define | XENH_ISR_OFFSET XENH_STATUS_OFFSET
| Interrupt status register generates a interrupt if the corresponding bits of interrupt enable register bits are set. More...
#define | XENH_IER_OFFSET XENH_IRQ_EN_OFFSET
| Interrupt Enable Register corresponds to Status bits. More...