xadcps: Xadcps_v2_3

| xadcps Xilinx SDK Drivers API Documentation

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Data Structures | Macros | Functions | Variables
Xadcps_v2_3

## Data Structures
struct | XAdcPs_Config
| This typedef contains configuration information for the XADC/ADC device. More...
struct | XAdcPs
| The driver's instance data. More...

## Macros
#define | XAdcPs_IsEventSamplingModeSet(InstancePtr)
| This macro checks if the XADC device is in Event Sampling mode. More...
#define | XAdcPs_IsExternalMuxModeSet(InstancePtr)
| This macro checks if the XADC device is in External Mux mode. More...
#define | XAdcPs_RawToTemperature(AdcData) ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
| This macro converts XADC Raw Data to Temperature(centigrades). More...
#define | XAdcPs_RawToVoltage(AdcData) ((((float)(AdcData))* (3.0f))/65536.0f)
| This macro converts XADC/ADC Raw Data to Voltage(volts). More...
#define | XAdcPs_TemperatureToRaw(Temperature) ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
| This macro converts Temperature in centigrades to XADC/ADC Raw Data. More...
#define | XAdcPs_VoltageToRaw(Voltage) ((int)((Voltage)*65536.0f/3.0f))
| This macro converts Voltage in Volts to XADC/ADC Raw Data. More...
#define | XAdcPs_WriteFifo(InstancePtr, Data)
| This macro is used for writing to the XADC Registers using the command FIFO. More...
#define | XAdcPs_ReadFifo(InstancePtr)
| This macro is used for reading from the XADC Registers using the data FIFO. More...
#define | XAdcPs_ReadReg(BaseAddress, RegOffset) (Xil_In32((BaseAddress) + (RegOffset)))
| Read a register of the XADC device. More...
#define | XAdcPs_WriteReg(BaseAddress, RegOffset, Data) (Xil_Out32((BaseAddress) + (RegOffset), (Data)))
| Write a register of the XADC device. More...
#define | XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite)
| Formats the data to be written to the the XADC registers. More...

## Functions
void | XAdcPs_WriteInternalReg (XAdcPs *InstancePtr, u32 RegOffset, u32 Data)
| This function is used for writing to XADC Registers using the command FIFO. More...
u32 | XAdcPs_ReadInternalReg (XAdcPs *InstancePtr, u32 RegOffset)
| This function is used for reading from the XADC Registers using the Data FIFO. More...
int | XAdcPs_CfgInitialize (XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr, u32 EffectiveAddr)
| This function initializes a specific XAdcPs device/instance. More...
void | XAdcPs_SetConfigRegister (XAdcPs *InstancePtr, u32 Data)
| The functions sets the contents of the Config Register. More...
u32 | XAdcPs_GetConfigRegister (XAdcPs *InstancePtr)
| The functions reads the contents of the Config Register. More...
u32 | XAdcPs_GetMiscStatus (XAdcPs *InstancePtr)
| The functions reads the contents of the Miscellaneous Status Register. More...
void | XAdcPs_SetMiscCtrlRegister (XAdcPs *InstancePtr, u32 Data)
| The functions sets the contents of the Miscellaneous Control register. More...
u32 | XAdcPs_GetMiscCtrlRegister (XAdcPs *InstancePtr)
| The functions reads the contents of the Miscellaneous control register. More...
void | XAdcPs_Reset (XAdcPs *InstancePtr)
| This function resets the XADC Hard Macro in the device. More...
u16 | XAdcPs_GetAdcData (XAdcPs *InstancePtr, u8 Channel)
| Get the ADC converted data for the specified channel. More...
u16 | XAdcPs_GetCalibCoefficient (XAdcPs *InstancePtr, u8 CoeffType)
| This function gets the calibration coefficient data for the specified parameter. More...
u16 | XAdcPs_GetMinMaxMeasurement (XAdcPs *InstancePtr, u8 MeasurementType)
| This function reads the Minimum/Maximum measurement for one of the specified parameters. More...
void | XAdcPs_SetAvg (XAdcPs *InstancePtr, u8 Average)
| This function sets the number of samples of averaging that is to be done for all the channels in both the single channel mode and sequence mode of operations. More...
u8 | XAdcPs_GetAvg (XAdcPs *InstancePtr)
| This function returns the number of samples of averaging configured for all the channels in the Configuration Register 0. More...
int | XAdcPs_SetSingleChParams (XAdcPs *InstancePtr, u8 Channel, int IncreaseAcqCycles, int IsEventMode, int IsDifferentialMode)
| The function sets the given parameters in the Configuration Register 0 in the single channel mode. More...
void | XAdcPs_SetAlarmEnables (XAdcPs *InstancePtr, u16 AlmEnableMask)
| This function enables the alarm outputs for the specified alarms in the Configuration Register 1. More...
u16 | XAdcPs_GetAlarmEnables (XAdcPs *InstancePtr)
| This function gets the status of the alarm output enables in the Configuration Register 1. More...
void | XAdcPs_SetCalibEnables (XAdcPs *InstancePtr, u16 Calibration)
| This function enables the specified calibration in the Configuration Register 1 : More...
u16 | XAdcPs_GetCalibEnables (XAdcPs *InstancePtr)
| This function reads the value of the calibration enables from the Configuration Register 1. More...
void | XAdcPs_SetSequencerMode (XAdcPs *InstancePtr, u8 SequencerMode)
| This function sets the specified Channel Sequencer Mode in the Configuration Register 1 : More...
u8 | XAdcPs_GetSequencerMode (XAdcPs *InstancePtr)
| This function gets the channel sequencer mode from the Configuration Register 1. More...
void | XAdcPs_SetAdcClkDivisor (XAdcPs *InstancePtr, u8 Divisor)
| The function sets the frequency of the ADCCLK by configuring the DCLK to ADCCLK ratio in the Configuration Register #2. More...
u8 | XAdcPs_GetAdcClkDivisor (XAdcPs *InstancePtr)
| The function gets the ADCCLK divisor from the Configuration Register 2. More...
int | XAdcPs_SetSeqChEnables (XAdcPs *InstancePtr, u32 ChEnableMask)
| This function enables the specified channels in the ADC Channel Selection Sequencer Registers. More...
u32 | XAdcPs_GetSeqChEnables (XAdcPs *InstancePtr)
| This function gets the channel enable bits status from the ADC Channel Selection Sequencer Registers. More...
int | XAdcPs_SetSeqAvgEnables (XAdcPs *InstancePtr, u32 AvgEnableChMask)
| This function enables the averaging for the specified channels in the ADC Channel Averaging Enable Sequencer Registers. More...
u32 | XAdcPs_GetSeqAvgEnables (XAdcPs *InstancePtr)
| This function returns the channels for which the averaging has been enabled in the ADC Channel Averaging Enables Sequencer Registers. More...
int | XAdcPs_SetSeqInputMode (XAdcPs *InstancePtr, u32 InputModeChMask)
| This function sets the Analog input mode for the specified channels in the ADC Channel Analog-Input Mode Sequencer Registers. More...
u32 | XAdcPs_GetSeqInputMode (XAdcPs *InstancePtr)
| This function gets the Analog input mode for all the channels from the ADC Channel Analog-Input Mode Sequencer Registers. More...
int | XAdcPs_SetSeqAcqTime (XAdcPs *InstancePtr, u32 AcqCyclesChMask)
| This function sets the number of Acquisition cycles in the ADC Channel Acquisition Time Sequencer Registers. More...
u32 | XAdcPs_GetSeqAcqTime (XAdcPs *InstancePtr)
| This function gets the status of acquisition from the ADC Channel Acquisition Time Sequencer Registers. More...
void | XAdcPs_SetAlarmThreshold (XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value)
| This functions sets the contents of the given Alarm Threshold Register. More...
u16 | XAdcPs_GetAlarmThreshold (XAdcPs *InstancePtr, u8 AlarmThrReg)
| This function returns the contents of the specified Alarm Threshold Register. More...
void | XAdcPs_EnableUserOverTemp (XAdcPs *InstancePtr)
| This function enables programming of the powerdown temperature for the OverTemp signal in the OT Powerdown register. More...
void | XAdcPs_DisableUserOverTemp (XAdcPs *InstancePtr)
| This function disables programming of the powerdown temperature for the OverTemp signal in the OT Powerdown register. More...
void | XAdcPs_SetSequencerEvent (XAdcPs *InstancePtr, int IsEventMode)
| The function enables the Event mode or Continuous mode in the sequencer mode. More...
int | XAdcPs_GetSamplingMode (XAdcPs *InstancePtr)
| This function returns the sampling mode. More...
void | XAdcPs_SetMuxMode (XAdcPs *InstancePtr, int MuxMode, u8 Channel)
| This function sets the External Mux mode. More...
void | XAdcPs_SetPowerdownMode (XAdcPs *InstancePtr, u32 Mode)
| This function sets the Power Down mode. More...
u32 | XAdcPs_GetPowerdownMode (XAdcPs *InstancePtr)
| This function gets the Power Down mode. More...
XAdcPs_Config * | XAdcPs_LookupConfig (u16 DeviceId)
| Functions in xadcps_sinit.c. More...
int | XAdcPs_SelfTest (XAdcPs *InstancePtr)
| Functions in xadcps_selftest.c. More...
void | XAdcPs_IntrEnable (XAdcPs *InstancePtr, u32 Mask)
| Functions in xadcps_intr.c. More...
void | XAdcPs_IntrDisable (XAdcPs *InstancePtr, u32 Mask)
| This function disables the specified interrupts in the device. More...
u32 | XAdcPs_IntrGetEnabled (XAdcPs *InstancePtr)
| This function returns the enabled interrupts read from the Interrupt Mask Register (IPIER). More...
u32 | XAdcPs_IntrGetStatus (XAdcPs *InstancePtr)
| This function returns the interrupt status read from Interrupt Status Register(IPISR). More...
void | XAdcPs_IntrClear (XAdcPs *InstancePtr, u32 Mask)
| This function clears the specified interrupts in the Interrupt Status Register (IPISR). More...

## Variables
XAdcPs_Config | XAdcPs_ConfigTable [XPAR_XADCPS_NUM_INSTANCES]
| This table contains configuration information for each XADC Monitor/ADC device in the system. More...
XAdcPs_Config | XAdcPs_ConfigTable []
| This table contains configuration information for each XADC Monitor/ADC device in the system. More...

## Indexes for the different channels.
#define | XADCPS_CH_TEMP 0x0
| On Chip Temperature. More...
#define | XADCPS_CH_VCCINT 0x1
| VCCINT. More...
#define | XADCPS_CH_VCCAUX 0x2
| VCCAUX. More...
#define | XADCPS_CH_VPVN 0x3
| VP/VN Dedicated analog inputs. More...
#define | XADCPS_CH_VREFP 0x4
| VREFP. More...
#define | XADCPS_CH_VREFN 0x5
| VREFN. More...
#define | XADCPS_CH_VBRAM 0x6
| On-chip VBRAM Data Reg, 7 series. More...
#define | XADCPS_CH_SUPPLY_CALIB 0x07
| Supply Calib Data Reg. More...
#define | XADCPS_CH_ADC_CALIB 0x08
| ADC Offset Channel Reg. More...
#define | XADCPS_CH_GAINERR_CALIB 0x09
| Gain Error Channel Reg. More...
#define | XADCPS_CH_VCCPINT 0x0D
| On-chip PS VCCPINT Channel , Zynq. More...
#define | XADCPS_CH_VCCPAUX 0x0E
| On-chip PS VCCPAUX Channel , Zynq. More...
#define | XADCPS_CH_VCCPDRO 0x0F
| On-chip PS VCCPDRO Channel , Zynq. More...
#define | XADCPS_CH_AUX_MIN 16
| Channel number for 1st Aux Channel. More...
#define | XADCPS_CH_AUX_MAX 31
| Channel number for Last Aux channel. More...

## Indexes for reading the Calibration Coefficient Data.
#define | XADCPS_CALIB_SUPPLY_COEFF 0
| Supply Offset Calib Coefficient. More...
#define | XADCPS_CALIB_ADC_COEFF 1
| ADC Offset Calib Coefficient. More...
#define | XADCPS_CALIB_GAIN_ERROR_COEFF 2
| Gain Error Calib Coefficient. More...

## Indexes for reading the Minimum/Maximum Measurement Data.
#define | XADCPS_MAX_TEMP 0
| Maximum Temperature Data. More...
#define | XADCPS_MAX_VCCINT 1
| Maximum VCCINT Data. More...
#define | XADCPS_MAX_VCCAUX 2
| Maximum VCCAUX Data. More...
#define | XADCPS_MAX_VBRAM 3
| Maximum VBRAM Data. More...
#define | XADCPS_MIN_TEMP 4
| Minimum Temperature Data. More...
#define | XADCPS_MIN_VCCINT 5
| Minimum VCCINT Data. More...
#define | XADCPS_MIN_VCCAUX 6
| Minimum VCCAUX Data. More...
#define | XADCPS_MIN_VBRAM 7
| Minimum VBRAM Data. More...
#define | XADCPS_MAX_VCCPINT 8
| Maximum VCCPINT Register , Zynq. More...
#define | XADCPS_MAX_VCCPAUX 9
| Maximum VCCPAUX Register , Zynq. More...
#define | XADCPS_MAX_VCCPDRO 0xA
| Maximum VCCPDRO Register , Zynq. More...
#define | XADCPS_MIN_VCCPINT 0xC
| Minimum VCCPINT Register , Zynq. More...
#define | XADCPS_MIN_VCCPAUX 0xD
| Minimum VCCPAUX Register , Zynq. More...
#define | XADCPS_MIN_VCCPDRO 0xE
| Minimum VCCPDRO Register , Zynq. More...

## Alarm Threshold(Limit) Register (ATR) indexes.
#define | XADCPS_ATR_TEMP_UPPER 0
| High user Temperature. More...
#define | XADCPS_ATR_VCCINT_UPPER 1
| VCCINT high voltage limit register. More...
#define | XADCPS_ATR_VCCAUX_UPPER 2
| VCCAUX high voltage limit register. More...
#define | XADCPS_ATR_OT_UPPER 3
| VCCAUX high voltage limit register. More...
#define | XADCPS_ATR_TEMP_LOWER 4
| Upper Over Temperature limit Reg. More...
#define | XADCPS_ATR_VCCINT_LOWER 5
| VCCINT high voltage limit register. More...
#define | XADCPS_ATR_VCCAUX_LOWER 6
| VCCAUX low voltage limit register. More...
#define | XADCPS_ATR_OT_LOWER 7
| Lower Over Temperature limit. More...
#define | XADCPS_ATR_VBRAM_UPPER_ 8
| VRBAM Upper Alarm Reg, 7 Series. More...
#define | XADCPS_ATR_VCCPINT_UPPER 9
| VCCPINT Upper Alarm Reg, Zynq. More...
#define | XADCPS_ATR_VCCPAUX_UPPER 0xA
| VCCPAUX Upper Alarm Reg, Zynq. More...
#define | XADCPS_ATR_VCCPDRO_UPPER 0xB
| VCCPDRO Upper Alarm Reg, Zynq. More...
#define | XADCPS_ATR_VBRAM_LOWER 0xC
| VRBAM Lower Alarm Reg, 7 Series. More...
#define | XADCPS_ATR_VCCPINT_LOWER 0xD
| VCCPINT Lower Alarm Reg , Zynq. More...
#define | XADCPS_ATR_VCCPAUX_LOWER 0xE
| VCCPAUX Lower Alarm Reg , Zynq. More...
#define | XADCPS_ATR_VCCPDRO_LOWER 0xF
| VCCPDRO Lower Alarm Reg , Zynq. More...

## Averaging to be done for the channels.
#define | XADCPS_AVG_0_SAMPLES 0
| No Averaging. More...
#define | XADCPS_AVG_16_SAMPLES 1
| Average 16 samples. More...
#define | XADCPS_AVG_64_SAMPLES 2
| Average 64 samples. More...
#define | XADCPS_AVG_256_SAMPLES 3
| Average 256 samples. More...

## Channel Sequencer Modes of operation
#define | XADCPS_SEQ_MODE_SAFE 0
| Default Safe Mode. More...
#define | XADCPS_SEQ_MODE_ONEPASS 1
| Onepass through Sequencer. More...
#define | XADCPS_SEQ_MODE_CONTINPASS 2
| Continuous Cycling Sequencer. More...
#define | XADCPS_SEQ_MODE_SINGCHAN 3
| Single channel -No Sequencing. More...
#define | XADCPS_SEQ_MODE_SIMUL_SAMPLING 4
| Simultaneous sampling. More...
#define | XADCPS_SEQ_MODE_INDEPENDENT 8
| Independent mode. More...

## Power Down Modes
#define | XADCPS_PD_MODE_NONE 0
| No Power Down. More...
#define | XADCPS_PD_MODE_ADCB 1
| Power Down ADC B. More...
#define | XADCPS_PD_MODE_XADC 2
| Power Down ADC A and ADC B. More...

## Register offsets of XADC in the Device Config
The following constants provide access to each of the registers of the XADC device.
#define | XADCPS_CFG_OFFSET 0x00
| Configuration Register. More...
#define | XADCPS_INT_STS_OFFSET 0x04
| Interrupt Status Register. More...
#define | XADCPS_INT_MASK_OFFSET 0x08
| Interrupt Mask Register. More...
#define | XADCPS_MSTS_OFFSET 0x0C
| Misc status register. More...
#define | XADCPS_CMDFIFO_OFFSET 0x10
| Command FIFO Register. More...
#define | XADCPS_RDFIFO_OFFSET 0x14
| Read FIFO Register. More...
#define | XADCPS_MCTL_OFFSET 0x18
| Misc control register. More...

## XADC Config Register Bit definitions
#define | XADCPS_CFG_ENABLE_MASK 0x80000000
| Enable access from PS mask. More...
#define | XADCPS_CFG_CFIFOTH_MASK 0x00F00000
| Command FIFO Threshold mask. More...
#define | XADCPS_CFG_DFIFOTH_MASK 0x000F0000
| Data FIFO Threshold mask. More...
#define | XADCPS_CFG_WEDGE_MASK 0x00002000
| Write Edge Mask. More...
#define | XADCPS_CFG_REDGE_MASK 0x00001000
| Read Edge Mask. More...
#define | XADCPS_CFG_TCKRATE_MASK 0x00000300
| Clock freq control. More...
#define | XADCPS_CFG_IGAP_MASK 0x0000001F
| Idle Gap between successive commands. More...

## XADC Interrupt Status/Mask Register Bit definitions
The definitions are same for the Interrupt Status Register and Interrupt Mask Register. They are defined only once.
#define | XADCPS_INTX_ALL_MASK 0x000003FF
| Alarm Signals Mask. More...
#define | XADCPS_INTX_CFIFO_LTH_MASK 0x00000200
| CMD FIFO less than threshold. More...
#define | XADCPS_INTX_DFIFO_GTH_MASK 0x00000100
| Data FIFO greater than threshold. More...
#define | XADCPS_INTX_OT_MASK 0x00000080
| Over temperature Alarm Status. More...
#define | XADCPS_INTX_ALM_ALL_MASK 0x0000007F
| Alarm Signals Mask. More...
#define | XADCPS_INTX_ALM6_MASK 0x00000040
| Alarm 6 Mask. More...
#define | XADCPS_INTX_ALM5_MASK 0x00000020
| Alarm 5 Mask. More...
#define | XADCPS_INTX_ALM4_MASK 0x00000010
| Alarm 4 Mask. More...
#define | XADCPS_INTX_ALM3_MASK 0x00000008
| Alarm 3 Mask. More...
#define | XADCPS_INTX_ALM2_MASK 0x00000004
| Alarm 2 Mask. More...
#define | XADCPS_INTX_ALM1_MASK 0x00000002
| Alarm 1 Mask. More...
#define | XADCPS_INTX_ALM0_MASK 0x00000001
| Alarm 0 Mask. More...

## XADC Miscellaneous Register Bit definitions
#define | XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000
| Command FIFO Level mask. More...
#define | XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000
| Data FIFO Level Mask. More...
#define | XADCPS_MSTS_CFIFOF_MASK 0x00000800
| Command FIFO Full Mask. More...
#define | XADCPS_MSTS_CFIFOE_MASK 0x00000400
| Command FIFO Empty Mask. More...
#define | XADCPS_MSTS_DFIFOF_MASK 0x00000200
| Data FIFO Full Mask. More...
#define | XADCPS_MSTS_DFIFOE_MASK 0x00000100
| Data FIFO Empty Mask. More...
#define | XADCPS_MSTS_OT_MASK 0x00000080
| Over Temperature Mask. More...
#define | XADCPS_MSTS_ALM_MASK 0x0000007F
| Alarms Mask. More...

## XADC Miscellaneous Control Register Bit definitions
#define | XADCPS_MCTL_RESET_MASK 0x00000010
| Reset XADC. More...
#define | XADCPS_MCTL_FLUSH_MASK 0x00000001
| Flush the FIFOs. More...

## Internal Register offsets of the XADC
The following constants provide access to each of the internal registers of the XADC device.
#define | XADCPS_TEMP_OFFSET 0x00
| On-chip Temperature Reg. More...
#define | XADCPS_VCCINT_OFFSET 0x01
| On-chip VCCINT Data Reg. More...
#define | XADCPS_VCCAUX_OFFSET 0x02
| On-chip VCCAUX Data Reg. More...
#define | XADCPS_VPVN_OFFSET 0x03
| ADC out of VP/VN. More...
#define | XADCPS_VREFP_OFFSET 0x04
| On-chip VREFP Data Reg. More...
#define | XADCPS_VREFN_OFFSET 0x05
| On-chip VREFN Data Reg. More...
#define | XADCPS_VBRAM_OFFSET 0x06
| On-chip VBRAM , 7 Series. More...
#define | XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08
| ADC A Supply Offset Reg. More...
#define | XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09
| ADC A Offset Data Reg. More...
#define | XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A
| ADC A Gain Error Reg. More...
#define | XADCPS_VCCPINT_OFFSET 0x0D
| On-chip VCCPINT Reg, Zynq. More...
#define | XADCPS_VCCPAUX_OFFSET 0x0E
| On-chip VCCPAUX Reg, Zynq. More...
#define | XADCPS_VCCPDRO_OFFSET 0x0F
| On-chip VCCPDRO Reg, Zynq. More...
#define | XADCPS_AUX00_OFFSET 0x10
| ADC out of VAUXP0/VAUXN0. More...
#define | XADCPS_AUX01_OFFSET 0x11
| ADC out of VAUXP1/VAUXN1. More...
#define | XADCPS_AUX02_OFFSET 0x12
| ADC out of VAUXP2/VAUXN2. More...
#define | XADCPS_AUX03_OFFSET 0x13
| ADC out of VAUXP3/VAUXN3. More...
#define | XADCPS_AUX04_OFFSET 0x14
| ADC out of VAUXP4/VAUXN4. More...
#define | XADCPS_AUX05_OFFSET 0x15
| ADC out of VAUXP5/VAUXN5. More...
#define | XADCPS_AUX06_OFFSET 0x16
| ADC out of VAUXP6/VAUXN6. More...
#define | XADCPS_AUX07_OFFSET 0x17
| ADC out of VAUXP7/VAUXN7. More...
#define | XADCPS_AUX08_OFFSET 0x18
| ADC out of VAUXP8/VAUXN8. More...
#define | XADCPS_AUX09_OFFSET 0x19
| ADC out of VAUXP9/VAUXN9. More...
#define | XADCPS_AUX10_OFFSET 0x1A
| ADC out of VAUXP10/VAUXN10. More...
#define | XADCPS_AUX11_OFFSET 0x1B
| ADC out of VAUXP11/VAUXN11. More...
#define | XADCPS_AUX12_OFFSET 0x1C
| ADC out of VAUXP12/VAUXN12. More...
#define | XADCPS_AUX13_OFFSET 0x1D
| ADC out of VAUXP13/VAUXN13. More...
#define | XADCPS_AUX14_OFFSET 0x1E
| ADC out of VAUXP14/VAUXN14. More...
#define | XADCPS_AUX15_OFFSET 0x1F
| ADC out of VAUXP15/VAUXN15. More...
#define | XADCPS_MAX_TEMP_OFFSET 0x20
| Max Temperature Reg. More...
#define | XADCPS_MAX_VCCINT_OFFSET 0x21
| Max VCCINT Register. More...
#define | XADCPS_MAX_VCCAUX_OFFSET 0x22
| Max VCCAUX Register. More...
#define | XADCPS_MAX_VCCBRAM_OFFSET 0x23
| Max BRAM Register, 7 series. More...
#define | XADCPS_MIN_TEMP_OFFSET 0x24
| Min Temperature Reg. More...
#define | XADCPS_MIN_VCCINT_OFFSET 0x25
| Min VCCINT Register. More...
#define | XADCPS_MIN_VCCAUX_OFFSET 0x26
| Min VCCAUX Register. More...
#define | XADCPS_MIN_VCCBRAM_OFFSET 0x27
| Min BRAM Register, 7 series. More...
#define | XADCPS_MAX_VCCPINT_OFFSET 0x28
| Max VCCPINT Register, Zynq. More...
#define | XADCPS_MAX_VCCPAUX_OFFSET 0x29
| Max VCCPAUX Register, Zynq. More...
#define | XADCPS_MAX_VCCPDRO_OFFSET 0x2A
| Max VCCPDRO Register, Zynq. More...
#define | XADCPS_MIN_VCCPINT_OFFSET 0x2C
| Min VCCPINT Register, Zynq. More...
#define | XADCPS_MIN_VCCPAUX_OFFSET 0x2D
| Min VCCPAUX Register, Zynq. More...
#define | XADCPS_MIN_VCCPDRO_OFFSET 0x2E
| Min VCCPDRO Register,Zynq. More...
#define | XADCPS_FLAG_OFFSET 0x3F
| Flag Register. More...
#define | XADCPS_CFR0_OFFSET 0x40
| Configuration Register 0. More...
#define | XADCPS_CFR1_OFFSET 0x41
| Configuration Register 1. More...
#define | XADCPS_CFR2_OFFSET 0x42
| Configuration Register 2. More...
#define | XADCPS_SEQ00_OFFSET 0x48
| Seq Reg 00 Adc Channel Selection. More...
#define | XADCPS_SEQ01_OFFSET 0x49
| Seq Reg 01 Adc Channel Selection. More...
#define | XADCPS_SEQ02_OFFSET 0x4A
| Seq Reg 02 Adc Average Enable. More...
#define | XADCPS_SEQ03_OFFSET 0x4B
| Seq Reg 03 Adc Average Enable. More...
#define | XADCPS_SEQ04_OFFSET 0x4C
| Seq Reg 04 Adc Input Mode Select. More...
#define | XADCPS_SEQ05_OFFSET 0x4D
| Seq Reg 05 Adc Input Mode Select. More...
#define | XADCPS_SEQ06_OFFSET 0x4E
| Seq Reg 06 Adc Acquisition Select. More...
#define | XADCPS_SEQ07_OFFSET 0x4F
| Seq Reg 07 Adc Acquisition Select. More...
#define | XADCPS_ATR_TEMP_UPPER_OFFSET 0x50
| Temp Upper Alarm Register. More...
#define | XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51
| VCCINT Upper Alarm Reg. More...
#define | XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52
| VCCAUX Upper Alarm Reg. More...
#define | XADCPS_ATR_OT_UPPER_OFFSET 0x53
| Over Temp Upper Alarm Reg. More...
#define | XADCPS_ATR_TEMP_LOWER_OFFSET 0x54
| Temp Lower Alarm Register. More...
#define | XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55
| VCCINT Lower Alarm Reg. More...
#define | XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56
| VCCAUX Lower Alarm Reg. More...
#define | XADCPS_ATR_OT_LOWER_OFFSET 0x57
| Over Temp Lower Alarm Reg. More...
#define | XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58
| VBRAM Upper Alarm, 7 series. More...
#define | XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59
| VCCPINT Upper Alarm, Zynq. More...
#define | XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A
| VCCPAUX Upper Alarm, Zynq. More...
#define | XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B
| VCCPDRO Upper Alarm, Zynq. More...
#define | XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C
| VRBAM Lower Alarm, 7 Series. More...
#define | XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D
| VCCPINT Lower Alarm, Zynq. More...
#define | XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E
| VCCPAUX Lower Alarm, Zynq. More...
#define | XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F
| VCCPDRO Lower Alarm, Zynq. More...

## Configuration Register 0 (CFR0) mask(s)
#define | XADCPS_CFR0_CAL_AVG_MASK 0x8000
| Averaging enable Mask. More...
#define | XADCPS_CFR0_AVG_VALID_MASK 0x3000
| Averaging bit Mask. More...
#define | XADCPS_CFR0_AVG1_MASK 0x0000
| No Averaging. More...
#define | XADCPS_CFR0_AVG16_MASK 0x1000
| Average 16 samples. More...
#define | XADCPS_CFR0_AVG64_MASK 0x2000
| Average 64 samples. More...
#define | XADCPS_CFR0_AVG256_MASK 0x3000
| Average 256 samples. More...
#define | XADCPS_CFR0_AVG_SHIFT 12
| Averaging bits shift. More...
#define | XADCPS_CFR0_MUX_MASK 0x0800
| External Mask Enable. More...
#define | XADCPS_CFR0_DU_MASK 0x0400
| Bipolar/Unipolar mode. More...
#define | XADCPS_CFR0_EC_MASK 0x0200
| Event driven/ Continuous mode selection. More...
#define | XADCPS_CFR0_ACQ_MASK 0x0100
| Add acquisition by 6 ADCCLK. More...
#define | XADCPS_CFR0_CHANNEL_MASK 0x001F
| Channel number bit Mask. More...

## Configuration Register 1 (CFR1) mask(s)
#define | XADCPS_CFR1_SEQ_VALID_MASK 0xF000
| Sequence bit Mask. More...
#define | XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000
| Default Safe Mode. More...
#define | XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000
| Onepass through Seq. More...
#define | XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000
| Continuous Cycling Seq. More...
#define | XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000
| Single channel - No Seq. More...
#define | XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000
| Simulataneous Sampling Mask. More...
#define | XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000
| Independent Mode. More...
#define | XADCPS_CFR1_SEQ_SHIFT 12
| Sequence bit shift. More...
#define | XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800
| Alm 6 - VCCPDRO, Zynq. More...
#define | XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400
| Alm 5 - VCCPAUX, Zynq. More...
#define | XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200
| Alm 4 - VCCPINT, Zynq. More...
#define | XADCPS_CFR1_ALM_VBRAM_MASK 0x0100
| Alm 3 - VBRAM, 7 series. More...
#define | XADCPS_CFR1_CAL_VALID_MASK 0x00F0
| Valid Calibration Mask. More...
#define | XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080
| Calibration 3 -Power Supply Gain/Offset Enable. More...
#define | XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040
| Calibration 2 -Power Supply Offset Enable. More...
#define | XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020
| Calibration 1 -ADC Gain Offset Enable. More...
#define | XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010
| Calibration 0 -ADC Offset Enable. More...
#define | XADCPS_CFR1_CAL_DISABLE_MASK 0x0000
| No Calibration. More...
#define | XADCPS_CFR1_ALM_ALL_MASK 0x0F0F
| Mask for all alarms. More...
#define | XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008
| Alarm 2 - VCCAUX Enable. More...
#define | XADCPS_CFR1_ALM_VCCINT_MASK 0x0004
| Alarm 1 - VCCINT Enable. More...
#define | XADCPS_CFR1_ALM_TEMP_MASK 0x0002
| Alarm 0 - Temperature. More...
#define | XADCPS_CFR1_OT_MASK 0x0001
| Over Temperature Enable. More...

## Configuration Register 2 (CFR2) mask(s)
#define | XADCPS_CFR2_CD_VALID_MASK 0xFF00
| Clock Divisor bit Mask. More...
#define | XADCPS_CFR2_CD_SHIFT 8
| Num of shift on division. More...
#define | XADCPS_CFR2_CD_MIN 8
| Minimum value of divisor. More...
#define | XADCPS_CFR2_CD_MIN 8
| Minimum value of divisor. More...
#define | XADCPS_CFR2_CD_MAX 255
| Maximum value of divisor. More...
#define | XADCPS_CFR2_PD_MASK 0x0030
| Power Down Mask. More...
#define | XADCPS_CFR2_PD_XADC_MASK 0x0030
| Power Down XADC Mask. More...
#define | XADCPS_CFR2_PD_ADC1_MASK 0x0020
| Power Down ADC1 Mask. More...
#define | XADCPS_CFR2_PD_SHIFT 4
| Power Down Shift. More...

## Sequence Register (SEQ) Bit Definitions
#define | XADCPS_SEQ_CH_CALIB 0x00000001
| ADC Calibration Channel. More...
#define | XADCPS_SEQ_CH_VCCPINT 0x00000020
| VCCPINT, Zynq Only. More...
#define | XADCPS_SEQ_CH_VCCPAUX 0x00000040
| VCCPAUX, Zynq Only. More...
#define | XADCPS_SEQ_CH_VCCPDRO 0x00000080
| VCCPDRO, Zynq Only. More...
#define | XADCPS_SEQ_CH_TEMP 0x00000100
| On Chip Temperature Channel. More...
#define | XADCPS_SEQ_CH_VCCINT 0x00000200
| VCCINT Channel. More...
#define | XADCPS_SEQ_CH_VCCAUX 0x00000400
| VCCAUX Channel. More...
#define | XADCPS_SEQ_CH_VPVN 0x00000800
| VP/VN analog inputs Channel. More...
#define | XADCPS_SEQ_CH_VREFP 0x00001000
| VREFP Channel. More...
#define | XADCPS_SEQ_CH_VREFN 0x00002000
| VREFN Channel. More...
#define | XADCPS_SEQ_CH_VBRAM 0x00004000
| VBRAM Channel, 7 series. More...
#define | XADCPS_SEQ_CH_AUX00 0x00010000
| 1st Aux Channel More...
#define | XADCPS_SEQ_CH_AUX01 0x00020000
| 2nd Aux Channel More...
#define | XADCPS_SEQ_CH_AUX02 0x00040000
| 3rd Aux Channel More...
#define | XADCPS_SEQ_CH_AUX03 0x00080000
| 4th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX04 0x00100000
| 5th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX05 0x00200000
| 6th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX06 0x00400000
| 7th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX07 0x00800000
| 8th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX08 0x01000000
| 9th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX09 0x02000000
| 10th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX10 0x04000000
| 11th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX11 0x08000000
| 12th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX12 0x10000000
| 13th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX13 0x20000000
| 14th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX14 0x40000000
| 15th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX15 0x80000000
| 16th Aux Channel More...
#define | XADCPS_SEQ00_CH_VALID_MASK 0x7FE1
| Mask for the valid channels. More...
#define | XADCPS_SEQ01_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XADCPS_SEQ02_CH_VALID_MASK 0x7FE0
| Mask for the valid channels. More...
#define | XADCPS_SEQ03_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XADCPS_SEQ04_CH_VALID_MASK 0x0800
| Mask for the valid channels. More...
#define | XADCPS_SEQ05_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XADCPS_SEQ06_CH_VALID_MASK 0x0800
| Mask for the valid channels. More...
#define | XADCPS_SEQ07_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XADCPS_SEQ_CH_AUX_SHIFT 16
| Shift for the Aux Channel. More...

## OT Upper Alarm Threshold Register Bit Definitions
#define | XADCPS_ATR_OT_UPPER_ENB_MASK 0x000F
| Mask for OT enable. More...
#define | XADCPS_ATR_OT_UPPER_VAL_MASK 0xFFF0
| Mask for OT value. More...
#define | XADCPS_ATR_OT_UPPER_VAL_SHIFT 4
| Shift for OT value. More...
#define | XADCPS_ATR_OT_UPPER_ENB_VAL 0x0003
| Value for OT enable. More...
#define | XADCPS_ATR_OT_UPPER_VAL_MAX 0x0FFF
| Max OT value. More...

## JTAG DRP Bit Definitions
#define | XADCPS_JTAG_DATA_MASK 0x0000FFFF
| Mask for the Data. More...
#define | XADCPS_JTAG_ADDR_MASK 0x03FF0000
| Mask for the Addr. More...
#define | XADCPS_JTAG_ADDR_SHIFT 16
| Shift for the Addr. More...
#define | XADCPS_JTAG_CMD_MASK 0x3C000000
| Mask for the Cmd. More...
#define | XADCPS_JTAG_CMD_WRITE_MASK 0x08000000
| Mask for CMD Write. More...
#define | XADCPS_JTAG_CMD_READ_MASK 0x04000000
| Mask for CMD Read. More...
#define | XADCPS_JTAG_CMD_SHIFT 26
| Shift for the Cmd. More...

## Unlock Register Definitions
#define | XADCPS_UNLK_OFFSET 0x034
| Unlock Register. More...
#define | XADCPS_UNLK_VALUE 0x757BDF0D
| Unlock Value. More...

## Macro Definition Documentation

#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A

ADC A Gain Error Reg.

#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09

ADC A Offset Data Reg.

#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08

ADC A Supply Offset Reg.

Referenced by XAdcPs_GetCalibCoefficient().

#define XADCPS_ATR_OT_LOWER 7

Lower Over Temperature limit.

#define XADCPS_ATR_OT_LOWER_OFFSET 0x57

Over Temp Lower Alarm Reg.

#define XADCPS_ATR_OT_UPPER 3

VCCAUX high voltage limit register.

#define XADCPS_ATR_OT_UPPER_ENB_MASK 0x000F

Mask for OT enable.

Referenced by XAdcPs_DisableUserOverTemp(), and XAdcPs_EnableUserOverTemp().

#define XADCPS_ATR_OT_UPPER_ENB_VAL 0x0003

Value for OT enable.

Referenced by XAdcPs_EnableUserOverTemp().

#define XADCPS_ATR_OT_UPPER_OFFSET 0x53

Over Temp Upper Alarm Reg.

Referenced by XAdcPs_DisableUserOverTemp(), and XAdcPs_EnableUserOverTemp().

#define XADCPS_ATR_OT_UPPER_VAL_MASK 0xFFF0

Mask for OT value.

#define XADCPS_ATR_OT_UPPER_VAL_MAX 0x0FFF

Max OT value.

#define XADCPS_ATR_OT_UPPER_VAL_SHIFT 4

Shift for OT value.

#define XADCPS_ATR_TEMP_LOWER 4

Upper Over Temperature limit Reg.

Referenced by XAdcIntrExample().

#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54

Temp Lower Alarm Register.

#define XADCPS_ATR_TEMP_UPPER 0

High user Temperature.

Referenced by XAdcIntrExample().

#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50

Temp Upper Alarm Register.

Referenced by XAdcPs_GetAlarmThreshold(), and XAdcPs_SetAlarmThreshold().

#define XADCPS_ATR_VBRAM_LOWER 0xC

VRBAM Lower Alarm Reg, 7 Series.

#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C

VRBAM Lower Alarm, 7 Series.

#define XADCPS_ATR_VBRAM_UPPER_ 8

VRBAM Upper Alarm Reg, 7 Series.

#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58

VBRAM Upper Alarm, 7 series.

#define XADCPS_ATR_VCCAUX_LOWER 6

VCCAUX low voltage limit register.

#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56

VCCAUX Lower Alarm Reg.

#define XADCPS_ATR_VCCAUX_UPPER 2

VCCAUX high voltage limit register.

#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52

VCCAUX Upper Alarm Reg.

#define XADCPS_ATR_VCCINT_LOWER 5

VCCINT high voltage limit register.

#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55

VCCINT Lower Alarm Reg.

#define XADCPS_ATR_VCCINT_UPPER 1

VCCINT high voltage limit register.

Referenced by XAdcPs_SelfTest().

#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51

VCCINT Upper Alarm Reg.

#define XADCPS_ATR_VCCPAUX_LOWER 0xE

VCCPAUX Lower Alarm Reg , Zynq.

Referenced by XAdcIntrExample().

#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E

VCCPAUX Lower Alarm, Zynq.

#define XADCPS_ATR_VCCPAUX_UPPER 0xA

VCCPAUX Upper Alarm Reg, Zynq.

Referenced by XAdcIntrExample().

#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A

VCCPAUX Upper Alarm, Zynq.

#define XADCPS_ATR_VCCPDRO_LOWER 0xF

VCCPDRO Lower Alarm Reg , Zynq.

Referenced by XAdcPs_GetAlarmThreshold(), and XAdcPs_SetAlarmThreshold().

#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F

VCCPDRO Lower Alarm, Zynq.

#define XADCPS_ATR_VCCPDRO_UPPER 0xB

VCCPDRO Upper Alarm Reg, Zynq.

#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B

VCCPDRO Upper Alarm, Zynq.

#define XADCPS_ATR_VCCPINT_LOWER 0xD

VCCPINT Lower Alarm Reg , Zynq.

#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D

VCCPINT Lower Alarm, Zynq.

#define XADCPS_ATR_VCCPINT_UPPER 9

VCCPINT Upper Alarm Reg, Zynq.

#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59

VCCPINT Upper Alarm, Zynq.

#define XADCPS_AUX00_OFFSET 0x10

ADC out of VAUXP0/VAUXN0.

#define XADCPS_AUX01_OFFSET 0x11

ADC out of VAUXP1/VAUXN1.

#define XADCPS_AUX02_OFFSET 0x12

ADC out of VAUXP2/VAUXN2.

#define XADCPS_AUX03_OFFSET 0x13

ADC out of VAUXP3/VAUXN3.

#define XADCPS_AUX04_OFFSET 0x14

ADC out of VAUXP4/VAUXN4.

#define XADCPS_AUX05_OFFSET 0x15

ADC out of VAUXP5/VAUXN5.

#define XADCPS_AUX06_OFFSET 0x16

ADC out of VAUXP6/VAUXN6.

#define XADCPS_AUX07_OFFSET 0x17

ADC out of VAUXP7/VAUXN7.

#define XADCPS_AUX08_OFFSET 0x18

ADC out of VAUXP8/VAUXN8.

#define XADCPS_AUX09_OFFSET 0x19

ADC out of VAUXP9/VAUXN9.

#define XADCPS_AUX10_OFFSET 0x1A

ADC out of VAUXP10/VAUXN10.

#define XADCPS_AUX11_OFFSET 0x1B

ADC out of VAUXP11/VAUXN11.

#define XADCPS_AUX12_OFFSET 0x1C

ADC out of VAUXP12/VAUXN12.

#define XADCPS_AUX13_OFFSET 0x1D

ADC out of VAUXP13/VAUXN13.

#define XADCPS_AUX14_OFFSET 0x1E

ADC out of VAUXP14/VAUXN14.

#define XADCPS_AUX15_OFFSET 0x1F

ADC out of VAUXP15/VAUXN15.

#define XADCPS_AVG_0_SAMPLES 0

No Averaging.

#define XADCPS_AVG_16_SAMPLES 1

Average 16 samples.

#define XADCPS_AVG_256_SAMPLES 3

Average 256 samples.

Referenced by XAdcPs_SetAvg().

#define XADCPS_AVG_64_SAMPLES 2

Average 64 samples.

#define XADCPS_CALIB_ADC_COEFF 1

ADC Offset Calib Coefficient.

#define XADCPS_CALIB_GAIN_ERROR_COEFF 2

Gain Error Calib Coefficient.

Referenced by XAdcPs_GetCalibCoefficient().

#define XADCPS_CALIB_SUPPLY_COEFF 0

Supply Offset Calib Coefficient.

#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000

Command FIFO Threshold mask.

Referenced by XAdcPs_CfgInitialize().

#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000

Data FIFO Threshold mask.

Referenced by XAdcPs_CfgInitialize().

#define XADCPS_CFG_ENABLE_MASK 0x80000000

Enable access from PS mask.

Referenced by XAdcPs_CfgInitialize().

#define XADCPS_CFG_IGAP_MASK 0x0000001F

Idle Gap between successive commands.

#define XADCPS_CFG_OFFSET 0x00

Configuration Register.

Referenced by XAdcPs_CfgInitialize(), XAdcPs_GetConfigRegister(), and XAdcPs_SetConfigRegister().

#define XADCPS_CFG_REDGE_MASK 0x00001000

Read Edge Mask.

#define XADCPS_CFG_TCKRATE_MASK 0x00000300

Clock freq control.

#define XADCPS_CFG_WEDGE_MASK 0x00002000

Write Edge Mask.

#define XADCPS_CFR0_ACQ_MASK 0x0100

Add acquisition by 6 ADCCLK.

Referenced by XAdcPs_SetSingleChParams().

#define XADCPS_CFR0_AVG16_MASK 0x1000

Average 16 samples.

#define XADCPS_CFR0_AVG1_MASK 0x0000

No Averaging.

#define XADCPS_CFR0_AVG256_MASK 0x3000

Average 256 samples.

#define XADCPS_CFR0_AVG64_MASK 0x2000

Average 64 samples.

#define XADCPS_CFR0_AVG_SHIFT 12

Averaging bits shift.

Referenced by XAdcPs_GetAvg(), and XAdcPs_SetAvg().

#define XADCPS_CFR0_AVG_VALID_MASK 0x3000

Averaging bit Mask.

Referenced by XAdcPs_GetAvg(), XAdcPs_SetAvg(), and XAdcPs_SetSingleChParams().

#define XADCPS_CFR0_CAL_AVG_MASK 0x8000

Averaging enable Mask.

#define XADCPS_CFR0_CHANNEL_MASK 0x001F

Channel number bit Mask.

Referenced by XAdcPs_SetMuxMode(), and XAdcPs_SetSingleChParams().

#define XADCPS_CFR0_DU_MASK 0x0400

Bipolar/Unipolar mode.

Referenced by XAdcPs_SetSingleChParams().

#define XADCPS_CFR0_EC_MASK 0x0200

Event driven/ Continuous mode selection.

Referenced by XAdcPs_GetSamplingMode(), XAdcPs_SetSequencerEvent(), and XAdcPs_SetSingleChParams().

#define XADCPS_CFR0_MUX_MASK 0x0800

External Mask Enable.

Referenced by XAdcPs_SetMuxMode().

#define XADCPS_CFR0_OFFSET 0x40

Configuration Register 0.

Referenced by XAdcPs_GetAvg(), XAdcPs_GetSamplingMode(), XAdcPs_SetAvg(), XAdcPs_SetMuxMode(), XAdcPs_SetSequencerEvent(), and XAdcPs_SetSingleChParams().

#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F

Mask for all alarms.

Referenced by XAdcPs_GetAlarmEnables(), and XAdcPs_SetAlarmEnables().

#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002

Alarm 0 - Temperature.

Referenced by XAdcIntrExample().

#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100

Alm 3 - VBRAM, 7 series.

#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008

Alarm 2 - VCCAUX Enable.

#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004

Alarm 1 - VCCINT Enable.

#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400

Alm 5 - VCCPAUX, Zynq.

Referenced by XAdcIntrExample().

#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800

Alm 6 - VCCPDRO, Zynq.

#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200

Alm 4 - VCCPINT, Zynq.

#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020

Calibration 1 -ADC Gain Offset Enable.

#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010

Calibration 0 -ADC Offset Enable.

Referenced by XAdcPs_SetCalibEnables().

#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000

No Calibration.

Referenced by XAdcPs_SetCalibEnables().

#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080

Calibration 3 -Power Supply Gain/Offset Enable.

#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040

Calibration 2 -Power Supply Offset Enable.

#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0

Valid Calibration Mask.

Referenced by XAdcPs_GetCalibEnables(), and XAdcPs_SetCalibEnables().

#define XADCPS_CFR1_OFFSET 0x41

Configuration Register 1.

Referenced by XAdcPs_GetAlarmEnables(), XAdcPs_GetCalibEnables(), XAdcPs_GetSequencerMode(), XAdcPs_SetAlarmEnables(), XAdcPs_SetCalibEnables(), and XAdcPs_SetSequencerMode().

#define XADCPS_CFR1_OT_MASK 0x0001

Over Temperature Enable.

#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000

Continuous Cycling Seq.

#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000

Independent Mode.

#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000

Onepass through Seq.

#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000

Default Safe Mode.

#define XADCPS_CFR1_SEQ_SHIFT 12

Sequence bit shift.

Referenced by XAdcPs_GetSequencerMode(), and XAdcPs_SetSequencerMode().

#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000

Simulataneous Sampling Mask.

#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000

Single channel - No Seq.

#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000

Sequence bit Mask.

Referenced by XAdcPs_GetSequencerMode(), and XAdcPs_SetSequencerMode().

#define XADCPS_CFR2_CD_MAX 255

Maximum value of divisor.

#define XADCPS_CFR2_CD_MIN 8

Minimum value of divisor.

#define XADCPS_CFR2_CD_MIN 8

Minimum value of divisor.

#define XADCPS_CFR2_CD_SHIFT 8

Num of shift on division.

Referenced by XAdcPs_GetAdcClkDivisor(), and XAdcPs_SetAdcClkDivisor().

#define XADCPS_CFR2_CD_VALID_MASK 0xFF00

Clock Divisor bit Mask.

#define XADCPS_CFR2_OFFSET 0x42

Configuration Register 2.

Referenced by XAdcPs_GetAdcClkDivisor(), XAdcPs_GetPowerdownMode(), XAdcPs_SetAdcClkDivisor(), and XAdcPs_SetPowerdownMode().

#define XADCPS_CFR2_PD_ADC1_MASK 0x0020

Power Down ADC1 Mask.

#define XADCPS_CFR2_PD_MASK 0x0030

Power Down Mask.

Referenced by XAdcPs_GetPowerdownMode(), and XAdcPs_SetPowerdownMode().

#define XADCPS_CFR2_PD_SHIFT 4

Power Down Shift.

Referenced by XAdcPs_GetPowerdownMode(), and XAdcPs_SetPowerdownMode().

#define XADCPS_CFR2_PD_XADC_MASK 0x0030

Power Down XADC Mask.

#define XADCPS_CH_ADC_CALIB 0x08

ADC Offset Channel Reg.

Referenced by XAdcPs_SetSingleChParams().

#define XADCPS_CH_AUX_MAX 31

Channel number for Last Aux channel.

Referenced by XAdcPs_GetAdcData(), and XAdcPs_SetSingleChParams().

#define XADCPS_CH_AUX_MIN 16

Channel number for 1st Aux Channel.

Referenced by XAdcPs_SetSingleChParams().

#define XADCPS_CH_GAINERR_CALIB 0x09

Gain Error Channel Reg.

#define XADCPS_CH_SUPPLY_CALIB 0x07

Supply Calib Data Reg.

#define XADCPS_CH_TEMP 0x0

On Chip Temperature.

Referenced by XAdcIntrExample().

#define XADCPS_CH_VBRAM 0x6

On-chip VBRAM Data Reg, 7 series.

Referenced by XAdcPs_GetAdcData(), and XAdcPs_SetSingleChParams().

#define XADCPS_CH_VCCAUX 0x2

VCCAUX.

#define XADCPS_CH_VCCINT 0x1

VCCINT.

#define XADCPS_CH_VCCPAUX 0x0E

On-chip PS VCCPAUX Channel , Zynq.

Referenced by XAdcIntrExample().

#define XADCPS_CH_VCCPDRO 0x0F

On-chip PS VCCPDRO Channel , Zynq.

#define XADCPS_CH_VCCPINT 0x0D

On-chip PS VCCPINT Channel , Zynq.

Referenced by XAdcPs_GetAdcData(), and XAdcPs_SetSingleChParams().

#define XADCPS_CH_VPVN 0x3

VP/VN Dedicated analog inputs.

Referenced by XAdcPs_SetSingleChParams().

#define XADCPS_CH_VREFN 0x5

VREFN.

#define XADCPS_CH_VREFP 0x4

VREFP.

#define XADCPS_CMDFIFO_OFFSET 0x10

Command FIFO Register.

#define XADCPS_FLAG_OFFSET 0x3F

Flag Register.

#define XAdcPs_FormatWriteData | ( |  | RegOffset,
|  |  | Data,
|  |  | ReadWrite
| ) |  |

Value:
((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \
((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | \
(Data & XADCPS_JTAG_DATA_MASK))
XADCPS_JTAG_ADDR_MASK
#define XADCPS_JTAG_ADDR_MASK
Mask for the Addr.
Definition: xadcps_hw.h:411
XADCPS_JTAG_DATA_MASK
#define XADCPS_JTAG_DATA_MASK
Mask for the Data.
Definition: xadcps_hw.h:410
XADCPS_JTAG_ADDR_SHIFT
#define XADCPS_JTAG_ADDR_SHIFT
Shift for the Addr.
Definition: xadcps_hw.h:412
XADCPS_JTAG_CMD_WRITE_MASK
#define XADCPS_JTAG_CMD_WRITE_MASK
Mask for CMD Write.
Definition: xadcps_hw.h:414
XADCPS_JTAG_CMD_READ_MASK
#define XADCPS_JTAG_CMD_READ_MASK
Mask for CMD Read.
Definition: xadcps_hw.h:415

Formats the data to be written to the the XADC registers.

Parameters

  RegOffset | is the offset of the Register
  Data | is the data to be written to the Register if it is a write.
  ReadWrite | specifies whether it is a Read or a Write. Use 0 for Read, 1 for Write.

Returns
  None.

Note
  C-style Signature: void XAdcPs_FormatWriteData(u32 RegOffset, u16 Data, int ReadWrite)

Referenced by XAdcPs_ReadInternalReg(), and XAdcPs_WriteInternalReg().

#define XADCPS_INT_MASK_OFFSET 0x08

Interrupt Mask Register.

Referenced by XAdcPs_IntrDisable(), XAdcPs_IntrEnable(), and XAdcPs_IntrGetEnabled().

#define XADCPS_INT_STS_OFFSET 0x04

Interrupt Status Register.

Referenced by XAdcPs_IntrClear(), and XAdcPs_IntrGetStatus().

#define XADCPS_INTX_ALL_MASK 0x000003FF

Alarm Signals Mask.

Referenced by XAdcPs_IntrClear(), XAdcPs_IntrDisable(), XAdcPs_IntrEnable(), XAdcPs_IntrGetEnabled(), and XAdcPs_IntrGetStatus().

#define XADCPS_INTX_ALM0_MASK 0x00000001

Alarm 0 Mask.

Referenced by XAdcIntrExample().

#define XADCPS_INTX_ALM1_MASK 0x00000002

Alarm 1 Mask.

#define XADCPS_INTX_ALM2_MASK 0x00000004

Alarm 2 Mask.

#define XADCPS_INTX_ALM3_MASK 0x00000008

Alarm 3 Mask.

#define XADCPS_INTX_ALM4_MASK 0x00000010

Alarm 4 Mask.

#define XADCPS_INTX_ALM5_MASK 0x00000020

Alarm 5 Mask.

Referenced by XAdcIntrExample().

#define XADCPS_INTX_ALM6_MASK 0x00000040

Alarm 6 Mask.

#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F

Alarm Signals Mask.

#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200

CMD FIFO less than threshold.

#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100

Data FIFO greater than threshold.

#define XADCPS_INTX_OT_MASK 0x00000080

Over temperature Alarm Status.

#define XAdcPs_IsEventSamplingModeSet | ( |  | InstancePtr | ) |

Value:
(((XAdcPs_ReadInternalReg(InstancePtr, \
XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
TRUE : FALSE))
XADCPS_CFR0_OFFSET
#define XADCPS_CFR0_OFFSET
Configuration Register 0.
Definition: xadcps_hw.h:220
XAdcPs_ReadInternalReg
u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset)
This function is used for reading from the XADC Registers using the Data FIFO.
Definition: xadcps.c:1806
XADCPS_CFR0_EC_MASK
#define XADCPS_CFR0_EC_MASK
Event driven/ Continuous mode selection.
Definition: xadcps_hw.h:277

This macro checks if the XADC device is in Event Sampling mode.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  - TRUE if the device is in Event Sampling Mode.
  - FALSE if the device is in Continuous Sampling Mode.

Note
  C-Style signature: int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);

#define XAdcPs_IsExternalMuxModeSet | ( |  | InstancePtr | ) |

Value:
(((XAdcPs_ReadInternalReg(InstancePtr, \
XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
TRUE : FALSE))
XADCPS_CFR0_MUX_MASK
#define XADCPS_CFR0_MUX_MASK
External Mask Enable.
Definition: xadcps_hw.h:275
XADCPS_CFR0_OFFSET
#define XADCPS_CFR0_OFFSET
Configuration Register 0.
Definition: xadcps_hw.h:220
XAdcPs_ReadInternalReg
u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset)
This function is used for reading from the XADC Registers using the Data FIFO.
Definition: xadcps.c:1806

This macro checks if the XADC device is in External Mux mode.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  - TRUE if the device is in External Mux Mode.
  - FALSE if the device is NOT in External Mux Mode.

Note
  C-Style signature: int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);

#define XADCPS_JTAG_ADDR_MASK 0x03FF0000

Mask for the Addr.

#define XADCPS_JTAG_ADDR_SHIFT 16

Shift for the Addr.

#define XADCPS_JTAG_CMD_MASK 0x3C000000

Mask for the Cmd.

#define XADCPS_JTAG_CMD_READ_MASK 0x04000000

Mask for CMD Read.

#define XADCPS_JTAG_CMD_SHIFT 26

Shift for the Cmd.

#define XADCPS_JTAG_CMD_WRITE_MASK 0x08000000

Mask for CMD Write.

#define XADCPS_JTAG_DATA_MASK 0x0000FFFF

Mask for the Data.

#define XADCPS_MAX_TEMP 0

Maximum Temperature Data.

#define XADCPS_MAX_TEMP_OFFSET 0x20

Max Temperature Reg.

Referenced by XAdcPs_GetMinMaxMeasurement().

#define XADCPS_MAX_VBRAM 3

Maximum VBRAM Data.

#define XADCPS_MAX_VCCAUX 2

Maximum VCCAUX Data.

#define XADCPS_MAX_VCCAUX_OFFSET 0x22

Max VCCAUX Register.

#define XADCPS_MAX_VCCBRAM_OFFSET 0x23

Max BRAM Register, 7 series.

#define XADCPS_MAX_VCCINT 1

Maximum VCCINT Data.

#define XADCPS_MAX_VCCINT_OFFSET 0x21

Max VCCINT Register.

#define XADCPS_MAX_VCCPAUX 9

Maximum VCCPAUX Register , Zynq.

#define XADCPS_MAX_VCCPAUX_OFFSET 0x29

Max VCCPAUX Register, Zynq.

#define XADCPS_MAX_VCCPDRO 0xA

Maximum VCCPDRO Register , Zynq.

Referenced by XAdcPs_GetMinMaxMeasurement().

#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A

Max VCCPDRO Register, Zynq.

#define XADCPS_MAX_VCCPINT 8

Maximum VCCPINT Register , Zynq.

#define XADCPS_MAX_VCCPINT_OFFSET 0x28

Max VCCPINT Register, Zynq.

#define XADCPS_MCTL_FLUSH_MASK 0x00000001

Flush the FIFOs.

#define XADCPS_MCTL_OFFSET 0x18

Misc control register.

Referenced by XAdcPs_CfgInitialize(), XAdcPs_GetMiscCtrlRegister(), XAdcPs_Reset(), and XAdcPs_SetMiscCtrlRegister().

#define XADCPS_MCTL_RESET_MASK 0x00000010

Reset XADC.

#define XADCPS_MIN_TEMP 4

Minimum Temperature Data.

#define XADCPS_MIN_TEMP_OFFSET 0x24

Min Temperature Reg.

#define XADCPS_MIN_VBRAM 7

Minimum VBRAM Data.

#define XADCPS_MIN_VCCAUX 6

Minimum VCCAUX Data.

#define XADCPS_MIN_VCCAUX_OFFSET 0x26

Min VCCAUX Register.

#define XADCPS_MIN_VCCBRAM_OFFSET 0x27

Min BRAM Register, 7 series.

#define XADCPS_MIN_VCCINT 5

Minimum VCCINT Data.

#define XADCPS_MIN_VCCINT_OFFSET 0x25

Min VCCINT Register.

#define XADCPS_MIN_VCCPAUX 0xD

Minimum VCCPAUX Register , Zynq.

#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D

Min VCCPAUX Register, Zynq.

#define XADCPS_MIN_VCCPDRO 0xE

Minimum VCCPDRO Register , Zynq.

Referenced by XAdcPs_GetMinMaxMeasurement().

#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E

Min VCCPDRO Register,Zynq.

#define XADCPS_MIN_VCCPINT 0xC

Minimum VCCPINT Register , Zynq.

Referenced by XAdcPs_GetMinMaxMeasurement().

#define XADCPS_MIN_VCCPINT_OFFSET 0x2C

Min VCCPINT Register, Zynq.

#define XADCPS_MSTS_ALM_MASK 0x0000007F

Alarms Mask.

#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000

Command FIFO Level mask.

#define XADCPS_MSTS_CFIFOE_MASK 0x00000400

Command FIFO Empty Mask.

#define XADCPS_MSTS_CFIFOF_MASK 0x00000800

Command FIFO Full Mask.

#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000

Data FIFO Level Mask.

#define XADCPS_MSTS_DFIFOE_MASK 0x00000100

Data FIFO Empty Mask.

#define XADCPS_MSTS_DFIFOF_MASK 0x00000200

Data FIFO Full Mask.

#define XADCPS_MSTS_OFFSET 0x0C

Misc status register.

Referenced by XAdcPs_GetMiscStatus().

#define XADCPS_MSTS_OT_MASK 0x00000080

Over Temperature Mask.

#define XADCPS_PD_MODE_ADCB 1

Power Down ADC B.

#define XADCPS_PD_MODE_NONE 0

No Power Down.

#define XADCPS_PD_MODE_XADC 2

Power Down ADC A and ADC B.

Referenced by XAdcPs_SetPowerdownMode().

#define XAdcPs_RawToTemperature | ( |  | AdcData | ) | ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)

This macro converts XADC Raw Data to Temperature(centigrades).

Parameters

  AdcData | is the Raw ADC Data from XADC.

Returns
  The Temperature in centigrades.

Note
  C-Style signature: float XAdcPs_RawToTemperature(u32 AdcData);

#define XAdcPs_RawToVoltage | ( |  | AdcData | ) | ((((float)(AdcData))* (3.0f))/65536.0f)

This macro converts XADC/ADC Raw Data to Voltage(volts).

Parameters

  AdcData | is the XADC/ADC Raw Data.

Returns
  The Voltage in volts.

Note
  C-Style signature: float XAdcPs_RawToVoltage(u32 AdcData);

#define XADCPS_RDFIFO_OFFSET 0x14

Read FIFO Register.

#define XAdcPs_ReadFifo | ( |  | InstancePtr | ) |

Value:
XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XADCPS_RDFIFO_OFFSET);
XADCPS_RDFIFO_OFFSET
#define XADCPS_RDFIFO_OFFSET
Read FIFO Register.
Definition: xadcps_hw.h:84
XAdcPs_ReadReg
#define XAdcPs_ReadReg(BaseAddress, RegOffset)
Read a register of the XADC device.
Definition: xadcps_hw.h:448

This macro is used for reading from the XADC Registers using the data FIFO.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  Data read from the FIFO

Note
  C-Style signature: u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);

Referenced by XAdcPs_ReadInternalReg(), and XAdcPs_WriteInternalReg().

#define XAdcPs_ReadReg | ( |  | BaseAddress,
|  |  | RegOffset
| ) |  | (Xil_In32((BaseAddress) + (RegOffset)))

Read a register of the XADC device.

This macro provides register access to all registers using the register offsets defined above.

Parameters

  BaseAddress | contains the base address of the device.
  RegOffset | is the offset of the register to read.

Returns
  The contents of the register.

Note
  C-style Signature: u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset);

Referenced by XAdcPs_CfgInitialize(), XAdcPs_GetConfigRegister(), XAdcPs_GetMiscCtrlRegister(), XAdcPs_GetMiscStatus(), XAdcPs_IntrClear(), XAdcPs_IntrDisable(), XAdcPs_IntrEnable(), XAdcPs_IntrGetEnabled(), and XAdcPs_IntrGetStatus().

#define XADCPS_SEQ00_CH_VALID_MASK 0x7FE1

Mask for the valid channels.

Referenced by XAdcPs_GetSeqChEnables(), and XAdcPs_SetSeqChEnables().

#define XADCPS_SEQ00_OFFSET 0x48

Seq Reg 00 Adc Channel Selection.

Referenced by XAdcPs_GetSeqChEnables(), and XAdcPs_SetSeqChEnables().

#define XADCPS_SEQ01_CH_VALID_MASK 0xFFFF

Mask for the valid channels.

Referenced by XAdcPs_GetSeqChEnables(), and XAdcPs_SetSeqChEnables().

#define XADCPS_SEQ01_OFFSET 0x49

Seq Reg 01 Adc Channel Selection.

Referenced by XAdcPs_GetSeqChEnables(), and XAdcPs_SetSeqChEnables().

#define XADCPS_SEQ02_CH_VALID_MASK 0x7FE0

Mask for the valid channels.

Referenced by XAdcPs_GetSeqAvgEnables(), and XAdcPs_SetSeqAvgEnables().

#define XADCPS_SEQ02_OFFSET 0x4A

Seq Reg 02 Adc Average Enable.

Referenced by XAdcPs_GetSeqAvgEnables(), and XAdcPs_SetSeqAvgEnables().

#define XADCPS_SEQ03_CH_VALID_MASK 0xFFFF

Mask for the valid channels.

Referenced by XAdcPs_GetSeqAvgEnables(), and XAdcPs_SetSeqAvgEnables().

#define XADCPS_SEQ03_OFFSET 0x4B

Seq Reg 03 Adc Average Enable.

Referenced by XAdcPs_GetSeqAvgEnables(), and XAdcPs_SetSeqAvgEnables().

#define XADCPS_SEQ04_CH_VALID_MASK 0x0800

Mask for the valid channels.

Referenced by XAdcPs_GetSeqInputMode(), and XAdcPs_SetSeqInputMode().

#define XADCPS_SEQ04_OFFSET 0x4C

Seq Reg 04 Adc Input Mode Select.

Referenced by XAdcPs_GetSeqInputMode(), and XAdcPs_SetSeqInputMode().

#define XADCPS_SEQ05_CH_VALID_MASK 0xFFFF

Mask for the valid channels.

Referenced by XAdcPs_GetSeqInputMode(), and XAdcPs_SetSeqInputMode().

#define XADCPS_SEQ05_OFFSET 0x4D

Seq Reg 05 Adc Input Mode Select.

Referenced by XAdcPs_GetSeqInputMode(), and XAdcPs_SetSeqInputMode().

#define XADCPS_SEQ06_CH_VALID_MASK 0x0800

Mask for the valid channels.

Referenced by XAdcPs_GetSeqAcqTime(), and XAdcPs_SetSeqAcqTime().

#define XADCPS_SEQ06_OFFSET 0x4E

Seq Reg 06 Adc Acquisition Select.

Referenced by XAdcPs_GetSeqAcqTime(), and XAdcPs_SetSeqAcqTime().

#define XADCPS_SEQ07_CH_VALID_MASK 0xFFFF

Mask for the valid channels.

Referenced by XAdcPs_GetSeqAcqTime(), and XAdcPs_SetSeqAcqTime().

#define XADCPS_SEQ07_OFFSET 0x4F

Seq Reg 07 Adc Acquisition Select.

Referenced by XAdcPs_GetSeqAcqTime(), and XAdcPs_SetSeqAcqTime().

#define XADCPS_SEQ_CH_AUX00 0x00010000

1st Aux Channel

#define XADCPS_SEQ_CH_AUX01 0x00020000

2nd Aux Channel

#define XADCPS_SEQ_CH_AUX02 0x00040000

3rd Aux Channel

#define XADCPS_SEQ_CH_AUX03 0x00080000

4th Aux Channel

#define XADCPS_SEQ_CH_AUX04 0x00100000

5th Aux Channel

#define XADCPS_SEQ_CH_AUX05 0x00200000

6th Aux Channel

#define XADCPS_SEQ_CH_AUX06 0x00400000

7th Aux Channel

#define XADCPS_SEQ_CH_AUX07 0x00800000

8th Aux Channel

#define XADCPS_SEQ_CH_AUX08 0x01000000

9th Aux Channel

#define XADCPS_SEQ_CH_AUX09 0x02000000

10th Aux Channel

#define XADCPS_SEQ_CH_AUX10 0x04000000

11th Aux Channel

#define XADCPS_SEQ_CH_AUX11 0x08000000

12th Aux Channel

#define XADCPS_SEQ_CH_AUX12 0x10000000

13th Aux Channel

#define XADCPS_SEQ_CH_AUX13 0x20000000

14th Aux Channel

#define XADCPS_SEQ_CH_AUX14 0x40000000

15th Aux Channel

#define XADCPS_SEQ_CH_AUX15 0x80000000

16th Aux Channel

#define XADCPS_SEQ_CH_AUX_SHIFT 16

Shift for the Aux Channel.

Referenced by XAdcPs_GetSeqAcqTime(), XAdcPs_GetSeqAvgEnables(), XAdcPs_GetSeqChEnables(), XAdcPs_GetSeqInputMode(), XAdcPs_SetSeqAcqTime(), XAdcPs_SetSeqAvgEnables(), XAdcPs_SetSeqChEnables(), and XAdcPs_SetSeqInputMode().

#define XADCPS_SEQ_CH_CALIB 0x00000001

ADC Calibration Channel.

#define XADCPS_SEQ_CH_TEMP 0x00000100

On Chip Temperature Channel.

#define XADCPS_SEQ_CH_VBRAM 0x00004000

VBRAM Channel, 7 series.

#define XADCPS_SEQ_CH_VCCAUX 0x00000400

VCCAUX Channel.

#define XADCPS_SEQ_CH_VCCINT 0x00000200

VCCINT Channel.

#define XADCPS_SEQ_CH_VCCPAUX 0x00000040

VCCPAUX, Zynq Only.

#define XADCPS_SEQ_CH_VCCPDRO 0x00000080

VCCPDRO, Zynq Only.

#define XADCPS_SEQ_CH_VCCPINT 0x00000020

VCCPINT, Zynq Only.

#define XADCPS_SEQ_CH_VPVN 0x00000800

VP/VN analog inputs Channel.

#define XADCPS_SEQ_CH_VREFN 0x00002000

VREFN Channel.

#define XADCPS_SEQ_CH_VREFP 0x00001000

VREFP Channel.

#define XADCPS_SEQ_MODE_CONTINPASS 2

Continuous Cycling Sequencer.

#define XADCPS_SEQ_MODE_INDEPENDENT 8

Independent mode.

Referenced by XAdcIntrExample(), and XAdcPs_SetSequencerMode().

#define XADCPS_SEQ_MODE_ONEPASS 1

Onepass through Sequencer.

#define XADCPS_SEQ_MODE_SAFE 0

Default Safe Mode.

Referenced by XAdcIntrExample(), XAdcPs_SetSeqAcqTime(), XAdcPs_SetSeqAvgEnables(), XAdcPs_SetSeqChEnables(), and XAdcPs_SetSeqInputMode().

#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4

Simultaneous sampling.

Referenced by XAdcPs_SetSequencerMode().

#define XADCPS_SEQ_MODE_SINGCHAN 3

Single channel -No Sequencing.

Referenced by XAdcPs_SetSingleChParams().

#define XADCPS_TEMP_OFFSET 0x00

On-chip Temperature Reg.

Referenced by XAdcPs_GetAdcData().

#define XAdcPs_TemperatureToRaw | ( |  | Temperature | ) | ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))

This macro converts Temperature in centigrades to XADC/ADC Raw Data.

Parameters

  Temperature | is the Temperature in centigrades to be converted to XADC/ADC Raw Data.

Returns
  The XADC/ADC Raw Data.

Note
  C-Style signature: int XAdcPs_TemperatureToRaw(float Temperature);

#define XADCPS_UNLK_OFFSET 0x034

Unlock Register.

Referenced by XAdcPs_CfgInitialize().

#define XADCPS_UNLK_VALUE 0x757BDF0D

Unlock Value.

Referenced by XAdcPs_CfgInitialize().

#define XADCPS_VBRAM_OFFSET 0x06

On-chip VBRAM , 7 Series.

#define XADCPS_VCCAUX_OFFSET 0x02

On-chip VCCAUX Data Reg.

#define XADCPS_VCCINT_OFFSET 0x01

On-chip VCCINT Data Reg.

#define XADCPS_VCCPAUX_OFFSET 0x0E

On-chip VCCPAUX Reg, Zynq.

#define XADCPS_VCCPDRO_OFFSET 0x0F

On-chip VCCPDRO Reg, Zynq.

#define XADCPS_VCCPINT_OFFSET 0x0D

On-chip VCCPINT Reg, Zynq.

#define XAdcPs_VoltageToRaw | ( |  | Voltage | ) | ((int)((Voltage)*65536.0f/3.0f))

This macro converts Voltage in Volts to XADC/ADC Raw Data.

Parameters

  Voltage | is the Voltage in volts to be converted to XADC/ADC Raw Data.

Returns
  The XADC/ADC Raw Data.

Note
  C-Style signature: int XAdcPs_VoltageToRaw(float Voltage);

#define XADCPS_VPVN_OFFSET 0x03

ADC out of VP/VN.

#define XADCPS_VREFN_OFFSET 0x05

On-chip VREFN Data Reg.

#define XADCPS_VREFP_OFFSET 0x04

On-chip VREFP Data Reg.

#define XAdcPs_WriteFifo | ( |  | InstancePtr,
|  |  | Data
| ) |  |

Value:
XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XADCPS_CMDFIFO_OFFSET, Data);
XADCPS_CMDFIFO_OFFSET
#define XADCPS_CMDFIFO_OFFSET
Command FIFO Register.
Definition: xadcps_hw.h:83
XAdcPs_WriteReg
#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data)
Write a register of the XADC device.
Definition: xadcps_hw.h:468

This macro is used for writing to the XADC Registers using the command FIFO.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  Data | is the value to be written to XADC register.

Returns
  None.

Note
  C-Style signature: void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);

Referenced by XAdcPs_ReadInternalReg(), and XAdcPs_WriteInternalReg().

#define XAdcPs_WriteReg | ( |  | BaseAddress,
|  |  | RegOffset,
|  |  | Data
| ) |  | (Xil_Out32((BaseAddress) + (RegOffset), (Data)))

Write a register of the XADC device.

This macro provides register access to all registers using the register offsets defined above.

Parameters

  BaseAddress | contains the base address of the device.
  RegOffset | is the offset of the register to write.
  Data | is the value to write to the register.

Returns
  None.

Note
  C-style Signature: void XAdcPs_WriteReg(u32 BaseAddress, u32 RegOffset,u32 Data)

Referenced by XAdcPs_CfgInitialize(), XAdcPs_IntrClear(), XAdcPs_IntrDisable(), XAdcPs_IntrEnable(), XAdcPs_Reset(), XAdcPs_SetConfigRegister(), and XAdcPs_SetMiscCtrlRegister().

## Function Documentation

int XAdcPs_CfgInitialize | ( | XAdcPs * | InstancePtr,
|  | XAdcPs_Config * | ConfigPtr,
|  | u32 | EffectiveAddr
| ) |  |

This function initializes a specific XAdcPs device/instance.

Functions in xadcps.c.

This function must be called prior to using the XADC device.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  ConfigPtr | points to the XAdcPs device configuration structure.
  EffectiveAddr | is the device base address in the virtual memory address space. If the address translation is not used then the physical address is passed. Unexpected errors may occur if the address mapping is changed after this function is invoked.

Returns
  - XST_SUCCESS if successful.

Note
  The user needs to first call the XAdcPs_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XAdcPs_CfgInitialize() API.

References XAdcPs_Config::BaseAddress, XAdcPs::Config, XAdcPs_Config::DeviceId, XAdcPs::IsReady, XADCPS_CFG_CFIFOTH_MASK, XADCPS_CFG_DFIFOTH_MASK, XADCPS_CFG_ENABLE_MASK, XADCPS_CFG_OFFSET, XADCPS_MCTL_OFFSET, XAdcPs_ReadReg, XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE, and XAdcPs_WriteReg.

Referenced by XAdcIntrExample().

void XAdcPs_DisableUserOverTemp | ( | XAdcPs * | InstancePtr | ) |

This function disables programming of the powerdown temperature for the OverTemp signal in the OT Powerdown register.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  None.

Note
  None.

References XAdcPs::IsReady, XADCPS_ATR_OT_UPPER_ENB_MASK, XADCPS_ATR_OT_UPPER_OFFSET, XAdcPs_ReadInternalReg(), and XAdcPs_WriteInternalReg().

void XAdcPs_EnableUserOverTemp | ( | XAdcPs * | InstancePtr | ) |

This function enables programming of the powerdown temperature for the OverTemp signal in the OT Powerdown register.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  None.

Note
  None.

References XAdcPs::IsReady, XADCPS_ATR_OT_UPPER_ENB_MASK, XADCPS_ATR_OT_UPPER_ENB_VAL, XADCPS_ATR_OT_UPPER_OFFSET, XAdcPs_ReadInternalReg(), and XAdcPs_WriteInternalReg().

u8 XAdcPs_GetAdcClkDivisor | ( | XAdcPs * | InstancePtr | ) |

The function gets the ADCCLK divisor from the Configuration Register 2.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  The divisor read from the Configuration Register 2.

Note
  The ADCCLK is an internal clock used by the ADC and is synchronized to the DCLK clock. The ADCCLK is equal to DCLK divided by the user selection in the Configuration Register 2.

References XAdcPs::IsReady, XADCPS_CFR2_CD_SHIFT, XADCPS_CFR2_OFFSET, and XAdcPs_ReadInternalReg().

u16 XAdcPs_GetAdcData | ( | XAdcPs * | InstancePtr,
|  | u8 | Channel
| ) |  |

Get the ADC converted data for the specified channel.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  Channel | is the channel number. Use the XADCPS_CH_* defined in the file xadcps.h. The valid channels are 0 to 6 13 to 31

Returns
  A 16-bit value representing the ADC converted data for the specified channel. The XADC Monitor/ADC device guarantees a 10 bit resolution for the ADC converted data and data is the 10 MSB bits of the 16 data read from the device.

Note
  The channels 7,8,9 are used for calibration of the device and hence there is no associated data with this channel.

References XAdcPs::IsReady, XADCPS_CH_AUX_MAX, XADCPS_CH_VBRAM, XADCPS_CH_VCCPINT, XAdcPs_ReadInternalReg(), and XADCPS_TEMP_OFFSET.

Referenced by XAdcIntrExample().

u16 XAdcPs_GetAlarmEnables | ( | XAdcPs * | InstancePtr | ) |

This function gets the status of the alarm output enables in the Configuration Register 1.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  This is the bit-mask of the enabled alarm outputs in the Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and XADCPS_CFR1_OT_MASK defined in xadcps_hw.h to interpret the returned value. Bit positions of 1 indicate that the alarm output is enabled. Bit positions of 0 indicate that the alarm output is disabled.

Note
  The implementation of the alarm enables in the Configuration register 1 is such that alarms for the bit positions of 1 will be disabled and alarms for bit positions of 0 will be enabled. The enabled alarm outputs returned by this function is the negated value of the the data read from the Configuration Register 1.

References XAdcPs::IsReady, XADCPS_CFR1_ALM_ALL_MASK, XADCPS_CFR1_OFFSET, and XAdcPs_ReadInternalReg().

u16 XAdcPs_GetAlarmThreshold | ( | XAdcPs * | InstancePtr,
|  | u8 | AlarmThrReg
| ) |  |

This function returns the contents of the specified Alarm Threshold Register.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  AlarmThrReg | is the index of an Alarm Threshold Register to be read. Use XADCPS_ATR_* constants defined in xadcps_hw.h to specify the index.

Returns
  A 16-bit value representing the contents of the selected Alarm Threshold Register.

Note
  None.

References XAdcPs::IsReady, XADCPS_ATR_TEMP_UPPER_OFFSET, XADCPS_ATR_VCCPDRO_LOWER, and XAdcPs_ReadInternalReg().

Referenced by XAdcPs_SelfTest().

u8 XAdcPs_GetAvg | ( | XAdcPs * | InstancePtr | ) |

This function returns the number of samples of averaging configured for all the channels in the Configuration Register 0.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  The averaging read from the Configuration Register 0 is returned. Use the XADCPS_AVG_* bit definitions defined in xadcps.h file to interpret the returned value :
  - XADCPS_AVG_0_SAMPLES means no averaging
  - XADCPS_AVG_16_SAMPLES means 16 samples of averaging
  - XADCPS_AVG_64_SAMPLES means 64 samples of averaging
  - XADCPS_AVG_256_SAMPLES means 256 samples of averaging

Note
  None.

References XAdcPs::IsReady, XADCPS_CFR0_AVG_SHIFT, XADCPS_CFR0_AVG_VALID_MASK, XADCPS_CFR0_OFFSET, and XAdcPs_ReadInternalReg().

u16 XAdcPs_GetCalibCoefficient | ( | XAdcPs * | InstancePtr,
|  | u8 | CoeffType
| ) |  |

This function gets the calibration coefficient data for the specified parameter.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  CoeffType | specifies the calibration coefficient to be read. Use XADCPS_CALIB_* constants defined in xadcps.h to specify the calibration coefficient to be read.

Returns
  A 16-bit value representing the calibration coefficient. The XADC device guarantees a 10 bit resolution for the ADC converted data and data is the 10 MSB bits of the 16 data read from the device.

Note
  None.

References XAdcPs::IsReady, XADCPS_ADC_A_SUPPLY_CALIB_OFFSET, XADCPS_CALIB_GAIN_ERROR_COEFF, and XAdcPs_ReadInternalReg().

u16 XAdcPs_GetCalibEnables | ( | XAdcPs * | InstancePtr | ) |

This function reads the value of the calibration enables from the Configuration Register 1.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  The value of the calibration enables in the Configuration Register 1 :
  - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction
  - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset correction
  - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset correction
  - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor gain and offset correction
  - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration

Note
  None.

References XAdcPs::IsReady, XADCPS_CFR1_CAL_VALID_MASK, XADCPS_CFR1_OFFSET, and XAdcPs_ReadInternalReg().

u32 XAdcPs_GetConfigRegister | ( | XAdcPs * | InstancePtr | ) |

The functions reads the contents of the Config Register.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  A 32-bit value representing the contents of the Config Register. Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to interpret the returned value.

Note
  None.

References XAdcPs::IsReady, XADCPS_CFG_OFFSET, and XAdcPs_ReadReg.

u16 XAdcPs_GetMinMaxMeasurement | ( | XAdcPs * | InstancePtr,
|  | u8 | MeasurementType
| ) |  |

This function reads the Minimum/Maximum measurement for one of the specified parameters.

Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to specify the parameters (Temperature, VccInt, VccAux, VBram, VccPInt, VccPAux and VccPDro).

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  MeasurementType | specifies the parameter for which the Minimum/Maximum measurement has to be read. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to specify the data to be read.

Returns
  A 16-bit value representing the maximum/minimum measurement for specified parameter. The XADC device guarantees a 10 bit resolution for the ADC converted data and data is the 10 MSB bits of the 16 data read from the device.

Note
  None.

References XAdcPs::IsReady, XADCPS_MAX_TEMP_OFFSET, XADCPS_MAX_VCCPDRO, XADCPS_MIN_VCCPDRO, XADCPS_MIN_VCCPINT, and XAdcPs_ReadInternalReg().

u32 XAdcPs_GetMiscCtrlRegister | ( | XAdcPs * | InstancePtr | ) |

The functions reads the contents of the Miscellaneous control register.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  A 32-bit value representing the contents of the Config Register. Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to interpret the returned value.

Note
  None.

References XAdcPs::IsReady, XADCPS_MCTL_OFFSET, and XAdcPs_ReadReg.

u32 XAdcPs_GetMiscStatus | ( | XAdcPs * | InstancePtr | ) |

The functions reads the contents of the Miscellaneous Status Register.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  A 32-bit value representing the contents of the Miscellaneous Status Register. Use the XADCPS_MSTS_*_MASK constants defined in xadcps_hw.h to interpret the returned value.

Note
  None.

References XAdcPs::IsReady, XADCPS_MSTS_OFFSET, and XAdcPs_ReadReg.

u32 XAdcPs_GetPowerdownMode | ( | XAdcPs * | InstancePtr | ) |

This function gets the Power Down mode.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  Mode specifies the Power Down Mode
  - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and ADC B are enabled)
  - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
  - XADCPS_PD_MODE_XADC specifies the Power Down of both ADC A and ADC B.

Note
  None.

References XAdcPs::IsReady, XADCPS_CFR2_OFFSET, XADCPS_CFR2_PD_MASK, XADCPS_CFR2_PD_SHIFT, and XAdcPs_ReadInternalReg().

int XAdcPs_GetSamplingMode | ( | XAdcPs * | InstancePtr | ) |

This function returns the sampling mode.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  The sampling mode
  - 0 specifies continuous sampling
  - 1 specifies event driven sampling mode

Note
  None.

References XAdcPs::IsReady, XADCPS_CFR0_EC_MASK, XADCPS_CFR0_OFFSET, and XAdcPs_ReadInternalReg().

u32 XAdcPs_GetSeqAcqTime | ( | XAdcPs * | InstancePtr | ) |

This function gets the status of acquisition from the ADC Channel Acquisition Time Sequencer Registers.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  The acquisition time for all the channels. Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the Channel numbers. Bit masks of 1 are the channels for which acquisition cycles are extended and bit mask of 0 are the channels for which acquisition cycles are not extended.

Note
  None

References XAdcPs::IsReady, XAdcPs_ReadInternalReg(), XADCPS_SEQ06_CH_VALID_MASK, XADCPS_SEQ06_OFFSET, XADCPS_SEQ07_CH_VALID_MASK, XADCPS_SEQ07_OFFSET, and XADCPS_SEQ_CH_AUX_SHIFT.

u32 XAdcPs_GetSeqAvgEnables | ( | XAdcPs * | InstancePtr | ) |

This function returns the channels for which the averaging has been enabled in the ADC Channel Averaging Enables Sequencer Registers.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  The status of averaging (enabled/disabled) for all the channels. Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the Channel numbers. Bit masks of 1 are the channels for which averaging is enabled and bit mask of 0 are the channels for averaging is disabled

Note
  None

References XAdcPs::IsReady, XAdcPs_ReadInternalReg(), XADCPS_SEQ02_CH_VALID_MASK, XADCPS_SEQ02_OFFSET, XADCPS_SEQ03_CH_VALID_MASK, XADCPS_SEQ03_OFFSET, and XADCPS_SEQ_CH_AUX_SHIFT.

u32 XAdcPs_GetSeqChEnables | ( | XAdcPs * | InstancePtr | ) |

This function gets the channel enable bits status from the ADC Channel Selection Sequencer Registers.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the Channel numbers. Bit masks of 1 are the channels that are enabled and bit mask of 0 are the channels that are disabled.
  None

Note
  None

References XAdcPs::IsReady, XAdcPs_ReadInternalReg(), XADCPS_SEQ00_CH_VALID_MASK, XADCPS_SEQ00_OFFSET, XADCPS_SEQ01_CH_VALID_MASK, XADCPS_SEQ01_OFFSET, and XADCPS_SEQ_CH_AUX_SHIFT.

u32 XAdcPs_GetSeqInputMode | ( | XAdcPs * | InstancePtr | ) |

This function gets the Analog input mode for all the channels from the ADC Channel Analog-Input Mode Sequencer Registers.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  The input mode for all the channels. Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the Channel numbers. Bit masks of 1 are the channels for which input mode is differential and bit mask of 0 are the channels for which input mode is unipolar.

Note
  None.

References XAdcPs::IsReady, XAdcPs_ReadInternalReg(), XADCPS_SEQ04_CH_VALID_MASK, XADCPS_SEQ04_OFFSET, XADCPS_SEQ05_CH_VALID_MASK, XADCPS_SEQ05_OFFSET, and XADCPS_SEQ_CH_AUX_SHIFT.

u8 XAdcPs_GetSequencerMode | ( | XAdcPs * | InstancePtr | ) |

This function gets the channel sequencer mode from the Configuration Register 1.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  The channel sequencer mode :
  - XADCPS_SEQ_MODE_SAFE : Default safe mode
  - XADCPS_SEQ_MODE_ONEPASS : One pass through sequence
  - XADCPS_SEQ_MODE_CONTINPASS : Continuous channel sequencing
  - XADCPS_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
  - XADCPS_SEQ_MODE_SIMUL_SAMPLING : Simulataneous sampling mode
  - XADCPS_SEQ_MODE_INDEPENDENT : Independent mode

Note
  None.

References XAdcPs::IsReady, XADCPS_CFR1_OFFSET, XADCPS_CFR1_SEQ_SHIFT, XADCPS_CFR1_SEQ_VALID_MASK, and XAdcPs_ReadInternalReg().

Referenced by XAdcPs_SetSeqAcqTime(), XAdcPs_SetSeqAvgEnables(), XAdcPs_SetSeqChEnables(), XAdcPs_SetSeqInputMode(), and XAdcPs_SetSingleChParams().

void XAdcPs_IntrClear | ( | XAdcPs * | InstancePtr,
|  | u32 | Mask
| ) |  |

This function clears the specified interrupts in the Interrupt Status Register (IPISR).

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  Mask | is the bit-mask of the interrupts to be cleared. Bit positions of 1 will be cleared. Bit positions of 0 will not change the previous interrupt status. This mask is formed by OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h.

Returns
  None.

Note
  None.

References XAdcPs_Config::BaseAddress, XAdcPs::Config, XAdcPs::IsReady, XADCPS_INT_STS_OFFSET, XADCPS_INTX_ALL_MASK, XAdcPs_ReadReg, and XAdcPs_WriteReg.

Referenced by XAdcIntrExample().

void XAdcPs_IntrDisable | ( | XAdcPs * | InstancePtr,
|  | u32 | Mask
| ) |  |

This function disables the specified interrupts in the device.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  Mask | is the bit-mask of the interrupts to be disabled. Bit positions of 1 will be disabled. Bit positions of 0 will keep the previous setting. This mask is formed by OR'ing XADCPS_INTX_* bits defined in xadcps_hw.h.

Returns
  None.

Note
  None

References XAdcPs_Config::BaseAddress, XAdcPs::Config, XAdcPs::IsReady, XADCPS_INT_MASK_OFFSET, XADCPS_INTX_ALL_MASK, XAdcPs_ReadReg, and XAdcPs_WriteReg.

void XAdcPs_IntrEnable | ( | XAdcPs * | InstancePtr,
|  | u32 | Mask
| ) |  |

Functions in xadcps_intr.c.

This function enables the specified interrupts in the device.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  Mask | is the bit-mask of the interrupts to be enabled. Bit positions of 1 will be enabled. Bit positions of 0 will keep the previous setting. This mask is formed by OR'ing XADCPS_INTX_* bits defined in xadcps_hw.h.

Returns
  None.

Note
  None.

References XAdcPs_Config::BaseAddress, XAdcPs::Config, XAdcPs::IsReady, XADCPS_INT_MASK_OFFSET, XADCPS_INTX_ALL_MASK, XAdcPs_ReadReg, and XAdcPs_WriteReg.

Referenced by XAdcIntrExample().

u32 XAdcPs_IntrGetEnabled | ( | XAdcPs * | InstancePtr | ) |

This function returns the enabled interrupts read from the Interrupt Mask Register (IPIER).

Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to interpret the returned value.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  A 32-bit value representing the contents of the I.

Note
  None.

References XAdcPs_Config::BaseAddress, XAdcPs::Config, XAdcPs::IsReady, XADCPS_INT_MASK_OFFSET, XADCPS_INTX_ALL_MASK, and XAdcPs_ReadReg.

u32 XAdcPs_IntrGetStatus | ( | XAdcPs * | InstancePtr | ) |

This function returns the interrupt status read from Interrupt Status Register(IPISR).

Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to interpret the returned value.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  A 32-bit value representing the contents of the IPISR.

Note
  The device must be configured at hardware build time to include interrupt component for this function to work.

References XAdcPs_Config::BaseAddress, XAdcPs::Config, XAdcPs::IsReady, XADCPS_INT_STS_OFFSET, XADCPS_INTX_ALL_MASK, and XAdcPs_ReadReg.

Referenced by XAdcIntrExample().

XAdcPs_Config * XAdcPs_LookupConfig | ( | u16 | DeviceId | ) |

Functions in xadcps_sinit.c.

This function looks up the device configuration based on the unique device ID.

The table XAdcPs_ConfigTable contains the configuration info for each device in the system.

Parameters

  DeviceId | contains the ID of the device for which the device configuration pointer is to be returned.

Returns
  - A pointer to the configuration found.
  - NULL if the specified device ID was not found.

Note
  None.

Referenced by XAdcIntrExample().

u32 XAdcPs_ReadInternalReg | ( | XAdcPs * | InstancePtr,
|  | u32 | RegOffset
| ) |  |

This function is used for reading from the XADC Registers using the Data FIFO.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  RegOffset | is the offset of the XADC register to be read.

Returns
  Data read from the FIFO

Note
  None.

References XAdcPs_FormatWriteData, XAdcPs_ReadFifo, and XAdcPs_WriteFifo.

Referenced by XAdcPs_DisableUserOverTemp(), XAdcPs_EnableUserOverTemp(), XAdcPs_GetAdcClkDivisor(), XAdcPs_GetAdcData(), XAdcPs_GetAlarmEnables(), XAdcPs_GetAlarmThreshold(), XAdcPs_GetAvg(), XAdcPs_GetCalibCoefficient(), XAdcPs_GetCalibEnables(), XAdcPs_GetMinMaxMeasurement(), XAdcPs_GetPowerdownMode(), XAdcPs_GetSamplingMode(), XAdcPs_GetSeqAcqTime(), XAdcPs_GetSeqAvgEnables(), XAdcPs_GetSeqChEnables(), XAdcPs_GetSeqInputMode(), XAdcPs_GetSequencerMode(), XAdcPs_SetAlarmEnables(), XAdcPs_SetAvg(), XAdcPs_SetCalibEnables(), XAdcPs_SetMuxMode(), XAdcPs_SetPowerdownMode(), XAdcPs_SetSequencerEvent(), XAdcPs_SetSequencerMode(), and XAdcPs_SetSingleChParams().

void XAdcPs_Reset | ( | XAdcPs * | InstancePtr | ) |

This function resets the XADC Hard Macro in the device.

Parameters

  InstancePtr | is a pointer to the Xxadc instance.

Returns
  None.

Note
  None.

References XAdcPs::IsReady, XADCPS_MCTL_OFFSET, and XAdcPs_WriteReg.

Referenced by XAdcPs_SelfTest().

int XAdcPs_SelfTest | ( | XAdcPs * | InstancePtr | ) |

Functions in xadcps_selftest.c.

Run a self-test on the driver/device.

The test

- Resets the device,
- Writes a value into the Alarm Threshold register and reads it back for comparison.
- Resets the device again.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.

Returns
  - XST_SUCCESS if the value read from the Alarm Threshold register is the same as the value written.
  - XST_FAILURE Otherwise

Note
  This is a destructive test in that resets of the device are performed. Refer to the device specification for the device status after the reset operation.

References XAdcPs::IsReady, XADCPS_ATR_VCCINT_UPPER, XAdcPs_GetAlarmThreshold(), XAdcPs_Reset(), and XAdcPs_SetAlarmThreshold().

Referenced by XAdcIntrExample().

void XAdcPs_SetAdcClkDivisor | ( | XAdcPs * | InstancePtr,
|  | u8 | Divisor
| ) |  |

The function sets the frequency of the ADCCLK by configuring the DCLK to ADCCLK ratio in the Configuration Register #2.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  Divisor | is clock divisor used to derive ADCCLK from DCLK. Valid values of the divisor are 0 to 255. Values 0, 1, 2 are all mapped to 2. Refer to the device specification for more details

Returns
  None.

Note
  - The ADCCLK is an internal clock used by the ADC and is synchronized to the DCLK clock. The ADCCLK is equal to DCLK divided by the user selection in the Configuration Register 2.
  - There is no Assert on the minimum value of the Divisor.

References XAdcPs::IsReady, XADCPS_CFR2_CD_SHIFT, XADCPS_CFR2_OFFSET, and XAdcPs_WriteInternalReg().

void XAdcPs_SetAlarmEnables | ( | XAdcPs * | InstancePtr,
|  | u16 | AlmEnableMask
| ) |  |

This function enables the alarm outputs for the specified alarms in the Configuration Register 1.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  AlmEnableMask | is the bit-mask of the alarm outputs to be enabled in the Configuration Register 1. Bit positions of 1 will be enabled. Bit positions of 0 will be disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and XADCPS_CFR1_OT_MASK masks defined in xadcps_hw.h.

Returns
  None.

Note
  The implementation of the alarm enables in the Configuration register 1 is such that the alarms for bit positions of 1 will be disabled and alarms for bit positions of 0 will be enabled. The alarm outputs specified by the AlmEnableMask are negated before writing to the Configuration Register 1.

References XAdcPs::IsReady, XADCPS_CFR1_ALM_ALL_MASK, XADCPS_CFR1_OFFSET, XAdcPs_ReadInternalReg(), and XAdcPs_WriteInternalReg().

Referenced by XAdcIntrExample().

void XAdcPs_SetAlarmThreshold | ( | XAdcPs * | InstancePtr,
|  | u8 | AlarmThrReg,
|  | u16 | Value
| ) |  |

This functions sets the contents of the given Alarm Threshold Register.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  AlarmThrReg | is the index of an Alarm Threshold Register to be set. Use XADCPS_ATR_* constants defined in xadcps.h to specify the index.
  Value | is the 16-bit threshold value to write into the register.

Returns
  None.

Note
  Use XAdcPs_SetOverTemp() to set the Over Temperature upper threshold value.

References XAdcPs::IsReady, XADCPS_ATR_TEMP_UPPER_OFFSET, XADCPS_ATR_VCCPDRO_LOWER, and XAdcPs_WriteInternalReg().

Referenced by XAdcIntrExample(), and XAdcPs_SelfTest().

void XAdcPs_SetAvg | ( | XAdcPs * | InstancePtr,
|  | u8 | Average
| ) |  |

This function sets the number of samples of averaging that is to be done for all the channels in both the single channel mode and sequence mode of operations.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  Average | is the number of samples of averaging programmed to the Configuration Register 0. Use the XADCPS_AVG_* definitions defined in xadcps.h file : XADCPS_AVG_0_SAMPLES for no averaging XADCPS_AVG_16_SAMPLES for 16 samples of averaging XADCPS_AVG_64_SAMPLES for 64 samples of averaging XADCPS_AVG_256_SAMPLES for 256 samples of averaging

Returns
  None.

Note
  None.

References XAdcPs::IsReady, XADCPS_AVG_256_SAMPLES, XADCPS_CFR0_AVG_SHIFT, XADCPS_CFR0_AVG_VALID_MASK, XADCPS_CFR0_OFFSET, XAdcPs_ReadInternalReg(), and XAdcPs_WriteInternalReg().

void XAdcPs_SetCalibEnables | ( | XAdcPs * | InstancePtr,
|  | u16 | Calibration
| ) |  |

This function enables the specified calibration in the Configuration Register 1 :

- XADCPS_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction
- XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset correction
- XADCPS_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor offset correction
- XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor gain and offset correction
- XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  Calibration | is the Calibration to be applied. Use XADCPS_CFR1_CAL*_* bits defined in xadcps_hw.h. Multiple calibrations can be enabled at a time by oring the XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits. Calibration can be disabled by specifying XADCPS_CFR1_CAL_DISABLE_MASK;

Returns
  None.

Note
  None.

References XAdcPs::IsReady, XADCPS_CFR1_CAL_ADC_OFFSET_MASK, XADCPS_CFR1_CAL_DISABLE_MASK, XADCPS_CFR1_CAL_VALID_MASK, XADCPS_CFR1_OFFSET, XAdcPs_ReadInternalReg(), and XAdcPs_WriteInternalReg().

void XAdcPs_SetConfigRegister | ( | XAdcPs * | InstancePtr,
|  | u32 | Data
| ) |  |

The functions sets the contents of the Config Register.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  Data | is the 32 bit data to be written to the Register.

Returns
  None.

Note
  None.

References XAdcPs::IsReady, XADCPS_CFG_OFFSET, and XAdcPs_WriteReg.

void XAdcPs_SetMiscCtrlRegister | ( | XAdcPs * | InstancePtr,
|  | u32 | Data
| ) |  |

The functions sets the contents of the Miscellaneous Control register.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  Data | is the 32 bit data to be written to the Register.

Returns
  None.

Note
  None.

References XAdcPs::IsReady, XADCPS_MCTL_OFFSET, and XAdcPs_WriteReg.

void XAdcPs_SetMuxMode | ( | XAdcPs * | InstancePtr,
|  | int | MuxMode,
|  | u8 | Channel
| ) |  |

This function sets the External Mux mode.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  MuxMode | specifies whether External Mux is used FALSE specifies NO external MUX TRUE specifies External Mux is used
  Channel | specifies the channel to be used for the external Mux. Please read the Device Spec for which channels are valid for which mode.

Returns
  None.

Note
  There is no Assert in this function for checking the channel number if the external Mux is used. The user should provide a valid channel number.

References XAdcPs::IsReady, XADCPS_CFR0_CHANNEL_MASK, XADCPS_CFR0_MUX_MASK, XADCPS_CFR0_OFFSET, XAdcPs_ReadInternalReg(), and XAdcPs_WriteInternalReg().

void XAdcPs_SetPowerdownMode | ( | XAdcPs * | InstancePtr,
|  | u32 | Mode
| ) |  |

This function sets the Power Down mode.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  Mode | specifies the Power Down Mode XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and ADC B are enabled) XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B XADCPS_PD_MODE_XADC specifies the Power Down of both ADC A and ADC B.

Returns
  None.

Note
  None.

References XAdcPs::IsReady, XADCPS_CFR2_OFFSET, XADCPS_CFR2_PD_MASK, XADCPS_CFR2_PD_SHIFT, XADCPS_PD_MODE_XADC, XAdcPs_ReadInternalReg(), and XAdcPs_WriteInternalReg().

int XAdcPs_SetSeqAcqTime | ( | XAdcPs * | InstancePtr,
|  | u32 | AcqCyclesChMask
| ) |  |

This function sets the number of Acquisition cycles in the ADC Channel Acquisition Time Sequencer Registers.

The sequencer must be disabled before writing to these regsiters.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  AcqCyclesChMask | is the bit mask of all the channels for which the number of acquisition cycles is to be extended. Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel numbers. Acquisition cycles will be extended to 10 ADCCLK cycles for bit masks of 1 and will be the default 4 ADCCLK cycles for bit masks of 0. The AcqCyclesChMask is a 32 bit mask that is written to the two 16 bit ADC Channel Acquisition Time Sequencer Registers.

Returns
  - XST_SUCCESS if the given values were written successfully to the Channel Sequencer Registers.
  - XST_FAILURE if the channel sequencer is enabled.

Note
  None.

References XAdcPs::IsReady, XAdcPs_GetSequencerMode(), XADCPS_SEQ06_CH_VALID_MASK, XADCPS_SEQ06_OFFSET, XADCPS_SEQ07_CH_VALID_MASK, XADCPS_SEQ07_OFFSET, XADCPS_SEQ_CH_AUX_SHIFT, XADCPS_SEQ_MODE_SAFE, and XAdcPs_WriteInternalReg().

int XAdcPs_SetSeqAvgEnables | ( | XAdcPs * | InstancePtr,
|  | u32 | AvgEnableChMask
| ) |  |

This function enables the averaging for the specified channels in the ADC Channel Averaging Enable Sequencer Registers.

The sequencer must be disabled before writing to these regsiters.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  AvgEnableChMask | is the bit mask of all the channels for which averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel numbers. Averaging will be enabled for bit masks of 1 and disabled for bit mask of 0. The AvgEnableChMask is a 32 bit mask that is written to the two 16 bit ADC Channel Averaging Enable Sequencer Registers.

Returns
  - XST_SUCCESS if the given values were written successfully to the ADC Channel Averaging Enables Sequencer Registers.
  - XST_FAILURE if the channel sequencer is enabled.

Note
  None

References XAdcPs::IsReady, XAdcPs_GetSequencerMode(), XADCPS_SEQ02_CH_VALID_MASK, XADCPS_SEQ02_OFFSET, XADCPS_SEQ03_CH_VALID_MASK, XADCPS_SEQ03_OFFSET, XADCPS_SEQ_CH_AUX_SHIFT, XADCPS_SEQ_MODE_SAFE, and XAdcPs_WriteInternalReg().

int XAdcPs_SetSeqChEnables | ( | XAdcPs * | InstancePtr,
|  | u32 | ChEnableMask
| ) |  |

This function enables the specified channels in the ADC Channel Selection Sequencer Registers.

The sequencer must be disabled before writing to these regsiters.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  ChEnableMask | is the bit mask of all the channels to be enabled. Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel numbers. Bit masks of 1 will be enabled and bit mask of 0 will be disabled. The ChEnableMask is a 32 bit mask that is written to the two 16 bit ADC Channel Selection Sequencer Registers.

Returns
  - XST_SUCCESS if the given values were written successfully to the ADC Channel Selection Sequencer Registers.
  - XST_FAILURE if the channel sequencer is enabled.

Note
  None

References XAdcPs::IsReady, XAdcPs_GetSequencerMode(), XADCPS_SEQ00_CH_VALID_MASK, XADCPS_SEQ00_OFFSET, XADCPS_SEQ01_CH_VALID_MASK, XADCPS_SEQ01_OFFSET, XADCPS_SEQ_CH_AUX_SHIFT, XADCPS_SEQ_MODE_SAFE, and XAdcPs_WriteInternalReg().

int XAdcPs_SetSeqInputMode | ( | XAdcPs * | InstancePtr,
|  | u32 | InputModeChMask
| ) |  |

This function sets the Analog input mode for the specified channels in the ADC Channel Analog-Input Mode Sequencer Registers.

The sequencer must be disabled before writing to these regsiters.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  InputModeChMask | is the bit mask of all the channels for which the input mode is differential mode. Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the channel numbers. Differential input mode will be set for bit masks of 1 and unipolar input mode for bit masks of 0. The InputModeChMask is a 32 bit mask that is written to the two 16 bit ADC Channel Analog-Input Mode Sequencer Registers.

Returns
  - XST_SUCCESS if the given values were written successfully to the ADC Channel Analog-Input Mode Sequencer Registers.
  - XST_FAILURE if the channel sequencer is enabled.

Note
  None

References XAdcPs::IsReady, XAdcPs_GetSequencerMode(), XADCPS_SEQ04_CH_VALID_MASK, XADCPS_SEQ04_OFFSET, XADCPS_SEQ05_CH_VALID_MASK, XADCPS_SEQ05_OFFSET, XADCPS_SEQ_CH_AUX_SHIFT, XADCPS_SEQ_MODE_SAFE, and XAdcPs_WriteInternalReg().

void XAdcPs_SetSequencerEvent | ( | XAdcPs * | InstancePtr,
|  | int | IsEventMode
| ) |  |

The function enables the Event mode or Continuous mode in the sequencer mode.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  IsEventMode | is a boolean parameter that specifies continuous sampling (specify FALSE) or event driven sampling mode (specify TRUE) for the given channel.

Returns
  None.

Note
  None.

References XAdcPs::IsReady, XADCPS_CFR0_EC_MASK, XADCPS_CFR0_OFFSET, XAdcPs_ReadInternalReg(), and XAdcPs_WriteInternalReg().

void XAdcPs_SetSequencerMode | ( | XAdcPs * | InstancePtr,
|  | u8 | SequencerMode
| ) |  |

This function sets the specified Channel Sequencer Mode in the Configuration Register 1 :

        - Default safe mode (XADCPS_SEQ_MODE_SAFE)
        - One pass through sequence (XADCPS_SEQ_MODE_ONEPASS)
        - Continuous channel sequencing (XADCPS_SEQ_MODE_CONTINPASS)
        - Single Channel/Sequencer off (XADCPS_SEQ_MODE_SINGCHAN)
        - Simulataneous sampling mode (XADCPS_SEQ_MODE_SIMUL_SAMPLING)
        - Independent mode (XADCPS_SEQ_MODE_INDEPENDENT)

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  SequencerMode | is the sequencer mode to be set. Use XADCPS_SEQ_MODE_* bits defined in xadcps.h.

Returns
  None.

Note
  Only one of the modes can be enabled at a time. Please read the Spec of the XADC for further information about the sequencer modes.

References XAdcPs::IsReady, XADCPS_CFR1_OFFSET, XADCPS_CFR1_SEQ_SHIFT, XADCPS_CFR1_SEQ_VALID_MASK, XAdcPs_ReadInternalReg(), XADCPS_SEQ_MODE_INDEPENDENT, XADCPS_SEQ_MODE_SIMUL_SAMPLING, and XAdcPs_WriteInternalReg().

Referenced by XAdcIntrExample().

int XAdcPs_SetSingleChParams | ( | XAdcPs * | InstancePtr,
|  | u8 | Channel,
|  | int | IncreaseAcqCycles,
|  | int | IsEventMode,
|  | int | IsDifferentialMode
| ) |  |

The function sets the given parameters in the Configuration Register 0 in the single channel mode.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  Channel | is the channel number for the singel channel mode. The valid channels are 0 to 6, 8, and 13 to 31. If the external Mux is used then this specifies the channel oonnected to the external Mux. Please read the Device Spec to know which channels are valid.
  IncreaseAcqCycles | is a boolean parameter which specifies whether the Acquisition time for the external channels has to be increased to 10 ADCCLK cycles (specify TRUE) or remain at the default 4 ADCCLK cycles (specify FALSE). This parameter is only valid for the external channels.
  IsEventMode | specifies whether the operation of the ADC is Event driven or Continuous mode.
  IsDifferentialMode | is a boolean parameter which specifies unipolar(specify FALSE) or differential mode (specify TRUE) for the analog inputs. The input mode is only valid for the external channels.

Returns
  - XST_SUCCESS if the given values were written successfully to the Configuration Register 0.
  - XST_FAILURE if the channel sequencer is enabled or the input parameters are not valid for the selected channel.

Note
  - The number of samples for the averaging for all the channels is set by using the function XAdcPs_SetAvg.
  - The calibration of the device is done by doing a ADC conversion on the calibration channel(channel 8). The input parameters IncreaseAcqCycles, IsDifferentialMode and IsEventMode are not valid for this channel

References XAdcPs::IsReady, XADCPS_CFR0_ACQ_MASK, XADCPS_CFR0_AVG_VALID_MASK, XADCPS_CFR0_CHANNEL_MASK, XADCPS_CFR0_DU_MASK, XADCPS_CFR0_EC_MASK, XADCPS_CFR0_OFFSET, XADCPS_CH_ADC_CALIB, XADCPS_CH_AUX_MAX, XADCPS_CH_AUX_MIN, XADCPS_CH_VBRAM, XADCPS_CH_VCCPINT, XADCPS_CH_VPVN, XAdcPs_GetSequencerMode(), XAdcPs_ReadInternalReg(), XADCPS_SEQ_MODE_SINGCHAN, and XAdcPs_WriteInternalReg().

void XAdcPs_WriteInternalReg | ( | XAdcPs * | InstancePtr,
|  | u32 | RegOffset,
|  | u32 | Data
| ) |  |

This function is used for writing to XADC Registers using the command FIFO.

Parameters

  InstancePtr | is a pointer to the XAdcPs instance.
  RegOffset | is the offset of the XADC register to be written.
  Data | is the data to be written.

Returns
  None.

Note
  None.

References XAdcPs_FormatWriteData, XAdcPs_ReadFifo, and XAdcPs_WriteFifo.

Referenced by XAdcPs_DisableUserOverTemp(), XAdcPs_EnableUserOverTemp(), XAdcPs_SetAdcClkDivisor(), XAdcPs_SetAlarmEnables(), XAdcPs_SetAlarmThreshold(), XAdcPs_SetAvg(), XAdcPs_SetCalibEnables(), XAdcPs_SetMuxMode(), XAdcPs_SetPowerdownMode(), XAdcPs_SetSeqAcqTime(), XAdcPs_SetSeqAvgEnables(), XAdcPs_SetSeqChEnables(), XAdcPs_SetSeqInputMode(), XAdcPs_SetSequencerEvent(), XAdcPs_SetSequencerMode(), and XAdcPs_SetSingleChParams().

## Variable Documentation

XAdcPs_Config XAdcPs_ConfigTable[]

This table contains configuration information for each XADC Monitor/ADC device in the system.

XAdcPs_Config XAdcPs_ConfigTable[XPAR_XADCPS_NUM_INSTANCES]

Initial value:
=
{
{
XPAR_XADCPS_0_DEVICE_ID,
XPAR_XADCPS_0_BASEADDR
}
}

This table contains configuration information for each XADC Monitor/ADC device in the system.