xadcps: xadcps_hw.h File Reference

| xadcps Xilinx SDK Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List
- Examples

Macros
xadcps_hw.h File Reference

## Macros
#define | XAdcPs_ReadReg(BaseAddress, RegOffset) (Xil_In32((BaseAddress) + (RegOffset)))
| Read a register of the XADC device. More...
#define | XAdcPs_WriteReg(BaseAddress, RegOffset, Data) (Xil_Out32((BaseAddress) + (RegOffset), (Data)))
| Write a register of the XADC device. More...
#define | XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite)
| Formats the data to be written to the the XADC registers. More...
Register offsets of XADC in the Device Config
The following constants provide access to each of the registers of the XADC device.
#define | XADCPS_CFG_OFFSET 0x00
| Configuration Register. More...
#define | XADCPS_INT_STS_OFFSET 0x04
| Interrupt Status Register. More...
#define | XADCPS_INT_MASK_OFFSET 0x08
| Interrupt Mask Register. More...
#define | XADCPS_MSTS_OFFSET 0x0C
| Misc status register. More...
#define | XADCPS_CMDFIFO_OFFSET 0x10
| Command FIFO Register. More...
#define | XADCPS_RDFIFO_OFFSET 0x14
| Read FIFO Register. More...
#define | XADCPS_MCTL_OFFSET 0x18
| Misc control register. More...
XADC Config Register Bit definitions
#define | XADCPS_CFG_ENABLE_MASK 0x80000000
| Enable access from PS mask. More...
#define | XADCPS_CFG_CFIFOTH_MASK 0x00F00000
| Command FIFO Threshold mask. More...
#define | XADCPS_CFG_DFIFOTH_MASK 0x000F0000
| Data FIFO Threshold mask. More...
#define | XADCPS_CFG_WEDGE_MASK 0x00002000
| Write Edge Mask. More...
#define | XADCPS_CFG_REDGE_MASK 0x00001000
| Read Edge Mask. More...
#define | XADCPS_CFG_TCKRATE_MASK 0x00000300
| Clock freq control. More...
#define | XADCPS_CFG_IGAP_MASK 0x0000001F
| Idle Gap between successive commands. More...
XADC Interrupt Status/Mask Register Bit definitions
The definitions are same for the Interrupt Status Register and Interrupt Mask Register. They are defined only once.
#define | XADCPS_INTX_ALL_MASK 0x000003FF
| Alarm Signals Mask. More...
#define | XADCPS_INTX_CFIFO_LTH_MASK 0x00000200
| CMD FIFO less than threshold. More...
#define | XADCPS_INTX_DFIFO_GTH_MASK 0x00000100
| Data FIFO greater than threshold. More...
#define | XADCPS_INTX_OT_MASK 0x00000080
| Over temperature Alarm Status. More...
#define | XADCPS_INTX_ALM_ALL_MASK 0x0000007F
| Alarm Signals Mask. More...
#define | XADCPS_INTX_ALM6_MASK 0x00000040
| Alarm 6 Mask. More...
#define | XADCPS_INTX_ALM5_MASK 0x00000020
| Alarm 5 Mask. More...
#define | XADCPS_INTX_ALM4_MASK 0x00000010
| Alarm 4 Mask. More...
#define | XADCPS_INTX_ALM3_MASK 0x00000008
| Alarm 3 Mask. More...
#define | XADCPS_INTX_ALM2_MASK 0x00000004
| Alarm 2 Mask. More...
#define | XADCPS_INTX_ALM1_MASK 0x00000002
| Alarm 1 Mask. More...
#define | XADCPS_INTX_ALM0_MASK 0x00000001
| Alarm 0 Mask. More...
XADC Miscellaneous Register Bit definitions
#define | XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000
| Command FIFO Level mask. More...
#define | XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000
| Data FIFO Level Mask. More...
#define | XADCPS_MSTS_CFIFOF_MASK 0x00000800
| Command FIFO Full Mask. More...
#define | XADCPS_MSTS_CFIFOE_MASK 0x00000400
| Command FIFO Empty Mask. More...
#define | XADCPS_MSTS_DFIFOF_MASK 0x00000200
| Data FIFO Full Mask. More...
#define | XADCPS_MSTS_DFIFOE_MASK 0x00000100
| Data FIFO Empty Mask. More...
#define | XADCPS_MSTS_OT_MASK 0x00000080
| Over Temperature Mask. More...
#define | XADCPS_MSTS_ALM_MASK 0x0000007F
| Alarms Mask. More...
XADC Miscellaneous Control Register Bit definitions
#define | XADCPS_MCTL_RESET_MASK 0x00000010
| Reset XADC. More...
#define | XADCPS_MCTL_FLUSH_MASK 0x00000001
| Flush the FIFOs. More...
Internal Register offsets of the XADC
The following constants provide access to each of the internal registers of the XADC device.
#define | XADCPS_TEMP_OFFSET 0x00
| On-chip Temperature Reg. More...
#define | XADCPS_VCCINT_OFFSET 0x01
| On-chip VCCINT Data Reg. More...
#define | XADCPS_VCCAUX_OFFSET 0x02
| On-chip VCCAUX Data Reg. More...
#define | XADCPS_VPVN_OFFSET 0x03
| ADC out of VP/VN. More...
#define | XADCPS_VREFP_OFFSET 0x04
| On-chip VREFP Data Reg. More...
#define | XADCPS_VREFN_OFFSET 0x05
| On-chip VREFN Data Reg. More...
#define | XADCPS_VBRAM_OFFSET 0x06
| On-chip VBRAM , 7 Series. More...
#define | XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08
| ADC A Supply Offset Reg. More...
#define | XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09
| ADC A Offset Data Reg. More...
#define | XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A
| ADC A Gain Error Reg. More...
#define | XADCPS_VCCPINT_OFFSET 0x0D
| On-chip VCCPINT Reg, Zynq. More...
#define | XADCPS_VCCPAUX_OFFSET 0x0E
| On-chip VCCPAUX Reg, Zynq. More...
#define | XADCPS_VCCPDRO_OFFSET 0x0F
| On-chip VCCPDRO Reg, Zynq. More...
#define | XADCPS_AUX00_OFFSET 0x10
| ADC out of VAUXP0/VAUXN0. More...
#define | XADCPS_AUX01_OFFSET 0x11
| ADC out of VAUXP1/VAUXN1. More...
#define | XADCPS_AUX02_OFFSET 0x12
| ADC out of VAUXP2/VAUXN2. More...
#define | XADCPS_AUX03_OFFSET 0x13
| ADC out of VAUXP3/VAUXN3. More...
#define | XADCPS_AUX04_OFFSET 0x14
| ADC out of VAUXP4/VAUXN4. More...
#define | XADCPS_AUX05_OFFSET 0x15
| ADC out of VAUXP5/VAUXN5. More...
#define | XADCPS_AUX06_OFFSET 0x16
| ADC out of VAUXP6/VAUXN6. More...
#define | XADCPS_AUX07_OFFSET 0x17
| ADC out of VAUXP7/VAUXN7. More...
#define | XADCPS_AUX08_OFFSET 0x18
| ADC out of VAUXP8/VAUXN8. More...
#define | XADCPS_AUX09_OFFSET 0x19
| ADC out of VAUXP9/VAUXN9. More...
#define | XADCPS_AUX10_OFFSET 0x1A
| ADC out of VAUXP10/VAUXN10. More...
#define | XADCPS_AUX11_OFFSET 0x1B
| ADC out of VAUXP11/VAUXN11. More...
#define | XADCPS_AUX12_OFFSET 0x1C
| ADC out of VAUXP12/VAUXN12. More...
#define | XADCPS_AUX13_OFFSET 0x1D
| ADC out of VAUXP13/VAUXN13. More...
#define | XADCPS_AUX14_OFFSET 0x1E
| ADC out of VAUXP14/VAUXN14. More...
#define | XADCPS_AUX15_OFFSET 0x1F
| ADC out of VAUXP15/VAUXN15. More...
#define | XADCPS_MAX_TEMP_OFFSET 0x20
| Max Temperature Reg. More...
#define | XADCPS_MAX_VCCINT_OFFSET 0x21
| Max VCCINT Register. More...
#define | XADCPS_MAX_VCCAUX_OFFSET 0x22
| Max VCCAUX Register. More...
#define | XADCPS_MAX_VCCBRAM_OFFSET 0x23
| Max BRAM Register, 7 series. More...
#define | XADCPS_MIN_TEMP_OFFSET 0x24
| Min Temperature Reg. More...
#define | XADCPS_MIN_VCCINT_OFFSET 0x25
| Min VCCINT Register. More...
#define | XADCPS_MIN_VCCAUX_OFFSET 0x26
| Min VCCAUX Register. More...
#define | XADCPS_MIN_VCCBRAM_OFFSET 0x27
| Min BRAM Register, 7 series. More...
#define | XADCPS_MAX_VCCPINT_OFFSET 0x28
| Max VCCPINT Register, Zynq. More...
#define | XADCPS_MAX_VCCPAUX_OFFSET 0x29
| Max VCCPAUX Register, Zynq. More...
#define | XADCPS_MAX_VCCPDRO_OFFSET 0x2A
| Max VCCPDRO Register, Zynq. More...
#define | XADCPS_MIN_VCCPINT_OFFSET 0x2C
| Min VCCPINT Register, Zynq. More...
#define | XADCPS_MIN_VCCPAUX_OFFSET 0x2D
| Min VCCPAUX Register, Zynq. More...
#define | XADCPS_MIN_VCCPDRO_OFFSET 0x2E
| Min VCCPDRO Register,Zynq. More...
#define | XADCPS_FLAG_OFFSET 0x3F
| Flag Register. More...
#define | XADCPS_CFR0_OFFSET 0x40
| Configuration Register 0. More...
#define | XADCPS_CFR1_OFFSET 0x41
| Configuration Register 1. More...
#define | XADCPS_CFR2_OFFSET 0x42
| Configuration Register 2. More...
#define | XADCPS_SEQ00_OFFSET 0x48
| Seq Reg 00 Adc Channel Selection. More...
#define | XADCPS_SEQ01_OFFSET 0x49
| Seq Reg 01 Adc Channel Selection. More...
#define | XADCPS_SEQ02_OFFSET 0x4A
| Seq Reg 02 Adc Average Enable. More...
#define | XADCPS_SEQ03_OFFSET 0x4B
| Seq Reg 03 Adc Average Enable. More...
#define | XADCPS_SEQ04_OFFSET 0x4C
| Seq Reg 04 Adc Input Mode Select. More...
#define | XADCPS_SEQ05_OFFSET 0x4D
| Seq Reg 05 Adc Input Mode Select. More...
#define | XADCPS_SEQ06_OFFSET 0x4E
| Seq Reg 06 Adc Acquisition Select. More...
#define | XADCPS_SEQ07_OFFSET 0x4F
| Seq Reg 07 Adc Acquisition Select. More...
#define | XADCPS_ATR_TEMP_UPPER_OFFSET 0x50
| Temp Upper Alarm Register. More...
#define | XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51
| VCCINT Upper Alarm Reg. More...
#define | XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52
| VCCAUX Upper Alarm Reg. More...
#define | XADCPS_ATR_OT_UPPER_OFFSET 0x53
| Over Temp Upper Alarm Reg. More...
#define | XADCPS_ATR_TEMP_LOWER_OFFSET 0x54
| Temp Lower Alarm Register. More...
#define | XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55
| VCCINT Lower Alarm Reg. More...
#define | XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56
| VCCAUX Lower Alarm Reg. More...
#define | XADCPS_ATR_OT_LOWER_OFFSET 0x57
| Over Temp Lower Alarm Reg. More...
#define | XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58
| VBRAM Upper Alarm, 7 series. More...
#define | XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59
| VCCPINT Upper Alarm, Zynq. More...
#define | XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A
| VCCPAUX Upper Alarm, Zynq. More...
#define | XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B
| VCCPDRO Upper Alarm, Zynq. More...
#define | XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C
| VRBAM Lower Alarm, 7 Series. More...
#define | XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D
| VCCPINT Lower Alarm, Zynq. More...
#define | XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E
| VCCPAUX Lower Alarm, Zynq. More...
#define | XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F
| VCCPDRO Lower Alarm, Zynq. More...
Configuration Register 0 (CFR0) mask(s)
#define | XADCPS_CFR0_CAL_AVG_MASK 0x8000
| Averaging enable Mask. More...
#define | XADCPS_CFR0_AVG_VALID_MASK 0x3000
| Averaging bit Mask. More...
#define | XADCPS_CFR0_AVG1_MASK 0x0000
| No Averaging. More...
#define | XADCPS_CFR0_AVG16_MASK 0x1000
| Average 16 samples. More...
#define | XADCPS_CFR0_AVG64_MASK 0x2000
| Average 64 samples. More...
#define | XADCPS_CFR0_AVG256_MASK 0x3000
| Average 256 samples. More...
#define | XADCPS_CFR0_AVG_SHIFT 12
| Averaging bits shift. More...
#define | XADCPS_CFR0_MUX_MASK 0x0800
| External Mask Enable. More...
#define | XADCPS_CFR0_DU_MASK 0x0400
| Bipolar/Unipolar mode. More...
#define | XADCPS_CFR0_EC_MASK 0x0200
| Event driven/ Continuous mode selection. More...
#define | XADCPS_CFR0_ACQ_MASK 0x0100
| Add acquisition by 6 ADCCLK. More...
#define | XADCPS_CFR0_CHANNEL_MASK 0x001F
| Channel number bit Mask. More...
Configuration Register 1 (CFR1) mask(s)
#define | XADCPS_CFR1_SEQ_VALID_MASK 0xF000
| Sequence bit Mask. More...
#define | XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000
| Default Safe Mode. More...
#define | XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000
| Onepass through Seq. More...
#define | XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000
| Continuous Cycling Seq. More...
#define | XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000
| Single channel - No Seq. More...
#define | XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000
| Simulataneous Sampling Mask. More...
#define | XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000
| Independent Mode. More...
#define | XADCPS_CFR1_SEQ_SHIFT 12
| Sequence bit shift. More...
#define | XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800
| Alm 6 - VCCPDRO, Zynq. More...
#define | XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400
| Alm 5 - VCCPAUX, Zynq. More...
#define | XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200
| Alm 4 - VCCPINT, Zynq. More...
#define | XADCPS_CFR1_ALM_VBRAM_MASK 0x0100
| Alm 3 - VBRAM, 7 series. More...
#define | XADCPS_CFR1_CAL_VALID_MASK 0x00F0
| Valid Calibration Mask. More...
#define | XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080
| Calibration 3 -Power Supply Gain/Offset Enable. More...
#define | XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040
| Calibration 2 -Power Supply Offset Enable. More...
#define | XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020
| Calibration 1 -ADC Gain Offset Enable. More...
#define | XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010
| Calibration 0 -ADC Offset Enable. More...
#define | XADCPS_CFR1_CAL_DISABLE_MASK 0x0000
| No Calibration. More...
#define | XADCPS_CFR1_ALM_ALL_MASK 0x0F0F
| Mask for all alarms. More...
#define | XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008
| Alarm 2 - VCCAUX Enable. More...
#define | XADCPS_CFR1_ALM_VCCINT_MASK 0x0004
| Alarm 1 - VCCINT Enable. More...
#define | XADCPS_CFR1_ALM_TEMP_MASK 0x0002
| Alarm 0 - Temperature. More...
#define | XADCPS_CFR1_OT_MASK 0x0001
| Over Temperature Enable. More...
Configuration Register 2 (CFR2) mask(s)
#define | XADCPS_CFR2_CD_VALID_MASK 0xFF00
| Clock Divisor bit Mask. More...
#define | XADCPS_CFR2_CD_SHIFT 8
| Num of shift on division. More...
#define | XADCPS_CFR2_CD_MIN 8
| Minimum value of divisor. More...
#define | XADCPS_CFR2_CD_MAX 255
| Maximum value of divisor. More...
#define | XADCPS_CFR2_CD_MIN 8
| Minimum value of divisor. More...
#define | XADCPS_CFR2_PD_MASK 0x0030
| Power Down Mask. More...
#define | XADCPS_CFR2_PD_XADC_MASK 0x0030
| Power Down XADC Mask. More...
#define | XADCPS_CFR2_PD_ADC1_MASK 0x0020
| Power Down ADC1 Mask. More...
#define | XADCPS_CFR2_PD_SHIFT 4
| Power Down Shift. More...
Sequence Register (SEQ) Bit Definitions
#define | XADCPS_SEQ_CH_CALIB 0x00000001
| ADC Calibration Channel. More...
#define | XADCPS_SEQ_CH_VCCPINT 0x00000020
| VCCPINT, Zynq Only. More...
#define | XADCPS_SEQ_CH_VCCPAUX 0x00000040
| VCCPAUX, Zynq Only. More...
#define | XADCPS_SEQ_CH_VCCPDRO 0x00000080
| VCCPDRO, Zynq Only. More...
#define | XADCPS_SEQ_CH_TEMP 0x00000100
| On Chip Temperature Channel. More...
#define | XADCPS_SEQ_CH_VCCINT 0x00000200
| VCCINT Channel. More...
#define | XADCPS_SEQ_CH_VCCAUX 0x00000400
| VCCAUX Channel. More...
#define | XADCPS_SEQ_CH_VPVN 0x00000800
| VP/VN analog inputs Channel. More...
#define | XADCPS_SEQ_CH_VREFP 0x00001000
| VREFP Channel. More...
#define | XADCPS_SEQ_CH_VREFN 0x00002000
| VREFN Channel. More...
#define | XADCPS_SEQ_CH_VBRAM 0x00004000
| VBRAM Channel, 7 series. More...
#define | XADCPS_SEQ_CH_AUX00 0x00010000
| 1st Aux Channel More...
#define | XADCPS_SEQ_CH_AUX01 0x00020000
| 2nd Aux Channel More...
#define | XADCPS_SEQ_CH_AUX02 0x00040000
| 3rd Aux Channel More...
#define | XADCPS_SEQ_CH_AUX03 0x00080000
| 4th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX04 0x00100000
| 5th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX05 0x00200000
| 6th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX06 0x00400000
| 7th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX07 0x00800000
| 8th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX08 0x01000000
| 9th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX09 0x02000000
| 10th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX10 0x04000000
| 11th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX11 0x08000000
| 12th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX12 0x10000000
| 13th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX13 0x20000000
| 14th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX14 0x40000000
| 15th Aux Channel More...
#define | XADCPS_SEQ_CH_AUX15 0x80000000
| 16th Aux Channel More...
#define | XADCPS_SEQ00_CH_VALID_MASK 0x7FE1
| Mask for the valid channels. More...
#define | XADCPS_SEQ01_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XADCPS_SEQ02_CH_VALID_MASK 0x7FE0
| Mask for the valid channels. More...
#define | XADCPS_SEQ03_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XADCPS_SEQ04_CH_VALID_MASK 0x0800
| Mask for the valid channels. More...
#define | XADCPS_SEQ05_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XADCPS_SEQ06_CH_VALID_MASK 0x0800
| Mask for the valid channels. More...
#define | XADCPS_SEQ07_CH_VALID_MASK 0xFFFF
| Mask for the valid channels. More...
#define | XADCPS_SEQ_CH_AUX_SHIFT 16
| Shift for the Aux Channel. More...
OT Upper Alarm Threshold Register Bit Definitions
#define | XADCPS_ATR_OT_UPPER_ENB_MASK 0x000F
| Mask for OT enable. More...
#define | XADCPS_ATR_OT_UPPER_VAL_MASK 0xFFF0
| Mask for OT value. More...
#define | XADCPS_ATR_OT_UPPER_VAL_SHIFT 4
| Shift for OT value. More...
#define | XADCPS_ATR_OT_UPPER_ENB_VAL 0x0003
| Value for OT enable. More...
#define | XADCPS_ATR_OT_UPPER_VAL_MAX 0x0FFF
| Max OT value. More...
JTAG DRP Bit Definitions
#define | XADCPS_JTAG_DATA_MASK 0x0000FFFF
| Mask for the Data. More...
#define | XADCPS_JTAG_ADDR_MASK 0x03FF0000
| Mask for the Addr. More...
#define | XADCPS_JTAG_ADDR_SHIFT 16
| Shift for the Addr. More...
#define | XADCPS_JTAG_CMD_MASK 0x3C000000
| Mask for the Cmd. More...
#define | XADCPS_JTAG_CMD_WRITE_MASK 0x08000000
| Mask for CMD Write. More...
#define | XADCPS_JTAG_CMD_READ_MASK 0x04000000
| Mask for CMD Read. More...
#define | XADCPS_JTAG_CMD_SHIFT 26
| Shift for the Cmd. More...
Unlock Register Definitions
#define | XADCPS_UNLK_OFFSET 0x034
| Unlock Register. More...
#define | XADCPS_UNLK_VALUE 0x757BDF0D
| Unlock Value. More...