v_hdmiphy1: xhdmiphy1_hw.h File Reference

| v_hdmiphy1 Xilinx SDK Drivers API Documentation

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xhdmiphy1_hw.h File Reference

## Overview

This header file contains the identifiers and low-level driver functions (or macros) that can be used to access the device.

High-level driver functions are defined in xhdmiphy1.h.

Note
  None.

    MODIFICATION HISTORY:

    Ver   Who  Date     Changes

               dd/mm/yy

    1.0   gm   10/12/18 Initial release.

## Macros
#define | XHdmiphy1_ReadReg(BaseAddress, RegOffset) XHdmiphy1_In32((BaseAddress) + (RegOffset))
| This is a low-level function that reads from the specified register. More...
#define | XHdmiphy1_WriteReg(BaseAddress, RegOffset, Data) XHdmiphy1_Out32((BaseAddress) + (RegOffset), (Data))
| This is a low-level function that writes to the specified register. More...
HDMIPHY core registers: General registers.
Address mapping for the Video PHY core.
#define | XHDMIPHY1_VERSION_REG 0x000
#define | XHDMIPHY1_BANK_SELECT_REG 0x00C
#define | XHDMIPHY1_REF_CLK_SEL_REG 0x010
#define | XHDMIPHY1_PLL_RESET_REG 0x014
#define | XHDMIPHY1_COMMON_INIT_REG 0x014
#define | XHDMIPHY1_PLL_LOCK_STATUS_REG 0x018
#define | XHDMIPHY1_TX_INIT_REG 0x01C
#define | XHDMIPHY1_TX_INIT_STATUS_REG 0x020
#define | XHDMIPHY1_RX_INIT_REG 0x024
#define | XHDMIPHY1_RX_INIT_STATUS_REG 0x028
#define | XHDMIPHY1_IBUFDS_GTXX_CTRL_REG 0x02C
#define | XHDMIPHY1_POWERDOWN_CONTROL_REG 0x030
#define | XHDMIPHY1_LOOPBACK_CONTROL_REG 0x038
HDMIPHY core registers: Dynamic reconfiguration port (DRP) registers.
#define | XHDMIPHY1_DRP_CONTROL_CH1_REG 0x040
#define | XHDMIPHY1_DRP_CONTROL_CH2_REG 0x044
#define | XHDMIPHY1_DRP_CONTROL_CH3_REG 0x048
#define | XHDMIPHY1_DRP_CONTROL_CH4_REG 0x04C
#define | XHDMIPHY1_DRP_STATUS_CH1_REG 0x050
#define | XHDMIPHY1_DRP_STATUS_CH2_REG 0x054
#define | XHDMIPHY1_DRP_STATUS_CH3_REG 0x058
#define | XHDMIPHY1_DRP_STATUS_CH4_REG 0x05C
#define | XHDMIPHY1_DRP_CONTROL_COMMON_REG 0x060
#define | XHDMIPHY1_DRP_STATUS_COMMON_REG 0x064
#define | XHDMIPHY1_DRP_CONTROL_TXMMCM_REG 0x124
#define | XHDMIPHY1_DRP_STATUS_TXMMCM_REG 0x128
#define | XHDMIPHY1_DRP_CONTROL_RXMMCM_REG 0x144
#define | XHDMIPHY1_DRP_STATUS_RXMMCM_REG 0x148
HDMIPHY core registers: CPLL Calibration registers.
#define | XHDMIPHY1_CPLL_CAL_PERIOD_REG 0x068
#define | XHDMIPHY1_CPLL_CAL_TOL_REG 0x06C
HDMIPHY core registers: GT Debug INTF registers.
#define | XHDMIPHY1_GT_DBG_GPI_REG 0x068
#define | XHDMIPHY1_GT_DBG_GPO_REG 0x06C
HDMIPHY core registers: Transmitter function registers.
#define | XHDMIPHY1_TX_CONTROL_REG 0x070
#define | XHDMIPHY1_TX_BUFFER_BYPASS_REG 0x074
#define | XHDMIPHY1_TX_STATUS_REG 0x078
#define | XHDMIPHY1_TX_DRIVER_CH12_REG 0x07C
#define | XHDMIPHY1_TX_DRIVER_CH34_REG 0x080
#define | XHDMIPHY1_TX_DRIVER_EXT_REG 0x084
#define | XHDMIPHY1_TX_RATE_CH12_REG 0x08C
#define | XHDMIPHY1_TX_RATE_CH34_REG 0x090
HDMIPHY core registers: Receiver function registers.
#define | XHDMIPHY1_RX_RATE_CH12_REG 0x98
#define | XHDMIPHY1_RX_RATE_CH34_REG 0x9C
#define | XHDMIPHY1_RX_CONTROL_REG 0x100
#define | XHDMIPHY1_RX_STATUS_REG 0x104
#define | XHDMIPHY1_RX_EQ_CDR_REG 0x108
#define | XHDMIPHY1_RX_TDLOCK_REG 0x10C
HDMIPHY core registers: Interrupt registers.
#define | XHDMIPHY1_INTR_EN_REG 0x110
#define | XHDMIPHY1_INTR_DIS_REG 0x114
#define | XHDMIPHY1_INTR_MASK_REG 0x118
#define | XHDMIPHY1_INTR_STS_REG 0x11C
User clocking registers: MMCM and BUFGGT registers.
#define | XHDMIPHY1_MMCM_TXUSRCLK_CTRL_REG 0x0120
#define | XHDMIPHY1_MMCM_TXUSRCLK_REG1 0x0124
#define | XHDMIPHY1_MMCM_TXUSRCLK_REG2 0x0128
#define | XHDMIPHY1_MMCM_TXUSRCLK_REG3 0x012C
#define | XHDMIPHY1_MMCM_TXUSRCLK_REG4 0x0130
#define | XHDMIPHY1_BUFGGT_TXUSRCLK_REG 0x0134
#define | XHDMIPHY1_MISC_TXUSRCLK_REG 0x0138
#define | XHDMIPHY1_MMCM_RXUSRCLK_CTRL_REG 0x0140
#define | XHDMIPHY1_MMCM_RXUSRCLK_REG1 0x0144
#define | XHDMIPHY1_MMCM_RXUSRCLK_REG2 0x0148
#define | XHDMIPHY1_MMCM_RXUSRCLK_REG3 0x014C
#define | XHDMIPHY1_MMCM_RXUSRCLK_REG4 0x0150
#define | XHDMIPHY1_BUFGGT_RXUSRCLK_REG 0x0154
#define | XHDMIPHY1_MISC_RXUSRCLK_REG 0x0158
Clock detector (HDMI) registers.
#define | XHDMIPHY1_CLKDET_CTRL_REG 0x0200
#define | XHDMIPHY1_CLKDET_STAT_REG 0x0204
#define | XHDMIPHY1_CLKDET_FREQ_TMR_TO_REG 0x0208
#define | XHDMIPHY1_CLKDET_FREQ_TX_REG 0x020C
#define | XHDMIPHY1_CLKDET_FREQ_RX_REG 0x0210
#define | XHDMIPHY1_CLKDET_TMR_TX_REG 0x0214
#define | XHDMIPHY1_CLKDET_TMR_RX_REG 0x0218
#define | XHDMIPHY1_CLKDET_FREQ_DRU_REG 0x021C
Data recovery unit registers (HDMI).
#define | XHDMIPHY1_DRU_CTRL_REG 0x0300
#define | XHDMIPHY1_DRU_STAT_REG 0x0304
#define | XHDMIPHY1_DRU_CFREQ_L_REG(Ch) (0x0308 + (12 * (Ch - 1)))
#define | XHDMIPHY1_DRU_CFREQ_H_REG(Ch) (0x030C + (12 * (Ch - 1)))
#define | XHDMIPHY1_DRU_GAIN_REG(Ch) (0x0310 + (12 * (Ch - 1)))
TMDS Clock Pattern Generator registers (HDMI).
#define | XHDMIPHY1_PATGEN_CTRL_REG 0x0340
HDMIPHY core masks, shifts, and register values.
#define | XHDMIPHY1_VERSION_INTER_REV_MASK 0x000000FF
| Internal revision. More...
#define | XHDMIPHY1_VERSION_CORE_PATCH_MASK 0x00000F00
| Core patch details. More...
#define | XHDMIPHY1_VERSION_CORE_PATCH_SHIFT 8
| Shift bits for core patch details. More...
#define | XHDMIPHY1_VERSION_CORE_VER_REV_MASK 0x0000F000
| Core version revision. More...
#define | XHDMIPHY1_VERSION_CORE_VER_REV_SHIFT 12
| Shift bits for core version revision. More...
#define | XHDMIPHY1_VERSION_CORE_VER_MNR_MASK 0x00FF0000
| Core minor version. More...
#define | XHDMIPHY1_VERSION_CORE_VER_MNR_SHIFT 16
| Shift bits for core minor version. More...
#define | XHDMIPHY1_VERSION_CORE_VER_MJR_MASK 0xFF000000
| Core major version. More...
#define | XHDMIPHY1_VERSION_CORE_VER_MJR_SHIFT 24
| Shift bits for core major version. More...
#define | XHDMIPHY1_BANK_SELECT_TX_MASK 0x00F
#define | XHDMIPHY1_BANK_SELECT_RX_MASK 0xF00
#define | XHDMIPHY1_BANK_SELECT_RX_SHIFT 8
#define | XHDMIPHY1_REF_CLK_SEL_QPLL0_MASK 0x0000000F
#define | XHDMIPHY1_REF_CLK_SEL_CPLL_MASK 0x000000F0
#define | XHDMIPHY1_REF_CLK_SEL_CPLL_SHIFT 4
#define | XHDMIPHY1_REF_CLK_SEL_QPLL1_MASK 0x00000F00
#define | XHDMIPHY1_REF_CLK_SEL_QPLL1_SHIFT 8
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTREFCLK0 1
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTREFCLK1 2
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTNORTHREFCLK0 3
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTNORTHREFCLK1 4
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTSOUTHREFCLK0 5
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTSOUTHREFCLK1 6
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTEASTREFCLK0 3
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTEASTREFCLK1 4
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTWESTREFCLK0 5
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTWESTREFCLK1 6
#define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTGREFCLK 7
#define | XHDMIPHY1_REF_CLK_SEL_SYSCLKSEL_MASK 0x0F000000
#define | XHDMIPHY1_REF_CLK_SEL_SYSCLKSEL_SHIFT 24
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL0 0
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL1 1
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_CPLL 0
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL 1
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL0 3
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL1 2
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_OUT_CH 0
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN 1
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN0 2
#define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN1 3
#define | XHDMIPHY1_REF_CLK_SEL_RXSYSCLKSEL_OUT_MASK(G)
#define | XHDMIPHY1_REF_CLK_SEL_TXSYSCLKSEL_OUT_MASK(G)
#define | XHDMIPHY1_REF_CLK_SEL_RXSYSCLKSEL_DATA_MASK(G)
#define | XHDMIPHY1_REF_CLK_SEL_TXSYSCLKSEL_DATA_MASK(G)
#define | XHDMIPHY1_REF_CLK_SEL_RXSYSCLKSEL_OUT_SHIFT(G)
#define | XHDMIPHY1_REF_CLK_SEL_TXSYSCLKSEL_OUT_SHIFT(G)
#define | XHDMIPHY1_REF_CLK_SEL_RXSYSCLKSEL_DATA_SHIFT(G)
#define | XHDMIPHY1_REF_CLK_SEL_TXSYSCLKSEL_DATA_SHIFT(G)
#define | XHDMIPHY1_PLL_RESET_CPLL_MASK 0x1
#define | XHDMIPHY1_PLL_RESET_QPLL0_MASK 0x2
#define | XHDMIPHY1_PLL_RESET_QPLL1_MASK 0x4
#define | XHDMIPHY1_GTWIZ_RESET_ALL_MASK 0x1
#define | XHDMIPHY1_PCIERST_ALL_CH_MASK 0x2
#define | XHDMIPHY1_PLL_LOCK_STATUS_CPLL_MASK(Ch) (0x01 << (Ch - 1))
#define | XHDMIPHY1_PLL_LOCK_STATUS_QPLL0_MASK 0x10
#define | XHDMIPHY1_PLL_LOCK_STATUS_QPLL1_MASK 0x20
#define | XHDMIPHY1_PLL_LOCK_STATUS_CPLL_ALL_MASK
#define | XHDMIPHY1_PLL_LOCK_STATUS_CPLL_HDMI_MASK
#define | XHDMIPHY1_PLL_LOCK_STATUS_RPLL_MASK 0xC0
#define | XHDMIPHY1_PLL_LOCK_STATUS_LCPLL_MASK 0x300
#define | XHDMIPHY1_TXRX_INIT_GTRESET_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TXRX_INIT_PMARESET_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TXRX_INIT_PCSRESET_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_INIT_USERRDY_MASK(Ch) (0x08 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TXRX_LNKRDY_SB_MASK(Ch) (0x10 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TXRX_MSTRESET_MASK(Ch) (0x20 << (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_INIT_USERRDY_MASK(Ch) (0x40 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TXRX_INIT_PLLGTRESET_MASK(Ch) (0x80 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TXRX_INIT_GTRESET_ALL_MASK
#define | XHDMIPHY1_TXRX_LNKRDY_SB_ALL_MASK
#define | XHDMIPHY1_TXRX_MSTRESET_ALL_MASK
#define | XHDMIPHY1_TX_INIT_USERRDY_ALL_MASK
#define | XHDMIPHY1_RX_INIT_USERRDY_ALL_MASK
#define | XHDMIPHY1_TXRX_INIT_PLLGTRESET_ALL_MASK
#define | XHDMIPHY1_TXRX_INIT_STATUS_RESETDONE_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TXRX_INIT_STATUS_PMARESETDONE_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TXRX_INIT_STATUS_POWERGOOD_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TXRX_INIT_STATUS_RESETDONE_ALL_MASK
#define | XHDMIPHY1_TXRX_INIT_STATUS_PMARESETDONE_ALL_MASK
#define | XHDMIPHY1_IBUFDS_GTXX_CTRL_GTREFCLK0_CEB_MASK 0x1
#define | XHDMIPHY1_IBUFDS_GTXX_CTRL_GTREFCLK1_CEB_MASK 0x2
#define | XHDMIPHY1_POWERDOWN_CONTROL_CPLLPD_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XHDMIPHY1_POWERDOWN_CONTROL_QPLL0PD_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XHDMIPHY1_POWERDOWN_CONTROL_QPLL1PD_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XHDMIPHY1_POWERDOWN_CONTROL_RXPD_MASK(Ch) (0x18 << (8 * (Ch - 1)))
#define | XHDMIPHY1_POWERDOWN_CONTROL_RXPD_SHIFT(Ch) (3 + (8 * (Ch - 1)))
#define | XHDMIPHY1_POWERDOWN_CONTROL_TXPD_MASK(Ch) (0x60 << (8 * (Ch - 1)))
#define | XHDMIPHY1_POWERDOWN_CONTROL_TXPD_SHIFT(Ch) (5 + (8 * (Ch - 1)))
#define | XHDMIPHY1_LOOPBACK_CONTROL_CH_MASK(Ch) (0x03 << (8 * (Ch - 1)))
#define | XHDMIPHY1_LOOPBACK_CONTROL_CH_SHIFT(Ch) (8 * (Ch - 1))
#define | XHDMIPHY1_DRP_CONTROL_DRPADDR_MASK 0x00000FFF
#define | XHDMIPHY1_DRP_CONTROL_DRPEN_MASK 0x00001000
#define | XHDMIPHY1_DRP_CONTROL_DRPWE_MASK 0x00002000
#define | XHDMIPHY1_DRP_CONTROL_DRPRESET_MASK 0x00004000
#define | XHDMIPHY1_DRP_CONTROL_DRPDI_MASK 0xFFFF0000
#define | XHDMIPHY1_DRP_CONTROL_DRPDI_SHIFT 16
#define | XHDMIPHY1_DRP_STATUS_DRPO_MASK 0x0FFFF
#define | XHDMIPHY1_DRP_STATUS_DRPRDY_MASK 0x10000
#define | XHDMIPHY1_DRP_STATUS_DRPBUSY_MASK 0x20000
#define | XHDMIPHY1_CPLL_CAL_PERIOD_MASK 0x3FFFF
#define | XHDMIPHY1_CPLL_CAL_TOL_MASK 0x3FFFF
#define | XHDMIPHY1_TX_GPI_MASK(Ch) (0x01 << (Ch - 1))
#define | XHDMIPHY1_RX_GPI_MASK(Ch) (0x10 << (Ch - 1))
#define | XHDMIPHY1_TX_GPO_MASK(Ch) (0x01 << (Ch - 1))
#define | XHDMIPHY1_RX_GPO_MASK(Ch) (0x10 << (Ch - 1))
#define | XHDMIPHY1_TX_CONTROL_TX8B10BEN_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_CONTROL_TX8B10BEN_ALL_MASK
#define | XHDMIPHY1_TX_CONTROL_TXPOLARITY_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_CONTROL_TXPOLARITY_ALL_MASK
#define | XHDMIPHY1_TX_CONTROL_TXPRBSSEL_MASK(Ch) (0x5C << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_CONTROL_TXPRBSSEL_ALL_MASK
#define | XHDMIPHY1_TX_CONTROL_TXPRBSSEL_SHIFT(Ch) (2 + (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_CONTROL_TXPRBSFORCEERR_MASK(Ch) (0x20 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_CONTROL_TXPRBSFORCEERR_ALL_MASK
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHDLYRESET_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHALIGN_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHALIGNEN_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHDLYPD_MASK(Ch) (0x08 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHINIT_MASK(Ch) (0x10 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXDLYRESET_MASK(Ch) (0x20 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXDLYBYPASS_MASK(Ch) (0x40 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_BUFFER_BYPASS_TXDLYEN_MASK(Ch) (0x80 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_STATUS_TXPHALIGNDONE_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_STATUS_TXPHINITDONE_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_STATUS_TXDLYRESETDONE_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_STATUS_TXBUFSTATUS_MASK(Ch) (0x18 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_STATUS_TXBUFSTATUS_SHIFT(Ch) (3 + (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_DRIVER_TXDIFFCTRL_MASK(Ch) (0x000F << (16 * ((Ch - 1) % 2)))
#define | XHDMIPHY1_TX_DRIVER_TXDIFFCTRL_SHIFT(Ch) (16 * ((Ch - 1) % 2))
#define | XHDMIPHY1_TX_DRIVER_TXELECIDLE_MASK(Ch) (0x0010 << (16 * ((Ch - 1) % 2)))
#define | XHDMIPHY1_TX_DRIVER_TXELECIDLE_SHIFT(Ch) (4 + (16 * ((Ch - 1) % 2)))
#define | XHDMIPHY1_TX_DRIVER_TXINHIBIT_MASK(Ch) (0x0020 << (16 * ((Ch - 1) % 2)))
#define | XHDMIPHY1_TX_DRIVER_TXINHIBIT_SHIFT(Ch) (5 + (16 * ((Ch - 1) % 2)))
#define | XHDMIPHY1_TX_DRIVER_TXPOSTCURSOR_MASK(Ch) (0x07C0 << (16 * ((Ch - 1) % 2)))
#define | XHDMIPHY1_TX_DRIVER_TXPOSTCURSOR_SHIFT(Ch) (6 + (16 * ((Ch - 1) % 2)))
#define | XHDMIPHY1_TX_DRIVER_TXPRECURSOR_MASK(Ch) (0xF800 << (16 * ((Ch - 1) % 2)))
#define | XHDMIPHY1_TX_DRIVER_TXPRECURSOR_SHIFT(Ch) (11 + (16 * ((Ch - 1) % 2)))
#define | XHDMIPHY1_TX_DRIVER_EXT_TXDIFFCTRL_MASK(Ch) (0x0001 << (8 * (Ch - 1)))
#define | XHDMIPHY1_TX_DRIVER_EXT_TXDIFFCTRL_SHIFT(Ch) (8 * (Ch - 1))
#define | XHDMIPHY1_TX_RATE_MASK(Ch) (0x00FF << (16 * ((Ch - 1) % 2)))
#define | XHDMIPHY1_TX_RATE_SHIFT(Ch) (16 * ((Ch - 1) % 2))
#define | XHDMIPHY1_RX_RATE_MASK(Ch) (0x00FF << (16 * ((Ch - 1) % 2)))
#define | XHDMIPHY1_RX_RATE_SHIFT(Ch) (16 * ((Ch - 1) % 2))
#define | XHDMIPHY1_RX_CONTROL_RX8B10BEN_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_CONTROL_RX8B10BEN_ALL_MASK
#define | XHDMIPHY1_RX_CONTROL_RXPOLARITY_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_CONTROL_RXPOLARITY_ALL_MASK
#define | XHDMIPHY1_RX_CONTROL_RXPRBSCNTRESET_MASK(Ch) (0x08 << (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_CONTROL_RXPRBSSEL_MASK(Ch) (0xF0 << (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_CONTROL_RXPRBSSEL_ALL_MASK
#define | XHDMIPHY1_RX_CONTROL_RXPRBSSEL_SHIFT(Ch) (4 + (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_STATUS_RXCDRLOCK_MASK(Ch) (0x1 << (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_STATUS_RXBUFSTATUS_MASK(Ch) (0xE << (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_STATUS_RXBUFSTATUS_SHIFT(Ch) (1 + (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_CONTROL_RXLPMEN_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_STATUS_RXCDRHOLD_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_STATUS_RXOSOVRDEN_MASK(Ch) (0x04 << (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_STATUS_RXLPMLFKLOVRDEN_MASK(Ch) (0x08 << (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_STATUS_RXLPMHFOVRDEN_MASK(Ch) (0x10 << (8 * (Ch - 1)))
#define | XHDMIPHY1_RX_CONTROL_RXLPMEN_ALL_MASK
#define | XHDMIPHY1_INTR_TXRESETDONE_MASK 0x00000001
#define | XHDMIPHY1_INTR_RXRESETDONE_MASK 0x00000002
#define | XHDMIPHY1_INTR_CPLL_LOCK_MASK 0x00000004
#define | XHDMIPHY1_INTR_QPLL0_LOCK_MASK 0x00000008
#define | XHDMIPHY1_INTR_LCPLL_LOCK_MASK 0x00000008
#define | XHDMIPHY1_INTR_TXALIGNDONE_MASK 0x00000010
#define | XHDMIPHY1_INTR_QPLL1_LOCK_MASK 0x00000020
#define | XHDMIPHY1_INTR_RPLL_LOCK_MASK 0x00000020
#define | XHDMIPHY1_INTR_TXCLKDETFREQCHANGE_MASK 0x00000040
#define | XHDMIPHY1_INTR_RXCLKDETFREQCHANGE_MASK 0x00000080
#define | XHDMIPHY1_INTR_TXMMCMUSRCLK_LOCK_MASK 0x00000200
#define | XHDMIPHY1_INTR_RXMMCMUSRCLK_LOCK_MASK 0x00000400
#define | XHDMIPHY1_INTR_TXGPO_RE_MASK 0x00000800
#define | XHDMIPHY1_INTR_RXGPO_RE_MASK 0x00001000
#define | XHDMIPHY1_INTR_TXTMRTIMEOUT_MASK 0x40000000
#define | XHDMIPHY1_INTR_RXTMRTIMEOUT_MASK 0x80000000
#define | XHDMIPHY1_INTR_QPLL_LOCK_MASK XHDMIPHY1_INTR_QPLL0_LOCK_MASK
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_CFG_NEW_MASK 0x01
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_RST_MASK 0x02
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_CFG_SUCCESS_MASK 0x10
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_LOCKED_MASK 0x200
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_PWRDWN_MASK 0x400
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_LOCKED_MASK_MASK 0x800
#define | XHDMIPHY1_MMCM_USRCLK_CTRL_CLKINSEL_MASK 0x1000
#define | XHDMIPHY1_MMCM_USRCLK_REG1_DIVCLK_MASK 0x00000FF
#define | XHDMIPHY1_MMCM_USRCLK_REG1_CLKFBOUT_MULT_MASK 0x000FF00
#define | XHDMIPHY1_MMCM_USRCLK_REG1_CLKFBOUT_MULT_SHIFT 8
#define | XHDMIPHY1_MMCM_USRCLK_REG1_CLKFBOUT_FRAC_MASK 0x3FF0000
#define | XHDMIPHY1_MMCM_USRCLK_REG1_CLKFBOUT_FRAC_SHIFT 16
#define | XHDMIPHY1_MMCM_USRCLK_REG2_DIVCLK_MASK 0x00000FF
#define | XHDMIPHY1_MMCM_USRCLK_REG2_CLKOUT0_FRAC_MASK 0x3FF0000
#define | XHDMIPHY1_MMCM_USRCLK_REG2_CLKOUT0_FRAC_SHIFT 16
#define | XHDMIPHY1_MMCM_USRCLK_REG34_DIVCLK_MASK 0x00000FF
#define | XHDMIPHY1_BUFGGT_XXUSRCLK_CLR_MASK 0x1
#define | XHDMIPHY1_BUFGGT_XXUSRCLK_DIV_MASK 0xE
#define | XHDMIPHY1_BUFGGT_XXUSRCLK_DIV_SHIFT 1
#define | XHDMIPHY1_MISC_XXUSRCLK_CKOUT1_OEN_MASK 0x1
#define | XHDMIPHY1_MISC_XXUSRCLK_REFCLK_CEB_MASK 0x2
#define | XHDMIPHY1_CLKDET_CTRL_RUN_MASK 0x1
#define | XHDMIPHY1_CLKDET_CTRL_TX_TMR_CLR_MASK 0x2
#define | XHDMIPHY1_CLKDET_CTRL_RX_TMR_CLR_MASK 0x4
#define | XHDMIPHY1_CLKDET_CTRL_TX_FREQ_RST_MASK 0x8
#define | XHDMIPHY1_CLKDET_CTRL_RX_FREQ_RST_MASK 0x10
#define | XHDMIPHY1_CLKDET_CTRL_FREQ_LOCK_THRESH_MASK 0x1FE0
#define | XHDMIPHY1_CLKDET_CTRL_FREQ_LOCK_THRESH_SHIFT 5
#define | XHDMIPHY1_CLKDET_STAT_TX_FREQ_ZERO_MASK 0x1
#define | XHDMIPHY1_CLKDET_STAT_RX_FREQ_ZERO_MASK 0x2
#define | XHDMIPHY1_CLKDET_STAT_TX_REFCLK_LOCK_MASK 0x3
#define | XHDMIPHY1_CLKDET_STAT_TX_REFCLK_LOCK_CAP_MASK 0x4
#define | XHDMIPHY1_DRU_CTRL_RST_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XHDMIPHY1_DRU_CTRL_EN_MASK(Ch) (0x02 << (8 * (Ch - 1)))
#define | XHDMIPHY1_DRU_STAT_ACTIVE_MASK(Ch) (0x01 << (8 * (Ch - 1)))
#define | XHDMIPHY1_DRU_STAT_VERSION_MASK 0xFF000000
#define | XHDMIPHY1_DRU_STAT_VERSION_SHIFT 24
#define | XHDMIPHY1_DRU_CFREQ_H_MASK 0x1F
#define | XHDMIPHY1_DRU_GAIN_G1_MASK 0x00001F
#define | XHDMIPHY1_DRU_GAIN_G1_SHIFT 0
#define | XHDMIPHY1_DRU_GAIN_G1_P_MASK 0x001F00
#define | XHDMIPHY1_DRU_GAIN_G1_P_SHIFT 8
#define | XHDMIPHY1_DRU_GAIN_G2_MASK 0x1F0000
#define | XHDMIPHY1_DRU_GAIN_G2_SHIFT 16
#define | XHDMIPHY1_PATGEN_CTRL_ENABLE_MASK 0x80000000
#define | XHDMIPHY1_PATGEN_CTRL_ENABLE_SHIFT 31
#define | XHDMIPHY1_PATGEN_CTRL_RATIO_MASK 0x7
#define | XHDMIPHY1_PATGEN_CTRL_RATIO_SHIFT 0
Register access macro definitions.
#define | XHdmiphy1_In32 Xil_In32
#define | XHdmiphy1_Out32 Xil_Out32