rfdc: Rfdc_v7_0

| rfdc Xilinx SDK Drivers API Documentation

- Overview
- Data Structures
- APIs
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Data Structures | Typedefs | Functions
Rfdc_v7_0

## Data Structures
struct | XRFdc_PLL_Settings
| PLL settings. More...
struct | XRFdc_Tile_Clock_Settings
| ClkIntraTile Settings. More...
struct | XRFdc_Distribution
| Clk Distribution. More...
struct | XRFdc_Distribution_Settings
| Clk Distribution Settings. More...
struct | XRFdc_Signal_Detector_Settings
| ADC Signal Detect Settings. More...
struct | XRFdc_QMC_Settings
| QMC settings. More...
struct | XRFdc_CoarseDelay_Settings
| Coarse delay settings. More...
struct | XRFdc_Mixer_Settings
| Mixer settings. More...
struct | XRFdc_Threshold_Settings
| ADC block Threshold settings. More...
struct | XRFdc_Calibration_Coefficients
| RFSoC Calibration coefficients generic struct. More...
struct | XRFdc_DSA_Settings
| RFSoC DSA settings. More...
struct | XRFdc_Cal_Freeze_Settings
| RFSoC Calibration freeze settings struct. More...
struct | XRFdc_TileStatus
| RFSoC Tile status. More...
struct | XRFdc_IPStatus
| RFSoC Data converter IP status. More...
struct | XRFdc_BlockStatus
| status of DAC or ADC blocks in the RFSoC Data converter. More...
struct | XRFdc_DACBlock_AnalogDataPath_Config
| DAC block Analog DataPath Config settings. More...
struct | XRFdc_DACBlock_DigitalDataPath_Config
| DAC block Digital DataPath Config settings. More...
struct | XRFdc_ADCBlock_AnalogDataPath_Config
| ADC block Analog DataPath Config settings. More...
struct | XRFdc_ADCBlock_DigitalDataPath_Config
| DAC block Digital DataPath Config settings. More...
struct | XRFdc_DACTile_Config
| DAC Tile Config structure. More...
struct | XRFdc_ADCTile_Config
| ADC Tile Config Structure. More...
struct | XRFdc_Config
| RFdc Config Structure. More...
struct | XRFdc_DACBlock_AnalogDataPath
| DAC Block Analog DataPath Structure. More...
struct | XRFdc_DACBlock_DigitalDataPath
| DAC Block Digital DataPath Structure. More...
struct | XRFdc_ADCBlock_AnalogDataPath
| ADC Block Analog DataPath Structure. More...
struct | XRFdc_ADCBlock_DigitalDataPath
| ADC Block Digital DataPath Structure. More...
struct | XRFdc_DAC_Tile
| DAC Tile Structure. More...
struct | XRFdc_ADC_Tile
| ADC Tile Structure. More...
struct | XRFdc
| RFdc Structure. More...

## Typedefs
typedef void(* | XRFdc_StatusHandler )(void *CallBackRef, u32 Type, u32 Tile_Id, u32 Block_Id, u32 StatusEvent)
| The handler data type allows the user to define a callback function to respond to interrupt events in the system. More...

## Functions
XRFdc_Config * | XRFdc_LookupConfig (u16 DeviceId)
| Looks up the device configuration based on the unique device ID. More...
u32 | XRFdc_RegisterMetal (XRFdc *InstancePtr, u16 DeviceId, struct metal_device **DevicePtr)
| Register/open the deviceand map RFDC to the IO region. More...
u32 | XRFdc_CfgInitialize (XRFdc *InstancePtr, XRFdc_Config *ConfigPtr)
| Initializes a specific XRFdc instance such that the driver is ready to use. More...
u32 | XRFdc_StartUp (XRFdc *InstancePtr, u32 Type, int Tile_Id)
| The API Restarts the requested tile. More...
u32 | XRFdc_Shutdown (XRFdc *InstancePtr, u32 Type, int Tile_Id)
| The API stops the tile as requested. More...
u32 | XRFdc_Reset (XRFdc *InstancePtr, u32 Type, int Tile_Id)
| The API resets the requested tile. More...
u32 | XRFdc_GetIPStatus (XRFdc *InstancePtr, XRFdc_IPStatus *IPStatusPtr)
| The API returns the IP status. More...
u32 | XRFdc_GetBlockStatus (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_BlockStatus *BlockStatusPtr)
| The API returns the requested block status. More...
u32 | XRFdc_SetMixerSettings (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_Mixer_Settings *MixerSettingsPtr)
| The API is used to update various mixer settings, fine, coarse, NCO etc. More...
u32 | XRFdc_GetMixerSettings (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_Mixer_Settings *MixerSettingsPtr)
| The API returns back Mixer/NCO settings to the caller. More...
u32 | XRFdc_SetQMCSettings (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_QMC_Settings *QMCSettingsPtr)
| This API is used to update various QMC settings, eg gain, phase, offset etc. More...
u32 | XRFdc_GetQMCSettings (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_QMC_Settings *QMCSettingsPtr)
| QMC settings are returned back to the caller through this API. More...
u32 | XRFdc_GetCoarseDelaySettings (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr)
| Coarse delay settings are returned back to the caller. More...
u32 | XRFdc_SetCoarseDelaySettings (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr)
| Coarse delay settings passed are used to update the corresponding block level registers. More...
u32 | XRFdc_GetInterpolationFactor (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *InterpolationFactorPtr)
| Interpolation factor are returned back to the caller. More...
u32 | XRFdc_GetDecimationFactor (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *DecimationFactorPtr)
| Decimation factor are returned back to the caller. More...
u32 | XRFdc_GetFabWrVldWords (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *FabricDataRatePtr)
| This API returns the the number of fabric write valid words requested for the block. More...
u32 | XRFdc_GetFabRdVldWords (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *FabricDataRatePtr)
| This API returns the the number of fabric read valid words requested for the block. More...
u32 | XRFdc_SetFabRdVldWords (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 FabricRdVldWords)
| Fabric data rate for the requested ADC block is set by writing to the corresponding register. More...
u32 | XRFdc_SetFabWrVldWords (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 FabricWrVldWords)
| Fabric data rate for the requested DAC block is set by writing to the corresponding register. More...
u32 | XRFdc_GetThresholdSettings (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Threshold_Settings *ThresholdSettingsPtr)
| Threshold settings are read from the corresponding registers and are passed back to the caller. More...
u32 | XRFdc_SetThresholdSettings (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Threshold_Settings *ThresholdSettingsPtr)
| Threshold settings are updated into the relevant registers. More...
u32 | XRFdc_SetDecoderMode (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 DecoderMode)
| Decoder mode is updated into the relevant registers. More...
u32 | XRFdc_UpdateEvent (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 Event)
| This function will trigger the update event for an event. More...
u32 | XRFdc_GetDecoderMode (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *DecoderModePtr)
| Decoder mode is read and returned back. More...
u32 | XRFdc_ResetNCOPhase (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id)
| Resets the NCO phase of the current block phase accumulator. More...
void | XRFdc_DumpRegs (XRFdc *InstancePtr, u32 Type, int Tile_Id)
| This Prints the offset of the register along with the content. More...
u32 | XRFdc_MultiBand (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 DigitalDataPathMask, u32 MixerInOutDataType, u32 DataConverterMask)
| User-level API to setup multiband configuration. More...
u32 | XRFdc_IntrHandler (u32 Vector, void *XRFdcPtr)
| This function is the interrupt handler for the driver. More...
u32 | XRFdc_IntrClr (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask)
| This function clear the interrupts. More...
u32 | XRFdc_GetIntrStatus (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *IntrStsPtr)
| This function returns the interrupt status read from Interrupt Status Register(ISR). More...
u32 | XRFdc_IntrDisable (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask)
| This function clears the interrupt mask. More...
u32 | XRFdc_IntrEnable (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask)
| This function sets the interrupt mask. More...
u32 | XRFdc_GetEnabledInterrupts (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *IntrMask)
| This function gets a mask of enabled interrupts. More...
u32 | XRFdc_SetThresholdClrMode (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 ThresholdToUpdate, u32 ClrMode)
| This API sets the threshold clear mode. More...
u32 | XRFdc_ThresholdStickyClear (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 ThresholdToUpdate)
| This API is to clear the Sticky bit in threshold config registers. More...
void | XRFdc_SetStatusHandler (XRFdc *InstancePtr, void *CallBackRef, XRFdc_StatusHandler FunctionPtr)
| This function sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software. More...
u32 | XRFdc_SetupFIFO (XRFdc *InstancePtr, u32 Type, int Tile_Id, u8 Enable)
| Enable and Disable the ADC/DAC FIFO. More...
u32 | XRFdc_GetFIFOStatus (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 *EnablePtr)
| Current status of ADC/DAC FIFO. More...
u32 | XRFdc_SetNyquistZone (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 NyquistZone)
| Set the Nyquist zone. More...
u32 | XRFdc_GetNyquistZone (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *NyquistZonePtr)
| Get the Nyquist zone. More...
u32 | XRFdc_GetOutputCurr (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *OutputCurrPtr)
| Get Output Current for DAC block. More...
u32 | XRFdc_SetDecimationFactor (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 DecimationFactor)
| This API is to set the decimation factor and also update the FIFO write words w.r.t to decimation factor. More...
u32 | XRFdc_SetInterpolationFactor (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 InterpolationFactor)
| This API is to set the interpolation factor and also update the FIFO read words w.r.t to interpolation factor. More...
u32 | XRFdc_SetFabClkOutDiv (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u16 FabClkDiv)
| This API is to set the divider for clock fabric out. More...
u32 | XRFdc_SetCalibrationMode (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u8 CalibrationMode)
| This API is to set the Calibration mode. More...
u32 | XRFdc_GetCalibrationMode (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u8 *CalibrationModePtr)
| This API is to get the Calibration mode. More...
u32 | XRFdc_GetClockSource (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 *ClockSourcePtr)
| This function gets Clock source. More...
u32 | XRFdc_GetPLLLockStatus (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 *LockStatusPtr)
| This function gets PLL lock status. More...
u32 | XRFdc_GetPLLConfig (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, XRFdc_PLL_Settings *PLLSettings)
| This API is used to get the PLL Configurations. More...
u32 | XRFdc_DynamicPLLConfig (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 Source, double RefClkFreq, double SamplingRate)
| This function used for dynamically switch between internal PLL and external clcok source and configuring the internal PLL. More...
u32 | XRFdc_SetInvSincFIR (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u16 Mode)
| This API is used to set the mode for the Inverse-Sinc filter. More...
u32 | XRFdc_GetInvSincFIR (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u16 *ModePtr)
| This API is used to get the Inverse-Sinc filter mode. More...
u32 | XRFdc_GetLinkCoupling (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr)
| This function is used to get the Link Coupling mode. More...
u32 | XRFdc_GetFabClkOutDiv (XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u16 *FabClkDivPtr)
| This API is to get the divider for clock fabric out. More...
u32 | XRFdc_SetDither (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode)
| This function is used to set the IM3 Dither mode. More...
u32 | XRFdc_GetDither (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr)
| This function is used to get the IM3 Dither mode. More...
u32 | XRFdc_SetClkDistribution (XRFdc *InstancePtr, XRFdc_Distribution_Settings *DistributionSettingsPtr)
| This function is used to set the clock distribution. More...
u32 | XRFdc_GetClkDistribution (XRFdc *InstancePtr, XRFdc_Distribution_Settings *DistributionSettingsPtr)
| This function is used to get the clock distribution. More...
u32 | XRFdc_SetDataPathMode (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode)
| This API is to set the DAC Datapath mode. More...
u32 | XRFdc_GetDataPathMode (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr)
| This API is to get the DAC Datapath mode. More...
u32 | XRFdc_SetIMRPassMode (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode)
| This API is to set the DAC Image Reject Filter Pass mode. More...
u32 | XRFdc_GetIMRPassMode (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr)
| This API is to get the DAC Image Reject Filter Pass mode. More...
u32 | XRFdc_SetSignalDetector (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Signal_Detector_Settings *SettingsPtr)
| This function is used to set the ADC Signal Detector Settings. More...
u32 | XRFdc_GetSignalDetector (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Signal_Detector_Settings *SettingsPtr)
| This function is used to get the ADC Signal Detector Settings. More...
u32 | XRFdc_DisableCoefficientsOverride (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock)
| This function is used to disable Calibration Coefficients override. More...
u32 | XRFdc_SetCalCoefficients (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock, XRFdc_Calibration_Coefficients *CoeffPtr)
| This function is used to set the ADC Calibration Coefficients. More...
u32 | XRFdc_GetCalCoefficients (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock, XRFdc_Calibration_Coefficients *CoeffPtr)
| This function is used to get the ADC Calibration Coefficients. More...
u32 | XRFdc_SetCalFreeze (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Cal_Freeze_Settings *CalFreezePtr)
| This function is used to set calibration freeze settings. More...
u32 | XRFdc_GetCalFreeze (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Cal_Freeze_Settings *CalFreezePtr)
| This function is used to get calibration freeze settings and status. More...
u32 | XRFdc_SetDACVOP (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 uACurrent)
| Set Output Current for DAC block. More...
u32 | XRFdc_SetDACCompMode (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Enable)
| Sets VOP compatibility mode. More...
u32 | XRFdc_GetDACCompMode (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *EnabledPtr)
| Gets VOP compatibility mode. More...
u32 | XRFdc_SetDSA (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_DSA_Settings *SettingsPtr)
| Set DSA for ADC block. More...
u32 | XRFdc_GetDSA (XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_DSA_Settings *SettingsPtr)
| Get DSA for ADC block. More...
s32 | XRFdc_GetDeviceNameByDeviceId (char *DevNamePtr, u16 DevId)
| Traverse "/sys/bus/platform/device" directory, to find RFDC device entry, corresponding to provided device id. More...

## Register Map
Register offsets from the base address of an RFDC ADC and DAC device.
#define | XRFDC_CLK_EN_OFFSET 0x000U
| ADC Clock Enable Register. More...
#define | XRFDC_ADC_DEBUG_RST_OFFSET 0x004U
| ADC Debug Reset Register. More...
#define | XRFDC_ADC_FABRIC_RATE_OFFSET 0x008U
| ADC Fabric Rate Register. More...
#define | XRFDC_ADC_FABRIC_OFFSET 0x00CU
| ADC Fabric Register. More...
#define | XRFDC_ADC_FABRIC_ISR_OFFSET 0x010U
| ADC Fabric ISR Register. More...
#define | XRFDC_DAC_FABRIC_ISR_OFFSET 0x014U
| DAC Fabric ISR Register. More...
#define | XRFDC_ADC_FABRIC_IMR_OFFSET 0x014U
| ADC Fabric IMR Register. More...
#define | XRFDC_DAC_FABRIC_IMR_OFFSET 0x018U
| DAC Fabric IMR Register. More...
#define | XRFDC_ADC_FABRIC_DBG_OFFSET 0x018U
| ADC Fabric Debug Register. More...
#define | XRFDC_ADC_UPDATE_DYN_OFFSET 0x01CU
| ADC Update Dynamic Register. More...
#define | XRFDC_DAC_UPDATE_DYN_OFFSET 0x020U
| DAC Update Dynamic Register. More...
#define | XRFDC_ADC_FIFO_LTNC_CRL_OFFSET 0x020U
| ADC FIFO Latency Control Register. More...
#define | XRFDC_ADC_DEC_ISR_OFFSET 0x030U
| ADC Decoder interface ISR Register. More...
#define | XRFDC_DAC_DATAPATH_OFFSET 0x034U
| ADC Decoder interface IMR Register. More...
#define | XRFDC_ADC_DEC_IMR_OFFSET 0x034U
| ADC Decoder interface IMR Register. More...
#define | XRFDC_DATPATH_ISR_OFFSET 0x038U
| ADC Data Path ISR Register. More...
#define | XRFDC_DATPATH_IMR_OFFSET 0x03CU
| ADC Data Path IMR Register. More...
#define | XRFDC_ADC_DECI_CONFIG_OFFSET 0x040U
| ADC Decimation Config Register. More...
#define | XRFDC_DAC_INTERP_CTRL_OFFSET 0x040U
| DAC Interpolation Control Register. More...
#define | XRFDC_ADC_DECI_MODE_OFFSET 0x044U
| ADC Decimation mode Register. More...
#define | XRFDC_DAC_ITERP_DATA_OFFSET 0x044U
| DAC interpolation data. More...
#define | XRFDC_ADC_MXR_CFG0_OFFSET 0x080U
| ADC I channel mixer config Register. More...
#define | XRFDC_ADC_MXR_CFG1_OFFSET 0x084U
| ADC Q channel mixer config Register. More...
#define | XRFDC_MXR_MODE_OFFSET 0x088U
| ADC/DAC mixer mode Register. More...
#define | XRFDC_NCO_UPDT_OFFSET 0x08CU
| ADC/DAC NCO Update mode Register. More...
#define | XRFDC_NCO_RST_OFFSET 0x090U
| ADC/DAC NCO Phase Reset Register. More...
#define | XRFDC_ADC_NCO_FQWD_UPP_OFFSET 0x094U
| ADC NCO Frequency Word[47:32] Register. More...
#define | XRFDC_ADC_NCO_FQWD_MID_OFFSET 0x098U
| ADC NCO Frequency Word[31:16] Register. More...
#define | XRFDC_ADC_NCO_FQWD_LOW_OFFSET 0x09CU
| ADC NCO Frequency Word[15:0] Register. More...
#define | XRFDC_NCO_PHASE_UPP_OFFSET 0x0A0U
| ADC/DAC NCO Phase[17:16] Register. More...
#define | XRFDC_NCO_PHASE_LOW_OFFSET 0x0A4U
| ADC/DAC NCO Phase[15:0] Register. More...
#define | XRFDC_ADC_NCO_PHASE_MOD_OFFSET 0x0A8U
| ADC NCO Phase Mode Register. More...
#define | XRFDC_QMC_UPDT_OFFSET 0x0C8U
| ADC/DAC QMC Update Mode Register. More...
#define | XRFDC_QMC_CFG_OFFSET 0x0CCU
| ADC/DAC QMC Config Register. More...
#define | XRFDC_QMC_OFF_OFFSET 0x0D0U
| ADC/DAC QMC Offset Correction Register. More...
#define | XRFDC_QMC_GAIN_OFFSET 0x0D4U
| ADC/DAC QMC Gain Correction Register. More...
#define | XRFDC_QMC_PHASE_OFFSET 0x0D8U
| ADC/DAC QMC Phase Correction Register. More...
#define | XRFDC_ADC_CRSE_DLY_UPDT_OFFSET 0x0DCU
| ADC Coarse Delay Update Register. More...
#define | XRFDC_DAC_CRSE_DLY_UPDT_OFFSET 0x0E0U
| DAC Coarse Delay Update Register. More...
#define | XRFDC_ADC_CRSE_DLY_CFG_OFFSET 0x0E0U
| ADC Coarse delay Config Register. More...
#define | XRFDC_DAC_CRSE_DLY_CFG_OFFSET 0x0DCU
| DAC Coarse delay Config Register. More...
#define | XRFDC_ADC_DAT_SCAL_CFG_OFFSET 0x0E4U
| ADC Data Scaling Config Register. More...
#define | XRFDC_ADC_SWITCH_MATRX_OFFSET 0x0E8U
| ADC Switch Matrix Config Register. More...
#define | XRFDC_ADC_TRSHD0_CFG_OFFSET 0x0ECU
| ADC Threshold0 Config Register. More...
#define | XRFDC_ADC_TRSHD0_AVG_UP_OFFSET 0x0F0U
| ADC Threshold0 Average[31:16] Register. More...
#define | XRFDC_ADC_TRSHD0_AVG_LO_OFFSET 0x0F4U
| ADC Threshold0 Average[15:0] Register. More...
#define | XRFDC_ADC_TRSHD0_UNDER_OFFSET 0x0F8U
| ADC Threshold0 Under Threshold Register. More...
#define | XRFDC_ADC_TRSHD0_OVER_OFFSET 0x0FCU
| ADC Threshold0 Over Threshold Register. More...
#define | XRFDC_ADC_TRSHD1_CFG_OFFSET 0x100U
| ADC Threshold1 Config Register. More...
#define | XRFDC_ADC_TRSHD1_AVG_UP_OFFSET 0x104U
| ADC Threshold1 Average[31:16] Register. More...
#define | XRFDC_ADC_TRSHD1_AVG_LO_OFFSET 0x108U
| ADC Threshold1 Average[15:0] Register. More...
#define | XRFDC_ADC_TRSHD1_UNDER_OFFSET 0x10CU
| ADC Threshold1 Under Threshold Register. More...
#define | XRFDC_ADC_TRSHD1_OVER_OFFSET 0x110U
| ADC Threshold1 Over Threshold Register. More...
#define | XRFDC_ADC_FEND_DAT_CRL_OFFSET 0x140U
| ADC Front end Data Control Register. More...
#define | XRFDC_ADC_TI_DCB_CRL0_OFFSET 0x144U
| ADC Time Interleaved digital correction block gain control0 Register. More...
#define | XRFDC_ADC_TI_DCB_CRL1_OFFSET 0x148U
| ADC Time Interleaved digital correction block gain control1 Register. More...
#define | XRFDC_ADC_TI_DCB_CRL2_OFFSET 0x14CU
| ADC Time Interleaved digital correction block gain control2 Register. More...
#define | XRFDC_ADC_TI_DCB_CRL3_OFFSET 0x150U
| ADC Time Interleaved digital correction block gain control3 Register. More...
#define | XRFDC_ADC_TI_TISK_CRL0_OFFSET 0x154U
| ADC Time skew correction control bits0 Register. More...
#define | XRFDC_DAC_MC_CFG0_OFFSET 0x1C4U
| Static Configuration data for DAC Analog. More...
#define | XRFDC_ADC_TI_TISK_CRL1_OFFSET 0x158U
| ADC Time skew correction control bits1 Register. More...
#define | XRFDC_ADC_TI_TISK_CRL2_OFFSET 0x15CU
| ADC Time skew correction control bits2 Register. More...
#define | XRFDC_ADC_TI_TISK_CRL3_OFFSET 0x160U
| ADC Time skew correction control bits3 Register. More...
#define | XRFDC_ADC_TI_TISK_CRL4_OFFSET 0x164U
| ADC Time skew correction control bits4 Register. More...
#define | XRFDC_ADC_TI_TISK_DAC0_OFFSET 0x168U
| ADC Time skew DAC cal code of subadc ch0 Register. More...
#define | XRFDC_ADC_TI_TISK_DAC1_OFFSET 0x16CU
| ADC Time skew DAC cal code of subadc ch1 Register. More...
#define | XRFDC_ADC_TI_TISK_DAC2_OFFSET 0x170U
| ADC Time skew DAC cal code of subadc ch2 Register. More...
#define | XRFDC_ADC_TI_TISK_DAC3_OFFSET 0x174U
| ADC Time skew DAC cal code of subadc ch3 Register. More...
#define | XRFDC_ADC_TI_TISK_DACP0_OFFSET 0x178U
| ADC Time skew DAC cal code of subadc ch0 Register. More...
#define | XRFDC_ADC_TI_TISK_DACP1_OFFSET 0x17CU
| ADC Time skew DAC cal code of subadc ch1 Register. More...
#define | XRFDC_ADC_TI_TISK_DACP2_OFFSET 0x180U
| ADC Time skew DAC cal code of subadc ch2 Register. More...
#define | XRFDC_ADC_TI_TISK_DACP3_OFFSET 0x184U
| ADC Time skew DAC cal code of subadc ch3 Register. More...
#define | XRFDC_DAC_VOP_CTRL_OFFSET 0x198U
| DAC variable output power control Register. More...
#define | XRFDC_ADC0_SUBDRP_ADDR_OFFSET 0x198U
| subadc0, sub-drp address of target Register More...
#define | XRFDC_ADC0_SUBDRP_DAT_OFFSET 0x19CU
| subadc0, sub-drp data of target Register More...
#define | XRFDC_ADC1_SUBDRP_ADDR_OFFSET 0x1A0U
| subadc1, sub-drp address of target Register More...
#define | XRFDC_ADC1_SUBDRP_DAT_OFFSET 0x1A4U
| subadc1, sub-drp data of target Register More...
#define | XRFDC_ADC2_SUBDRP_ADDR_OFFSET 0x1A8U
| subadc2, sub-drp address of target Register More...
#define | XRFDC_ADC2_SUBDRP_DAT_OFFSET 0x1ACU
| subadc2, sub-drp data of target Register More...
#define | XRFDC_ADC3_SUBDRP_ADDR_OFFSET 0x1B0U
| subadc3, sub-drp address of target Register More...
#define | XRFDC_ADC3_SUBDRP_DAT_OFFSET 0x1B4U
| subadc3, sub-drp data of target Register More...
#define | XRFDC_ADC_RX_MC_PWRDWN_OFFSET 0x1C0U
| ADC Static configuration bits for ADC(RX) analog Register. More...
#define | XRFDC_ADC_DAC_MC_CFG0_OFFSET 0x1C4U
| ADC/DAC Static configuration bits for ADC/DAC analog Register. More...
#define | XRFDC_ADC_DAC_MC_CFG1_OFFSET 0x1C8U
| ADC/DAC Static configuration bits for ADC/DAC analog Register. More...
#define | XRFDC_ADC_DAC_MC_CFG2_OFFSET 0x1CCU
| ADC/DAC Static configuration bits for ADC/DAC analog Register. More...
#define | XRFDC_DAC_MC_CFG3_OFFSET 0x1D0U
| DAC Static configuration bits for DAC analog Register. More...
#define | XRFDC_ADC_RXPR_MC_CFG0_OFFSET 0x1D0U
| ADC RX Pair static Configuration Register. More...
#define | XRFDC_ADC_RXPR_MC_CFG1_OFFSET 0x1D4U
| ADC RX Pair static Configuration Register. More...
#define | XRFDC_ADC_TI_DCBSTS0_BG_OFFSET 0x200U
| ADC DCB Status0 BG Register. More...
#define | XRFDC_ADC_TI_DCBSTS0_FG_OFFSET 0x204U
| ADC DCB Status0 FG Register. More...
#define | XRFDC_ADC_TI_DCBSTS1_BG_OFFSET 0x208U
| ADC DCB Status1 BG Register. More...
#define | XRFDC_ADC_TI_DCBSTS1_FG_OFFSET 0x20CU
| ADC DCB Status1 FG Register. More...
#define | XRFDC_ADC_TI_DCBSTS2_BG_OFFSET 0x210U
| ADC DCB Status2 BG Register. More...
#define | XRFDC_ADC_TI_DCBSTS2_FG_OFFSET 0x214U
| ADC DCB Status2 FG Register. More...
#define | XRFDC_ADC_TI_DCBSTS3_BG_OFFSET 0x218U
| ADC DCB Status3 BG Register. More...
#define | XRFDC_ADC_TI_DCBSTS3_FG_OFFSET 0x21CU
| ADC DCB Status3 FG Register. More...
#define | XRFDC_ADC_TI_DCBSTS4_MB_OFFSET 0x220U
| ADC DCB Status4 MSB Register. More...
#define | XRFDC_ADC_TI_DCBSTS4_LB_OFFSET 0x224U
| ADC DCB Status4 LSB Register. More...
#define | XRFDC_ADC_TI_DCBSTS5_MB_OFFSET 0x228U
| ADC DCB Status5 MSB Register. More...
#define | XRFDC_ADC_TI_DCBSTS5_LB_OFFSET 0x22CU
| ADC DCB Status5 LSB Register. More...
#define | XRFDC_ADC_TI_DCBSTS6_MB_OFFSET 0x230U
| ADC DCB Status6 MSB Register. More...
#define | XRFDC_ADC_TI_DCBSTS6_LB_OFFSET 0x234U
| ADC DCB Status6 LSB Register. More...
#define | XRFDC_ADC_TI_DCBSTS7_MB_OFFSET 0x238U
| ADC DCB Status7 MSB Register. More...
#define | XRFDC_ADC_TI_DCBSTS7_LB_OFFSET 0x23CU
| ADC DCB Status7 LSB Register. More...
#define | XRFDC_DSA_UPDT_OFFSET 0x254U
| ADC DSA Update Trigger REgister. More...
#define | XRFDC_ADC_FIFO_LTNCY_LB_OFFSET 0x280U
| ADC FIFO Latency measurement LSB Register. More...
#define | XRFDC_ADC_FIFO_LTNCY_MB_OFFSET 0x284U
| ADC FIFO Latency measurement MSB Register. More...
#define | XRFDC_DAC_DECODER_CTRL_OFFSET 0x180U
| DAC Unary Decoder/ Randomizer settings. More...
#define | XRFDC_DAC_DECODER_CLK_OFFSET 0x184U
| Decoder Clock enable. More...
#define | XRFDC_ADC_SIG_DETECT_CTRL_OFFSET 0x114
| ADC Signal Detector Control. More...
#define | XRFDC_ADC_SIG_DETECT_THRESHOLD0_LEVEL_OFFSET 0x118
| ADC Signal Detector Threshold 0. More...
#define | XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_ON_OFFSET 0x11C
| ADC Signal Detector Threshold 0 on Counter. More...
#define | XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_OFF_OFFSET 0x120
| ADC Signal Detector Threshold 0 off Counter. More...
#define | XRFDC_ADC_SIG_DETECT_THRESHOLD1_LEVEL_OFFSET 0x124
| ADC Signal Detector Threshold 1. More...
#define | XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_ON_OFFSET 0x128
| ADC Signal Detector Threshold 1 on Counter. More...
#define | XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_OFF_OFFSET 0x12C
| ADC Signal Detector Threshold 1 off Counter. More...
#define | XRFDC_ADC_SIG_DETECT_MAGN_OFFSET 0x130
| ADC Signal Detector Magintude. More...
#define | XRFDC_HSCOM_CLK_DSTR_OFFSET 0x088U
| Clock Distribution Register. More...
#define | XRFDC_HSCOM_CLK_DSTR_MASK 0xC788U
| Clock Distribution Register. More...
#define | XRFDC_HSCOM_CLK_DSTR_MASK_ALT 0x1870U
| Clock Distribution Register for Intratile. More...
#define | XRFDC_HSCOM_PWR_OFFSET 0x094
| Control register during power-up sequence. More...
#define | XRFDC_HSCOM_CLK_DIV_OFFSET 0xB0
| Fabric clk out divider. More...
#define | XRFDC_HSCOM_PWR_STATE_OFFSET 0xB4
| Check powerup state. More...
#define | XRFDC_HSCOM_UPDT_DYN_OFFSET 0x0B8
| Trigger the update dynamic event. More...
#define | XRFDC_HSCOM_EFUSE_2_OFFSET 0x144
#define | XRFDC_DAC_INVSINC_OFFSET 0x0C0U
| Invsinc control. More...
#define | XRFDC_DAC_MB_CFG_OFFSET 0x0C4U
| Multiband config. More...
#define | XRFDC_MTS_SRDIST 0x1CA0U
#define | XRFDC_MTS_SRCAP_T1 (0x24U << 2U)
#define | XRFDC_MTS_SRCAP_PLL (0x0CU << 2U)
#define | XRFDC_MTS_SRCAP_DIG (0x2CU << 2U)
#define | XRFDC_MTS_SRDTC_T1 (0x27U << 2U)
#define | XRFDC_MTS_SRDTC_PLL (0x26U << 2U)
#define | XRFDC_MTS_SRFLAG (0x49U << 2U)
#define | XRFDC_MTS_CLKSTAT (0x24U << 2U)
#define | XRFDC_MTS_SRCOUNT_CTRL 0x004CU
#define | XRFDC_MTS_SRCOUNT_VAL 0x0050U
#define | XRFDC_MTS_SRFREQ_VAL 0x0054U
#define | XRFDC_MTS_FIFO_CTRL_ADC 0x0010U
#define | XRFDC_MTS_FIFO_CTRL_DAC 0x0014U
#define | XRFDC_MTS_DELAY_CTRL 0x0028U
#define | XRFDC_MTS_ADC_MARKER 0x0018U
#define | XRFDC_MTS_ADC_MARKER_CNT 0x0010U
#define | XRFDC_MTS_DAC_MARKER_CTRL 0x0048U
#define | XRFDC_MTS_DAC_MARKER_CNT (0x92U << 2U)
#define | XRFDC_MTS_DAC_MARKER_LOC (0x93U << 2U)
#define | XRFDC_RESET_OFFSET 0x00U
| Tile reset register. More...
#define | XRFDC_RESTART_OFFSET 0x04U
| Tile restart register. More...
#define | XRFDC_RESTART_STATE_OFFSET 0x08U
| Tile restart state register. More...
#define | XRFDC_CURRENT_STATE_OFFSET 0x0CU
| Current state register. More...
#define | XRFDC_CLOCK_DETECT_OFFSET 0x80U
| Clock detect register. More...
#define | XRFDC_STATUS_OFFSET 0x228U
| Common status register. More...
#define | XRFDC_COMMON_INTR_STS 0x100U
| Common Intr Status register. More...
#define | XRFDC_COMMON_INTR_ENABLE 0x104U
| Common Intr enable register. More...
#define | XRFDC_INTR_STS 0x200U
| Intr status register. More...
#define | XRFDC_INTR_ENABLE 0x204U
| Intr enable register. More...
#define | XRFDC_CONV_INTR_STS(X) (0x208U + (X * 0x08U))
#define | XRFDC_CONV_INTR_EN(X) (0x20CU + (X * 0x08U))
#define | XRFDC_CONV_CAL_STGS(X) (0x234U + (X * 0x04U))
#define | XRFDC_CONV_DSA_STGS(X) (0x244U + (X * 0x04U))
#define | XRFDC_CAL_GCB_COEFF0_FAB(X) (0x280U + (X * 0x10U))
#define | XRFDC_CAL_GCB_COEFF1_FAB(X) (0x284U + (X * 0x10U))
#define | XRFDC_CAL_GCB_COEFF2_FAB(X) (0x288U + (X * 0x10U))
#define | XRFDC_CAL_GCB_COEFF3_FAB(X) (0x28CU + (X * 0x10U))
#define | XRFDC_PLL_FREQ 0x300U
| PLL output frequency (before divider) register. More...
#define | XRFDC_PLL_FS 0x304U
| Sampling rate register. More...
#define | XRFDC_FIFO_ENABLE 0x230U
| FIFO Enable and Disable. More...
#define | XRFDC_PLL_SDM_CFG0 0x00U
| PLL Configuration bits for sdm. More...
#define | XRFDC_PLL_SDM_SEED0 0x18U
| PLL Bits for sdm LSB. More...
#define | XRFDC_PLL_SDM_SEED1 0x1CU
| PLL Bits for sdm MSB. More...
#define | XRFDC_PLL_VREG 0x44U
| PLL bits for voltage regulator. More...
#define | XRFDC_PLL_VREG 0x44U
| PLL bits for voltage regulator. More...
#define | XRFDC_PLL_VCO0 0x54U
| PLL bits for coltage controlled oscillator LSB. More...
#define | XRFDC_PLL_VCO1 0x58U
| PLL bits for coltage controlled oscillator MSB. More...
#define | XRFDC_PLL_CRS1 0x28U
| PLL bits for coarse frequency control LSB. More...
#define | XRFDC_PLL_CRS2 0x2CU
| PLL bits for coarse frequency control MSB. More...
#define | XRFDC_PLL_DIVIDER0 0x30U
| PLL Output Divider LSB register. More...
#define | XRFDC_PLL_DIVIDER1 0x34U
| PLL Output Divider MSB register. More...
#define | XRFDC_PLL_SPARE0 0x38U
| PLL spare inputs LSB. More...
#define | XRFDC_PLL_SPARE1 0x3CU
| PLL spare inputs MSB. More...
#define | XRFDC_PLL_REFDIV 0x40U
| PLL Reference Divider register. More...
#define | XRFDC_PLL_CHARGEPUMP 0x48U
| PLL bits for charge pumps. More...
#define | XRFDC_PLL_LPF0 0x4CU
| PLL bits for loop filters LSB. More...
#define | XRFDC_PLL_LPF1 0x50U
| PLL bits for loop filters MSB. More...
#define | XRFDC_PLL_FPDIV 0x5CU
| PLL Feedback Divider register. More...
#define | XRFDC_CLK_NETWORK_CTRL0 0x8CU
| Clock network control and trim register. More...
#define | XRFDC_CLK_NETWORK_CTRL1 0x90U
| Multi-tile sync and clock source control register. More...
#define | XRFDC_HSCOM_NETWORK_CTRL1_MASK 0x02FU
| Clock Network Register Mask for IntraTile. More...
#define | XRFDC_PLL_REFDIV_MASK 0x0E0U
| PLL Reference Divider Register Mask for IntraTile. More...
#define | XRFDC_PLL_DIVIDER0_ALT_MASK 0xC00U
| PLL Output Divider Register Mask for IntraTile. More...
#define | XRFDC_PLL_DIVIDER0_BYPPLL_MASK 0x800U
| PLL Output Divider Register Mask for IntraTile. More...
#define | XRFDC_PLL_DIVIDER0_BYPDIV_MASK 0x400U
| PLL Output Divider Register Mask for IntraTile. More...
#define | XRFDC_CAL_OCB1_OFFSET_COEFF0 0x200
| Foreground offset correction block. More...
#define | XRFDC_CAL_OCB1_OFFSET_COEFF1 0x208
| Foreground offset correction block. More...
#define | XRFDC_CAL_OCB1_OFFSET_COEFF2 0x210
| Foreground offset correction block. More...
#define | XRFDC_CAL_OCB1_OFFSET_COEFF3 0x218
| Foreground offset correction block. More...
#define | XRFDC_CAL_OCB2_OFFSET_COEFF0 0x204
| Background offset correction block. More...
#define | XRFDC_CAL_OCB2_OFFSET_COEFF1 0x20C
| Background offset correction block. More...
#define | XRFDC_CAL_OCB2_OFFSET_COEFF2 0x214
| Background offset correction block. More...
#define | XRFDC_CAL_OCB2_OFFSET_COEFF3 0x21C
| Background offset correction block. More...
#define | XRFDC_CAL_GCB_OFFSET_COEFF0 0x220
| Background gain correction block. More...
#define | XRFDC_CAL_GCB_OFFSET_COEFF1 0x224
| Background gain correction block. More...
#define | XRFDC_CAL_GCB_OFFSET_COEFF2 0x228
| Background gain correction block. More...
#define | XRFDC_CAL_GCB_OFFSET_COEFF3 0x22C
| Background gain correction block. More...
#define | XRFDC_CAL_GCB_OFFSET_COEFF0_ALT 0x220
| Background gain correction block (below Gen 3) More...
#define | XRFDC_CAL_GCB_OFFSET_COEFF1_ALT 0x228
| Background gain correction block (below Gen 3) More...
#define | XRFDC_CAL_GCB_OFFSET_COEFF2_ALT 0x230
| Background gain correction block (below Gen 3) More...
#define | XRFDC_CAL_GCB_OFFSET_COEFF3_ALT 0x238
| Background gain correction block (below Gen 3) More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF0 0x170
| Background time skew correction block. More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF1 0x174
| Background time skew correction block. More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF2 0x178
| Background time skew correction block. More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF3 0x17C
| Background time skew correction block. More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF4 0x180
| Background time skew correction block. More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF5 0x184
| Background time skew correction block. More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF6 0x188
| Background time skew correction block. More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF7 0x18C
| Background time skew correction block. More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF0_ALT 0x168
| Background time skew correction block (below Gen 3) More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF1_ALT 0x16C
| Background time skew correction block (below Gen 3) More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF2_ALT 0x170
| Background time skew correction block (below Gen 3) More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF3_ALT 0x174
| Background time skew correction block (below Gen 3) More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF4_ALT 0x178
| Background time skew correction block (below Gen 3) More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF5_ALT 0x17C
| Background time skew correction block (below Gen 3) More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF6_ALT 0x180
| Background time skew correction block (below Gen 3) More...
#define | XRFDC_CAL_TSCB_OFFSET_COEFF7_ALT 0x184
| Background time skew correction block (below Gen 3) More...

## Calibration Coefficients - Calibration coefficients and disable registers
This register contains bits for calibration coefficients for ADC.
#define | XRFDC_CAL_OCB_MASK 0xFFFFU
| offsets coeff mask More...
#define | XRFDC_CAL_GCB_MASK 0x0FFFU
| gain coeff mask More...
#define | XRFDC_CAL_GCB_FAB_MASK 0xFFF0U
| gain coeff mask for IP Gen 2 or below More...
#define | XRFDC_CAL_TSCB_MASK 0x01FFU
| time skew coeff mask More...
#define | XRFDC_CAL_GCB_FLSH_MASK 0x1000U
| GCB accumulator flush mask. More...
#define | XRFDC_CAL_GCB_ACEN_MASK 0x0800U
| GCB accumulator enable mask. More...
#define | XRFDC_CAL_GCB_ENFL_MASK 0x1800U
| GCB accumulator enable mask. More...
#define | XRFDC_CAL_OCB_EN_MASK 0x0001U
| offsets coeff override enable mask More...
#define | XRFDC_CAL_GCB_EN_MASK 0x0080U
| gain coeff override enable mask More...
#define | XRFDC_CAL_TSCB_EN_MASK 0x8000U
| time skew coeff override enable mask More...
#define | XRFDC_CAL_OCB_EN_SHIFT 0U
| offsets coeff shift More...
#define | XRFDC_CAL_GCB_EN_SHIFT 7U
| gain coeff shift More...
#define | XRFDC_CAL_TSCB_EN_SHIFT 15U
| time skew coeff shift More...
#define | XRFDC_CAL_GCB_FLSH_SHIFT 12U
| GCB accumulator flush shift. More...
#define | XRFDC_CAL_GCB_ACEN_SHIFT 11U
| GCB accumulator enable shift. More...
#define | XRFDC_CAL_SLICE_SHIFT 16U
| Coefficient shift for HSADCs. More...
#define | XRFDC_CAL_FREEZE_CAL_MASK 0x1U
| Calibration freeze enable mask. More...
#define | XRFDC_CAL_FREEZE_STS_MASK 0x2U
| Calibration freeze status mask. More...
#define | XRFDC_CAL_FREEZE_PIN_MASK 0x4U
| Calibration freeze pin disable mask. More...
#define | XRFDC_CAL_FREEZE_CAL_SHIFT 0U
| Calibration freeze enable shift. More...
#define | XRFDC_CAL_FREEZE_STS_SHIFT 1U
| Calibration freeze status shift. More...
#define | XRFDC_CAL_FREEZE_PIN_SHIFT 2U
| Calibration freeze pin disable shift. More...

## FIFO Enable - FIFO enable and disable register
This register contains bits for FIFO enable and disable for ADC and DAC.
#define | XRFDC_FIFO_EN_MASK 0x00000001U
| FIFO enable/disable. More...
#define | XRFDC_RESTART_MASK 0x00000001U
| Restart bit mask. More...

## Clock Enable - FIFO Latency, fabric, DataPath,
full-rate, output register This register contains bits for various clock enable options of the ADC. Read/Write apart from the reserved bits.
#define | XRFDC_CLK_EN_CAL_MASK 0x00000001U
| Enable Output Register clock. More...
#define | XRFDC_CLK_EN_DIG_MASK 0x00000002U
| Enable full-rate clock. More...
#define | XRFDC_CLK_EN_DP_MASK 0x00000004U
| Enable Data Path clock. More...
#define | XRFDC_CLK_EN_FAB_MASK 0x00000008U
| Enable fabric clock. More...
#define | XRFDC_DAT_CLK_EN_MASK 0x0000000FU
| Data Path Clk enable. More...
#define | XRFDC_CLK_EN_LM_MASK 0x00000010U
| Enable for FIFO Latency measurement clock. More...

## Debug reset - FIFO Latency, fabric, DataPath,
full-rate, output register This register contains bits for various Debug reset options of the ADC. Read/Write apart from the reserved bits.
#define | XRFDC_DBG_RST_CAL_MASK 0x00000001U
| Reset clk_cal clock domain. More...
#define | XRFDC_DBG_RST_DP_MASK 0x00000002U
| Reset data path clock domain. More...
#define | XRFDC_DBG_RST_FAB_MASK 0x00000004U
| Reset clock fabric clock domain. More...
#define | XRFDC_DBG_RST_DIG_MASK 0x00000008U
| Reset clk_dig clock domain. More...
#define | XRFDC_DBG_RST_DRP_CAL_MASK 0x00000010U
| Reset subadc-drp register on clock cal. More...
#define | XRFDC_DBG_RST_LM_MASK 0x00000020U
| Reset FIFO Latency measurement clock domain. More...

## Fabric rate - Fabric data rate for read and write
This register contains bits for read and write fabric data rate for ADC. Read/Write apart from the reserved bits.
#define | XRFDC_ADC_FAB_RATE_WR_MASK 0x0000000FU
| ADC FIFO Write Number of Words per clock. More...
#define | XRFDC_DAC_FAB_RATE_WR_MASK 0x0000001FU
| DAC FIFO Write Number of Words per clock. More...
#define | XRFDC_ADC_FAB_RATE_RD_MASK 0x00000F00U
| ADC FIFO Read Number of Words per clock. More...
#define | XRFDC_DAC_FAB_RATE_RD_MASK 0x00001F00U
| DAC FIFO Read Number of Words per clock. More...
#define | XRFDC_FAB_RATE_RD_SHIFT 8U
| Fabric Read shift. More...

## Fabric Offset - FIFO de-skew
This register contains bits of Fabric Offset. Read/Write apart from the reserved bits.
#define | XRFDC_FAB_RD_PTR_OFFST_MASK 0x0000003FU
| FIFO read pointer offset for interface de-skew. More...

## Fabric ISR - Interrupt status register for FIFO interface
This register contains bits of margin-indicator and user-data overlap (overflow/underflow). Read/Write apart from the reserved bits.
#define | XRFDC_FAB_ISR_USRDAT_OVR_MASK 0x00000001U
| User-data overlap- data written faster than read (overflow) More...
#define | XRFDC_FAB_ISR_USRDAT_UND_MASK 0x00000002U
| User-data overlap- data read faster than written (underflow) More...
#define | XRFDC_FAB_ISR_USRDAT_MASK 0x00000003U
| User-data overlap Mask. More...
#define | XRFDC_FAB_ISR_MARGIND_OVR_MASK 0x00000004U
| Marginal-indicator overlap (overflow) More...
#define | XRFDC_FAB_ISR_MARGIND_UND_MASK 0x00000008U
| Marginal-indicator overlap (underflow) More...

## Fabric IMR - Interrupt mask register for FIFO interface
This register contains bits of margin-indicator and user-data overlap (overflow/underflow). Read/Write apart from the reserved bits.
#define | XRFDC_FAB_IMR_USRDAT_OVR_MASK 0x00000001U
| User-data overlap- data written faster than read (overflow) More...
#define | XRFDC_FAB_IMR_USRDAT_UND_MASK 0x00000002U
| User-data overlap- data read faster than written (underflow) More...
#define | XRFDC_FAB_IMR_USRDAT_MASK 0x00000003U
| User-data overlap Mask. More...
#define | XRFDC_FAB_IMR_MARGIND_OVR_MASK 0x00000004U
| Marginal-indicator overlap (overflow) More...
#define | XRFDC_FAB_IMR_MARGIND_UND_MASK 0x00000008U
| Marginal-indicator overlap (underflow) More...

## Update Dynamic - Trigger a dynamic update event
This register contains bits of update event for slice, nco, qmc and coarse delay. Read/Write apart from the reserved bits.
#define | XRFDC_UPDT_EVNT_MASK 0x0000000FU
| Update event mask. More...
#define | XRFDC_UPDT_EVNT_SLICE_MASK 0x00000001U
| Trigger a slice update event apply to _DCONFIG reg. More...
#define | XRFDC_UPDT_EVNT_NCO_MASK 0x00000002U
| Trigger a update event apply to NCO_DCONFIG reg. More...
#define | XRFDC_UPDT_EVNT_QMC_MASK 0x00000004U
| Trigger a update event apply to QMC_DCONFIG reg. More...
#define | XRFDC_ADC_UPDT_CRSE_DLY_MASK 0x00000008U
| ADC Trigger a update event apply to Coarse delay_DCONFIG reg. More...
#define | XRFDC_DAC_UPDT_CRSE_DLY_MASK 0x00000020U
| DAC Trigger a update event apply to Coarse delay_DCONFIG reg. More...

## FIFO Latency control - Config registers for FIFO Latency measurement
This register contains bits of FIFO Latency ctrl for disable, restart and set fifo latency measurement. Read/Write apart from the reserved bits.
#define | XRFDC_FIFO_LTNCY_PRD_MASK 0x00000007U
| Set FIFO Latency measurement period. More...
#define | XRFDC_FIFO_LTNCY_RESTRT_MASK 0x00000008U
| Restart FIFO Latency measurement. More...
#define | XRFDC_FIFO_LTNCY_DIS_MASK 0x000000010U
| Disable FIFO Latency measurement. More...

## Decode ISR - ISR for Decoder Interface
This register contains bits of subadc 0,1,2 and 3 decoder overflow and underflow range. Read/Write apart from the reserved bits.
#define | XRFDC_DEC_ISR_SUBADC_MASK 0x000000FFU
| subadc decoder Mask More...
#define | XRFDC_DEC_ISR_SUBADC0_UND_MASK 0x00000001U
| subadc0 decoder underflow range More...
#define | XRFDC_DEC_ISR_SUBADC0_OVR_MASK 0x00000002U
| subadc0 decoder overflow range More...
#define | XRFDC_DEC_ISR_SUBADC1_UND_MASK 0x00000004U
| subadc1 decoder underflow range More...
#define | XRFDC_DEC_ISR_SUBADC1_OVR_MASK 0x00000008U
| subadc1 decoder overflow range More...
#define | XRFDC_DEC_ISR_SUBADC2_UND_MASK 0x00000010U
| subadc2 decoder underflow range More...
#define | XRFDC_DEC_ISR_SUBADC2_OVR_MASK 0x00000020U
| subadc2 decoder overflow range More...
#define | XRFDC_DEC_ISR_SUBADC3_UND_MASK 0x00000040U
| subadc3 decoder underflow range More...
#define | XRFDC_DEC_ISR_SUBADC3_OVR_MASK 0x00000080U
| subadc3 decoder overflow range More...

## Decode IMR - IMR for Decoder Interface
This register contains bits of subadc 0,1,2 and 3 decoder overflow and underflow range. Read/Write apart from the reserved bits.
#define | XRFDC_DEC_IMR_SUBADC0_UND_MASK 0x00000001U
| subadc0 decoder underflow range More...
#define | XRFDC_DEC_IMR_SUBADC0_OVR_MASK 0x00000002U
| subadc0 decoder overflow range More...
#define | XRFDC_DEC_IMR_SUBADC1_UND_MASK 0x00000004U
| subadc1 decoder underflow range More...
#define | XRFDC_DEC_IMR_SUBADC1_OVR_MASK 0x00000008U
| subadc1 decoder overflow range More...
#define | XRFDC_DEC_IMR_SUBADC2_UND_MASK 0x00000010U
| subadc2 decoder underflow range More...
#define | XRFDC_DEC_IMR_SUBADC2_OVR_MASK 0x00000020U
| subadc2 decoder overflow range More...
#define | XRFDC_DEC_IMR_SUBADC3_UND_MASK 0x00000040U
| subadc3 decoder underflow range More...
#define | XRFDC_DEC_IMR_SUBADC3_OVR_MASK 0x00000080U
| subadc3 decoder overflow range More...
#define | XRFDC_DEC_IMR_MASK 0x000000FFU

## DataPath (DAC)- FIFO Latency, Image Reject Filter, Mode,
This register contains bits for DataPath latency, Image Reject Filter and the Mode for the DAC. Read/Write apart from the reserved bits.
#define | XRFDC_DATAPATH_MODE_MASK 0x00000003U
| DataPath Mode. More...
#define | XRFDC_DATAPATH_IMR_MASK 0x00000004U
| IMR Mode. More...
#define | XRFDC_DATAPATH_LATENCY_MASK 0x00000008U
| DataPath Latency. More...

## DataPath ISR - ISR for Data Path interface
This register contains bits of QMC Gain/Phase overflow, offset overflow, Decimation I-Path and Interpolation Q-Path overflow for stages 0,1,2. Read/Write apart from the reserved bits.
#define | XRFDC_ADC_DAT_PATH_ISR_MASK 0x000000FFU
| ADC Data Path Overflow. More...
#define | XRFDC_DAC_DAT_PATH_ISR_MASK 0x000001FFU
| DAC Data Path Overflow. More...
#define | XRFDC_DAT_ISR_DECI_IPATH_MASK 0x00000007U
| Decimation I-Path overflow for stages 0,1,2. More...
#define | XRFDC_DAT_ISR_INTR_QPATH_MASK 0x00000038U
| Interpolation Q-Path overflow for stages 0,1,2. More...
#define | XRFDC_DAT_ISR_QMC_GAIN_MASK 0x00000040U
| QMC Gain/Phase overflow. More...
#define | XRFDC_DAT_ISR_QMC_OFFST_MASK 0x00000080U
| QMC offset overflow. More...
#define | XRFDC_DAC_DAT_ISR_INVSINC_MASK 0x00000100U
| Inverse-Sinc offset overflow. More...

## DataPath IMR - IMR for Data Path interface
This register contains bits of QMC Gain/Phase overflow, offset overflow, Decimation I-Path and Interpolation Q-Path overflow for stages 0,1,2. Read/Write apart from the reserved bits.
#define | XRFDC_DAT_IMR_DECI_IPATH_MASK 0x00000007U
| Decimation I-Path overflow for stages 0,1,2. More...
#define | XRFDC_DAT_IMR_INTR_QPATH_MASK 0x00000038U
| Interpolation Q-Path overflow for stages 0,1,2. More...
#define | XRFDC_DAT_IMR_QMC_GAIN_MASK 0x00000040U
| QMC Gain/Phase overflow. More...
#define | XRFDC_DAT_IMR_QMC_OFFST_MASK 0x00000080U
| QMC offset overflow. More...
#define | XRFDC_ADC_DAT_IMR_MASK 0x000000FFU
| ADC DataPath mask. More...
#define | XRFDC_DAC_DAT_IMR_MASK 0x00000FFFU
| DAC DataPath mask. More...

## Decimation Config - Decimation control
This register contains bits to configure the decimation in terms of the type of data. Read/Write apart from the reserved bits.
#define | XRFDC_DEC_CFG_MASK 0x00000003U
| ChannelA (2GSPS real data from Mixer I output) More...
#define | XRFDC_DEC_CFG_CHA_MASK 0x00000000U
| ChannelA(I) More...
#define | XRFDC_DEC_CFG_CHB_MASK 0x00000001U
| ChannelB (2GSPS real data from Mixer Q output) More...
#define | XRFDC_DEC_CFG_IQ_MASK 0x00000002U
| IQ-2GSPS. More...
#define | XRFDC_DEC_CFG_4GSPS_MASK 0x00000003U
| 4GSPS may be I or Q or Real depending on high level block config More...

## Decimation Mode - Decimation Rate
This register contains bits to configures the decimation rate. Read/Write apart from the reserved bits.
#define | XRFDC_DEC_MOD_MASK 0x00000007U
| Decimation mode Mask. More...
#define | XRFDC_DEC_MOD_MASK_EXT 0x0000003FU
| Decimation mode Mask. More...

## Mixer config0 - Configure I channel coarse mixer mode of operation
This register contains bits to set the output data sequence of I channel. Read/Write apart from the reserved bits.
#define | XRFDC_MIX_CFG0_MASK 0x00000FFFU
| Mixer Config0 Mask. More...
#define | XRFDC_MIX_I_DAT_WRD0_MASK 0x00000007U
| Output data word[0] of I channel. More...
#define | XRFDC_MIX_I_DAT_WRD1_MASK 0x00000038U
| Output data word[1] of I channel. More...
#define | XRFDC_MIX_I_DAT_WRD2_MASK 0x000001C0U
| Output data word[2] of I channel. More...
#define | XRFDC_MIX_I_DAT_WRD3_MASK 0x00000E00U
| Output data word[3] of I channel. More...

## Mixer config1 - Configure Q channel coarse mixer mode of operation
This register contains bits to set the output data sequence of Q channel. Read/Write apart from the reserved bits.
#define | XRFDC_MIX_CFG1_MASK 0x00000FFFU
| Mixer Config0 Mask. More...
#define | XRFDC_MIX_Q_DAT_WRD0_MASK 0x00000007U
| Output data word[0] of Q channel. More...
#define | XRFDC_MIX_Q_DAT_WRD1_MASK 0x00000038U
| Output data word[1] of Q channel. More...
#define | XRFDC_MIX_Q_DAT_WRD2_MASK 0x000001C0U
| Output data word[2] of Q channel. More...
#define | XRFDC_MIX_Q_DAT_WRD3_MASK 0x00000E00U
| Output data word[3] of Q channel. More...

## Mixer mode - Configure mixer mode of operation
This register contains bits to set NCO phases, NCO output scale and fine mixer multipliers. Read/Write apart from the reserved bits.
#define | XRFDC_EN_I_IQ_MASK 0x00000003U
| Enable fine mixer multipliers on IQ i/p for I output. More...
#define | XRFDC_EN_Q_IQ_MASK 0x0000000CU
| Enable fine mixer multipliers on IQ i/p for Q output. More...
#define | XRFDC_FINE_MIX_SCALE_MASK 0x00000010U
| NCO output scale. More...
#define | XRFDC_SEL_I_IQ_MASK 0x00000F00U
| Select NCO phases for I output. More...
#define | XRFDC_SEL_Q_IQ_MASK 0x0000F000U
| Select NCO phases for Q output. More...
#define | XRFDC_I_IQ_COS_MINSIN 0x00000C00U
| Select NCO phases for I output. More...
#define | XRFDC_Q_IQ_SIN_COS 0x00001000U
| Select NCO phases for Q output. More...
#define | XRFDC_MIXER_MODE_C2C_MASK 0x0000000FU
| Mixer mode C2C Mask. More...
#define | XRFDC_MIXER_MODE_R2C_MASK 0x00000005U
| Mixer mode R2C Mask. More...
#define | XRFDC_MIXER_MODE_C2R_MASK 0x00000003U
| Mixer mode C2R Mask. More...
#define | XRFDC_MIXER_MODE_OFF_MASK 0x00000000U
| Mixer mode OFF Mask. More...

## NCO update - NCO update mode
This register contains bits to Select event source, delay and reset delay. Read/Write apart from the reserved bits.
#define | XRFDC_NCO_UPDT_MODE_MASK 0x00000007U
| NCO event source selection mask. More...
#define | XRFDC_NCO_UPDT_MODE_GRP 0x00000000U
| NCO event source selection is Group. More...
#define | XRFDC_NCO_UPDT_MODE_SLICE 0x00000001U
| NCO event source selection is slice. More...
#define | XRFDC_NCO_UPDT_MODE_TILE 0x00000002U
| NCO event source selection is tile. More...
#define | XRFDC_NCO_UPDT_MODE_SYSREF 0x00000003U
| NCO event source selection is Sysref. More...
#define | XRFDC_NCO_UPDT_MODE_MARKER 0x00000004U
| NCO event source selection is Marker. More...
#define | XRFDC_NCO_UPDT_MODE_FABRIC 0x00000005U
| NCO event source selection is fabric. More...
#define | XRFDC_NCO_UPDT_DLY_MASK 0x00001FF8U
| delay in clk_dp cycles in application of event after arrival More...
#define | XRFDC_NCO_UPDT_RST_DLY_MASK 0x0000D000U
| optional delay on the NCO phase reset delay More...

## NCO Phase Reset - NCO Slice Phase Reset
This register contains bits to reset the nco phase of the current slice phase accumulator. Read/Write apart from the reserved bits.
#define | XRFDC_NCO_PHASE_RST_MASK 0x00000001U
| Reset NCO Phase of current slice. More...

## DAC interpolation data
This register contains bits for DAC interpolation data type
#define | XRFDC_DAC_INTERP_DATA_MASK 0x00000001U
| Data type mask. More...

## NCO Freq Word[47:32] - NCO Phase increment(nco freq 48-bit)
This register contains bits for frequency control word of the NCO. Read/Write apart from the reserved bits.
#define | XRFDC_NCO_FQWD_UPP_MASK 0x0000FFFFU
| NCO Phase increment[47:32]. More...
#define | XRFDC_NCO_FQWD_UPP_SHIFT 32U
| Freq Word upper shift. More...

## NCO Freq Word[31:16] - NCO Phase increment(nco freq 48-bit)
This register contains bits for frequency control word of the NCO. Read/Write apart from the reserved bits.
#define | XRFDC_NCO_FQWD_MID_MASK 0x0000FFFFU
| NCO Phase increment[31:16]. More...
#define | XRFDC_NCO_FQWD_MID_SHIFT 16U
| Freq Word Mid shift. More...

## NCO Freq Word[15:0] - NCO Phase increment(nco freq 48-bit)
This register contains bits for frequency control word of the NCO. Read/Write apart from the reserved bits.
#define | XRFDC_NCO_FQWD_LOW_MASK 0x0000FFFFU
| NCO Phase increment[15:0]. More...
#define | XRFDC_NCO_FQWD_MASK 0x0000FFFFFFFFFFFFU
| NCO Freq offset[48:0]. More...

## NCO Phase Offset[17:16] - NCO Phase offset
This register contains bits to set NCO Phase offset(18-bit offset added to the phase accumulator). Read/Write apart from the reserved bits.
#define | XRFDC_NCO_PHASE_UPP_MASK 0x00000003U
| NCO Phase offset[17:16]. More...
#define | XRFDC_NCO_PHASE_UPP_SHIFT 16U
| NCO phase upper shift. More...

## NCO Phase Offset[15:0] - NCO Phase offset
This register contains bits to set NCO Phase offset(18-bit offset added to the phase accumulator). Read/Write apart from the reserved bits.
#define | XRFDC_NCO_PHASE_LOW_MASK 0x0000FFFFU
| NCO Phase offset[15:0]. More...
#define | XRFDC_NCO_PHASE_MASK 0x0003FFFFU
| NCO Phase offset[17:0]. More...

## NCO Phase mode - NCO Control setting mode
This register contains bits to set NCO mode of operation. Read/Write apart from the reserved bits.
#define | XRFDC_NCO_PHASE_MOD_MASK 0x00000003U
| NCO mode of operation mask. More...
#define | XRFDC_NCO_PHASE_MOD_4PHASE 0x00000003U
| NCO output 4 successive phase. More...
#define | XRFDC_NCO_PHASE_MOD_EVEN 0x00000001U
| NCO output even phase. More...
#define | XRFDC_NCO_PHASE_MODE_ODD 0x00000002U
| NCO output odd phase. More...

## QMC update - QMC update mode
This register contains bits to Select event source and delay. Read/Write apart from the reserved bits.
#define | XRFDC_QMC_UPDT_MODE_MASK 0x00000007U
| QMC event source selection mask. More...
#define | XRFDC_QMC_UPDT_MODE_GRP 0x00000000U
| QMC event source selection is group. More...
#define | XRFDC_QMC_UPDT_MODE_SLICE 0x00000001U
| QMC event source selection is slice. More...
#define | XRFDC_QMC_UPDT_MODE_TILE 0x00000002U
| QMC event source selection is tile. More...
#define | XRFDC_QMC_UPDT_MODE_SYSREF 0x00000003U
| QMC event source selection is Sysref. More...
#define | XRFDC_QMC_UPDT_MODE_MARKER 0x00000004U
| QMC event source selection is Marker. More...
#define | XRFDC_QMC_UPDT_MODE_FABRIC 0x00000005U
| QMC event source selection is fabric. More...
#define | XRFDC_QMC_UPDT_DLY_MASK 0x00001FF8U
| delay in clk_dp cycles in application of event after arrival More...

## QMC Config - QMC Config register
This register contains bits to enable QMC gain and QMC Phase correction. Read/Write apart from the reserved bits.
#define | XRFDC_QMC_CFG_EN_GAIN_MASK 0x00000001U
| enable QMC gain correction mask More...
#define | XRFDC_QMC_CFG_EN_PHASE_MASK 0x00000002U
| enable QMC Phase correction mask More...
#define | XRFDC_QMC_CFG_PHASE_SHIFT 1U
| QMC config phase shift. More...

## QMC Offset - QMC offset correction
This register contains bits to set QMC offset correction factor. Read/Write apart from the reserved bits.
#define | XRFDC_QMC_OFFST_CRCTN_MASK 0x00000FFFU
| QMC offset correction factor. More...

## QMC Gain - QMC Gain correction
This register contains bits to set QMC gain correction factor. Read/Write apart from the reserved bits.
#define | XRFDC_QMC_GAIN_CRCTN_MASK 0x00003FFFU
| QMC gain correction factor. More...

## QMC Phase - QMC Phase correction
This register contains bits to set QMC phase correction factor. Read/Write apart from the reserved bits.
#define | XRFDC_QMC_PHASE_CRCTN_MASK 0x00000FFFU
| QMC phase correction factor. More...

## Coarse Delay Update - Coarse delay update mode.
This register contains bits to Select event source and delay. Read/Write apart from the reserved bits.
#define | XRFDC_CRSEDLY_UPDT_MODE_MASK 0x00000007U
| Coarse delay event source selection mask. More...
#define | XRFDC_CRSEDLY_UPDT_MODE_GRP 0x00000000U
| Coarse delay event source selection is group. More...
#define | XRFDC_CRSEDLY_UPDT_MODE_SLICE 0x00000001U
| Coarse delay event source selection is slice. More...
#define | XRFDC_CRSEDLY_UPDT_MODE_TILE 0x00000002U
| Coarse delay event source selection is tile. More...
#define | XRFDC_CRSEDLY_UPDT_MODE_SYSREF 0x00000003U
| Coarse delay event source selection is sysref. More...
#define | XRFDC_CRSEDLY_UPDT_MODE_MARKER 0x00000004U
| Coarse delay event source selection is Marker. More...
#define | XRFDC_CRSEDLY_UPDT_MODE_FABRIC 0x00000005U
| Coarse delay event source selection is fabric. More...
#define | XRFDC_CRSEDLY_UPDT_DLY_MASK 0x00001FF8U
| delay in clk_dp cycles in application of event after arrival More...

## Coarse delay Config - Coarse delay select
This register contains bits to select coarse delay. Read/Write apart from the reserved bits.
#define | XRFDC_CRSE_DLY_CFG_MASK 0x00000007U
| Coarse delay select. More...
#define | XRFDC_CRSE_DLY_CFG_MASK_EXT 0x0000003FU
| Extended coarse delay select. More...

## Data Scaling Config - Data Scaling enable
This register contains bits to enable data scaling. Read/Write apart from the reserved bits.
#define | XRFDC_DAT_SCALE_CFG_MASK 0x00000001U
| Enable data scaling. More...
#define | XRFDC_DAT_SCALE_CFG_MASK 0x00000001U
| Enable data scaling. More...

## Switch Matrix Config
This register contains bits to control crossbar switch that select data to mixer block. Read/Write apart from the reserved bits.
#define | XRFDC_SWITCH_MTRX_MASK 0x0000003FU
| Switch matrix mask. More...
#define | XRFDC_SEL_CB_TO_MIX1_MASK 0x00000003U
| Control crossbar switch that select the data to mixer block mux1. More...
#define | XRFDC_SEL_CB_TO_MIX0_MASK 0x0000000CU
| Control crossbar switch that select the data to mixer block mux0. More...
#define | XRFDC_SEL_CB_TO_QMC_MASK 0x00000010U
| Control crossbar switch that select the data to QMC. More...
#define | XRFDC_SEL_CB_TO_DECI_MASK 0x00000020U
| Control crossbar switch that select the data to decimation filter. More...
#define | XRFDC_SEL_CB_TO_MIX0_SHIFT 2U
| Crossbar Mixer0 shift. More...

## Threshold0 Config
This register contains bits to select mode, clear mode and to clear sticky bit. Read/Write apart from the reserved bits.
#define | XRFDC_TRSHD0_EN_MOD_MASK 0x00000003U
| Enable Threshold0 block. More...
#define | XRFDC_TRSHD0_CLR_MOD_MASK 0x00000004U
| Clear mode. More...
#define | XRFDC_TRSHD0_STIKY_CLR_MASK 0x00000008U
| Clear sticky bit. More...

## Threshold0 Average[31:16]
This register contains bits to select Threshold0 under averaging. Read/Write apart from the reserved bits.
#define | XRFDC_TRSHD0_AVG_UPP_MASK 0x0000FFFFU
| Threshold0 under Averaging[31:16]. More...
#define | XRFDC_TRSHD0_AVG_UPP_SHIFT 16U
| Threshold0 Avg upper shift. More...

## Threshold0 Average[15:0]
This register contains bits to select Threshold0 under averaging. Read/Write apart from the reserved bits.
#define | XRFDC_TRSHD0_AVG_LOW_MASK 0x0000FFFFU
| Threshold0 under Averaging[15:0]. More...

## Threshold0 Under threshold
This register contains bits to select Threshold0 under threshold. Read/Write apart from the reserved bits.
#define | XRFDC_TRSHD0_UNDER_MASK 0x00007FFFU
| Threshold0 under Threshold[14:0]. More...

## Threshold0 Over threshold
This register contains bits to select Threshold0 over threshold. Read/Write apart from the reserved bits.
#define | XRFDC_TRSHD0_OVER_MASK 0x00007FFFU
| Threshold0 under Threshold[14:0]. More...

## Threshold1 Config
This register contains bits to select mode, clear mode and to clear sticky bit. Read/Write apart from the reserved bits.
#define | XRFDC_TRSHD1_EN_MOD_MASK 0x00000003U
| Enable Threshold1 block. More...
#define | XRFDC_TRSHD1_CLR_MOD_MASK 0x00000004U
| Clear mode. More...
#define | XRFDC_TRSHD1_STIKY_CLR_MASK 0x00000008U
| Clear sticky bit. More...

## Threshold1 Average[31:16]
This register contains bits to select Threshold1 under averaging. Read/Write apart from the reserved bits.
#define | XRFDC_TRSHD1_AVG_UPP_MASK 0x0000FFFFU
| Threshold1 under Averaging[31:16]. More...
#define | XRFDC_TRSHD1_AVG_UPP_SHIFT 16U
| Threshold1 Avg upper shift. More...

## Threshold1 Average[15:0]
This register contains bits to select Threshold1 under averaging. Read/Write apart from the reserved bits.
#define | XRFDC_TRSHD1_AVG_LOW_MASK 0x0000FFFFU
| Threshold1 under Averaging[15:0]. More...

## Threshold1 Under threshold
This register contains bits to select Threshold1 under threshold. Read/Write apart from the reserved bits.
#define | XRFDC_TRSHD1_UNDER_MASK 0x00007FFFU
| Threshold1 under Threshold[14:0]. More...

## Threshold1 Over threshold
This register contains bits to select Threshold1 over threshold. Read/Write apart from the reserved bits.
#define | XRFDC_TRSHD1_OVER_MASK 0x00007FFFU
| Threshold1 under Threshold[14:0]. More...

## FrontEnd Data Control
This register contains bits to select raw data and cal coefficient to be streamed to memory. Read/Write apart from the reserved bits.
#define | XRFDC_FEND_DAT_CTRL_MASK 0x000000FFU
| raw data and cal coefficient to be streamed to memory More...

## TI Digital Correction Block control0
This register contains bits for Time Interleaved digital correction block gain and offset correction. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_CTRL0_MASK 0x0000FFFFU
| TI DCB gain and offset correction. More...
#define | XRFDC_TI_DCB_MODE_MASK 0x00007800U
| TI DCB Mode mask. More...

## TI Digital Correction Block control1
This register contains bits for Time Interleaved digital correction block gain and offset correction. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_CTRL1_MASK 0x00001FFFU
| TI DCB gain and offset correction. More...

## TI Digital Correction Block control2
This register contains bits for Time Interleaved digital correction block gain and offset correction. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_CTRL2_MASK 0x00001FFFU
| TI DCB gain and offset correction. More...

## TI Time Skew control0
This register contains bits for Time skew correction control bits0(enables, mode, multiplier factors, debug). Read/Write apart from the reserved bits.
#define | XRFDC_TI_TISK_EN_MASK 0x00000001U
| Block Enable. More...
#define | XRFDC_TI_TISK_MODE_MASK 0x00000002U
| Mode (2G/4G) More...
#define | XRFDC_TI_TISK_ZONE_MASK 0x00000004U
| Specifies Nyquist zone. More...
#define | XRFDC_TI_TISK_CHOP_EN_MASK 0x00000008U
| enable chopping mode More...
#define | XRFDC_TI_TISK_MU_CM_MASK 0x000000F0U
| Constant mu_cm multiplying common mode path. More...
#define | XRFDC_TI_TISK_MU_DF_MASK 0x00000F00U
| Constant mu_df multiplying differential path. More...
#define | XRFDC_TI_TISK_DBG_CTRL_MASK 0x0000F000U
| Debug control. More...
#define | XRFDC_TI_TISK_DBG_UPDT_RT_MASK 0x00001000U
| Debug update rate. More...
#define | XRFDC_TI_TISK_DITH_DLY_MASK 0x0000E000U
| Programmable delay on dither path to match data path. More...
#define | XRFDC_TISK_ZONE_SHIFT 2U
| Nyquist zone shift. More...
#define | XRFDC_TISK_EN_MASK 0x00000001U
| Block Enable. More...
#define | XRFDC_TISK_MODE_MASK 0x00000002U
| Mode (2G/4G) More...
#define | XRFDC_TISK_ZONE_MASK 0x00000004U
| Specifies Nyquist zone. More...
#define | XRFDC_TISK_CHOP_EN_MASK 0x00000008U
| enable chopping mode More...
#define | XRFDC_TISK_MU_CM_MASK 0x000000F0U
| Constant mu_cm multiplying common mode path. More...
#define | XRFDC_TISK_MU_DF_MASK 0x00000F00U
| Constant mu_df multiplying differential path. More...
#define | XRFDC_TISK_DBG_CTRL_MASK 0x0000F000U
| Debug control. More...
#define | XRFDC_TISK_DBG_UPDT_RT_MASK 0x00001000U
| Debug update rate. More...
#define | XRFDC_TISK_DITH_DLY_MASK 0x0000E000U
| Programmable delay on dither path to match data path. More...

## DAC MC Config0
This register contains bits for enable/disable shadow logic , Nyquist zone selection, enable full speed clock, Programmable delay.
#define | XRFDC_MC_CFG0_MIX_MODE_MASK 0x00000002U
| Enable Mixing mode. More...
#define | XRFDC_MC_CFG0_MIX_MODE_SHIFT 1U
| Mix mode shift. More...

## TI Time Skew control1
This register contains bits for Time skew correction control bits1 (Deadzone Parameters). Read/Write apart from the reserved bits.
#define | XRFDC_TISK_DZ_MIN_VAL_MASK 0x000000FFU
| Deadzone min. More...
#define | XRFDC_TISK_DZ_MAX_VAL_MASK 0x0000FF00U
| Deadzone max. More...

## TI Time Skew control2
This register contains bits for Time skew correction control bits2 (Filter parameters). Read/Write apart from the reserved bits.
#define | XRFDC_TISK_MU0_MASK 0x0000000FU
| Filter0 multiplying factor. More...
#define | XRFDC_TISK_BYPASS0_MASK 0x00000080U
| ByPass filter0. More...
#define | XRFDC_TISK_MU1_MASK 0x00000F00U
| Filter1 multiplying factor. More...
#define | XRFDC_TISK_BYPASS1_MASK 0x00008000U
| Filter1 multiplying factor. More...

## TI Time Skew control3
This register contains bits for Time skew control settling time following code update. Read/Write apart from the reserved bits.
#define | XRFDC_TISK_SETTLE_MASK 0x000000FFU
| Settling time following code update. More...

## TI Time Skew control4
This register contains bits for Time skew control setting time following code update. Read/Write apart from the reserved bits.
#define | XRFDC_TISK_CAL_PRI_MASK 0x00000001U
#define | XRFDC_TISK_DITH_INV_MASK 0x00000FF0U

## TI Time Skew DAC0
This register contains bits for Time skew DAC cal code of subadc ch0. Read/Write apart from the reserved bits.
#define | XRFDC_TISK_DAC0_CODE_MASK 0x000000FFU
| Code to correction DAC of subadc ch0 front end switch0. More...
#define | XRFDC_TISK_DAC0_OVRID_EN_MASK 0x00008000U
| override enable More...

## TI Time Skew DAC1
This register contains bits for Time skew DAC cal code of subadc ch1. Read/Write apart from the reserved bits.
#define | XRFDC_TISK_DAC1_CODE_MASK 0x000000FFU
| Code to correction DAC of subadc ch1 front end switch0. More...
#define | XRFDC_TISK_DAC1_OVRID_EN_MASK 0x00008000U
| override enable More...

## TI Time Skew DAC2
This register contains bits for Time skew DAC cal code of subadc ch2. Read/Write apart from the reserved bits.
#define | XRFDC_TISK_DAC2_CODE_MASK 0x000000FFU
| Code to correction DAC of subadc ch2 front end switch0. More...
#define | XRFDC_TISK_DAC2_OVRID_EN_MASK 0x00008000U
| override enable More...

## TI Time Skew DAC3
This register contains bits for Time skew DAC cal code of subadc ch3. Read/Write apart from the reserved bits.
#define | XRFDC_TISK_DAC3_CODE_MASK 0x000000FFU
| Code to correction DAC of subadc ch3 front end switch0. More...
#define | XRFDC_TISK_DAC3_OVRID_EN_MASK 0x00008000U
| override enable More...

## TI Time Skew DACP0
This register contains bits for Time skew DAC cal code of subadc ch0. Read/Write apart from the reserved bits.
#define | XRFDC_TISK_DACP0_CODE_MASK 0x000000FFU
| Code to correction DAC of subadc ch0 front end switch1. More...
#define | XRFDC_TISK_DACP0_OVRID_EN_MASK 0x00008000U
| override enable More...

## TI Time Skew DACP1
This register contains bits for Time skew DAC cal code of subadc ch1. Read/Write apart from the reserved bits.
#define | XRFDC_TISK_DACP1_CODE_MASK 0x000000FFU
| Code to correction DAC of subadc ch1 front end switch1. More...
#define | XRFDC_TISK_DACP1_OVRID_EN_MASK 0x00008000U
| override enable More...

## TI Time Skew DACP2
This register contains bits for Time skew DAC cal code of subadc ch2. Read/Write apart from the reserved bits.
#define | XRFDC_TISK_DACP2_CODE_MASK 0x000000FFU
| Code to correction DAC of subadc ch2 front end switch1. More...
#define | XRFDC_TISK_DACP2_OVRID_EN_MASK 0x00008000U
| override enable More...

## TI Time Skew DACP3
This register contains bits for Time skew DAC cal code of subadc ch3. Read/Write apart from the reserved bits.
#define | XRFDC_TISK_DACP3_CODE_MASK 0x000000FFU
| Code to correction DAC of subadc ch3 front end switch1. More...
#define | XRFDC_TISK_DACP3_OVRID_EN_MASK 0x00008000U
| override enable More...

## SubDRP ADC0 address
This register contains the sub-drp address of the target register. Read/Write apart from the reserved bits.
#define | XRFDC_SUBDRP_ADC0_ADDR_MASK 0x000000FFU
| sub-drp0 address More...

## SubDRP ADC0 Data
This register contains the sub-drp data of the target register. Read/Write apart from the reserved bits.
#define | XRFDC_SUBDRP_ADC0_DAT_MASK 0x0000FFFFU
| sub-drp0 data for read or write transaction More...

## SubDRP ADC1 address
This register contains the sub-drp address of the target register. Read/Write apart from the reserved bits.
#define | XRFDC_SUBDRP_ADC1_ADDR_MASK 0x000000FFU
| sub-drp1 address More...

## SubDRP ADC1 Data
This register contains the sub-drp data of the target register. Read/Write apart from the reserved bits.
#define | XRFDC_SUBDRP_ADC1_DAT_MASK 0x0000FFFFU
| sub-drp1 data for read or write transaction More...

## SubDRP ADC2 address
This register contains the sub-drp address of the target register. Read/Write apart from the reserved bits.
#define | XRFDC_SUBDRP_ADC2_ADDR_MASK 0x000000FFU
| sub-drp2 address More...

## SubDRP ADC2 Data
This register contains the sub-drp data of the target register. Read/Write apart from the reserved bits.
#define | XRFDC_SUBDRP_ADC2_DAT_MASK 0x0000FFFFU
| sub-drp2 data for read or write transaction More...

## SubDRP ADC3 address
This register contains the sub-drp address of the target register. Read/Write apart from the reserved bits.
#define | XRFDC_SUBDRP_ADC3_ADDR_MASK 0x000000FFU
| sub-drp3 address More...

## SubDRP ADC3 Data
This register contains the sub-drp data of the target register. Read/Write apart from the reserved bits.
#define | XRFDC_SUBDRP_ADC3_DAT_MASK 0x0000FFFFU
| sub-drp3 data for read or write transaction More...

## RX MC PWRDWN
This register contains the static configuration bits of ADC(RX) analog. Read/Write apart from the reserved bits.
#define | XRFDC_RX_MC_PWRDWN_MASK 0x0000FFFFU
| RX MC power down. More...

## RX MC Config0
This register contains the static configuration bits of ADC(RX) analog. Read/Write apart from the reserved bits.
#define | XRFDC_RX_MC_CFG0_MASK 0x0000FFFFU
| RX MC config0. More...
#define | XRFDC_RX_MC_CFG0_CM_MASK 0x00000040U
| Coupling mode mask. More...
#define | XRFDC_RX_MC_CFG0_IM3_DITH_MASK 0x00000020U
| IM3 Dither Enable mode mask. More...
#define | XRFDC_RX_MC_CFG0_IM3_DITH_SHIFT 5U
| IM3 Dither Enable mode shift. More...

## RX MC Config1
This register contains the static configuration bits of ADC(RX) analog. Read/Write apart from the reserved bits.
#define | XRFDC_RX_MC_CFG1_MASK 0x0000FFFFU
| RX MC Config1. More...

## RX MC Config2
This register contains the static configuration bits of ADC(RX) analog. Read/Write apart from the reserved bits.
#define | XRFDC_RX_MC_CFG2_MASK 0x0000FFFFU
| RX MC Config2. More...

## RX Pair MC Config0
This register contains the RX Pair (RX0 and RX1 or RX2 and RX3)static configuration bits of ADC(RX) analog. Read/Write apart from the reserved bits.
#define | XRFDC_RX_PR_MC_CFG0_MASK 0x0000FFFFU
| RX Pair MC Config0. More...

## RX Pair MC Config1
This register contains the RX Pair (RX0 and RX1 or RX2 and RX3)static configuration bits of ADC(RX) analog. Read/Write apart from the reserved bits.
#define | XRFDC_RX_PR_MC_CFG1_MASK 0x0000FFFFU
| RX Pair MC Config1. More...

## TI DCB Status0 BG
This register contains the subadc ch0 ocb1 BG offset correction factor value. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS0_BG_MASK 0x0000FFFFU
| DCB Status0 BG. More...

## TI DCB Status0 FG
This register contains the subadc ch0 ocb2 FG offset correction factor value(read and write). Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS0_FG_MASK 0x0000FFFFU
| DCB Status0 FG. More...

## TI DCB Status1 BG
This register contains the subadc ch1 ocb1 BG offset correction factor value. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS1_BG_MASK 0x0000FFFFU
| DCB Status1 BG. More...

## TI DCB Status1 FG
This register contains the subadc ch1 ocb2 FG offset correction factor value(read and write). Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS1_FG_MASK 0x0000FFFFU
| DCB Status1 FG. More...

## TI DCB Status2 BG
This register contains the subadc ch2 ocb1 BG offset correction factor value. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS2_BG_MASK 0x0000FFFFU
| DCB Status2 BG. More...

## TI DCB Status2 FG
This register contains the subadc ch2 ocb2 FG offset correction factor value(read and write). Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS2_FG_MASK 0x0000FFFFU
| DCB Status2 FG. More...

## TI DCB Status3 BG
This register contains the subadc ch3 ocb1 BG offset correction factor value. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS3_BG_MASK 0x0000FFFFU
| DCB Status3 BG. More...

## TI DCB Status3 FG
This register contains the subadc ch3 ocb2 FG offset correction factor value(read and write). Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS3_FG_MASK 0x0000FFFFU
| DCB Status3 FG. More...

## TI DCB Status4 MSB
This register contains the DCB status. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS4_MSB_MASK 0x0000FFFFU
| read the status of gcb acc0 msb bits(subadc chan0) More...

## TI DCB Status4 LSB
This register contains the DCB Status. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS4_LSB_MASK 0x0000FFFFU
| read the status of gcb acc0 lsb bits(subadc chan0) More...

## TI DCB Status5 MSB
This register contains the DCB status. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS5_MSB_MASK 0x0000FFFFU
| read the status of gcb acc1 msb bits(subadc chan1) More...

## TI DCB Status5 LSB
This register contains the DCB Status. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS5_LSB_MASK 0x0000FFFFU
| read the status of gcb acc1 lsb bits(subadc chan1) More...

## TI DCB Status6 MSB
This register contains the DCB status. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS6_MSB_MASK 0x0000FFFFU
| read the status of gcb acc2 msb bits(subadc chan2) More...

## TI DCB Status6 LSB
This register contains the DCB Status. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS6_LSB_MASK 0x0000FFFFU
| read the status of gcb acc2 lsb bits(subadc chan2) More...

## TI DCB Status7 MSB
This register contains the DCB status. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS7_MSB_MASK 0x0000FFFFU
| read the status of gcb acc3 msb bits(subadc chan3) More...

## TI DCB Status7 LSB
This register contains the DCB Status. Read/Write apart from the reserved bits.
#define | XRFDC_TI_DCB_STS7_LSB_MASK 0x0000FFFFU
| read the status of gcb acc3 lsb bits(subadc chan3) More...

## PLL_REFDIV
This register contains the bits for Reference Clock Divider
#define | XRFDC_REFCLK_DIV_MASK 0x1FU
#define | XRFDC_REFCLK_DIV_1_MASK 0x10U
| Mask for Div1. More...
#define | XRFDC_REFCLK_DIV_2_MASK 0x0U
| Mask for Div2. More...
#define | XRFDC_REFCLK_DIV_3_MASK 0x1U
| Mask for Div3. More...
#define | XRFDC_REFCLK_DIV_4_MASK 0x2U
| Mask for Div4. More...

## FIFO Latency
This register contains bits for result, key and done flag. Read/Write apart from the reserved bits.
#define | XRFDC_FIFO_LTNCY_RES_MASK 0x00000FFFU
| Latency measurement result. More...
#define | XRFDC_FIFO_LTNCY_KEY_MASK 0x00004000U
| Latency measurement result identification key. More...
#define | XRFDC_FIFO_LTNCY_DONE_MASK 0x00008000U
| Latency measurement done flag. More...

## Decoder Control
This register contains Unary Decoder/Randomizer settings to use.
#define | XRFDC_DEC_CTRL_MODE_MASK 0x00000007U
| Decoder mode. More...

## HSCOM Power state mask
This register contains HSCOM_PWR to check powerup_state.
#define | XRFDC_HSCOM_PWR_STATE_MASK 0x0000FFFFU
| powerup state mask More...

## Interpolation Control
This register contains Interpolation filter modes.
#define | XRFDC_INTERP_MODE_MASK 0x00000077U
| Interp filter mask. More...
#define | XRFDC_INTERP_MODE_I_MASK 0x00000007U
| Interp filter I. More...
#define | XRFDC_INTERP_MODE_Q_SHIFT 4U
| Interp mode Q shift. More...
#define | XRFDC_INTERP_MODE_MASK_EXT 0x00003F3FU
| Interp filter mask. More...
#define | XRFDC_INTERP_MODE_I_MASK_EXT 0x0000003FU
| Interp filter I. More...
#define | XRFDC_INTERP_MODE_Q_SHIFT_EXT 8U
| Interp mode Q shift. More...

## Tile Reset
This register contains Tile reset bit.
#define | XRFDC_TILE_RESET_MASK 0x00000001U
| Tile reset mask. More...

## Status register
This register contains common status bits.
#define | XRFDC_PWR_UP_STAT_MASK 0x00000004U
| Power Up state mask. More...
#define | XRFDC_PWR_UP_STAT_SHIFT 2U
| PowerUp status shift. More...
#define | XRFDC_PLL_LOCKED_MASK 0x00000008U
| PLL Locked mask. More...
#define | XRFDC_PLL_LOCKED_SHIFT 3U
| PLL locked shift. More...

## Restart State register
This register contains Start and End state bits.
#define | XRFDC_PWR_STATE_MASK 0x0000FFFFU
| State mask. More...
#define | XRFDC_RSR_START_SHIFT 8U
| Start state shift. More...

## Clock Detect register
This register contains Start and End state bits.
#define | XRFDC_CLOCK_DETECT_MASK 0x0000FFFFU
| Clock detect mask. More...

## Common interrupt enable register
This register contains bits to enable interrupt for ADC and DAC tiles.
#define | XRFDC_EN_INTR_DAC_TILE0_MASK 0x00000001U
| DAC Tile0 interrupt enable mask. More...
#define | XRFDC_EN_INTR_DAC_TILE1_MASK 0x00000002U
| DAC Tile1 interrupt enable mask. More...
#define | XRFDC_EN_INTR_DAC_TILE2_MASK 0x00000004U
| DAC Tile2 interrupt enable mask. More...
#define | XRFDC_EN_INTR_DAC_TILE3_MASK 0x00000008U
| DAC Tile3 interrupt enable mask. More...
#define | XRFDC_EN_INTR_ADC_TILE0_MASK 0x00000010U
| ADC Tile0 interrupt enable mask. More...
#define | XRFDC_EN_INTR_ADC_TILE1_MASK 0x00000020U
| ADC Tile1 interrupt enable mask. More...
#define | XRFDC_EN_INTR_ADC_TILE2_MASK 0x00000040U
| ADC Tile2 interrupt enable mask. More...
#define | XRFDC_EN_INTR_ADC_TILE3_MASK 0x00000080U
| ADC Tile3 interrupt enable mask. More...

## interrupt enable register
This register contains bits to enable interrupt for blocks.
#define | XRFDC_EN_INTR_SLICE_MASK 0x0000000FU
| Slice intr mask. More...
#define | XRFDC_EN_INTR_SLICE0_MASK 0x00000001U
| slice0 interrupt enable mask More...
#define | XRFDC_EN_INTR_SLICE1_MASK 0x00000002U
| slice1 interrupt enable mask More...
#define | XRFDC_EN_INTR_SLICE2_MASK 0x00000004U
| slice2 interrupt enable mask More...
#define | XRFDC_EN_INTR_SLICE3_MASK 0x00000008U
| slice3 interrupt enable mask More...
#define | XRFDC_INTR_COMMON_MASK 0x00000010U
| Common interrupt enable mask. More...

## Converter(X) interrupt register
This register contains bits to enable different interrupts for block X.
#define | XRFDC_INTR_OVR_RANGE_MASK 0x00000008U
| Over Range interrupt mask. More...
#define | XRFDC_INTR_OVR_VOLTAGE_MASK 0x00000004U
| Over Voltage interrupt mask. More...
#define | XRFDC_INTR_FIFO_OVR_MASK 0x00008000U
| FIFO OF mask. More...
#define | XRFDC_INTR_DAT_OVR_MASK 0x00004000U
| Data OF mask. More...
#define | XRFDC_INTR_CMODE_OVR_MASK 0x00040000U
| Common mode OV mask. More...
#define | XRFDC_INTR_CMODE_UNDR_MASK 0x00080000U
| Common mode UV mask. More...

## Multiband config register
This register contains bits to configure multiband.
#define | XRFDC_EN_MB_MASK 0x00000008U
| multi-band adder mask More...
#define | XRFDC_EN_MB_SHIFT 3U /** <Enable Multiband shift */
#define | XRFDC_ALT_BOND_MASK 0x0100 /** <Alt bondout mask */
#define | XRFDC_ALT_BOND_SHIFT 8U /** <Alt bondout shift */

## Invsinc control register
This register contains bits to configure Invsinc.
#define | XRFDC_EN_INVSINC_MASK 0x00000001U
| invsinc enable mask More...
#define | XRFDC_MODE_INVSINC_MASK 0x00000003U
| invsinc mode mask More...

## Macro Definition Documentation

#define XRFDC_ADC0_SUBDRP_ADDR_OFFSET 0x198U

subadc0, sub-drp address of target Register

#define XRFDC_ADC0_SUBDRP_DAT_OFFSET 0x19CU

subadc0, sub-drp data of target Register

#define XRFDC_ADC1_SUBDRP_ADDR_OFFSET 0x1A0U

subadc1, sub-drp address of target Register

#define XRFDC_ADC1_SUBDRP_DAT_OFFSET 0x1A4U

subadc1, sub-drp data of target Register

#define XRFDC_ADC2_SUBDRP_ADDR_OFFSET 0x1A8U

subadc2, sub-drp address of target Register

#define XRFDC_ADC2_SUBDRP_DAT_OFFSET 0x1ACU

subadc2, sub-drp data of target Register

#define XRFDC_ADC3_SUBDRP_ADDR_OFFSET 0x1B0U

subadc3, sub-drp address of target Register

#define XRFDC_ADC3_SUBDRP_DAT_OFFSET 0x1B4U

subadc3, sub-drp data of target Register

#define XRFDC_ADC_CRSE_DLY_CFG_OFFSET 0x0E0U

ADC Coarse delay Config Register.

Referenced by XRFdc_GetCoarseDelaySettings(), and XRFdc_SetCoarseDelaySettings().

#define XRFDC_ADC_CRSE_DLY_UPDT_OFFSET 0x0DCU

ADC Coarse Delay Update Register.

Referenced by XRFdc_GetCoarseDelaySettings(), XRFdc_SetCoarseDelaySettings(), and XRFdc_UpdateEvent().

#define XRFDC_ADC_DAC_MC_CFG0_OFFSET 0x1C4U

ADC/DAC Static configuration bits for ADC/DAC analog Register.

Referenced by XRFdc_GetDither(), XRFdc_SetDACVOP(), and XRFdc_SetDither().

#define XRFDC_ADC_DAC_MC_CFG1_OFFSET 0x1C8U

ADC/DAC Static configuration bits for ADC/DAC analog Register.

#define XRFDC_ADC_DAC_MC_CFG2_OFFSET 0x1CCU

ADC/DAC Static configuration bits for ADC/DAC analog Register.

Referenced by XRFdc_GetDACCompMode(), XRFdc_GetOutputCurr(), XRFdc_SetDACCompMode(), and XRFdc_SetDACVOP().

#define XRFDC_ADC_DAT_IMR_MASK 0x000000FFU

ADC DataPath mask.

Referenced by XRFdc_GetEnabledInterrupts(), and XRFdc_IntrEnable().

#define XRFDC_ADC_DAT_PATH_ISR_MASK 0x000000FFU

ADC Data Path Overflow.

Referenced by XRFdc_GetIntrStatus().

#define XRFDC_ADC_DAT_SCAL_CFG_OFFSET 0x0E4U

ADC Data Scaling Config Register.

#define XRFDC_ADC_DEBUG_RST_OFFSET 0x004U

ADC Debug Reset Register.

#define XRFDC_ADC_DEC_IMR_OFFSET 0x034U

ADC Decoder interface IMR Register.

Referenced by XRFdc_GetEnabledInterrupts(), XRFdc_IntrDisable(), and XRFdc_IntrEnable().

#define XRFDC_ADC_DEC_ISR_OFFSET 0x030U

ADC Decoder interface ISR Register.

Referenced by XRFdc_GetIntrStatus(), and XRFdc_IntrClr().

#define XRFDC_ADC_DECI_CONFIG_OFFSET 0x040U

ADC Decimation Config Register.

Referenced by XRFdc_SetDecimationFactor(), and XRFdc_SetMixerSettings().

#define XRFDC_ADC_DECI_MODE_OFFSET 0x044U

ADC Decimation mode Register.

Referenced by XRFdc_GetDecimationFactor(), and XRFdc_SetDecimationFactor().

#define XRFDC_ADC_FAB_RATE_RD_MASK 0x00000F00U

ADC FIFO Read Number of Words per clock.

Referenced by XRFdc_SetFabRdVldWords().

#define XRFDC_ADC_FAB_RATE_WR_MASK 0x0000000FU

ADC FIFO Write Number of Words per clock.

Referenced by XRFdc_GetFabRdVldWords(), XRFdc_GetFabWrVldWords(), and XRFdc_SetDecimationFactor().

#define XRFDC_ADC_FABRIC_DBG_OFFSET 0x018U

ADC Fabric Debug Register.

#define XRFDC_ADC_FABRIC_IMR_OFFSET 0x014U

ADC Fabric IMR Register.

Referenced by XRFdc_GetEnabledInterrupts(), XRFdc_IntrDisable(), and XRFdc_IntrEnable().

#define XRFDC_ADC_FABRIC_ISR_OFFSET 0x010U

ADC Fabric ISR Register.

Referenced by XRFdc_GetIntrStatus(), and XRFdc_IntrClr().

#define XRFDC_ADC_FABRIC_OFFSET 0x00CU

ADC Fabric Register.

#define XRFDC_ADC_FABRIC_RATE_OFFSET 0x008U

ADC Fabric Rate Register.

Referenced by XRFdc_GetFabRdVldWords(), XRFdc_GetFabWrVldWords(), XRFdc_SetDataPathMode(), XRFdc_SetDecimationFactor(), XRFdc_SetFabRdVldWords(), XRFdc_SetFabWrVldWords(), and XRFdc_SetInterpolationFactor().

#define XRFDC_ADC_FEND_DAT_CRL_OFFSET 0x140U

ADC Front end Data Control Register.

#define XRFDC_ADC_FIFO_LTNC_CRL_OFFSET 0x020U

ADC FIFO Latency Control Register.

#define XRFDC_ADC_FIFO_LTNCY_LB_OFFSET 0x280U

ADC FIFO Latency measurement LSB Register.

#define XRFDC_ADC_FIFO_LTNCY_MB_OFFSET 0x284U

ADC FIFO Latency measurement MSB Register.

#define XRFDC_ADC_MXR_CFG0_OFFSET 0x080U

ADC I channel mixer config Register.

Referenced by XRFdc_GetMixerSettings().

#define XRFDC_ADC_MXR_CFG1_OFFSET 0x084U

ADC Q channel mixer config Register.

Referenced by XRFdc_GetMixerSettings().

#define XRFDC_ADC_NCO_FQWD_LOW_OFFSET 0x09CU

ADC NCO Frequency Word[15:0] Register.

Referenced by XRFdc_GetMixerSettings(), and XRFdc_SetMixerSettings().

#define XRFDC_ADC_NCO_FQWD_MID_OFFSET 0x098U

ADC NCO Frequency Word[31:16] Register.

Referenced by XRFdc_GetMixerSettings(), and XRFdc_SetMixerSettings().

#define XRFDC_ADC_NCO_FQWD_UPP_OFFSET 0x094U

ADC NCO Frequency Word[47:32] Register.

Referenced by XRFdc_GetMixerSettings(), and XRFdc_SetMixerSettings().

#define XRFDC_ADC_NCO_PHASE_MOD_OFFSET 0x0A8U

ADC NCO Phase Mode Register.

Referenced by XRFdc_SetMixerSettings().

#define XRFDC_ADC_RX_MC_PWRDWN_OFFSET 0x1C0U

ADC Static configuration bits for ADC(RX) analog Register.

#define XRFDC_ADC_RXPR_MC_CFG0_OFFSET 0x1D0U

ADC RX Pair static Configuration Register.

Referenced by XRFdc_GetLinkCoupling().

#define XRFDC_ADC_RXPR_MC_CFG1_OFFSET 0x1D4U

ADC RX Pair static Configuration Register.

#define XRFDC_ADC_SIG_DETECT_CTRL_OFFSET 0x114

ADC Signal Detector Control.

Referenced by XRFdc_GetSignalDetector(), and XRFdc_SetSignalDetector().

#define XRFDC_ADC_SIG_DETECT_MAGN_OFFSET 0x130

ADC Signal Detector Magintude.

#define XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_OFF_OFFSET 0x120

ADC Signal Detector Threshold 0 off Counter.

#define XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_ON_OFFSET 0x11C

ADC Signal Detector Threshold 0 on Counter.

#define XRFDC_ADC_SIG_DETECT_THRESHOLD0_LEVEL_OFFSET 0x118

ADC Signal Detector Threshold 0.

Referenced by XRFdc_GetSignalDetector(), and XRFdc_SetSignalDetector().

#define XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_OFF_OFFSET 0x12C

ADC Signal Detector Threshold 1 off Counter.

#define XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_ON_OFFSET 0x128

ADC Signal Detector Threshold 1 on Counter.

#define XRFDC_ADC_SIG_DETECT_THRESHOLD1_LEVEL_OFFSET 0x124

ADC Signal Detector Threshold 1.

Referenced by XRFdc_GetSignalDetector(), and XRFdc_SetSignalDetector().

#define XRFDC_ADC_SWITCH_MATRX_OFFSET 0x0E8U

ADC Switch Matrix Config Register.

#define XRFDC_ADC_TI_DCB_CRL0_OFFSET 0x144U

ADC Time Interleaved digital correction block gain control0 Register.

Referenced by XRFdc_GetCalibrationMode(), and XRFdc_SetCalibrationMode().

#define XRFDC_ADC_TI_DCB_CRL1_OFFSET 0x148U

ADC Time Interleaved digital correction block gain control1 Register.

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_ADC_TI_DCB_CRL2_OFFSET 0x14CU

ADC Time Interleaved digital correction block gain control2 Register.

Referenced by XRFdc_DisableCoefficientsOverride(), and XRFdc_SetCalCoefficients().

#define XRFDC_ADC_TI_DCB_CRL3_OFFSET 0x150U

ADC Time Interleaved digital correction block gain control3 Register.

Referenced by XRFdc_DisableCoefficientsOverride(), and XRFdc_SetCalCoefficients().

#define XRFDC_ADC_TI_DCBSTS0_BG_OFFSET 0x200U

ADC DCB Status0 BG Register.

#define XRFDC_ADC_TI_DCBSTS0_FG_OFFSET 0x204U

ADC DCB Status0 FG Register.

#define XRFDC_ADC_TI_DCBSTS1_BG_OFFSET 0x208U

ADC DCB Status1 BG Register.

#define XRFDC_ADC_TI_DCBSTS1_FG_OFFSET 0x20CU

ADC DCB Status1 FG Register.

#define XRFDC_ADC_TI_DCBSTS2_BG_OFFSET 0x210U

ADC DCB Status2 BG Register.

#define XRFDC_ADC_TI_DCBSTS2_FG_OFFSET 0x214U

ADC DCB Status2 FG Register.

#define XRFDC_ADC_TI_DCBSTS3_BG_OFFSET 0x218U

ADC DCB Status3 BG Register.

#define XRFDC_ADC_TI_DCBSTS3_FG_OFFSET 0x21CU

ADC DCB Status3 FG Register.

#define XRFDC_ADC_TI_DCBSTS4_LB_OFFSET 0x224U

ADC DCB Status4 LSB Register.

#define XRFDC_ADC_TI_DCBSTS4_MB_OFFSET 0x220U

ADC DCB Status4 MSB Register.

#define XRFDC_ADC_TI_DCBSTS5_LB_OFFSET 0x22CU

ADC DCB Status5 LSB Register.

#define XRFDC_ADC_TI_DCBSTS5_MB_OFFSET 0x228U

ADC DCB Status5 MSB Register.

#define XRFDC_ADC_TI_DCBSTS6_LB_OFFSET 0x234U

ADC DCB Status6 LSB Register.

#define XRFDC_ADC_TI_DCBSTS6_MB_OFFSET 0x230U

ADC DCB Status6 MSB Register.

#define XRFDC_ADC_TI_DCBSTS7_LB_OFFSET 0x23CU

ADC DCB Status7 LSB Register.

#define XRFDC_ADC_TI_DCBSTS7_MB_OFFSET 0x238U

ADC DCB Status7 MSB Register.

#define XRFDC_ADC_TI_TISK_CRL0_OFFSET 0x154U

ADC Time skew correction control bits0 Register.

Referenced by XRFdc_GetNyquistZone(), and XRFdc_SetNyquistZone().

#define XRFDC_ADC_TI_TISK_CRL1_OFFSET 0x158U

ADC Time skew correction control bits1 Register.

#define XRFDC_ADC_TI_TISK_CRL2_OFFSET 0x15CU

ADC Time skew correction control bits2 Register.

#define XRFDC_ADC_TI_TISK_CRL3_OFFSET 0x160U

ADC Time skew correction control bits3 Register.

#define XRFDC_ADC_TI_TISK_CRL4_OFFSET 0x164U

ADC Time skew correction control bits4 Register.

#define XRFDC_ADC_TI_TISK_DAC0_OFFSET 0x168U

ADC Time skew DAC cal code of subadc ch0 Register.

#define XRFDC_ADC_TI_TISK_DAC1_OFFSET 0x16CU

ADC Time skew DAC cal code of subadc ch1 Register.

#define XRFDC_ADC_TI_TISK_DAC2_OFFSET 0x170U

ADC Time skew DAC cal code of subadc ch2 Register.

#define XRFDC_ADC_TI_TISK_DAC3_OFFSET 0x174U

ADC Time skew DAC cal code of subadc ch3 Register.

#define XRFDC_ADC_TI_TISK_DACP0_OFFSET 0x178U

ADC Time skew DAC cal code of subadc ch0 Register.

#define XRFDC_ADC_TI_TISK_DACP1_OFFSET 0x17CU

ADC Time skew DAC cal code of subadc ch1 Register.

#define XRFDC_ADC_TI_TISK_DACP2_OFFSET 0x180U

ADC Time skew DAC cal code of subadc ch2 Register.

#define XRFDC_ADC_TI_TISK_DACP3_OFFSET 0x184U

ADC Time skew DAC cal code of subadc ch3 Register.

#define XRFDC_ADC_TRSHD0_AVG_LO_OFFSET 0x0F4U

ADC Threshold0 Average[15:0] Register.

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_ADC_TRSHD0_AVG_UP_OFFSET 0x0F0U

ADC Threshold0 Average[31:16] Register.

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_ADC_TRSHD0_CFG_OFFSET 0x0ECU

ADC Threshold0 Config Register.

Referenced by XRFdc_GetThresholdSettings(), XRFdc_SetThresholdClrMode(), XRFdc_SetThresholdSettings(), and XRFdc_ThresholdStickyClear().

#define XRFDC_ADC_TRSHD0_OVER_OFFSET 0x0FCU

ADC Threshold0 Over Threshold Register.

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_ADC_TRSHD0_UNDER_OFFSET 0x0F8U

ADC Threshold0 Under Threshold Register.

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_ADC_TRSHD1_AVG_LO_OFFSET 0x108U

ADC Threshold1 Average[15:0] Register.

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_ADC_TRSHD1_AVG_UP_OFFSET 0x104U

ADC Threshold1 Average[31:16] Register.

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_ADC_TRSHD1_CFG_OFFSET 0x100U

ADC Threshold1 Config Register.

Referenced by XRFdc_GetThresholdSettings(), XRFdc_SetThresholdClrMode(), XRFdc_SetThresholdSettings(), and XRFdc_ThresholdStickyClear().

#define XRFDC_ADC_TRSHD1_OVER_OFFSET 0x110U

ADC Threshold1 Over Threshold Register.

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_ADC_TRSHD1_UNDER_OFFSET 0x10CU

ADC Threshold1 Under Threshold Register.

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_ADC_UPDATE_DYN_OFFSET 0x01CU

ADC Update Dynamic Register.

Referenced by XRFdc_SetCoarseDelaySettings(), XRFdc_SetMixerSettings(), XRFdc_SetQMCSettings(), and XRFdc_UpdateEvent().

#define XRFDC_ADC_UPDT_CRSE_DLY_MASK 0x00000008U

ADC Trigger a update event apply to Coarse delay_DCONFIG reg.

Referenced by XRFdc_SetCoarseDelaySettings().

#define XRFDC_CAL_FREEZE_CAL_MASK 0x1U

Calibration freeze enable mask.

Referenced by XRFdc_GetCalFreeze(), and XRFdc_SetCalFreeze().

#define XRFDC_CAL_FREEZE_CAL_SHIFT 0U

Calibration freeze enable shift.

Referenced by XRFdc_GetCalFreeze(), and XRFdc_SetCalFreeze().

#define XRFDC_CAL_FREEZE_PIN_MASK 0x4U

Calibration freeze pin disable mask.

Referenced by XRFdc_GetCalFreeze(), and XRFdc_SetCalFreeze().

#define XRFDC_CAL_FREEZE_PIN_SHIFT 2U

Calibration freeze pin disable shift.

Referenced by XRFdc_GetCalFreeze(), and XRFdc_SetCalFreeze().

#define XRFDC_CAL_FREEZE_STS_MASK 0x2U

Calibration freeze status mask.

Referenced by XRFdc_GetCalFreeze().

#define XRFDC_CAL_FREEZE_STS_SHIFT 1U

Calibration freeze status shift.

Referenced by XRFdc_GetCalFreeze().

#define XRFDC_CAL_GCB_ACEN_MASK 0x0800U

GCB accumulator enable mask.

Referenced by XRFdc_DisableCoefficientsOverride(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_GCB_ACEN_SHIFT 11U

GCB accumulator enable shift.

#define XRFDC_CAL_GCB_EN_MASK 0x0080U

gain coeff override enable mask

Referenced by XRFdc_DisableCoefficientsOverride(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_GCB_EN_SHIFT 7U

gain coeff shift

Referenced by XRFdc_SetCalCoefficients().

#define XRFDC_CAL_GCB_ENFL_MASK 0x1800U

GCB accumulator enable mask.

Referenced by XRFdc_DisableCoefficientsOverride().

#define XRFDC_CAL_GCB_FAB_MASK 0xFFF0U

gain coeff mask for IP Gen 2 or below

Referenced by XRFdc_GetCalCoefficients().

#define XRFDC_CAL_GCB_FLSH_MASK 0x1000U

GCB accumulator flush mask.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_GCB_FLSH_SHIFT 12U

GCB accumulator flush shift.

Referenced by XRFdc_SetCalCoefficients().

#define XRFDC_CAL_GCB_MASK 0x0FFFU

gain coeff mask

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_GCB_OFFSET_COEFF0 0x220

Background gain correction block.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_GCB_OFFSET_COEFF0_ALT 0x220

Background gain correction block (below Gen 3)

Referenced by XRFdc_GetCalCoefficients().

#define XRFDC_CAL_GCB_OFFSET_COEFF1 0x224

Background gain correction block.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_GCB_OFFSET_COEFF1_ALT 0x228

Background gain correction block (below Gen 3)

Referenced by XRFdc_GetCalCoefficients().

#define XRFDC_CAL_GCB_OFFSET_COEFF2 0x228

Background gain correction block.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_GCB_OFFSET_COEFF2_ALT 0x230

Background gain correction block (below Gen 3)

Referenced by XRFdc_GetCalCoefficients().

#define XRFDC_CAL_GCB_OFFSET_COEFF3 0x22C

Background gain correction block.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_GCB_OFFSET_COEFF3_ALT 0x238

Background gain correction block (below Gen 3)

Referenced by XRFdc_GetCalCoefficients().

#define XRFDC_CAL_OCB1_OFFSET_COEFF0 0x200

Foreground offset correction block.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_OCB1_OFFSET_COEFF1 0x208

Foreground offset correction block.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_OCB1_OFFSET_COEFF2 0x210

Foreground offset correction block.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_OCB1_OFFSET_COEFF3 0x218

Foreground offset correction block.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_OCB2_OFFSET_COEFF0 0x204

Background offset correction block.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_OCB2_OFFSET_COEFF1 0x20C

Background offset correction block.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_OCB2_OFFSET_COEFF2 0x214

Background offset correction block.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_OCB2_OFFSET_COEFF3 0x21C

Background offset correction block.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_OCB_EN_MASK 0x0001U

offsets coeff override enable mask

Referenced by XRFdc_DisableCoefficientsOverride(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_OCB_EN_SHIFT 0U

offsets coeff shift

#define XRFDC_CAL_OCB_MASK 0xFFFFU

offsets coeff mask

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_SLICE_SHIFT 16U

Coefficient shift for HSADCs.

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_EN_MASK 0x8000U

time skew coeff override enable mask

Referenced by XRFdc_DisableCoefficientsOverride(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_EN_SHIFT 15U

time skew coeff shift

Referenced by XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_MASK 0x01FFU

time skew coeff mask

Referenced by XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF0 0x170

Background time skew correction block.

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF0_ALT 0x168

Background time skew correction block (below Gen 3)

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF1 0x174

Background time skew correction block.

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF1_ALT 0x16C

Background time skew correction block (below Gen 3)

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF2 0x178

Background time skew correction block.

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF2_ALT 0x170

Background time skew correction block (below Gen 3)

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF3 0x17C

Background time skew correction block.

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF3_ALT 0x174

Background time skew correction block (below Gen 3)

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF4 0x180

Background time skew correction block.

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF4_ALT 0x178

Background time skew correction block (below Gen 3)

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF5 0x184

Background time skew correction block.

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF5_ALT 0x17C

Background time skew correction block (below Gen 3)

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF6 0x188

Background time skew correction block.

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF6_ALT 0x180

Background time skew correction block (below Gen 3)

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF7 0x18C

Background time skew correction block.

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CAL_TSCB_OFFSET_COEFF7_ALT 0x184

Background time skew correction block (below Gen 3)

Referenced by XRFdc_DisableCoefficientsOverride(), XRFdc_GetCalCoefficients(), and XRFdc_SetCalCoefficients().

#define XRFDC_CLK_EN_CAL_MASK 0x00000001U

Enable Output Register clock.

#define XRFDC_CLK_EN_DIG_MASK 0x00000002U

Enable full-rate clock.

#define XRFDC_CLK_EN_DP_MASK 0x00000004U

Enable Data Path clock.

#define XRFDC_CLK_EN_FAB_MASK 0x00000008U

Enable fabric clock.

#define XRFDC_CLK_EN_LM_MASK 0x00000010U

Enable for FIFO Latency measurement clock.

#define XRFDC_CLK_EN_OFFSET 0x000U

ADC Clock Enable Register.

Referenced by XRFdc_GetBlockStatus().

#define XRFDC_CLK_NETWORK_CTRL0 0x8CU

Clock network control and trim register.

#define XRFDC_CLK_NETWORK_CTRL1 0x90U

Multi-tile sync and clock source control register.

Referenced by XRFdc_DynamicPLLConfig(), and XRFdc_GetClockSource().

#define XRFDC_CLOCK_DETECT_MASK 0x0000FFFFU

Clock detect mask.

Referenced by XRFdc_SetClkDistribution().

#define XRFDC_CLOCK_DETECT_OFFSET 0x80U

Clock detect register.

Referenced by XRFdc_SetClkDistribution().

#define XRFDC_COMMON_INTR_ENABLE 0x104U

Common Intr enable register.

Referenced by XRFdc_GetEnabledInterrupts(), and XRFdc_IntrEnable().

#define XRFDC_COMMON_INTR_STS 0x100U

Common Intr Status register.

Referenced by XRFdc_IntrHandler().

#define XRFDC_CRSE_DLY_CFG_MASK 0x00000007U

Coarse delay select.

Referenced by XRFdc_SetCoarseDelaySettings().

#define XRFDC_CRSE_DLY_CFG_MASK_EXT 0x0000003FU

Extended coarse delay select.

Referenced by XRFdc_SetCoarseDelaySettings().

#define XRFDC_CRSEDLY_UPDT_DLY_MASK 0x00001FF8U

delay in clk_dp cycles in application of event after arrival

#define XRFDC_CRSEDLY_UPDT_MODE_FABRIC 0x00000005U

Coarse delay event source selection is fabric.

#define XRFDC_CRSEDLY_UPDT_MODE_GRP 0x00000000U

Coarse delay event source selection is group.

#define XRFDC_CRSEDLY_UPDT_MODE_MARKER 0x00000004U

Coarse delay event source selection is Marker.

#define XRFDC_CRSEDLY_UPDT_MODE_MASK 0x00000007U

Coarse delay event source selection mask.

#define XRFDC_CRSEDLY_UPDT_MODE_SLICE 0x00000001U

Coarse delay event source selection is slice.

#define XRFDC_CRSEDLY_UPDT_MODE_SYSREF 0x00000003U

Coarse delay event source selection is sysref.

#define XRFDC_CRSEDLY_UPDT_MODE_TILE 0x00000002U

Coarse delay event source selection is tile.

#define XRFDC_CURRENT_STATE_OFFSET 0x0CU

Current state register.

Referenced by XRFdc_GetIPStatus().

#define XRFDC_DAC_CRSE_DLY_CFG_OFFSET 0x0DCU

DAC Coarse delay Config Register.

Referenced by XRFdc_GetCoarseDelaySettings(), and XRFdc_SetCoarseDelaySettings().

#define XRFDC_DAC_CRSE_DLY_UPDT_OFFSET 0x0E0U

DAC Coarse Delay Update Register.

Referenced by XRFdc_GetCoarseDelaySettings(), XRFdc_SetCoarseDelaySettings(), and XRFdc_UpdateEvent().

#define XRFDC_DAC_DAT_IMR_MASK 0x00000FFFU

DAC DataPath mask.

Referenced by XRFdc_GetEnabledInterrupts(), and XRFdc_IntrEnable().

#define XRFDC_DAC_DAT_ISR_INVSINC_MASK 0x00000100U

Inverse-Sinc offset overflow.

#define XRFDC_DAC_DAT_PATH_ISR_MASK 0x000001FFU

DAC Data Path Overflow.

Referenced by XRFdc_GetIntrStatus().

#define XRFDC_DAC_DATAPATH_OFFSET 0x034U

ADC Decoder interface IMR Register.

Referenced by XRFdc_GetDataPathMode(), XRFdc_GetIMRPassMode(), XRFdc_SetDataPathMode(), and XRFdc_SetIMRPassMode().

#define XRFDC_DAC_DECODER_CLK_OFFSET 0x184U

Decoder Clock enable.

Referenced by XRFdc_SetDecoderMode().

#define XRFDC_DAC_DECODER_CTRL_OFFSET 0x180U

DAC Unary Decoder/ Randomizer settings.

Referenced by XRFdc_GetDecoderMode(), and XRFdc_SetDecoderMode().

#define XRFDC_DAC_FAB_RATE_RD_MASK 0x00001F00U

DAC FIFO Read Number of Words per clock.

Referenced by XRFdc_SetDataPathMode(), and XRFdc_SetInterpolationFactor().

#define XRFDC_DAC_FAB_RATE_WR_MASK 0x0000001FU

DAC FIFO Write Number of Words per clock.

Referenced by XRFdc_GetFabRdVldWords(), XRFdc_GetFabWrVldWords(), and XRFdc_SetFabWrVldWords().

#define XRFDC_DAC_FABRIC_IMR_OFFSET 0x018U

DAC Fabric IMR Register.

Referenced by XRFdc_GetEnabledInterrupts(), XRFdc_IntrDisable(), and XRFdc_IntrEnable().

#define XRFDC_DAC_FABRIC_ISR_OFFSET 0x014U

DAC Fabric ISR Register.

Referenced by XRFdc_GetIntrStatus(), and XRFdc_IntrClr().

#define XRFDC_DAC_INTERP_CTRL_OFFSET 0x040U

DAC Interpolation Control Register.

Referenced by XRFdc_GetInterpolationFactor(), and XRFdc_SetInterpolationFactor().

#define XRFDC_DAC_INTERP_DATA_MASK 0x00000001U

Data type mask.

Referenced by XRFdc_SetMixerSettings().

#define XRFDC_DAC_INVSINC_OFFSET 0x0C0U

Invsinc control.

Referenced by XRFdc_GetInvSincFIR(), and XRFdc_SetInvSincFIR().

#define XRFDC_DAC_ITERP_DATA_OFFSET 0x044U

DAC interpolation data.

Referenced by XRFdc_SetInterpolationFactor(), and XRFdc_SetMixerSettings().

#define XRFDC_DAC_MB_CFG_OFFSET 0x0C4U

Multiband config.

Referenced by XRFdc_MultiBand().

#define XRFDC_DAC_MC_CFG0_OFFSET 0x1C4U

Static Configuration data for DAC Analog.

Referenced by XRFdc_GetNyquistZone(), and XRFdc_SetNyquistZone().

#define XRFDC_DAC_MC_CFG3_OFFSET 0x1D0U

DAC Static configuration bits for DAC analog Register.

Referenced by XRFdc_GetOutputCurr(), and XRFdc_SetDACVOP().

#define XRFDC_DAC_UPDATE_DYN_OFFSET 0x020U

DAC Update Dynamic Register.

Referenced by XRFdc_SetCoarseDelaySettings(), XRFdc_SetMixerSettings(), XRFdc_SetQMCSettings(), and XRFdc_UpdateEvent().

#define XRFDC_DAC_UPDT_CRSE_DLY_MASK 0x00000020U

DAC Trigger a update event apply to Coarse delay_DCONFIG reg.

Referenced by XRFdc_SetCoarseDelaySettings().

#define XRFDC_DAC_VOP_CTRL_OFFSET 0x198U

DAC variable output power control Register.

Referenced by XRFdc_SetDACVOP().

#define XRFDC_DAT_CLK_EN_MASK 0x0000000FU

Data Path Clk enable.

Referenced by XRFdc_GetBlockStatus().

#define XRFDC_DAT_IMR_DECI_IPATH_MASK 0x00000007U

Decimation I-Path overflow for stages 0,1,2.

#define XRFDC_DAT_IMR_INTR_QPATH_MASK 0x00000038U

Interpolation Q-Path overflow for stages 0,1,2.

#define XRFDC_DAT_IMR_QMC_GAIN_MASK 0x00000040U

QMC Gain/Phase overflow.

#define XRFDC_DAT_IMR_QMC_OFFST_MASK 0x00000080U

QMC offset overflow.

#define XRFDC_DAT_ISR_DECI_IPATH_MASK 0x00000007U

Decimation I-Path overflow for stages 0,1,2.

#define XRFDC_DAT_ISR_INTR_QPATH_MASK 0x00000038U

Interpolation Q-Path overflow for stages 0,1,2.

#define XRFDC_DAT_ISR_QMC_GAIN_MASK 0x00000040U

QMC Gain/Phase overflow.

#define XRFDC_DAT_ISR_QMC_OFFST_MASK 0x00000080U

QMC offset overflow.

#define XRFDC_DAT_SCALE_CFG_MASK 0x00000001U

Enable data scaling.

#define XRFDC_DAT_SCALE_CFG_MASK 0x00000001U

Enable data scaling.

#define XRFDC_DATAPATH_IMR_MASK 0x00000004U

IMR Mode.

Referenced by XRFdc_GetIMRPassMode(), and XRFdc_SetIMRPassMode().

#define XRFDC_DATAPATH_LATENCY_MASK 0x00000008U

DataPath Latency.

#define XRFDC_DATAPATH_MODE_MASK 0x00000003U

DataPath Mode.

Referenced by XRFdc_GetDataPathMode(), and XRFdc_SetDataPathMode().

#define XRFDC_DATPATH_IMR_OFFSET 0x03CU

ADC Data Path IMR Register.

Referenced by XRFdc_GetEnabledInterrupts(), XRFdc_IntrDisable(), and XRFdc_IntrEnable().

#define XRFDC_DATPATH_ISR_OFFSET 0x038U

ADC Data Path ISR Register.

Referenced by XRFdc_GetIntrStatus(), and XRFdc_IntrClr().

#define XRFDC_DBG_RST_CAL_MASK 0x00000001U

Reset clk_cal clock domain.

#define XRFDC_DBG_RST_DIG_MASK 0x00000008U

Reset clk_dig clock domain.

#define XRFDC_DBG_RST_DP_MASK 0x00000002U

Reset data path clock domain.

#define XRFDC_DBG_RST_DRP_CAL_MASK 0x00000010U

Reset subadc-drp register on clock cal.

#define XRFDC_DBG_RST_FAB_MASK 0x00000004U

Reset clock fabric clock domain.

#define XRFDC_DBG_RST_LM_MASK 0x00000020U

Reset FIFO Latency measurement clock domain.

#define XRFDC_DEC_CFG_4GSPS_MASK 0x00000003U

4GSPS may be I or Q or Real depending on high level block config

Referenced by XRFdc_SetMixerSettings().

#define XRFDC_DEC_CFG_CHA_MASK 0x00000000U

ChannelA(I)

Referenced by XRFdc_SetMixerSettings().

#define XRFDC_DEC_CFG_CHB_MASK 0x00000001U

ChannelB (2GSPS real data from Mixer Q output)

#define XRFDC_DEC_CFG_IQ_MASK 0x00000002U

IQ-2GSPS.

Referenced by XRFdc_SetMixerSettings().

#define XRFDC_DEC_CFG_MASK 0x00000003U

ChannelA (2GSPS real data from Mixer I output)

Referenced by XRFdc_SetDecimationFactor(), and XRFdc_SetMixerSettings().

#define XRFDC_DEC_CTRL_MODE_MASK 0x00000007U

Decoder mode.

Referenced by XRFdc_GetDecoderMode(), and XRFdc_SetDecoderMode().

#define XRFDC_DEC_IMR_SUBADC0_OVR_MASK 0x00000002U

subadc0 decoder overflow range

#define XRFDC_DEC_IMR_SUBADC0_UND_MASK 0x00000001U

subadc0 decoder underflow range

#define XRFDC_DEC_IMR_SUBADC1_OVR_MASK 0x00000008U

subadc1 decoder overflow range

#define XRFDC_DEC_IMR_SUBADC1_UND_MASK 0x00000004U

subadc1 decoder underflow range

#define XRFDC_DEC_IMR_SUBADC2_OVR_MASK 0x00000020U

subadc2 decoder overflow range

#define XRFDC_DEC_IMR_SUBADC2_UND_MASK 0x00000010U

subadc2 decoder underflow range

#define XRFDC_DEC_IMR_SUBADC3_OVR_MASK 0x00000080U

subadc3 decoder overflow range

#define XRFDC_DEC_IMR_SUBADC3_UND_MASK 0x00000040U

subadc3 decoder underflow range

#define XRFDC_DEC_ISR_SUBADC0_OVR_MASK 0x00000002U

subadc0 decoder overflow range

#define XRFDC_DEC_ISR_SUBADC0_UND_MASK 0x00000001U

subadc0 decoder underflow range

#define XRFDC_DEC_ISR_SUBADC1_OVR_MASK 0x00000008U

subadc1 decoder overflow range

#define XRFDC_DEC_ISR_SUBADC1_UND_MASK 0x00000004U

subadc1 decoder underflow range

#define XRFDC_DEC_ISR_SUBADC2_OVR_MASK 0x00000020U

subadc2 decoder overflow range

#define XRFDC_DEC_ISR_SUBADC2_UND_MASK 0x00000010U

subadc2 decoder underflow range

#define XRFDC_DEC_ISR_SUBADC3_OVR_MASK 0x00000080U

subadc3 decoder overflow range

#define XRFDC_DEC_ISR_SUBADC3_UND_MASK 0x00000040U

subadc3 decoder underflow range

#define XRFDC_DEC_ISR_SUBADC_MASK 0x000000FFU

subadc decoder Mask

Referenced by XRFdc_GetIntrStatus().

#define XRFDC_DEC_MOD_MASK 0x00000007U

Decimation mode Mask.

Referenced by XRFdc_GetDecimationFactor(), and XRFdc_SetDecimationFactor().

#define XRFDC_DEC_MOD_MASK_EXT 0x0000003FU

Decimation mode Mask.

Referenced by XRFdc_GetDecimationFactor(), and XRFdc_SetDecimationFactor().

#define XRFDC_DSA_UPDT_OFFSET 0x254U

ADC DSA Update Trigger REgister.

Referenced by XRFdc_SetDSA().

#define XRFDC_EN_I_IQ_MASK 0x00000003U

Enable fine mixer multipliers on IQ i/p for I output.

Referenced by XRFdc_GetMixerSettings().

#define XRFDC_EN_INTR_ADC_TILE0_MASK 0x00000010U

ADC Tile0 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

#define XRFDC_EN_INTR_ADC_TILE1_MASK 0x00000020U

ADC Tile1 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

#define XRFDC_EN_INTR_ADC_TILE2_MASK 0x00000040U

ADC Tile2 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

#define XRFDC_EN_INTR_ADC_TILE3_MASK 0x00000080U

ADC Tile3 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

#define XRFDC_EN_INTR_DAC_TILE0_MASK 0x00000001U

DAC Tile0 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

#define XRFDC_EN_INTR_DAC_TILE1_MASK 0x00000002U

DAC Tile1 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

#define XRFDC_EN_INTR_DAC_TILE2_MASK 0x00000004U

DAC Tile2 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

#define XRFDC_EN_INTR_DAC_TILE3_MASK 0x00000008U

DAC Tile3 interrupt enable mask.

Referenced by XRFdc_IntrHandler().

#define XRFDC_EN_INTR_SLICE0_MASK 0x00000001U

slice0 interrupt enable mask

Referenced by XRFdc_IntrHandler().

#define XRFDC_EN_INTR_SLICE1_MASK 0x00000002U

slice1 interrupt enable mask

Referenced by XRFdc_IntrHandler().

#define XRFDC_EN_INTR_SLICE2_MASK 0x00000004U

slice2 interrupt enable mask

Referenced by XRFdc_IntrHandler().

#define XRFDC_EN_INTR_SLICE3_MASK 0x00000008U

slice3 interrupt enable mask

Referenced by XRFdc_IntrHandler().

#define XRFDC_EN_INTR_SLICE_MASK 0x0000000FU

Slice intr mask.

#define XRFDC_EN_INVSINC_MASK 0x00000001U

invsinc enable mask

Referenced by XRFdc_GetInvSincFIR(), and XRFdc_SetInvSincFIR().

#define XRFDC_EN_MB_MASK 0x00000008U

multi-band adder mask

#define XRFDC_EN_Q_IQ_MASK 0x0000000CU

Enable fine mixer multipliers on IQ i/p for Q output.

Referenced by XRFdc_GetMixerSettings().

#define XRFDC_FAB_IMR_MARGIND_OVR_MASK 0x00000004U

Marginal-indicator overlap (overflow)

#define XRFDC_FAB_IMR_MARGIND_UND_MASK 0x00000008U

Marginal-indicator overlap (underflow)

#define XRFDC_FAB_IMR_USRDAT_MASK 0x00000003U

User-data overlap Mask.

#define XRFDC_FAB_IMR_USRDAT_OVR_MASK 0x00000001U

User-data overlap- data written faster than read (overflow)

#define XRFDC_FAB_IMR_USRDAT_UND_MASK 0x00000002U

User-data overlap- data read faster than written (underflow)

#define XRFDC_FAB_ISR_MARGIND_OVR_MASK 0x00000004U

Marginal-indicator overlap (overflow)

#define XRFDC_FAB_ISR_MARGIND_UND_MASK 0x00000008U

Marginal-indicator overlap (underflow)

#define XRFDC_FAB_ISR_USRDAT_MASK 0x00000003U

User-data overlap Mask.

#define XRFDC_FAB_ISR_USRDAT_OVR_MASK 0x00000001U

User-data overlap- data written faster than read (overflow)

#define XRFDC_FAB_ISR_USRDAT_UND_MASK 0x00000002U

User-data overlap- data read faster than written (underflow)

#define XRFDC_FAB_RATE_RD_SHIFT 8U

Fabric Read shift.

Referenced by XRFdc_GetFabRdVldWords(), XRFdc_SetDataPathMode(), XRFdc_SetFabRdVldWords(), and XRFdc_SetInterpolationFactor().

#define XRFDC_FAB_RD_PTR_OFFST_MASK 0x0000003FU

FIFO read pointer offset for interface de-skew.

#define XRFDC_FEND_DAT_CTRL_MASK 0x000000FFU

raw data and cal coefficient to be streamed to memory

#define XRFDC_FIFO_EN_MASK 0x00000001U

FIFO enable/disable.

Referenced by XRFdc_GetFIFOStatus(), and XRFdc_SetupFIFO().

#define XRFDC_FIFO_ENABLE 0x230U

FIFO Enable and Disable.

Referenced by XRFdc_GetFIFOStatus(), and XRFdc_SetupFIFO().

#define XRFDC_FIFO_LTNCY_DIS_MASK 0x000000010U

Disable FIFO Latency measurement.

#define XRFDC_FIFO_LTNCY_DONE_MASK 0x00008000U

Latency measurement done flag.

#define XRFDC_FIFO_LTNCY_KEY_MASK 0x00004000U

Latency measurement result identification key.

#define XRFDC_FIFO_LTNCY_PRD_MASK 0x00000007U

Set FIFO Latency measurement period.

#define XRFDC_FIFO_LTNCY_RES_MASK 0x00000FFFU

Latency measurement result.

#define XRFDC_FIFO_LTNCY_RESTRT_MASK 0x00000008U

Restart FIFO Latency measurement.

#define XRFDC_FINE_MIX_SCALE_MASK 0x00000010U

NCO output scale.

Referenced by XRFdc_GetMixerSettings(), and XRFdc_SetMixerSettings().

#define XRFDC_HSCOM_CLK_DIV_OFFSET 0xB0

Fabric clk out divider.

Referenced by XRFdc_GetFabClkOutDiv(), XRFdc_SetDataPathMode(), and XRFdc_SetFabClkOutDiv().

#define XRFDC_HSCOM_CLK_DSTR_MASK 0xC788U

Clock Distribution Register.

Referenced by XRFdc_GetClkDistribution(), and XRFdc_SetClkDistribution().

#define XRFDC_HSCOM_CLK_DSTR_MASK_ALT 0x1870U

Clock Distribution Register for Intratile.

Referenced by XRFdc_GetClkDistribution().

#define XRFDC_HSCOM_CLK_DSTR_OFFSET 0x088U

Clock Distribution Register.

Referenced by XRFdc_GetClkDistribution(), and XRFdc_SetClkDistribution().

#define XRFDC_HSCOM_NETWORK_CTRL1_MASK 0x02FU

Clock Network Register Mask for IntraTile.

#define XRFDC_HSCOM_PWR_OFFSET 0x094

Control register during power-up sequence.

#define XRFDC_HSCOM_PWR_STATE_MASK 0x0000FFFFU

powerup state mask

#define XRFDC_HSCOM_PWR_STATE_OFFSET 0xB4

Check powerup state.

Referenced by XRFdc_DynamicPLLConfig().

#define XRFDC_HSCOM_UPDT_DYN_OFFSET 0x0B8

Trigger the update dynamic event.

Referenced by XRFdc_UpdateEvent().

#define XRFDC_I_IQ_COS_MINSIN 0x00000C00U

Select NCO phases for I output.

#define XRFDC_INTERP_MODE_I_MASK 0x00000007U

Interp filter I.

Referenced by XRFdc_GetInterpolationFactor().

#define XRFDC_INTERP_MODE_I_MASK_EXT 0x0000003FU

Interp filter I.

Referenced by XRFdc_GetInterpolationFactor().

#define XRFDC_INTERP_MODE_MASK 0x00000077U

Interp filter mask.

Referenced by XRFdc_SetInterpolationFactor().

#define XRFDC_INTERP_MODE_MASK_EXT 0x00003F3FU

Interp filter mask.

Referenced by XRFdc_SetInterpolationFactor().

#define XRFDC_INTERP_MODE_Q_SHIFT 4U

Interp mode Q shift.

Referenced by XRFdc_SetInterpolationFactor().

#define XRFDC_INTERP_MODE_Q_SHIFT_EXT 8U

Interp mode Q shift.

Referenced by XRFdc_SetInterpolationFactor().

#define XRFDC_INTR_CMODE_OVR_MASK 0x00040000U

Common mode OV mask.

Referenced by XRFdc_GetIntrStatus().

#define XRFDC_INTR_CMODE_UNDR_MASK 0x00080000U

Common mode UV mask.

Referenced by XRFdc_GetIntrStatus().

#define XRFDC_INTR_COMMON_MASK 0x00000010U

Common interrupt enable mask.

Referenced by XRFdc_GetIntrStatus(), and XRFdc_IntrHandler().

#define XRFDC_INTR_DAT_OVR_MASK 0x00004000U

Data OF mask.

Referenced by XRFdc_GetIntrStatus().

#define XRFDC_INTR_ENABLE 0x204U

Intr enable register.

Referenced by XRFdc_GetEnabledInterrupts(), XRFdc_IntrDisable(), and XRFdc_IntrEnable().

#define XRFDC_INTR_FIFO_OVR_MASK 0x00008000U

FIFO OF mask.

Referenced by XRFdc_GetIntrStatus().

#define XRFDC_INTR_OVR_RANGE_MASK 0x00000008U

Over Range interrupt mask.

Referenced by XRFdc_GetIntrStatus().

#define XRFDC_INTR_OVR_VOLTAGE_MASK 0x00000004U

Over Voltage interrupt mask.

Referenced by XRFdc_GetIntrStatus().

#define XRFDC_INTR_STS 0x200U

Intr status register.

Referenced by XRFdc_GetIntrStatus(), and XRFdc_IntrHandler().

#define XRFDC_MC_CFG0_MIX_MODE_MASK 0x00000002U

Enable Mixing mode.

Referenced by XRFdc_GetNyquistZone(), and XRFdc_SetNyquistZone().

#define XRFDC_MC_CFG0_MIX_MODE_SHIFT 1U

Mix mode shift.

Referenced by XRFdc_GetNyquistZone().

#define XRFDC_MIX_CFG0_MASK 0x00000FFFU

Mixer Config0 Mask.

Referenced by XRFdc_GetMixerSettings().

#define XRFDC_MIX_CFG1_MASK 0x00000FFFU

Mixer Config0 Mask.

Referenced by XRFdc_GetMixerSettings().

#define XRFDC_MIX_I_DAT_WRD0_MASK 0x00000007U

Output data word[0] of I channel.

#define XRFDC_MIX_I_DAT_WRD1_MASK 0x00000038U

Output data word[1] of I channel.

#define XRFDC_MIX_I_DAT_WRD2_MASK 0x000001C0U

Output data word[2] of I channel.

#define XRFDC_MIX_I_DAT_WRD3_MASK 0x00000E00U

Output data word[3] of I channel.

#define XRFDC_MIX_Q_DAT_WRD0_MASK 0x00000007U

Output data word[0] of Q channel.

#define XRFDC_MIX_Q_DAT_WRD1_MASK 0x00000038U

Output data word[1] of Q channel.

#define XRFDC_MIX_Q_DAT_WRD2_MASK 0x000001C0U

Output data word[2] of Q channel.

#define XRFDC_MIX_Q_DAT_WRD3_MASK 0x00000E00U

Output data word[3] of Q channel.

#define XRFDC_MIXER_MODE_C2C_MASK 0x0000000FU

Mixer mode C2C Mask.

#define XRFDC_MIXER_MODE_C2R_MASK 0x00000003U

Mixer mode C2R Mask.

#define XRFDC_MIXER_MODE_OFF_MASK 0x00000000U

Mixer mode OFF Mask.

#define XRFDC_MIXER_MODE_R2C_MASK 0x00000005U

Mixer mode R2C Mask.

#define XRFDC_MODE_INVSINC_MASK 0x00000003U

invsinc mode mask

Referenced by XRFdc_GetInvSincFIR(), and XRFdc_SetInvSincFIR().

#define XRFDC_MXR_MODE_OFFSET 0x088U

ADC/DAC mixer mode Register.

Referenced by XRFdc_GetMixerSettings(), and XRFdc_SetMixerSettings().

#define XRFDC_NCO_FQWD_LOW_MASK 0x0000FFFFU

NCO Phase increment[15:0].

#define XRFDC_NCO_FQWD_MASK 0x0000FFFFFFFFFFFFU

NCO Freq offset[48:0].

Referenced by XRFdc_GetMixerSettings().

#define XRFDC_NCO_FQWD_MID_MASK 0x0000FFFFU

NCO Phase increment[31:16].

Referenced by XRFdc_SetMixerSettings().

#define XRFDC_NCO_FQWD_MID_SHIFT 16U

Freq Word Mid shift.

Referenced by XRFdc_GetMixerSettings(), and XRFdc_SetMixerSettings().

#define XRFDC_NCO_FQWD_UPP_MASK 0x0000FFFFU

NCO Phase increment[47:32].

Referenced by XRFdc_SetMixerSettings().

#define XRFDC_NCO_FQWD_UPP_SHIFT 32U

Freq Word upper shift.

Referenced by XRFdc_GetMixerSettings(), and XRFdc_SetMixerSettings().

#define XRFDC_NCO_PHASE_LOW_MASK 0x0000FFFFU

NCO Phase offset[15:0].

#define XRFDC_NCO_PHASE_LOW_OFFSET 0x0A4U

ADC/DAC NCO Phase[15:0] Register.

Referenced by XRFdc_GetMixerSettings(), and XRFdc_SetMixerSettings().

#define XRFDC_NCO_PHASE_MASK 0x0003FFFFU

NCO Phase offset[17:0].

Referenced by XRFdc_GetMixerSettings().

#define XRFDC_NCO_PHASE_MOD_4PHASE 0x00000003U

NCO output 4 successive phase.

#define XRFDC_NCO_PHASE_MOD_EVEN 0x00000001U

NCO output even phase.

Referenced by XRFdc_SetMixerSettings().

#define XRFDC_NCO_PHASE_MOD_MASK 0x00000003U

NCO mode of operation mask.

#define XRFDC_NCO_PHASE_MODE_ODD 0x00000002U

NCO output odd phase.

Referenced by XRFdc_SetMixerSettings().

#define XRFDC_NCO_PHASE_RST_MASK 0x00000001U

Reset NCO Phase of current slice.

Referenced by XRFdc_ResetNCOPhase().

#define XRFDC_NCO_PHASE_UPP_MASK 0x00000003U

NCO Phase offset[17:16].

Referenced by XRFdc_SetMixerSettings().

#define XRFDC_NCO_PHASE_UPP_OFFSET 0x0A0U

ADC/DAC NCO Phase[17:16] Register.

Referenced by XRFdc_GetMixerSettings(), and XRFdc_SetMixerSettings().

#define XRFDC_NCO_PHASE_UPP_SHIFT 16U

NCO phase upper shift.

Referenced by XRFdc_GetMixerSettings(), and XRFdc_SetMixerSettings().

#define XRFDC_NCO_RST_OFFSET 0x090U

ADC/DAC NCO Phase Reset Register.

Referenced by XRFdc_ResetNCOPhase().

#define XRFDC_NCO_UPDT_DLY_MASK 0x00001FF8U

delay in clk_dp cycles in application of event after arrival

#define XRFDC_NCO_UPDT_MODE_FABRIC 0x00000005U

NCO event source selection is fabric.

#define XRFDC_NCO_UPDT_MODE_GRP 0x00000000U

NCO event source selection is Group.

#define XRFDC_NCO_UPDT_MODE_MARKER 0x00000004U

NCO event source selection is Marker.

#define XRFDC_NCO_UPDT_MODE_MASK 0x00000007U

NCO event source selection mask.

Referenced by XRFdc_GetMixerSettings(), XRFdc_SetMixerSettings(), and XRFdc_UpdateEvent().

#define XRFDC_NCO_UPDT_MODE_SLICE 0x00000001U

NCO event source selection is slice.

#define XRFDC_NCO_UPDT_MODE_SYSREF 0x00000003U

NCO event source selection is Sysref.

#define XRFDC_NCO_UPDT_MODE_TILE 0x00000002U

NCO event source selection is tile.

#define XRFDC_NCO_UPDT_OFFSET 0x08CU

ADC/DAC NCO Update mode Register.

Referenced by XRFdc_GetMixerSettings(), XRFdc_SetMixerSettings(), and XRFdc_UpdateEvent().

#define XRFDC_NCO_UPDT_RST_DLY_MASK 0x0000D000U

optional delay on the NCO phase reset delay

#define XRFDC_PLL_CHARGEPUMP 0x48U

PLL bits for charge pumps.

#define XRFDC_PLL_CRS1 0x28U

PLL bits for coarse frequency control LSB.

#define XRFDC_PLL_CRS2 0x2CU

PLL bits for coarse frequency control MSB.

#define XRFDC_PLL_DIVIDER0 0x30U

PLL Output Divider LSB register.

Referenced by XRFdc_DynamicPLLConfig(), XRFdc_GetClockSource(), and XRFdc_GetPLLConfig().

#define XRFDC_PLL_DIVIDER0_ALT_MASK 0xC00U

PLL Output Divider Register Mask for IntraTile.

Referenced by XRFdc_DynamicPLLConfig().

#define XRFDC_PLL_DIVIDER0_BYPDIV_MASK 0x400U

PLL Output Divider Register Mask for IntraTile.

#define XRFDC_PLL_DIVIDER0_BYPPLL_MASK 0x800U

PLL Output Divider Register Mask for IntraTile.

#define XRFDC_PLL_DIVIDER1 0x34U

PLL Output Divider MSB register.

#define XRFDC_PLL_FPDIV 0x5CU

PLL Feedback Divider register.

Referenced by XRFdc_GetPLLConfig().

#define XRFDC_PLL_FREQ 0x300U

PLL output frequency (before divider) register.

Referenced by XRFdc_DynamicPLLConfig(), and XRFdc_GetPLLConfig().

#define XRFDC_PLL_FS 0x304U

Sampling rate register.

Referenced by XRFdc_DynamicPLLConfig(), and XRFdc_GetPLLConfig().

#define XRFDC_PLL_LOCKED_MASK 0x00000008U

PLL Locked mask.

Referenced by XRFdc_GetIPStatus(), and XRFdc_GetPLLLockStatus().

#define XRFDC_PLL_LOCKED_SHIFT 3U

PLL locked shift.

Referenced by XRFdc_GetIPStatus().

#define XRFDC_PLL_LPF0 0x4CU

PLL bits for loop filters LSB.

#define XRFDC_PLL_LPF1 0x50U

PLL bits for loop filters MSB.

#define XRFDC_PLL_REFDIV 0x40U

PLL Reference Divider register.

Referenced by XRFdc_GetPLLConfig().

#define XRFDC_PLL_REFDIV_MASK 0x0E0U

PLL Reference Divider Register Mask for IntraTile.

#define XRFDC_PLL_SDM_CFG0 0x00U

PLL Configuration bits for sdm.

#define XRFDC_PLL_SDM_SEED0 0x18U

PLL Bits for sdm LSB.

#define XRFDC_PLL_SDM_SEED1 0x1CU

PLL Bits for sdm MSB.

#define XRFDC_PLL_SPARE0 0x38U

PLL spare inputs LSB.

#define XRFDC_PLL_SPARE1 0x3CU

PLL spare inputs MSB.

#define XRFDC_PLL_VCO0 0x54U

PLL bits for coltage controlled oscillator LSB.

#define XRFDC_PLL_VCO1 0x58U

PLL bits for coltage controlled oscillator MSB.

#define XRFDC_PLL_VREG 0x44U

PLL bits for voltage regulator.

PLL voltage regulator.

#define XRFDC_PLL_VREG 0x44U

PLL bits for voltage regulator.

PLL voltage regulator.

#define XRFDC_PWR_STATE_MASK 0x0000FFFFU

State mask.

#define XRFDC_PWR_UP_STAT_MASK 0x00000004U

Power Up state mask.

Referenced by XRFdc_DynamicPLLConfig(), and XRFdc_GetIPStatus().

#define XRFDC_PWR_UP_STAT_SHIFT 2U

PowerUp status shift.

Referenced by XRFdc_DynamicPLLConfig(), and XRFdc_GetIPStatus().

#define XRFDC_Q_IQ_SIN_COS 0x00001000U

Select NCO phases for Q output.

#define XRFDC_QMC_CFG_EN_GAIN_MASK 0x00000001U

enable QMC gain correction mask

Referenced by XRFdc_GetQMCSettings(), and XRFdc_SetQMCSettings().

#define XRFDC_QMC_CFG_EN_PHASE_MASK 0x00000002U

enable QMC Phase correction mask

Referenced by XRFdc_GetQMCSettings(), and XRFdc_SetQMCSettings().

#define XRFDC_QMC_CFG_OFFSET 0x0CCU

ADC/DAC QMC Config Register.

Referenced by XRFdc_GetQMCSettings(), and XRFdc_SetQMCSettings().

#define XRFDC_QMC_CFG_PHASE_SHIFT 1U

QMC config phase shift.

Referenced by XRFdc_GetQMCSettings(), and XRFdc_SetQMCSettings().

#define XRFDC_QMC_GAIN_CRCTN_MASK 0x00003FFFU

QMC gain correction factor.

Referenced by XRFdc_GetQMCSettings(), and XRFdc_SetQMCSettings().

#define XRFDC_QMC_GAIN_OFFSET 0x0D4U

ADC/DAC QMC Gain Correction Register.

Referenced by XRFdc_GetQMCSettings(), and XRFdc_SetQMCSettings().

#define XRFDC_QMC_OFF_OFFSET 0x0D0U

ADC/DAC QMC Offset Correction Register.

Referenced by XRFdc_GetQMCSettings(), and XRFdc_SetQMCSettings().

#define XRFDC_QMC_OFFST_CRCTN_MASK 0x00000FFFU

QMC offset correction factor.

Referenced by XRFdc_GetQMCSettings(), and XRFdc_SetQMCSettings().

#define XRFDC_QMC_PHASE_CRCTN_MASK 0x00000FFFU

QMC phase correction factor.

Referenced by XRFdc_GetQMCSettings(), and XRFdc_SetQMCSettings().

#define XRFDC_QMC_PHASE_OFFSET 0x0D8U

ADC/DAC QMC Phase Correction Register.

Referenced by XRFdc_GetQMCSettings(), and XRFdc_SetQMCSettings().

#define XRFDC_QMC_UPDT_DLY_MASK 0x00001FF8U

delay in clk_dp cycles in application of event after arrival

#define XRFDC_QMC_UPDT_MODE_FABRIC 0x00000005U

QMC event source selection is fabric.

#define XRFDC_QMC_UPDT_MODE_GRP 0x00000000U

QMC event source selection is group.

#define XRFDC_QMC_UPDT_MODE_MARKER 0x00000004U

QMC event source selection is Marker.

#define XRFDC_QMC_UPDT_MODE_MASK 0x00000007U

QMC event source selection mask.

Referenced by XRFdc_GetCoarseDelaySettings(), XRFdc_GetQMCSettings(), XRFdc_SetCoarseDelaySettings(), XRFdc_SetQMCSettings(), and XRFdc_UpdateEvent().

#define XRFDC_QMC_UPDT_MODE_SLICE 0x00000001U

QMC event source selection is slice.

#define XRFDC_QMC_UPDT_MODE_SYSREF 0x00000003U

QMC event source selection is Sysref.

#define XRFDC_QMC_UPDT_MODE_TILE 0x00000002U

QMC event source selection is tile.

#define XRFDC_QMC_UPDT_OFFSET 0x0C8U

ADC/DAC QMC Update Mode Register.

Referenced by XRFdc_GetQMCSettings(), XRFdc_SetQMCSettings(), and XRFdc_UpdateEvent().

#define XRFDC_REFCLK_DIV_1_MASK 0x10U

Mask for Div1.

#define XRFDC_REFCLK_DIV_2_MASK 0x0U

Mask for Div2.

Referenced by XRFdc_GetPLLConfig().

#define XRFDC_REFCLK_DIV_3_MASK 0x1U

Mask for Div3.

Referenced by XRFdc_GetPLLConfig().

#define XRFDC_REFCLK_DIV_4_MASK 0x2U

Mask for Div4.

Referenced by XRFdc_GetPLLConfig().

#define XRFDC_RESET_OFFSET 0x00U

Tile reset register.

#define XRFDC_RESTART_MASK 0x00000001U

Restart bit mask.

#define XRFDC_RESTART_OFFSET 0x04U

Tile restart register.

#define XRFDC_RESTART_STATE_OFFSET 0x08U

Tile restart state register.

#define XRFDC_RSR_START_SHIFT 8U

Start state shift.

#define XRFDC_RX_MC_CFG0_CM_MASK 0x00000040U

Coupling mode mask.

Referenced by XRFdc_GetLinkCoupling().

#define XRFDC_RX_MC_CFG0_IM3_DITH_MASK 0x00000020U

IM3 Dither Enable mode mask.

Referenced by XRFdc_GetDither(), and XRFdc_SetDither().

#define XRFDC_RX_MC_CFG0_IM3_DITH_SHIFT 5U

IM3 Dither Enable mode shift.

Referenced by XRFdc_SetDither().

#define XRFDC_RX_MC_CFG0_MASK 0x0000FFFFU

RX MC config0.

#define XRFDC_RX_MC_CFG1_MASK 0x0000FFFFU

RX MC Config1.

#define XRFDC_RX_MC_CFG2_MASK 0x0000FFFFU

RX MC Config2.

#define XRFDC_RX_MC_PWRDWN_MASK 0x0000FFFFU

RX MC power down.

#define XRFDC_RX_PR_MC_CFG0_MASK 0x0000FFFFU

RX Pair MC Config0.

#define XRFDC_RX_PR_MC_CFG1_MASK 0x0000FFFFU

RX Pair MC Config1.

#define XRFDC_SEL_CB_TO_DECI_MASK 0x00000020U

Control crossbar switch that select the data to decimation filter.

#define XRFDC_SEL_CB_TO_MIX0_MASK 0x0000000CU

Control crossbar switch that select the data to mixer block mux0.

#define XRFDC_SEL_CB_TO_MIX0_SHIFT 2U

Crossbar Mixer0 shift.

#define XRFDC_SEL_CB_TO_MIX1_MASK 0x00000003U

Control crossbar switch that select the data to mixer block mux1.

#define XRFDC_SEL_CB_TO_QMC_MASK 0x00000010U

Control crossbar switch that select the data to QMC.

#define XRFDC_SEL_I_IQ_MASK 0x00000F00U

Select NCO phases for I output.

#define XRFDC_SEL_Q_IQ_MASK 0x0000F000U

Select NCO phases for Q output.

#define XRFDC_STATUS_OFFSET 0x228U

Common status register.

Referenced by XRFdc_DynamicPLLConfig(), XRFdc_GetIPStatus(), and XRFdc_GetPLLLockStatus().

#define XRFDC_SUBDRP_ADC0_ADDR_MASK 0x000000FFU

sub-drp0 address

#define XRFDC_SUBDRP_ADC0_DAT_MASK 0x0000FFFFU

sub-drp0 data for read or write transaction

#define XRFDC_SUBDRP_ADC1_ADDR_MASK 0x000000FFU

sub-drp1 address

#define XRFDC_SUBDRP_ADC1_DAT_MASK 0x0000FFFFU

sub-drp1 data for read or write transaction

#define XRFDC_SUBDRP_ADC2_ADDR_MASK 0x000000FFU

sub-drp2 address

#define XRFDC_SUBDRP_ADC2_DAT_MASK 0x0000FFFFU

sub-drp2 data for read or write transaction

#define XRFDC_SUBDRP_ADC3_ADDR_MASK 0x000000FFU

sub-drp3 address

#define XRFDC_SUBDRP_ADC3_DAT_MASK 0x0000FFFFU

sub-drp3 data for read or write transaction

#define XRFDC_SWITCH_MTRX_MASK 0x0000003FU

Switch matrix mask.

#define XRFDC_TI_DCB_CTRL0_MASK 0x0000FFFFU

TI DCB gain and offset correction.

#define XRFDC_TI_DCB_CTRL1_MASK 0x00001FFFU

TI DCB gain and offset correction.

#define XRFDC_TI_DCB_CTRL2_MASK 0x00001FFFU

TI DCB gain and offset correction.

#define XRFDC_TI_DCB_MODE_MASK 0x00007800U

TI DCB Mode mask.

Referenced by XRFdc_GetCalibrationMode(), and XRFdc_SetCalibrationMode().

#define XRFDC_TI_DCB_STS0_BG_MASK 0x0000FFFFU

DCB Status0 BG.

#define XRFDC_TI_DCB_STS0_FG_MASK 0x0000FFFFU

DCB Status0 FG.

#define XRFDC_TI_DCB_STS1_BG_MASK 0x0000FFFFU

DCB Status1 BG.

#define XRFDC_TI_DCB_STS1_FG_MASK 0x0000FFFFU

DCB Status1 FG.

#define XRFDC_TI_DCB_STS2_BG_MASK 0x0000FFFFU

DCB Status2 BG.

#define XRFDC_TI_DCB_STS2_FG_MASK 0x0000FFFFU

DCB Status2 FG.

#define XRFDC_TI_DCB_STS3_BG_MASK 0x0000FFFFU

DCB Status3 BG.

#define XRFDC_TI_DCB_STS3_FG_MASK 0x0000FFFFU

DCB Status3 FG.

#define XRFDC_TI_DCB_STS4_LSB_MASK 0x0000FFFFU

read the status of gcb acc0 lsb bits(subadc chan0)

#define XRFDC_TI_DCB_STS4_MSB_MASK 0x0000FFFFU

read the status of gcb acc0 msb bits(subadc chan0)

#define XRFDC_TI_DCB_STS5_LSB_MASK 0x0000FFFFU

read the status of gcb acc1 lsb bits(subadc chan1)

#define XRFDC_TI_DCB_STS5_MSB_MASK 0x0000FFFFU

read the status of gcb acc1 msb bits(subadc chan1)

#define XRFDC_TI_DCB_STS6_LSB_MASK 0x0000FFFFU

read the status of gcb acc2 lsb bits(subadc chan2)

#define XRFDC_TI_DCB_STS6_MSB_MASK 0x0000FFFFU

read the status of gcb acc2 msb bits(subadc chan2)

#define XRFDC_TI_DCB_STS7_LSB_MASK 0x0000FFFFU

read the status of gcb acc3 lsb bits(subadc chan3)

#define XRFDC_TI_DCB_STS7_MSB_MASK 0x0000FFFFU

read the status of gcb acc3 msb bits(subadc chan3)

#define XRFDC_TI_TISK_CHOP_EN_MASK 0x00000008U

enable chopping mode

#define XRFDC_TI_TISK_DBG_CTRL_MASK 0x0000F000U

Debug control.

#define XRFDC_TI_TISK_DBG_UPDT_RT_MASK 0x00001000U

Debug update rate.

#define XRFDC_TI_TISK_DITH_DLY_MASK 0x0000E000U

Programmable delay on dither path to match data path.

#define XRFDC_TI_TISK_EN_MASK 0x00000001U

Block Enable.

#define XRFDC_TI_TISK_MODE_MASK 0x00000002U

Mode (2G/4G)

#define XRFDC_TI_TISK_MU_CM_MASK 0x000000F0U

Constant mu_cm multiplying common mode path.

#define XRFDC_TI_TISK_MU_DF_MASK 0x00000F00U

Constant mu_df multiplying differential path.

#define XRFDC_TI_TISK_ZONE_MASK 0x00000004U

Specifies Nyquist zone.

Referenced by XRFdc_GetNyquistZone(), and XRFdc_SetNyquistZone().

#define XRFDC_TILE_RESET_MASK 0x00000001U

Tile reset mask.

#define XRFDC_TISK_BYPASS0_MASK 0x00000080U

ByPass filter0.

#define XRFDC_TISK_BYPASS1_MASK 0x00008000U

Filter1 multiplying factor.

#define XRFDC_TISK_CHOP_EN_MASK 0x00000008U

enable chopping mode

#define XRFDC_TISK_DAC0_CODE_MASK 0x000000FFU

Code to correction DAC of subadc ch0 front end switch0.

#define XRFDC_TISK_DAC0_OVRID_EN_MASK 0x00008000U

override enable

#define XRFDC_TISK_DAC1_CODE_MASK 0x000000FFU

Code to correction DAC of subadc ch1 front end switch0.

#define XRFDC_TISK_DAC1_OVRID_EN_MASK 0x00008000U

override enable

#define XRFDC_TISK_DAC2_CODE_MASK 0x000000FFU

Code to correction DAC of subadc ch2 front end switch0.

#define XRFDC_TISK_DAC2_OVRID_EN_MASK 0x00008000U

override enable

#define XRFDC_TISK_DAC3_CODE_MASK 0x000000FFU

Code to correction DAC of subadc ch3 front end switch0.

#define XRFDC_TISK_DAC3_OVRID_EN_MASK 0x00008000U

override enable

#define XRFDC_TISK_DACP0_CODE_MASK 0x000000FFU

Code to correction DAC of subadc ch0 front end switch1.

#define XRFDC_TISK_DACP0_OVRID_EN_MASK 0x00008000U

override enable

#define XRFDC_TISK_DACP1_CODE_MASK 0x000000FFU

Code to correction DAC of subadc ch1 front end switch1.

#define XRFDC_TISK_DACP1_OVRID_EN_MASK 0x00008000U

override enable

#define XRFDC_TISK_DACP2_CODE_MASK 0x000000FFU

Code to correction DAC of subadc ch2 front end switch1.

#define XRFDC_TISK_DACP2_OVRID_EN_MASK 0x00008000U

override enable

#define XRFDC_TISK_DACP3_CODE_MASK 0x000000FFU

Code to correction DAC of subadc ch3 front end switch1.

#define XRFDC_TISK_DACP3_OVRID_EN_MASK 0x00008000U

override enable

#define XRFDC_TISK_DBG_CTRL_MASK 0x0000F000U

Debug control.

#define XRFDC_TISK_DBG_UPDT_RT_MASK 0x00001000U

Debug update rate.

#define XRFDC_TISK_DITH_DLY_MASK 0x0000E000U

Programmable delay on dither path to match data path.

#define XRFDC_TISK_DZ_MAX_VAL_MASK 0x0000FF00U

Deadzone max.

#define XRFDC_TISK_DZ_MIN_VAL_MASK 0x000000FFU

Deadzone min.

#define XRFDC_TISK_EN_MASK 0x00000001U

Block Enable.

#define XRFDC_TISK_MODE_MASK 0x00000002U

Mode (2G/4G)

#define XRFDC_TISK_MU0_MASK 0x0000000FU

Filter0 multiplying factor.

#define XRFDC_TISK_MU1_MASK 0x00000F00U

Filter1 multiplying factor.

#define XRFDC_TISK_MU_CM_MASK 0x000000F0U

Constant mu_cm multiplying common mode path.

#define XRFDC_TISK_MU_DF_MASK 0x00000F00U

Constant mu_df multiplying differential path.

#define XRFDC_TISK_SETTLE_MASK 0x000000FFU

Settling time following code update.

#define XRFDC_TISK_ZONE_MASK 0x00000004U

Specifies Nyquist zone.

#define XRFDC_TISK_ZONE_SHIFT 2U

Nyquist zone shift.

Referenced by XRFdc_GetNyquistZone().

#define XRFDC_TRSHD0_AVG_LOW_MASK 0x0000FFFFU

Threshold0 under Averaging[15:0].

#define XRFDC_TRSHD0_AVG_UPP_MASK 0x0000FFFFU

Threshold0 under Averaging[31:16].

#define XRFDC_TRSHD0_AVG_UPP_SHIFT 16U

Threshold0 Avg upper shift.

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_TRSHD0_CLR_MOD_MASK 0x00000004U

Clear mode.

Referenced by XRFdc_SetThresholdClrMode().

#define XRFDC_TRSHD0_EN_MOD_MASK 0x00000003U

Enable Threshold0 block.

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_TRSHD0_OVER_MASK 0x00007FFFU

Threshold0 under Threshold[14:0].

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_TRSHD0_STIKY_CLR_MASK 0x00000008U

Clear sticky bit.

Referenced by XRFdc_ThresholdStickyClear().

#define XRFDC_TRSHD0_UNDER_MASK 0x00007FFFU

Threshold0 under Threshold[14:0].

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_TRSHD1_AVG_LOW_MASK 0x0000FFFFU

Threshold1 under Averaging[15:0].

#define XRFDC_TRSHD1_AVG_UPP_MASK 0x0000FFFFU

Threshold1 under Averaging[31:16].

#define XRFDC_TRSHD1_AVG_UPP_SHIFT 16U

Threshold1 Avg upper shift.

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_TRSHD1_CLR_MOD_MASK 0x00000004U

Clear mode.

Referenced by XRFdc_SetThresholdClrMode().

#define XRFDC_TRSHD1_EN_MOD_MASK 0x00000003U

Enable Threshold1 block.

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_TRSHD1_OVER_MASK 0x00007FFFU

Threshold1 under Threshold[14:0].

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_TRSHD1_STIKY_CLR_MASK 0x00000008U

Clear sticky bit.

Referenced by XRFdc_ThresholdStickyClear().

#define XRFDC_TRSHD1_UNDER_MASK 0x00007FFFU

Threshold1 under Threshold[14:0].

Referenced by XRFdc_GetThresholdSettings(), and XRFdc_SetThresholdSettings().

#define XRFDC_UPDT_EVNT_MASK 0x0000000FU

Update event mask.

Referenced by XRFdc_SetCoarseDelaySettings(), XRFdc_SetMixerSettings(), and XRFdc_SetQMCSettings().

#define XRFDC_UPDT_EVNT_NCO_MASK 0x00000002U

Trigger a update event apply to NCO_DCONFIG reg.

Referenced by XRFdc_SetMixerSettings().

#define XRFDC_UPDT_EVNT_QMC_MASK 0x00000004U

Trigger a update event apply to QMC_DCONFIG reg.

Referenced by XRFdc_SetQMCSettings().

#define XRFDC_UPDT_EVNT_SLICE_MASK 0x00000001U

Trigger a slice update event apply to _DCONFIG reg.

## Typedef Documentation

typedef void(* XRFdc_StatusHandler)(void *CallBackRef, u32 Type, u32 Tile_Id, u32 Block_Id, u32 StatusEvent)

The handler data type allows the user to define a callback function to respond to interrupt events in the system.

This function is executed in interrupt context, so amount of processing should be minimized.

Parameters

  CallBackRef | is the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer.
  Type | indicates ADC/DAC.
  Tile_Id | indicates Tile number (0-3).
  Block_Id | indicates Block number (0-3).
  StatusEvent | indicates one or more interrupt occurred.

## Function Documentation

u32 XRFdc_CfgInitialize | ( | XRFdc * | InstancePtr,
|  | XRFdc_Config * | ConfigPtr
| ) |  |

Initializes a specific XRFdc instance such that the driver is ready to use.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  ConfigPtr | is a reference to a structure containing information about xrfdc. This function initializes an InstancePtr object for a specific device specified by the contents of Config.

Returns
  - XRFDC_SUCCESS if successful.

Note
  The user needs to first call the XRFdc_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XRFdc_CfgInitialize() API.

Referenced by RFdcMTS_Example().

u32 XRFdc_DisableCoefficientsOverride | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | CalibrationBlock
| ) |  |

This function is used to disable Calibration Coefficients override.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | indicates Tile number (0-3).
  Block_Id | indicates Block number(0-3 for LS, 0-1 for HS).
  CalibrationBlock | indicates the calibration block.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_ADC_TI_DCB_CRL1_OFFSET, XRFDC_ADC_TI_DCB_CRL2_OFFSET, XRFDC_ADC_TI_DCB_CRL3_OFFSET, XRFDC_CAL_GCB_ACEN_MASK, XRFDC_CAL_GCB_EN_MASK, XRFDC_CAL_GCB_ENFL_MASK, XRFDC_CAL_GCB_MASK, XRFDC_CAL_OCB_EN_MASK, XRFDC_CAL_TSCB_EN_MASK, XRFDC_CAL_TSCB_OFFSET_COEFF0, XRFDC_CAL_TSCB_OFFSET_COEFF0_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF1, XRFDC_CAL_TSCB_OFFSET_COEFF1_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF2, XRFDC_CAL_TSCB_OFFSET_COEFF2_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF3, XRFDC_CAL_TSCB_OFFSET_COEFF3_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF4, XRFDC_CAL_TSCB_OFFSET_COEFF4_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF5, XRFDC_CAL_TSCB_OFFSET_COEFF5_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF6, XRFDC_CAL_TSCB_OFFSET_COEFF6_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF7, and XRFDC_CAL_TSCB_OFFSET_COEFF7_ALT.

void XRFdc_DumpRegs | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | int | Tile_Id
| ) |  |

This Prints the offset of the register along with the content.

This API is meant to be used for debug purposes. It prints to the console the contents of registers for the passed Tile_Id. If -1 is passed, it prints the contents of the registers for all the tiles for the respective ADC or DAC

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3, and -1.

Returns
  None

Note
  None.

u32 XRFdc_DynamicPLLConfig | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u8 | Source,
|  | double | RefClkFreq,
|  | double | SamplingRate
| ) |  |

This function used for dynamically switch between internal PLL and external clcok source and configuring the internal PLL.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | indicates ADC/DAC
  Tile_Id | indicates Tile number (0-3)
  Source | Clock source internal PLL or external clock source
  RefClkFreq | Reference Clock Frequency in MHz(102.40625MHz - 1.2GHz)
  SamplingRate | Sampling Rate in MHz(0.1- 6.554GHz for DAC and 0.5/1.0 - 2.058/4.116GHz for ADC based on the device package).

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  This API enables automatic selection of the VCO which will work in IP version 2.0.1 and above. Using older version of IP this API is not likely to work.

References XRFDC_CLK_NETWORK_CTRL1, XRFDC_CLK_NETWORK_CTRL1_USE_PLL_MASK, XRFdc_GetClockSource(), XRFDC_HSCOM_PWR_STATE_OFFSET, XRFDC_PLL_DIVIDER0, XRFDC_PLL_DIVIDER0_ALT_MASK, XRFDC_PLL_FREQ, XRFDC_PLL_FS, XRFDC_PWR_UP_STAT_MASK, XRFDC_PWR_UP_STAT_SHIFT, XRFdc_Shutdown(), XRFdc_StartUp(), XRFDC_STATUS_OFFSET, XRFdc_WriteReg, and XRFdc_WriteReg16.

Referenced by RFdcMTS_Example().

u32 XRFdc_GetBlockStatus | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_BlockStatus * | BlockStatusPtr
| ) |  |

The API returns the requested block status.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3. XRFdc_BlockStatus.
  BlockStatusPtr | is Pointer to the XRFdc_BlockStatus structure through which the ADC/DAC block status is returned.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if block not enabled.

Note
  Common API for ADC/DAC blocks.

References XRFDC_CLK_EN_OFFSET, and XRFDC_DAT_CLK_EN_MASK.

u32 XRFdc_GetCalCoefficients | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | CalibrationBlock,
|  | XRFdc_Calibration_Coefficients * | CoeffPtr
| ) |  |

This function is used to get the ADC Calibration Coefficients.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | indicates Tile number (0-3).
  Block_Id | indicates Block number(0-3 for LS, 0-1 for HS).
  CalibrationBlock | indicates the block to be read from
  CoeffPtr | is pointer to the XRFdc_Calibration_Coefficients structure to get the calibration coefficients.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_ADC_TI_DCB_CRL1_OFFSET, XRFDC_CAL_GCB_FAB_MASK, XRFDC_CAL_GCB_FLSH_MASK, XRFDC_CAL_GCB_MASK, XRFDC_CAL_GCB_OFFSET_COEFF0, XRFDC_CAL_GCB_OFFSET_COEFF0_ALT, XRFDC_CAL_GCB_OFFSET_COEFF1, XRFDC_CAL_GCB_OFFSET_COEFF1_ALT, XRFDC_CAL_GCB_OFFSET_COEFF2, XRFDC_CAL_GCB_OFFSET_COEFF2_ALT, XRFDC_CAL_GCB_OFFSET_COEFF3, XRFDC_CAL_GCB_OFFSET_COEFF3_ALT, XRFDC_CAL_OCB1_OFFSET_COEFF0, XRFDC_CAL_OCB1_OFFSET_COEFF1, XRFDC_CAL_OCB1_OFFSET_COEFF2, XRFDC_CAL_OCB1_OFFSET_COEFF3, XRFDC_CAL_OCB2_OFFSET_COEFF0, XRFDC_CAL_OCB2_OFFSET_COEFF1, XRFDC_CAL_OCB2_OFFSET_COEFF2, XRFDC_CAL_OCB2_OFFSET_COEFF3, XRFDC_CAL_OCB_MASK, XRFDC_CAL_SLICE_SHIFT, XRFDC_CAL_TSCB_MASK, XRFDC_CAL_TSCB_OFFSET_COEFF0, XRFDC_CAL_TSCB_OFFSET_COEFF0_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF1, XRFDC_CAL_TSCB_OFFSET_COEFF1_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF2, XRFDC_CAL_TSCB_OFFSET_COEFF2_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF3, XRFDC_CAL_TSCB_OFFSET_COEFF3_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF4, XRFDC_CAL_TSCB_OFFSET_COEFF4_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF5, XRFDC_CAL_TSCB_OFFSET_COEFF5_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF6, XRFDC_CAL_TSCB_OFFSET_COEFF6_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF7, and XRFDC_CAL_TSCB_OFFSET_COEFF7_ALT.

u32 XRFdc_GetCalFreeze | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_Cal_Freeze_Settings * | CalFreezePtr
| ) |  |

This function is used to get calibration freeze settings and status.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | indicates Tile number (0-3).
  Block_Id | indicates Block number(0-3 for LS, 0-1 for HS).
  CalFreezePtr | pointer to be filled the settings/status.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_CAL_FREEZE_CAL_MASK, XRFDC_CAL_FREEZE_CAL_SHIFT, XRFDC_CAL_FREEZE_PIN_MASK, XRFDC_CAL_FREEZE_PIN_SHIFT, XRFDC_CAL_FREEZE_STS_MASK, and XRFDC_CAL_FREEZE_STS_SHIFT.

u32 XRFdc_GetCalibrationMode | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u8 * | CalibrationModePtr
| ) |  |

This API is to get the Calibration mode.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  CalibrationModePtr | pointer to get the calibration mode.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_ADC_TI_DCB_CRL0_OFFSET, and XRFDC_TI_DCB_MODE_MASK.

Referenced by XRFdc_GetMixerSettings(), XRFdc_GetNyquistZone(), XRFdc_SetMixerSettings(), and XRFdc_SetNyquistZone().

u32 XRFdc_GetClkDistribution | ( | XRFdc * | InstancePtr,
|  | XRFdc_Distribution_Settings * | DistributionSettingsPtr
| ) |  |

This function is used to get the clock distribution.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  DistributionSettingsPtr | pointer to get the distribution settings

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if no valid distribution found.

References XRFdc_GetPLLConfig(), XRFDC_HSCOM_CLK_DSTR_MASK, XRFDC_HSCOM_CLK_DSTR_MASK_ALT, XRFDC_HSCOM_CLK_DSTR_OFFSET, and XRFdc_ReadReg16.

u32 XRFdc_GetClockSource | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 * | ClockSourcePtr
| ) |  |

This function gets Clock source.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | indicates ADC/DAC.
  Tile_Id | indicates Tile number (0-3).
  ClockSourcePtr | Pointer to return the clock source

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if tile not enabled.

Note
  None.

References XRFDC_CLK_NETWORK_CTRL1, XRFDC_CLK_NETWORK_CTRL1_USE_PLL_MASK, XRFDC_PLL_DIVIDER0, and XRFdc_ReadReg16.

Referenced by XRFdc_DynamicPLLConfig(), XRFdc_GetPLLConfig(), and XRFdc_GetPLLLockStatus().

u32 XRFdc_GetCoarseDelaySettings | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_CoarseDelay_Settings * | CoarseDelaySettingsPtr
| ) |  |

Coarse delay settings are returned back to the caller.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  CoarseDelaySettingsPtr | Pointer to the XRFdc_CoarseDelay_Settings structure in which the Coarse Delay settings are passed.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  None.

References XRFDC_ADC_CRSE_DLY_CFG_OFFSET, XRFDC_ADC_CRSE_DLY_UPDT_OFFSET, XRFDC_DAC_CRSE_DLY_CFG_OFFSET, XRFDC_DAC_CRSE_DLY_UPDT_OFFSET, XRFDC_QMC_UPDT_MODE_MASK, and XRFdc_ReadReg16.

u32 XRFdc_GetDACCompMode | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | EnabledPtr
| ) |  |

Gets VOP compatibility mode.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  mode | is ADC/DAC block number inside the tile. Valid values are 0-3.
  EnabledPtr | is pointer a that is filled with whether the mode is enabled (1) or disabled(0).

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  None.

References XRFDC_ADC_DAC_MC_CFG2_OFFSET.

u32 XRFdc_GetDataPathMode | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | ModePtr
| ) |  |

This API is to get the DAC Datapath mode.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  ModePtr | pointer used to return value.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for DAC blocks

References XRFDC_DAC_DATAPATH_OFFSET, and XRFDC_DATAPATH_MODE_MASK.

u32 XRFdc_GetDecimationFactor | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | DecimationFactorPtr
| ) |  |

Decimation factor are returned back to the caller.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  DecimationFactorPtr | Pointer to return the Decimation factor for DAC blocks.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_ADC_DECI_MODE_OFFSET, XRFDC_DEC_MOD_MASK, and XRFDC_DEC_MOD_MASK_EXT.

Referenced by RFdcMTS_Example().

u32 XRFdc_GetDecoderMode | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | DecoderModePtr
| ) |  |

Decoder mode is read and returned back.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is DAC block number inside the tile. Valid values are 0-3.
  DecoderModePtr | Valid values are 1 (Maximum SNR, for non-randomized decoder), 2 (Maximum Linearity, for randomized decoder)

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for DAC blocks

References XRFDC_DAC_DECODER_CTRL_OFFSET, and XRFDC_DEC_CTRL_MODE_MASK.

s32 XRFdc_GetDeviceNameByDeviceId | ( | char * | DevNamePtr,
|  | u16 | DevId
| ) |  |

Traverse "/sys/bus/platform/device" directory, to find RFDC device entry, corresponding to provided device id.

If device entry corresponding to said device id is found, store it in output buffer DevNamePtr.

Parameters

  DevNamePtr | is base address of char array, where device name will be stored
  DevId | contains the ID of the device to look up the RFDC device name entry in "/sys/bus/platform/device"

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if device entry not found for given device id.

Note
  None.

Referenced by XRFdc_LookupConfig(), and XRFdc_RegisterMetal().

u32 XRFdc_GetDither | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | ModePtr
| ) |  |

This function is used to get the IM3 Dither mode.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | indicates Tile number (0-3).
  Block_Id | indicates Block number(0-3 for LS, 0-1 for HS).
  ModePtr | pointer to get link coupling mode.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_ADC_DAC_MC_CFG0_OFFSET, and XRFDC_RX_MC_CFG0_IM3_DITH_MASK.

u32 XRFdc_GetDSA | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_DSA_Settings * | SettingsPtr
| ) |  |

Get DSA for ADC block.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  AttenuationPtr | is the attenuation in dB

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Range 0 - ll dB with 0.5 dB resolution.

References XRFdc_ReadReg16.

u32 XRFdc_GetEnabledInterrupts | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | IntrMask
| ) |  |

This function gets a mask of enabled interrupts.

Parameters

  InstancePtr | is a pointer to the XRFdc instance
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3, and -1.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  IntrMask | is a pointer to the mask of enabled interrupts. '1' denotes an enabled interrupt, and '0' denotes a disabled interrupt.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if block not available.

Note
  None.

References XRFDC_ADC_DAT_IMR_MASK, XRFDC_ADC_DEC_IMR_OFFSET, XRFDC_ADC_FABRIC_IMR_OFFSET, XRFDC_COMMON_INTR_ENABLE, XRFDC_DAC_DAT_IMR_MASK, XRFDC_DAC_FABRIC_IMR_OFFSET, XRFDC_DATPATH_IMR_OFFSET, XRFDC_INTR_ENABLE, XRFdc_ReadReg, and XRFdc_ReadReg16.

u32 XRFdc_GetFabClkOutDiv | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u16 * | FabClkDivPtr
| ) |  |

This API is to get the divider for clock fabric out.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  FabClkDivPtr | is a pointer to get fabric clock for a tile. XRFDC_FAB_CLK_* defines the valid divider values.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  API is applicable for both ADC and DAC Tiles

References XRFDC_FAB_CLK_DIV_MASK, and XRFDC_HSCOM_CLK_DIV_OFFSET.

u32 XRFdc_GetFabRdVldWords | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | FabricRdVldWordsPtr
| ) |  |

This API returns the the number of fabric read valid words requested for the block.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  FabricRdVldWordsPtr | Pointer to return the fabric data rate for ADC/DAC block

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  ADC/DAC blocks

References XRFDC_ADC_FAB_RATE_WR_MASK, XRFDC_ADC_FABRIC_RATE_OFFSET, XRFDC_DAC_FAB_RATE_WR_MASK, XRFDC_FAB_RATE_RD_SHIFT, and XRFdc_ReadReg16.

u32 XRFdc_GetFabWrVldWords | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | FabricWrVldWordsPtr
| ) |  |

This API returns the the number of fabric write valid words requested for the block.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  FabricWrVldWordsPtr | Pointer to return the fabric data rate for DAC block

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  ADC/DAC blocks

References XRFDC_ADC_FAB_RATE_WR_MASK, XRFDC_ADC_FABRIC_RATE_OFFSET, XRFDC_DAC_FAB_RATE_WR_MASK, and XRFdc_ReadReg16.

u32 XRFdc_GetFIFOStatus | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u8 * | EnablePtr
| ) |  |

Current status of ADC/DAC FIFO.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  EnablePtr | valid values are 1 (FIFO enable) and 0 (FIFO Disable)

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Common API for ADC/DAC blocks

References XRFDC_FIFO_EN_MASK, and XRFDC_FIFO_ENABLE.

u32 XRFdc_GetIMRPassMode | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | ModePtr
| ) |  |

This API is to get the DAC Image Reject Filter Pass mode.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  ModePtr | pointer used to return value.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for DAC blocks

References XRFDC_DAC_DATAPATH_OFFSET, and XRFDC_DATAPATH_IMR_MASK.

u32 XRFdc_GetInterpolationFactor | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | InterpolationFactorPtr
| ) |  |

Interpolation factor are returned back to the caller.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  InterpolationFactorPtr | Pointer to return the interpolation factor for DAC blocks.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for DAC blocks

References XRFDC_DAC_INTERP_CTRL_OFFSET, XRFDC_INTERP_MODE_I_MASK, and XRFDC_INTERP_MODE_I_MASK_EXT.

Referenced by RFdcMTS_Example().

u32 XRFdc_GetIntrStatus | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | IntrStsPtr
| ) |  |

This function returns the interrupt status read from Interrupt Status Register(ISR).

Parameters

  InstancePtr | is a pointer to the XRFdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3, and -1.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  IntrStsPtr | is pointer to a32-bit value representing the contents of the Interrupt Status Registers (FIFO interface, Decoder interface, Data Path Interface).

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if block not available.

Note
  None.

References XRFDC_ADC_DAT_PATH_ISR_MASK, XRFDC_ADC_DEC_ISR_OFFSET, XRFDC_ADC_FABRIC_ISR_OFFSET, XRFDC_DAC_DAT_PATH_ISR_MASK, XRFDC_DAC_FABRIC_ISR_OFFSET, XRFDC_DATPATH_ISR_OFFSET, XRFDC_DEC_ISR_SUBADC_MASK, XRFDC_INTR_CMODE_OVR_MASK, XRFDC_INTR_CMODE_UNDR_MASK, XRFDC_INTR_COMMON_MASK, XRFDC_INTR_DAT_OVR_MASK, XRFDC_INTR_FIFO_OVR_MASK, XRFDC_INTR_OVR_RANGE_MASK, XRFDC_INTR_OVR_VOLTAGE_MASK, XRFDC_INTR_STS, XRFdc_ReadReg, and XRFdc_ReadReg16.

Referenced by XRFdc_IntrHandler().

u32 XRFdc_GetInvSincFIR | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u16 * | ModePtr
| ) |  |

This API is used to get the Inverse-Sinc filter mode.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is DAC block number inside the tile. Valid values are 0-3.
  ModePtr | is a pointer to get the inv-sinc status. valid values are 0(disable), 1(1st Nyquist zone) and 2(2nd Nyquist zone).

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only DAC blocks

References XRFDC_DAC_INVSINC_OFFSET, XRFDC_EN_INVSINC_MASK, and XRFDC_MODE_INVSINC_MASK.

u32 XRFdc_GetIPStatus | ( | XRFdc * | InstancePtr,
|  | XRFdc_IPStatus * | IPStatusPtr
| ) |  |

The API returns the IP status.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  IPStatusPtr | Pointer to the XRFdc_IPStatus structure through which the status is returned.

Returns
  - XRFDC_SUCCESS if successful.

Note
  None.

References XRFDC_CURRENT_STATE_OFFSET, XRFDC_PLL_LOCKED_MASK, XRFDC_PLL_LOCKED_SHIFT, XRFDC_PWR_UP_STAT_MASK, XRFDC_PWR_UP_STAT_SHIFT, XRFdc_ReadReg16, and XRFDC_STATUS_OFFSET.

Referenced by XRFdc_MultiConverter_Sync().

u32 XRFdc_GetLinkCoupling | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | ModePtr
| ) |  |

This function is used to get the Link Coupling mode.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | indicates Tile number (0-3).
  Block_Id | indicates Block number(0-3 for 2G, 0-1 for 4G).
  ModePtr | pointer to get link coupling mode.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_ADC_RXPR_MC_CFG0_OFFSET, and XRFDC_RX_MC_CFG0_CM_MASK.

u32 XRFdc_GetMixerSettings | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_Mixer_Settings * | MixerSettingsPtr
| ) |  |

The API returns back Mixer/NCO settings to the caller.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  MixerSettingsPtr | Pointer to the XRFdc_Mixer_Settings structure in which the Mixer/NCO settings are passed.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  FineMixerScale in Mixer_Settings structure can have 3 values. XRFDC_MIXER_SCALE_* represents the valid values. XRFDC_MIXER_SCALE_AUTO - If mixer mode is R2C, Mixer Scale is set to 1 and for other modes mixer scale is set to 0.7 XRFDC_MIXER_SCALE_1P0 - To set fine mixer scale to 1. XRFDC_MIXER_SCALE_0P7 - To set fine mixer scale to 0.7.

References XRFDC_ADC_MXR_CFG0_OFFSET, XRFDC_ADC_MXR_CFG1_OFFSET, XRFDC_ADC_NCO_FQWD_LOW_OFFSET, XRFDC_ADC_NCO_FQWD_MID_OFFSET, XRFDC_ADC_NCO_FQWD_UPP_OFFSET, XRFDC_EN_I_IQ_MASK, XRFDC_EN_Q_IQ_MASK, XRFDC_FINE_MIX_SCALE_MASK, XRFdc_GetCalibrationMode(), XRFdc_GetNyquistZone(), XRFDC_MIX_CFG0_MASK, XRFDC_MIX_CFG1_MASK, XRFDC_MXR_MODE_OFFSET, XRFDC_NCO_FQWD_MASK, XRFDC_NCO_FQWD_MID_SHIFT, XRFDC_NCO_FQWD_UPP_SHIFT, XRFDC_NCO_PHASE_LOW_OFFSET, XRFDC_NCO_PHASE_MASK, XRFDC_NCO_PHASE_UPP_OFFSET, XRFDC_NCO_PHASE_UPP_SHIFT, XRFDC_NCO_UPDT_MODE_MASK, XRFDC_NCO_UPDT_OFFSET, and XRFdc_ReadReg16.

Referenced by XRFdc_SetCalibrationMode().

u32 XRFdc_GetNyquistZone | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | NyquistZonePtr
| ) |  |

Get the Nyquist zone.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  NyquistZonePtr | Pointer to return the Nyquist zone.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Common API for ADC/DAC blocks

References XRFDC_ADC_TI_TISK_CRL0_OFFSET, XRFDC_DAC_MC_CFG0_OFFSET, XRFdc_GetCalibrationMode(), XRFDC_MC_CFG0_MIX_MODE_MASK, XRFDC_MC_CFG0_MIX_MODE_SHIFT, XRFDC_TI_TISK_ZONE_MASK, and XRFDC_TISK_ZONE_SHIFT.

Referenced by XRFdc_GetMixerSettings(), XRFdc_SetCalibrationMode(), and XRFdc_SetMixerSettings().

u32 XRFdc_GetOutputCurr | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 * | OutputCurrPtr
| ) |  |

Get Output Current for DAC block.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  OutputCurrPtr | pointer to return the output current.

Returns
  - Return Output Current for DAC block

References XRFDC_ADC_DAC_MC_CFG2_OFFSET, and XRFDC_DAC_MC_CFG3_OFFSET.

u32 XRFdc_GetPLLConfig | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | XRFdc_PLL_Settings * | PLLSettings
| ) |  |

This API is used to get the PLL Configurations.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | represents ADC or DAC.
  Tile_Id | Valid values are 0-3.
  PLLSettings | pointer to the XRFdc_PLL_Settings structure to get the PLL configurations

Note
  None.

References XRFdc_GetClockSource(), XRFDC_PLL_DIVIDER0, XRFDC_PLL_FPDIV, XRFDC_PLL_FREQ, XRFDC_PLL_FS, XRFDC_PLL_REFDIV, XRFdc_ReadReg, XRFdc_ReadReg16, XRFDC_REFCLK_DIV_2_MASK, XRFDC_REFCLK_DIV_3_MASK, and XRFDC_REFCLK_DIV_4_MASK.

Referenced by XRFdc_GetClkDistribution().

u32 XRFdc_GetPLLLockStatus | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 * | LockStatusPtr
| ) |  |

This function gets PLL lock status.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | indicates ADC/DAC.
  Tile_Id | indicates Tile number (0-3).
  LockStatusPtr | Pointer to return the PLL lock status

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  None.

References XRFdc_GetClockSource(), XRFDC_PLL_LOCKED_MASK, and XRFDC_STATUS_OFFSET.

u32 XRFdc_GetQMCSettings | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_QMC_Settings * | QMCSettingsPtr
| ) |  |

QMC settings are returned back to the caller through this API.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  QMCSettingsPtr | Pointer to the XRFdc_QMC_Settings structure in which the QMC settings are passed.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  None.

References XRFDC_QMC_CFG_EN_GAIN_MASK, XRFDC_QMC_CFG_EN_PHASE_MASK, XRFDC_QMC_CFG_OFFSET, XRFDC_QMC_CFG_PHASE_SHIFT, XRFDC_QMC_GAIN_CRCTN_MASK, XRFDC_QMC_GAIN_OFFSET, XRFDC_QMC_OFF_OFFSET, XRFDC_QMC_OFFST_CRCTN_MASK, XRFDC_QMC_PHASE_CRCTN_MASK, XRFDC_QMC_PHASE_OFFSET, XRFDC_QMC_UPDT_MODE_MASK, and XRFDC_QMC_UPDT_OFFSET.

u32 XRFdc_GetSignalDetector | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_Signal_Detector_Settings * | SettingsPtr
| ) |  |

This function is used to get the ADC Signal Detector Settings.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | indicates Tile number (0-3).
  Block_Id | indicates Block number(0-3 for LS, 0-1 for HS).
  SettingsPtr | pointer to the XRFdc_Signal_Detector_Settings structure to get the signal detector configurations

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_ADC_SIG_DETECT_CTRL_OFFSET, XRFDC_ADC_SIG_DETECT_FLUSH_MASK, XRFDC_ADC_SIG_DETECT_FLUSH_SHIFT, XRFDC_ADC_SIG_DETECT_HYST_MASK, XRFDC_ADC_SIG_DETECT_HYST_SHIFT, XRFDC_ADC_SIG_DETECT_INTG_MASK, XRFDC_ADC_SIG_DETECT_INTG_SHIFT, XRFDC_ADC_SIG_DETECT_MASK, XRFDC_ADC_SIG_DETECT_MODE_MASK, XRFDC_ADC_SIG_DETECT_MODE_READ_SHIFT, XRFDC_ADC_SIG_DETECT_TCONST_MASK, XRFDC_ADC_SIG_DETECT_TCONST_SHIFT, XRFDC_ADC_SIG_DETECT_THRESH_MASK, XRFDC_ADC_SIG_DETECT_THRESHOLD0_LEVEL_OFFSET, and XRFDC_ADC_SIG_DETECT_THRESHOLD1_LEVEL_OFFSET.

u32 XRFdc_GetThresholdSettings | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_Threshold_Settings * | ThresholdSettingsPtr
| ) |  |

Threshold settings are read from the corresponding registers and are passed back to the caller.

There can be two threshold settings: threshold0 and threshold1. Both of them are independent of each other. The function returns the requested threshold (which can be threshold0, threshold1, or both.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  ThresholdSettingsPtr | Pointer through which the register settings for thresholds are passed back..

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_ADC_TRSHD0_AVG_LO_OFFSET, XRFDC_ADC_TRSHD0_AVG_UP_OFFSET, XRFDC_ADC_TRSHD0_CFG_OFFSET, XRFDC_ADC_TRSHD0_OVER_OFFSET, XRFDC_ADC_TRSHD0_UNDER_OFFSET, XRFDC_ADC_TRSHD1_AVG_LO_OFFSET, XRFDC_ADC_TRSHD1_AVG_UP_OFFSET, XRFDC_ADC_TRSHD1_CFG_OFFSET, XRFDC_ADC_TRSHD1_OVER_OFFSET, XRFDC_ADC_TRSHD1_UNDER_OFFSET, XRFdc_ReadReg16, XRFDC_TRSHD0_AVG_UPP_SHIFT, XRFDC_TRSHD0_EN_MOD_MASK, XRFDC_TRSHD0_OVER_MASK, XRFDC_TRSHD0_UNDER_MASK, XRFDC_TRSHD1_AVG_UPP_SHIFT, XRFDC_TRSHD1_EN_MOD_MASK, XRFDC_TRSHD1_OVER_MASK, and XRFDC_TRSHD1_UNDER_MASK.

u32 XRFdc_IntrClr | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | IntrMask
| ) |  |

This function clear the interrupts.

Parameters

  InstancePtr | is a pointer to the XRFdc instance
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3, and -1.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  IntrMask | contains the interrupts to be cleared.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if block not available.

Note
  None.

References XRFDC_ADC_DEC_ISR_OFFSET, XRFDC_ADC_FABRIC_ISR_OFFSET, XRFDC_DAC_FABRIC_ISR_OFFSET, XRFDC_DATPATH_ISR_OFFSET, XRFdc_WriteReg, and XRFdc_WriteReg16.

Referenced by XRFdc_IntrHandler().

u32 XRFdc_IntrDisable | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | IntrMask
| ) |  |

This function clears the interrupt mask.

Parameters

  InstancePtr | is a pointer to the XRFdc instance
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3, and -1.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  IntrMask | contains the interrupts to be disabled. '1' disables an interrupt, and '0' remains no change.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if block not available.

Note
  None.

References XRFDC_ADC_DEC_IMR_OFFSET, XRFDC_ADC_FABRIC_IMR_OFFSET, XRFDC_DAC_FABRIC_IMR_OFFSET, XRFDC_DATPATH_IMR_OFFSET, XRFDC_INTR_ENABLE, XRFdc_ReadReg, and XRFdc_WriteReg.

Referenced by RFdcHandler().

u32 XRFdc_IntrEnable | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | IntrMask
| ) |  |

This function sets the interrupt mask.

Parameters

  InstancePtr | is a pointer to the XRFdc instance
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3, and -1.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  IntrMask | contains the interrupts to be enabled. '1' enables an interrupt, and '0' disables.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if block not available.

Note
  None.

References XRFDC_ADC_DAT_IMR_MASK, XRFDC_ADC_DEC_IMR_OFFSET, XRFDC_ADC_FABRIC_IMR_OFFSET, XRFDC_COMMON_INTR_ENABLE, XRFDC_DAC_DAT_IMR_MASK, XRFDC_DAC_FABRIC_IMR_OFFSET, XRFDC_DATPATH_IMR_OFFSET, XRFDC_INTR_ENABLE, XRFdc_ReadReg, XRFdc_ReadReg16, XRFdc_WriteReg, and XRFdc_WriteReg16.

u32 XRFdc_IntrHandler | ( | u32 | Vector,
|  | void * | XRFdcPtr
| ) |  |

This function is the interrupt handler for the driver.

It must be connected to an interrupt system by the application such that it can be called when an interrupt occurs.

Parameters

  Vector | is interrupt vector number. Libmetal status handler expects two parameters in the handler prototype, hence kept this parameter. This is not used inside the interrupt handler API.
  XRFdcPtr | contains a pointer to the driver instance

Note
  None.
  Vector param is not useful inside the interrupt handler, hence typecast with void to remove compilation warning.

References XRFDC_COMMON_INTR_STS, XRFDC_EN_INTR_ADC_TILE0_MASK, XRFDC_EN_INTR_ADC_TILE1_MASK, XRFDC_EN_INTR_ADC_TILE2_MASK, XRFDC_EN_INTR_ADC_TILE3_MASK, XRFDC_EN_INTR_DAC_TILE0_MASK, XRFDC_EN_INTR_DAC_TILE1_MASK, XRFDC_EN_INTR_DAC_TILE2_MASK, XRFDC_EN_INTR_DAC_TILE3_MASK, XRFDC_EN_INTR_SLICE0_MASK, XRFDC_EN_INTR_SLICE1_MASK, XRFDC_EN_INTR_SLICE2_MASK, XRFDC_EN_INTR_SLICE3_MASK, XRFdc_GetIntrStatus(), XRFDC_INTR_COMMON_MASK, XRFDC_INTR_STS, XRFdc_IntrClr(), and XRFdc_ReadReg16.

XRFdc_Config * XRFdc_LookupConfig | ( | u16 | DeviceId | ) |

Looks up the device configuration based on the unique device ID.

A table contains the configuration info for each device in the system.

Parameters

  DeviceId | contains the ID of the device to look up the configuration for.

Returns

A pointer to the configuration found or NULL if the specified device ID was not found. See xrfdc.h for the definition of XRFdc_Config.

Note
  None.

References XRFdc_GetDeviceNameByDeviceId().

Referenced by RFdcMTS_Example().

u32 XRFdc_MultiBand | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u8 | DigitalDataPathMask,
|  | u32 | MixerInOutDataType,
|  | u32 | DataConverterMask
| ) |  |

User-level API to setup multiband configuration.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  DigitalDataPathMask | is the DataPath mask. First 4 bits represent 4 data paths, 1 means enabled and 0 means disabled.
  MixerInOutDataType | is mixer data type, valid values are XRFDC_MB_DATATYPE_*
  DataConverterMask | is block enabled mask (input/output driving blocks). 1 means enabled and 0 means disabled.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Common API for ADC/DAC blocks

References XRFDC_DAC_MB_CFG_OFFSET.

u32 XRFdc_RegisterMetal | ( | XRFdc * | InstancePtr,
|  | u16 | DeviceId,
|  | struct metal_device ** | DevicePtr
| ) |  |

Register/open the deviceand map RFDC to the IO region.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  DeviceId | contains the ID of the device to register/map
  DevicePtr | is a pointer to the metal device.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  None.

References XRFdc_GetDeviceNameByDeviceId().

Referenced by RFdcMTS_Example().

u32 XRFdc_Reset | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | int | Tile_Id
| ) |  |

The API resets the requested tile.

It can reset all the tiles as well. In the process, all existing register settings are cleared and are replaced with the settings initially configured (through the GUI).

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3, and -1.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  None.

u32 XRFdc_ResetNCOPhase | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id
| ) |  |

Resets the NCO phase of the current block phase accumulator.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  None.

References XRFDC_NCO_PHASE_RST_MASK, and XRFDC_NCO_RST_OFFSET.

u32 XRFdc_SetCalCoefficients | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | CalibrationBlock,
|  | XRFdc_Calibration_Coefficients * | CoeffPtr
| ) |  |

This function is used to set the ADC Calibration Coefficients.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | indicates Tile number (0-3).
  Block_Id | indicates Block number(0-3 for LS, 0-1 for HS).
  CalibrationBlock | indicates the block to be written to.
  CoeffPtr | is pointer to the XRFdc_Calibration_Coefficients structure to set the calibration coefficients.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_ADC_TI_DCB_CRL1_OFFSET, XRFDC_ADC_TI_DCB_CRL2_OFFSET, XRFDC_ADC_TI_DCB_CRL3_OFFSET, XRFDC_CAL_GCB_ACEN_MASK, XRFDC_CAL_GCB_EN_MASK, XRFDC_CAL_GCB_EN_SHIFT, XRFDC_CAL_GCB_FLSH_MASK, XRFDC_CAL_GCB_FLSH_SHIFT, XRFDC_CAL_GCB_MASK, XRFDC_CAL_GCB_OFFSET_COEFF0, XRFDC_CAL_GCB_OFFSET_COEFF1, XRFDC_CAL_GCB_OFFSET_COEFF2, XRFDC_CAL_GCB_OFFSET_COEFF3, XRFDC_CAL_OCB1_OFFSET_COEFF0, XRFDC_CAL_OCB1_OFFSET_COEFF1, XRFDC_CAL_OCB1_OFFSET_COEFF2, XRFDC_CAL_OCB1_OFFSET_COEFF3, XRFDC_CAL_OCB2_OFFSET_COEFF0, XRFDC_CAL_OCB2_OFFSET_COEFF1, XRFDC_CAL_OCB2_OFFSET_COEFF2, XRFDC_CAL_OCB2_OFFSET_COEFF3, XRFDC_CAL_OCB_EN_MASK, XRFDC_CAL_OCB_MASK, XRFDC_CAL_SLICE_SHIFT, XRFDC_CAL_TSCB_EN_MASK, XRFDC_CAL_TSCB_EN_SHIFT, XRFDC_CAL_TSCB_MASK, XRFDC_CAL_TSCB_OFFSET_COEFF0, XRFDC_CAL_TSCB_OFFSET_COEFF0_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF1, XRFDC_CAL_TSCB_OFFSET_COEFF1_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF2, XRFDC_CAL_TSCB_OFFSET_COEFF2_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF3, XRFDC_CAL_TSCB_OFFSET_COEFF3_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF4, XRFDC_CAL_TSCB_OFFSET_COEFF4_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF5, XRFDC_CAL_TSCB_OFFSET_COEFF5_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF6, XRFDC_CAL_TSCB_OFFSET_COEFF6_ALT, XRFDC_CAL_TSCB_OFFSET_COEFF7, and XRFDC_CAL_TSCB_OFFSET_COEFF7_ALT.

u32 XRFdc_SetCalFreeze | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_Cal_Freeze_Settings * | CalFreezePtr
| ) |  |

This function is used to set calibration freeze settings.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | indicates Tile number (0-3).
  Block_Id | indicates Block number(0-3 for LS, 0-1 for HS).
  CalFreezePtr | pointer to the settings to be applied.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_CAL_FREEZE_CAL_MASK, XRFDC_CAL_FREEZE_CAL_SHIFT, XRFDC_CAL_FREEZE_PIN_MASK, and XRFDC_CAL_FREEZE_PIN_SHIFT.

u32 XRFdc_SetCalibrationMode | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u8 | CalibrationMode
| ) |  |

This API is to set the Calibration mode.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  CalibrationMode | valid values are 1 and 2.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_ADC_TI_DCB_CRL0_OFFSET, XRFdc_GetMixerSettings(), XRFdc_GetNyquistZone(), XRFdc_ReadReg16, XRFdc_SetMixerSettings(), XRFdc_SetNyquistZone(), XRFDC_TI_DCB_MODE_MASK, and XRFdc_WriteReg16.

u32 XRFdc_SetClkDistribution | ( | XRFdc * | InstancePtr,
|  | XRFdc_Distribution_Settings * | DistributionSettingsPtr
| ) |  |

This function is used to set the clock distribution.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  DistributionSettingsPtr | pointer to the distribution settings struct

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if could not set distribution.

References XRFDC_CLOCK_DETECT_MASK, XRFDC_CLOCK_DETECT_OFFSET, XRFDC_HSCOM_CLK_DSTR_MASK, XRFDC_HSCOM_CLK_DSTR_OFFSET, and XRFdc_Shutdown().

u32 XRFdc_SetCoarseDelaySettings | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_CoarseDelay_Settings * | CoarseDelaySettingsPtr
| ) |  |

Coarse delay settings passed are used to update the corresponding block level registers.

Driver structure is updated with the new values.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  CoarseDelaySettingsPtr | is Pointer to the XRFdc_CoarseDelay_Settings structure in which the CoarseDelay settings are passed.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  None.

References XRFDC_ADC_CRSE_DLY_CFG_OFFSET, XRFDC_ADC_CRSE_DLY_UPDT_OFFSET, XRFDC_ADC_UPDATE_DYN_OFFSET, XRFDC_ADC_UPDT_CRSE_DLY_MASK, XRFDC_CRSE_DLY_CFG_MASK, XRFDC_CRSE_DLY_CFG_MASK_EXT, XRFDC_DAC_CRSE_DLY_CFG_OFFSET, XRFDC_DAC_CRSE_DLY_UPDT_OFFSET, XRFDC_DAC_UPDATE_DYN_OFFSET, XRFDC_DAC_UPDT_CRSE_DLY_MASK, XRFDC_QMC_UPDT_MODE_MASK, and XRFDC_UPDT_EVNT_MASK.

u32 XRFdc_SetDACCompMode | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | Enable
| ) |  |

Sets VOP compatibility mode.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  mode | is ADC/DAC block number inside the tile. Valid values are 0-3.
  Enable | is whether to enable (1) or disable(0) the compatibility mode.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  None.

References XRFDC_ADC_DAC_MC_CFG2_OFFSET.

u32 XRFdc_SetDACVOP | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | uACurrent
| ) |  |

Set Output Current for DAC block.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  uACurrent | is the current in uA.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Range 6425 - 32000 uA with 25 uA resolution.

References XRFDC_ADC_DAC_MC_CFG0_OFFSET, XRFDC_ADC_DAC_MC_CFG2_OFFSET, XRFDC_DAC_MC_CFG3_OFFSET, XRFDC_DAC_VOP_CTRL_OFFSET, and XRFdc_ReadReg16.

u32 XRFdc_SetDataPathMode | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | Mode
| ) |  |

This API is to set the DAC Datapath mode.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  Mode | valid values are 0-3.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if tile not enabled / out of range.

Note
  Only for DAC blocks

References XRFDC_ADC_FABRIC_RATE_OFFSET, XRFDC_DAC_DATAPATH_OFFSET, XRFDC_DAC_FAB_RATE_RD_MASK, XRFDC_DATAPATH_MODE_MASK, XRFDC_FAB_CLK_DIV_CAL_MASK, XRFDC_FAB_RATE_RD_SHIFT, XRFDC_HSCOM_CLK_DIV_OFFSET, and XRFdc_SetNyquistZone().

u32 XRFdc_SetDecimationFactor | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | DecimationFactor
| ) |  |

This API is to set the decimation factor and also update the FIFO write words w.r.t to decimation factor.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  DecimationFactor | to be set for DAC block. XRFDC_INTERP_DECIM_* defines the valid values.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only ADC blocks

References XRFDC_ADC_DECI_CONFIG_OFFSET, XRFDC_ADC_DECI_MODE_OFFSET, XRFDC_ADC_FAB_RATE_WR_MASK, XRFDC_ADC_FABRIC_RATE_OFFSET, XRFDC_DEC_CFG_MASK, XRFDC_DEC_MOD_MASK, and XRFDC_DEC_MOD_MASK_EXT.

u32 XRFdc_SetDecoderMode | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | DecoderMode
| ) |  |

Decoder mode is updated into the relevant registers.

Driver structure is updated with the new values.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is DAC block number inside the tile. Valid values are 0-3.
  DecoderMode | Valid values are 1 (Maximum SNR, for non- randomized decoder), 2 (Maximum Linearity, for randomized decoder)

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only DAC blocks

References XRFDC_DAC_DECODER_CLK_OFFSET, XRFDC_DAC_DECODER_CTRL_OFFSET, and XRFDC_DEC_CTRL_MODE_MASK.

u32 XRFdc_SetDither | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | Mode
| ) |  |

This function is used to set the IM3 Dither mode.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | indicates Tile number (0-3).
  Block_Id | indicates Block number(0-3 for LS, 0-1 for HS).
  Mode | 0: Disable 1: Enable

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_ADC_DAC_MC_CFG0_OFFSET, XRFDC_RX_MC_CFG0_IM3_DITH_MASK, and XRFDC_RX_MC_CFG0_IM3_DITH_SHIFT.

u32 XRFdc_SetDSA | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_DSA_Settings * | SettingsPtr
| ) |  |

Set DSA for ADC block.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  Attenuation | is the attenuation in dB

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Range 0 - 11 dB with 0.5 dB resolution.

References XRFDC_DSA_UPDT_OFFSET, and XRFdc_ReadReg16.

u32 XRFdc_SetFabClkOutDiv | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u16 | FabClkDiv
| ) |  |

This API is to set the divider for clock fabric out.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  FabClkDiv | to be set for a tile. XRFDC_FAB_CLK_* defines the valid divider values.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  ADC and DAC Tiles

References XRFDC_FAB_CLK_DIV_MASK, and XRFDC_HSCOM_CLK_DIV_OFFSET.

u32 XRFdc_SetFabRdVldWords | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | FabricRdVldWords
| ) |  |

Fabric data rate for the requested ADC block is set by writing to the corresponding register.

The function writes the number of valid read words for the requested ADC block.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC block number inside the tile. Valid values are 0-3.
  FabricRdVldWords | is Read fabric rate to be set for ADC block.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for ADC blocks

References XRFDC_ADC_FAB_RATE_RD_MASK, XRFDC_ADC_FABRIC_RATE_OFFSET, and XRFDC_FAB_RATE_RD_SHIFT.

u32 XRFdc_SetFabWrVldWords | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | FabricWrVldWords
| ) |  |

Fabric data rate for the requested DAC block is set by writing to the corresponding register.

The function writes the number of valid write words for the requested DAC block.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  FabricWrVldWords | is write fabric rate to be set for DAC block.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only for DAC blocks

References XRFDC_ADC_FABRIC_RATE_OFFSET, and XRFDC_DAC_FAB_RATE_WR_MASK.

u32 XRFdc_SetIMRPassMode | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | Mode
| ) |  |

This API is to set the DAC Image Reject Filter Pass mode.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  Mode | valid values are 0 (for low pass) 1 (for high pass).

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if tile not enabled / bad parameter passed

Note
  Only for DAC blocks

References XRFDC_DAC_DATAPATH_OFFSET, and XRFDC_DATAPATH_IMR_MASK.

u32 XRFdc_SetInterpolationFactor | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | InterpolationFactor
| ) |  |

This API is to set the interpolation factor and also update the FIFO read words w.r.t to interpolation factor.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  InterpolationFactor | to be set for DAC block. XRFDC_INTERP_DECIM_* defines the valid values.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only DAC blocks

References XRFDC_ADC_FABRIC_RATE_OFFSET, XRFDC_DAC_FAB_RATE_RD_MASK, XRFDC_DAC_INTERP_CTRL_OFFSET, XRFDC_DAC_ITERP_DATA_OFFSET, XRFDC_FAB_RATE_RD_SHIFT, XRFDC_INTERP_MODE_MASK, XRFDC_INTERP_MODE_MASK_EXT, XRFDC_INTERP_MODE_Q_SHIFT, XRFDC_INTERP_MODE_Q_SHIFT_EXT, and XRFdc_ReadReg16.

u32 XRFdc_SetInvSincFIR | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u16 | Mode
| ) |  |

This API is used to set the mode for the Inverse-Sinc filter.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is DAC block number inside the tile. Valid values are 0-3.
  Mode | valid values are 0(disable), 1(1st Nyquist zone) and 2(2nd Nyquist zone).

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if block not enabled/invalid mode.

Note
  Only DAC blocks

References XRFDC_DAC_INVSINC_OFFSET, XRFDC_EN_INVSINC_MASK, and XRFDC_MODE_INVSINC_MASK.

u32 XRFdc_SetMixerSettings | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_Mixer_Settings * | MixerSettingsPtr
| ) |  |

The API is used to update various mixer settings, fine, coarse, NCO etc.

Mixer/NCO settings passed are used to update the corresponding block level registers. Driver structure is updated with the new values.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 DAC
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  MixerSettingsPtr | Pointer to the XRFdc_Mixer_Settings structure in which the Mixer/NCO settings are passed.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  FineMixerScale in Mixer_Settings structure can have 3 values. XRFDC_MIXER_SCALE_* represents the valid values. XRFDC_MIXER_SCALE_AUTO - If mixer mode is R2C, Mixer Scale is set to 1 and for other modes mixer scale is set to 0.7 XRFDC_MIXER_SCALE_1P0 - To set fine mixer scale to 1. XRFDC_MIXER_SCALE_0P7 - To set fine mixer scale to 0.7.

References XRFDC_ADC_DECI_CONFIG_OFFSET, XRFDC_ADC_NCO_FQWD_LOW_OFFSET, XRFDC_ADC_NCO_FQWD_MID_OFFSET, XRFDC_ADC_NCO_FQWD_UPP_OFFSET, XRFDC_ADC_NCO_PHASE_MOD_OFFSET, XRFDC_ADC_UPDATE_DYN_OFFSET, XRFDC_DAC_INTERP_DATA_MASK, XRFDC_DAC_ITERP_DATA_OFFSET, XRFDC_DAC_UPDATE_DYN_OFFSET, XRFDC_DEC_CFG_4GSPS_MASK, XRFDC_DEC_CFG_CHA_MASK, XRFDC_DEC_CFG_IQ_MASK, XRFDC_DEC_CFG_MASK, XRFDC_FINE_MIX_SCALE_MASK, XRFdc_GetCalibrationMode(), XRFdc_GetNyquistZone(), XRFDC_MXR_MODE_OFFSET, XRFDC_NCO_FQWD_MID_MASK, XRFDC_NCO_FQWD_MID_SHIFT, XRFDC_NCO_FQWD_UPP_MASK, XRFDC_NCO_FQWD_UPP_SHIFT, XRFDC_NCO_PHASE_LOW_OFFSET, XRFDC_NCO_PHASE_MOD_EVEN, XRFDC_NCO_PHASE_MODE_ODD, XRFDC_NCO_PHASE_UPP_MASK, XRFDC_NCO_PHASE_UPP_OFFSET, XRFDC_NCO_PHASE_UPP_SHIFT, XRFDC_NCO_UPDT_MODE_MASK, XRFDC_NCO_UPDT_OFFSET, XRFdc_ReadReg16, XRFDC_UPDT_EVNT_MASK, XRFDC_UPDT_EVNT_NCO_MASK, and XRFdc_WriteReg16.

Referenced by XRFdc_SetCalibrationMode().

u32 XRFdc_SetNyquistZone | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | NyquistZone
| ) |  |

Set the Nyquist zone.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  NyquistZone | valid values are 1 (Odd),2 (Even).

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Common API for ADC/DAC blocks

References XRFDC_ADC_TI_TISK_CRL0_OFFSET, XRFDC_DAC_MC_CFG0_OFFSET, XRFdc_GetCalibrationMode(), XRFDC_MC_CFG0_MIX_MODE_MASK, XRFdc_ReadReg16, XRFDC_TI_TISK_ZONE_MASK, and XRFdc_WriteReg16.

Referenced by XRFdc_SetCalibrationMode(), and XRFdc_SetDataPathMode().

u32 XRFdc_SetQMCSettings | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_QMC_Settings * | QMCSettingsPtr
| ) |  |

This API is used to update various QMC settings, eg gain, phase, offset etc.

QMC settings passed are used to update the corresponding block level registers. Driver structure is updated with the new values.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  QMCSettingsPtr | is Pointer to the XRFdc_QMC_Settings structure in which the QMC settings are passed.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  None.

References XRFDC_ADC_UPDATE_DYN_OFFSET, XRFDC_DAC_UPDATE_DYN_OFFSET, XRFDC_QMC_CFG_EN_GAIN_MASK, XRFDC_QMC_CFG_EN_PHASE_MASK, XRFDC_QMC_CFG_OFFSET, XRFDC_QMC_CFG_PHASE_SHIFT, XRFDC_QMC_GAIN_CRCTN_MASK, XRFDC_QMC_GAIN_OFFSET, XRFDC_QMC_OFF_OFFSET, XRFDC_QMC_OFFST_CRCTN_MASK, XRFDC_QMC_PHASE_CRCTN_MASK, XRFDC_QMC_PHASE_OFFSET, XRFDC_QMC_UPDT_MODE_MASK, XRFDC_QMC_UPDT_OFFSET, XRFDC_UPDT_EVNT_MASK, and XRFDC_UPDT_EVNT_QMC_MASK.

u32 XRFdc_SetSignalDetector | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_Signal_Detector_Settings * | SettingsPtr
| ) |  |

This function is used to set the ADC Signal Detector Settings.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | indicates Tile number (0-3).
  Block_Id | indicates Block number(0-3 for LS, 0-1 for HS).
  SettingsPtr | pointer to the XRFdc_Signal_Detector_Settings structure to set the signal detector configurations

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if tile not enabled, or invalid values.

Note
  Only for ADC blocks

References XRFDC_ADC_SIG_DETECT_CTRL_OFFSET, XRFDC_ADC_SIG_DETECT_FLUSH_SHIFT, XRFDC_ADC_SIG_DETECT_HYST_SHIFT, XRFDC_ADC_SIG_DETECT_INTG_SHIFT, XRFDC_ADC_SIG_DETECT_MASK, XRFDC_ADC_SIG_DETECT_MODE_WRITE_SHIFT, XRFDC_ADC_SIG_DETECT_TCONST_SHIFT, XRFDC_ADC_SIG_DETECT_THRESH_MASK, XRFDC_ADC_SIG_DETECT_THRESHOLD0_LEVEL_OFFSET, and XRFDC_ADC_SIG_DETECT_THRESHOLD1_LEVEL_OFFSET.

void XRFdc_SetStatusHandler | ( | XRFdc * | InstancePtr,
|  | void * | CallBackRef,
|  | XRFdc_StatusHandler | FunctionPtr
| ) |  |

This function sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software.

The handler executes in an interrupt context, so the amount of processing should be minimized

Parameters

  InstancePtr | is a pointer to the XRFdc instance.
  CallBackRef | is the upper layer callback reference passed back when the callback function is invoked.
  FunctionPtr | is the pointer to the callback function.

Note
  None.
  The handler is called within interrupt context, so it should finish its work quickly.

u32 XRFdc_SetThresholdClrMode | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | ThresholdToUpdate,
|  | u32 | ClrMode
| ) |  |

This API sets the threshold clear mode.

The clear mode can be through explicit DRP access (manual) or auto clear (QMC gain update event).

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADCC block number inside the tile. Valid values are 0-3.
  ThresholdToUpdate | Select which Threshold (Threshold0 or Threshold1 or both) to update.
  ClrMode | can be DRP access (manual) or auto clear (QMC gain update event).

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only ADC blocks

References XRFDC_ADC_TRSHD0_CFG_OFFSET, XRFDC_ADC_TRSHD1_CFG_OFFSET, XRFdc_ReadReg16, XRFDC_TRSHD0_CLR_MOD_MASK, XRFDC_TRSHD1_CLR_MOD_MASK, and XRFdc_WriteReg16.

u32 XRFdc_SetThresholdSettings | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | XRFdc_Threshold_Settings * | ThresholdSettingsPtr
| ) |  |

Threshold settings are updated into the relevant registers.

Driver structure is updated with the new values. There can be two threshold settings: threshold0 and threshold1. Both of them are independent of each other. The function returns the requested threshold (which can be threshold0, threshold1, or both.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  ThresholdSettingsPtr | Pointer through which the register settings for thresholds are passed to the API.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only ADC blocks

References XRFDC_ADC_TRSHD0_AVG_LO_OFFSET, XRFDC_ADC_TRSHD0_AVG_UP_OFFSET, XRFDC_ADC_TRSHD0_CFG_OFFSET, XRFDC_ADC_TRSHD0_OVER_OFFSET, XRFDC_ADC_TRSHD0_UNDER_OFFSET, XRFDC_ADC_TRSHD1_AVG_LO_OFFSET, XRFDC_ADC_TRSHD1_AVG_UP_OFFSET, XRFDC_ADC_TRSHD1_CFG_OFFSET, XRFDC_ADC_TRSHD1_OVER_OFFSET, XRFDC_ADC_TRSHD1_UNDER_OFFSET, XRFDC_TRSHD0_AVG_UPP_SHIFT, XRFDC_TRSHD0_EN_MOD_MASK, XRFDC_TRSHD0_OVER_MASK, XRFDC_TRSHD0_UNDER_MASK, XRFDC_TRSHD1_AVG_UPP_SHIFT, XRFDC_TRSHD1_EN_MOD_MASK, XRFDC_TRSHD1_OVER_MASK, XRFDC_TRSHD1_UNDER_MASK, and XRFdc_WriteReg16.

u32 XRFdc_SetupFIFO | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | int | Tile_Id,
|  | u8 | Enable
| ) |  |

Enable and Disable the ADC/DAC FIFO.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  Enable | valid values are 1 (FIFO enable) and 0 (FIFO Disable)

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Common API for ADC/DAC blocks

References XRFDC_FIFO_EN_MASK, and XRFDC_FIFO_ENABLE.

u32 XRFdc_Shutdown | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | int | Tile_Id
| ) |  |

The API stops the tile as requested.

It can also stop all the tiles if asked for. It does not clear any of the existing register settings. It just stops the requested tile(s).

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3, and -1.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  None.

Referenced by XRFdc_DynamicPLLConfig(), and XRFdc_SetClkDistribution().

u32 XRFdc_StartUp | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | int | Tile_Id
| ) |  |

The API Restarts the requested tile.

It can restart a single tile and alternatively can restart all the tiles. Existing register settings are not lost or altered in the process. It just starts the requested tile(s).

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3, and -1.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  None.

Referenced by XRFdc_DynamicPLLConfig().

u32 XRFdc_ThresholdStickyClear | ( | XRFdc * | InstancePtr,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | ThresholdToUpdate
| ) |  |

This API is to clear the Sticky bit in threshold config registers.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  ThresholdToUpdate | Select which Threshold (Threshold0 or Threshold1 or both) to update.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Only ADC blocks

References XRFDC_ADC_TRSHD0_CFG_OFFSET, XRFDC_ADC_TRSHD1_CFG_OFFSET, XRFDC_TRSHD0_STIKY_CLR_MASK, and XRFDC_TRSHD1_STIKY_CLR_MASK.

u32 XRFdc_UpdateEvent | ( | XRFdc * | InstancePtr,
|  | u32 | Type,
|  | u32 | Tile_Id,
|  | u32 | Block_Id,
|  | u32 | Event
| ) |  |

This function will trigger the update event for an event.

Parameters

  InstancePtr | is a pointer to the XRfdc instance.
  Type | is ADC or DAC. 0 for ADC and 1 for DAC
  Tile_Id | Valid values are 0-3.
  Block_Id | is ADC/DAC block number inside the tile. Valid values are 0-3.
  Event | is for which dynamic update event will trigger. XRFDC_EVENT_* defines the different events.

Returns
  - XRFDC_SUCCESS if successful.
  - XRFDC_FAILURE if error occurs.

Note
  Common API for ADC/DAC blocks

References XRFDC_ADC_CRSE_DLY_UPDT_OFFSET, XRFDC_ADC_UPDATE_DYN_OFFSET, XRFDC_DAC_CRSE_DLY_UPDT_OFFSET, XRFDC_DAC_UPDATE_DYN_OFFSET, XRFDC_HSCOM_UPDT_DYN_OFFSET, XRFDC_NCO_UPDT_MODE_MASK, XRFDC_NCO_UPDT_OFFSET, XRFDC_QMC_UPDT_MODE_MASK, XRFDC_QMC_UPDT_OFFSET, and XRFdc_WriteReg16.