vphy: xvphy_i.c File Reference

| vphy Xilinx SDK Drivers API Documentation

- Overview
- Data Structures
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Functions
xvphy_i.c File Reference

## Overview

Contains generic APIs that are locally called or used within the VPHY driver.

Note
  None.

    MODIFICATION HISTORY:

    Ver   Who  Date     Changes

    1.0   gm,  11/09/16 Initial release.
    1.4   gm   29/11/16 Fixed c++ compiler warnings
                        Added xcvr adaptor functions for C++ compilations
    1.6   gm   06/08/17 Added XVphy_MmcmLocked, XVphy_ErrorHandler and
                                 XVphy_PllLayoutErrorHandler APIs
    1.7   gm   13/09/17 Added GTYE4 support
    1.8   gm   23/07/18 Moved APIs XVphy_SetTxVoltageSwing and
                          XVphy_SetTxPreEmphasis to xvphy.c/h
               05/09/18 Added XVphy_GetRefClkSourcesCount API
    1.9   gm   11/04/18 Added XVphy_IsHDMI API

## Functions
u32 | XVphy_WriteCfgRefClkSelReg (XVphy *InstancePtr, u8 QuadId)
| This function writes the current software configuration for the reference clock selections to hardware for the specified quad on all channels. More...
void | XVphy_CfgPllRefClkSel (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_PllRefClkSelType RefClkSel)
| Configure the PLL reference clock selection for the specified channel(s). More...
void | XVphy_CfgSysClkDataSel (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_SysClkDataSelType SysClkDataSel)
| Configure the SYSCLKDATA reference clock selection for the direction. More...
void | XVphy_CfgSysClkOutSel (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_SysClkOutSelType SysClkOutSel)
| Configure the SYSCLKOUT reference clock selection for the direction. More...
XVphy_ChannelId | XVphy_GetRcfgChId (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_PllType PllType)
| Obtain the reconfiguration channel ID for given PLL type. More...
u32 | XVphy_GetQuadRefClkFreq (XVphy *InstancePtr, u8 QuadId, XVphy_PllRefClkSelType RefClkType)
| Obtain the current reference clock frequency for the quad based on the reference clock type. More...
XVphy_SysClkDataSelType | XVphy_GetSysClkDataSel (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_ChannelId ChId)
| Obtain the current [RT]XSYSCLKSEL[0] configuration. More...
XVphy_SysClkOutSelType | XVphy_GetSysClkOutSel (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, XVphy_ChannelId ChId)
| Obtain the current [RT]XSYSCLKSEL[1] configuration. More...
u32 | XVphy_IsPllLocked (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
| This function will check the status of a PLL lock on the specified channel. More...
u32 | XVphy_GtUserRdyEnable (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u8 Hold)
| This function will reset and enable the Video PHY's user core logic. More...
void | XVphy_MmcmReset (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, u8 Hold)
| This function will reset the mixed-mode clock manager (MMCM) core. More...
void | XVphy_MmcmLockedMaskEnable (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir, u8 Enable)
| This function will reset the mixed-mode clock manager (MMCM) core. More...
u8 | XVphy_MmcmLocked (XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir)
| This function will get the lock status of the mixed-mode clock manager (MMCM) core. More...
void | XVphy_SetBufgGtDiv (XVphy *InstancePtr, XVphy_DirectionType Dir, u8 Div)
| This function obtains the divider value of the BUFG_GT peripheral. More...
u32 | XVphy_PowerDownGtPll (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, u8 Hold)
| This function will power down the specified GT PLL. More...
u32 | XVphy_ClkCalcParams (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u32 PllClkInFreqHz)
| This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency. More...
u32 | XVphy_OutDivReconfig (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir)
| This function will set the current output divider configuration over DRP. More...
u32 | XVphy_DirReconfig (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir)
| This function will set the current RX/TX configuration over DRP. More...
u32 | XVphy_ClkReconfig (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
| This function will set the current clocking settings for each channel to hardware based on the configuration stored in the driver's instance. More...
void | XVphy_Ch2Ids (XVphy *InstancePtr, XVphy_ChannelId ChId, u8 *Id0, u8 *Id1)
| This function will set the channel IDs to correspond with the supplied channel ID based on the protocol. More...
XVphy_SysClkDataSelType | Pll2SysClkData (XVphy_PllType PllSelect)
| This function will translate from XVphy_PllType to XVphy_SysClkDataSelType. More...
XVphy_SysClkOutSelType | Pll2SysClkOut (XVphy_PllType PllSelect)
| This function will translate from XVphy_PllType to XVphy_SysClkOutSelType. More...
u32 | XVphy_PllCalculator (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir, u32 PllClkInFreqHz)
| This function will try to find the necessary PLL divisor values to produce the configured line rate given the specified PLL input frequency. More...
u64 | XVphy_GetPllVcoFreqHz (XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId, XVphy_DirectionType Dir)
| This function calculates the PLL VCO operating frequency. More...
u8 | XVphy_GetRefClkSourcesCount (XVphy *InstancePtr)
| This function returns the number of active reference clock sources based in the CFG. More...
u8 | XVphy_IsHDMI (XVphy *InstancePtr, XVphy_DirectionType Dir)
| This function checks if Instance is HDMI 2.0 or HDMI 2.1. More...
void | XVphy_ErrorHandler (XVphy *InstancePtr)
| This function is the error condition handler. More...