wdtps: xwdtps_hw.h File Reference

| wdtps Xilinx SDK Drivers API Documentation

- Overview
- Data Structures
- APIs
- File List
- Examples

Macros
xwdtps_hw.h File Reference

## Macros
#define | XWdtPs_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (u32)(RegOffset))
| Read the given register. More...
#define | XWdtPs_WriteReg(BaseAddress, RegOffset, Data) Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
| Write the given register. More...
Register Map
Offsets of registers from the start of the device
#define | XWDTPS_ZMR_OFFSET 0x00000000U
| Zero Mode Register. More...
#define | XWDTPS_CCR_OFFSET 0x00000004U
| Counter Control Register. More...
#define | XWDTPS_RESTART_OFFSET 0x00000008U
| Restart Register. More...
#define | XWDTPS_SR_OFFSET 0x0000000CU
| Status Register. More...
Zero Mode Register
This register controls how the time out is indicated and also contains the access code (0xABC) to allow writes to the register
#define | XWDTPS_ZMR_WDEN_MASK 0x00000001U
| enable the WDT More...
#define | XWDTPS_ZMR_RSTEN_MASK 0x00000002U
| enable the reset output More...
#define | XWDTPS_ZMR_IRQEN_MASK 0x00000004U
| enable the IRQ output More...
#define | XWDTPS_ZMR_RSTLN_MASK 0x00000070U
| set length of reset pulse More...
#define | XWDTPS_ZMR_RSTLN_SHIFT 4U
| shift for reset pulse More...
#define | XWDTPS_ZMR_IRQLN_MASK 0x00000180U
| set length of interrupt pulse More...
#define | XWDTPS_ZMR_IRQLN_SHIFT 7U
| shift for interrupt pulse More...
#define | XWDTPS_ZMR_ZKEY_MASK 0x00FFF000U
| mask for writing access key More...
#define | XWDTPS_ZMR_ZKEY_VAL 0x00ABC000U
| access key, 0xABC << 12 More...
Counter Control register
This register controls how fast the timer runs and the reset value and also contains the access code (0x248) to allow writes to the register
#define | XWDTPS_CCR_CLKSEL_MASK 0x00000003U
| counter clock prescale More...
#define | XWDTPS_CCR_CRV_MASK 0x00003FFCU
| counter reset value More...
#define | XWDTPS_CCR_CRV_SHIFT 2U
| shift for writing value More...
#define | XWDTPS_CCR_CKEY_MASK 0x03FFC000U
| mask for writing access key More...
#define | XWDTPS_CCR_CKEY_VAL 0x00920000U
| access key, 0x248 << 14 More...
#define | XWDTPS_CCR_PSCALE_0008 0x00000000U
| divide clock by 8 More...
#define | XWDTPS_CCR_PSCALE_0064 0x00000001U
| divide clock by 64 More...
#define | XWDTPS_CCR_PSCALE_0512 0x00000002U
| divide clock by 512 More...
#define | XWDTPS_CCR_PSCALE_4096 0x00000003U
| divide clock by 4096 More...
Restart register
This register resets the timer preventing a timeout. Value is specific 0x1999
#define | XWDTPS_RESTART_KEY_VAL 0x00001999U
| valid key More...
Status register
This register indicates timer reached zero count.
#define | XWDTPS_SR_WDZ_MASK 0x00000001U
| time out occurred More...