i2srx: I2srx_v1_0

| i2srx Xilinx SDK Drivers API Documentation

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Data Structures | Macros | Typedefs | Enumerations | Functions
I2srx_v1_0

## Data Structures
struct | XI2srx_Config
| This typedef contains configuration information for the XI2s Receiver. More...
struct | XI2s_Rx
| The XI2s Receiver driver instance data. More...
struct | XI2s_Rx_LogItem
| This structure is used to store log events. More...
struct | XI2s_Rx_Log
| The XI2s Receiver Log buffer. More...

## Macros
#define | XI2s_Rx_GetMaxChannels(InstancePtr)
| This macro reads the maximum number of XI2s channels available. More...
#define | XI2s_Rx_IsXI2sMaster(InstancePtr)
| This macro returns the XI2s operating mode. More...

## Typedefs
typedef void(* | XI2s_Rx_Callback )(void *CallbackRef)
| Callback function data type for handling interrupt requests from the XI2s Receiver peripheral. More...

## Enumerations
enum | XI2s_Rx_ChMuxInput { XI2S_RX_CHMUX_DISABLED = 0, XI2S_RX_CHMUX_XI2S_01, XI2S_RX_CHMUX_XI2S_23, XI2S_RX_CHMUX_XI2S_45, XI2S_RX_CHMUX_XI2S_67, XI2S_RX_CHMUX_WAVEGEN }
| This typedef specifies the input sources of the the XI2s Receiver. More...
enum | XI2s_Rx_Justification { XI2S_RX_JUSTIFY_LEFT = 0, XI2S_RX_JUSTIFY_RIGHT }
| This typedef specifies the justification of the the XI2s Receiver. More...

## Functions
int | XI2s_Rx_CfgInitialize (XI2s_Rx *InstancePtr, XI2srx_Config *CfgPtr, UINTPTR EffectiveAddr)
| This function initializes the XI2s Receiver. More...
void | XI2s_Rx_Enable (XI2s_Rx *InstancePtr, u8 Enable)
| This function enables/disables the XI2s Receiver. More...
void | XI2s_Rx_LatchAesChannelStatus (XI2s_Rx *InstancePtr)
| This function requests the XI2s Receiver to latch the AES Channel Status bits from the registers. More...
void | XI2s_Rx_IntrEnable (XI2s_Rx *InstancePtr, u32 Mask)
| This function enables the specified interrupt of the XI2s Receiver. More...
void | XI2s_Rx_IntrDisable (XI2s_Rx *InstancePtr, u32 Mask)
| This function disables the specified interrupt of the XI2s Receiver. More...
int | XI2s_Rx_SetChMux (XI2s_Rx *InstancePtr, XI2s_Rx_ChannelId ChID, XI2s_Rx_ChMuxInput InputSource)
| This function sets the input source for the specified AXI-Stream channel pair. More...
u32 | XI2s_Rx_SetSclkOutDiv (XI2s_Rx *InstancePtr, u32 MClk, u32 Fs)
| This function calculates the SCLK Output divider value of the I2s timing generator. More...
void | XI2s_Rx_SetAesChStatus (XI2s_Rx *InstancePtr, u8 *AesChStatusBuf)
| This function sets the AES Channel Status bits to insert. More...
void | XI2s_Rx_ClrAesChStatRegs (XI2s_Rx *InstancePtr)
| This function clears the captured AES Channel Status bits. More...
void | XI2s_Rx_JustifyEnable (XI2s_Rx *InstancePtr, u8 Enable)
| This function enables/disables the justification. More...
void | XI2s_Rx_Justify (XI2s_Rx *InstancePtr, XI2s_Rx_Justification Justify)
| This function is to enable right/left justification. More...
int | XI2s_Rx_SelfTest (XI2s_Rx *InstancePtr)
| Runs a self-test on the driver/device. More...
XI2srx_Config * | XI2s_Rx_LookupConfig (u16 DeviceId)
| This function returns a reference to an XI2srx_Config structure based on the core id, DeviceId. More...
int | XI2s_Rx_Initialize (XI2s_Rx *InstancePtr, u16 DeviceId)
| Initializes a specific XI2s_Rx instance such that the driver is ready to use. More...
void | XI2s_Rx_IntrHandler (void *InstancePtr)
| This function is the interrupt handler for the XI2s Receiver driver. More...
int | XI2s_Rx_SetHandler (XI2s_Rx *InstancePtr, XI2s_Rx_HandlerType HandlerType, XI2s_Rx_Callback FuncPtr, void *CallbackRef)
| This function installs an asynchronous callback function for the given HandlerType: More...
void | XI2s_Rx_LogDisplay (XI2s_Rx *InstancePtr)
| This function prints the contents of the logging buffer. More...
void | XI2s_Rx_LogReset (XI2s_Rx *InstancePtr)
| This function clears the contents of the logging buffer. More...
void | XI2s_Rx_LogWrite (XI2s_Rx *InstancePtr, XI2s_Rx_LogEvt Event, u8 Data)
| This function writes XI2s Receiver logs into the buffer. More...
XI2s_Rx_LogItem * | XI2s_Rx_LogRead (XI2s_Rx *InstancePtr)
| This function returns the next item in the logging buffer. More...
void | XI2s_Rx_SetAesChStat (u32 I2srx_SrcBuf[], u8 I2srx_DstBuf[])
| This function reads the source buffer and writes to a destination buffer. More...

## Handler Types
enum | XI2s_Rx_HandlerType { XI2S_RX_HANDLER_AES_BLKCMPLT = 0, XI2S_RX_HANDLER_AUD_OVRFLW, XI2S_RX_NUM_HANDLERS }
| These constants specify different types of handlers and is used to differentiate interrupt requests from the XI2s Receiver peripheral. More...
enum | XI2s_Rx_ChannelId { XI2S_RX_CHID0 = 0, XI2S_RX_CHID1, XI2S_RX_CHID2, XI2S_RX_CHID3, XI2S_RX_NUM_CHANNELS }
| These constants specify different channel ID's. More...
#define | XI2S_RX_LOG_ITEM_BUFFER_SIZE (256)
| @ name Log Item Buffer Size More...

## Handler Types
enum | XI2s_Rx_LogEvt { XI2S_RX_AES_BLKCMPLT_EVT, XI2S_RX_AUD_OVERFLOW_EVT, XI2S_RX_LOG_EVT_INVALID }
| These constants specify different types of handlers and is used to differentiate interrupt requests from the XI2s Receiver peripheral. More...

## Register Map
Register offsets for the XI2srx device.
#define | XI2S_RX_CORE_VER_OFFSET 0x00
| Core Version Register. More...
#define | XI2S_RX_CORE_CFG_OFFSET 0x04
| Core Configuration Register. More...
#define | XI2S_RX_CORE_CTRL_OFFSET 0x08
| Core Control Register. More...
#define | XI2S_RX_IRQCTRL_OFFSET 0x10
| Interrupt Control Register. More...
#define | XI2S_RX_IRQSTS_OFFSET 0x14
| Interrupt Status Register. More...
#define | XI2S_RX_TMR_CTRL_OFFSET 0x20
| XI2S Timing Control Register. More...
#define | XI2S_RX_CH01_OFFSET 0x30
| Audio Channel 0/1 Control Register. More...
#define | XI2S_RX_CH23_OFFSET 0x34
| Audio Channel 2/3 Control Register. More...
#define | XI2S_RX_CH45_OFFSET 0x38
| Audio Channel 4/5 Control Register. More...
#define | XI2S_RX_CH67_OFFSET 0x3C
| Audio Channel 6/7 Control Register. More...
#define | XI2S_RX_AES_CHSTS0_OFFSET 0x50
| AES Channel Status 0 Register. More...
#define | XI2S_RX_AES_CHSTS1_OFFSET 0x54
| AES Channel Status 1 Register. More...
#define | XI2S_RX_AES_CHSTS2_OFFSET 0x58
| AES Channel Status 2 Register. More...
#define | XI2S_RX_AES_CHSTS3_OFFSET 0x5C
| AES Channel Status 3 Register. More...
#define | XI2S_RX_AES_CHSTS4_OFFSET 0x60
| AES Channel Status 4 Register. More...
#define | XI2S_RX_AES_CHSTS5_OFFSET 0x64
| AES Channel Status 5 Register. More...

## Core Configuration Register masks and shifts
#define | XI2S_RX_REG_CFG_MSTR_SHIFT (0)
| Is XI2S Master bit shift. More...
#define | XI2S_RX_REG_CFG_MSTR_MASK (1 << XI2S_RX_REG_CFG_MSTR_SHIFT)
| Is XI2S Master mask. More...
#define | XI2S_RX_REG_CFG_NUM_CH_SHIFT (8)
| Maximum number of channels bit shift. More...
#define | XI2S_RX_REG_CFG_NUM_CH_MASK (0xF << XI2S_RX_REG_CFG_NUM_CH_SHIFT)
| Maximum number of channels mask. More...
#define | XI2S_RX_REG_CFG_DWDTH_SHIFT (16)
| XI2S Data Width bit shift. More...
#define | XI2S_RX_REG_CFG_DWDTH_MASK (1 << XI2S_RX_REG_CFG_DWDTH_SHIFT)
| XI2S Data Width mask. More...

## Core Control Register masks and shifts
#define | XI2S_RX_REG_CTRL_EN_SHIFT (0)
| Module Enable bit shift. More...
#define | XI2S_RX_REG_CTRL_EN_MASK (1 << XI2S_RX_REG_CTRL_EN_SHIFT)
| Module Enable mask. More...
#define | XI2S_RX_REG_CTRL_JFE_SHIFT (1)
| Justification Enable or Disable shift. More...
#define | XI2S_RX_REG_CTRL_JFE_MASK (1 << XI2S_RX_REG_CTRL_JFE_SHIFT)
| Justification Enable or Disable mask. More...
#define | XI2S_RX_REG_CTRL_LORJF_SHIFT (2)
| Left or Right Justification shift. More...
#define | XI2S_RX_REG_CTRL_LORJF_MASK (1 << XI2S_RX_REG_CTRL_LORJF_SHIFT)
| Left or Right Justification mask. More...
#define | XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT (16)
| Latch AES Channel Status bit shift. More...
#define | XI2S_RX_REG_CTRL_LATCH_CHSTS_MASK (1 << XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT)
| Latch AES Channel Status mask. More...

## Interrupt masks and shifts
#define | XI2S_RX_INTR_AES_BLKCMPLT_SHIFT (0)
| AES Block Complete Interrupt bit shift. More...
#define | XI2S_RX_INTR_AES_BLKCMPLT_MASK (1 << XI2S_RX_INTR_AES_BLKCMPLT_SHIFT)
| AES Block Complete Interrupt mask. More...
#define | XI2S_RX_INTR_AUDOVRFLW_SHIFT (1)
| Audio Overflow Detected Interrupt bit shift. More...
#define | XI2S_RX_INTR_AUDOVRFLW_MASK (1 << XI2S_RX_INTR_AUDOVRFLW_SHIFT)
| Audio Overflow Detected Interrupt mask. More...
#define | XI2S_RX_GINTR_EN_SHIFT (31)
| Global Interrupt Enable bit shift. More...
#define | XI2S_RX_GINTR_EN_MASK (1 << XI2S_RX_GINTR_EN_SHIFT)
| Global Interrupt Enable mask. More...

## XI2S Timing Control Register masks and shifts
#define | XI2S_RX_REG_TMR_SCLKDIV_SHIFT (0)
| SClk Divider bit shift. More...
#define | XI2S_RX_REG_TMR_SCLKDIV_MASK (0xF << XI2S_RX_REG_TMR_SCLKDIV_SHIFT)
| SClk Divider mask. More...

## Audio Channel Control Register masks and shifts
#define | XI2S_RX_REG_CHCTRL_CHMUX_SHIFT (0)
| Channel MUX bit shift. More...
#define | XI2S_RX_REG_CHCTRL_CHMUX_MASK (0x7 << XI2S_RX_REG_CHCTRL_CHMUX_SHIFT)
| Channel MUX mask. More...

## Register access macro definition
#define | XI2s_Rx_In32 Xil_In32
| Input Operations. More...
#define | XI2s_Rx_Out32 Xil_Out32
| Output Operations. More...
#define | XI2s_Rx_ReadReg(BaseAddress, RegOffset) XI2s_Rx_In32((BaseAddress) + ((u32)RegOffset))
| This macro reads a value from a XI2s Receiver register. More...
#define | XI2s_Rx_WriteReg(BaseAddress, RegOffset, Data) XI2s_Rx_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
| This macro writes a value to a XI2s Receiver register. More...

## Macro Definition Documentation

#define XI2S_RX_AES_CHSTS0_OFFSET 0x50

AES Channel Status 0 Register.

Referenced by XI2s_Rx_ClrAesChStatRegs(), and XI2s_Rx_SetAesChStatus().

#define XI2S_RX_AES_CHSTS1_OFFSET 0x54

AES Channel Status 1 Register.

Referenced by XI2s_Rx_ClrAesChStatRegs().

#define XI2S_RX_AES_CHSTS2_OFFSET 0x58

AES Channel Status 2 Register.

Referenced by XI2s_Rx_ClrAesChStatRegs().

#define XI2S_RX_AES_CHSTS3_OFFSET 0x5C

AES Channel Status 3 Register.

Referenced by XI2s_Rx_ClrAesChStatRegs().

#define XI2S_RX_AES_CHSTS4_OFFSET 0x60

AES Channel Status 4 Register.

Referenced by XI2s_Rx_ClrAesChStatRegs().

#define XI2S_RX_AES_CHSTS5_OFFSET 0x64

AES Channel Status 5 Register.

Referenced by XI2s_Rx_ClrAesChStatRegs().

#define XI2S_RX_CH01_OFFSET 0x30

Audio Channel 0/1 Control Register.

Referenced by XI2s_Rx_SetChMux().

#define XI2S_RX_CH23_OFFSET 0x34

Audio Channel 2/3 Control Register.

#define XI2S_RX_CH45_OFFSET 0x38

Audio Channel 4/5 Control Register.

#define XI2S_RX_CH67_OFFSET 0x3C

Audio Channel 6/7 Control Register.

#define XI2S_RX_CORE_CFG_OFFSET 0x04

Core Configuration Register.

#define XI2S_RX_CORE_CTRL_OFFSET 0x08

Core Control Register.

Referenced by XI2s_Rx_Enable(), XI2s_Rx_Justify(), XI2s_Rx_JustifyEnable(), and XI2s_Rx_LatchAesChannelStatus().

#define XI2S_RX_CORE_VER_OFFSET 0x00

Core Version Register.

#define XI2s_Rx_GetMaxChannels | ( |  | InstancePtr | ) |

Value:
((XI2s_Rx_ReadReg((InstancePtr)->Config.BaseAddress, (XI2S_RX_CORE_CFG_OFFSET))\
& XI2S_RX_REG_CFG_NUM_CH_MASK) >> XI2S_RX_REG_CFG_NUM_CH_SHIFT)
XI2S_RX_REG_CFG_NUM_CH_MASK
#define XI2S_RX_REG_CFG_NUM_CH_MASK
Maximum number of channels mask.
Definition: xi2srx_hw.h:92
XI2S_RX_CORE_CFG_OFFSET
#define XI2S_RX_CORE_CFG_OFFSET
Core Configuration Register.
Definition: xi2srx_hw.h:62
XI2s_Rx_ReadReg
#define XI2s_Rx_ReadReg(BaseAddress, RegOffset)
This macro reads a value from a XI2s Receiver register.
Definition: xi2srx_hw.h:189
XI2S_RX_REG_CFG_NUM_CH_SHIFT
#define XI2S_RX_REG_CFG_NUM_CH_SHIFT
Maximum number of channels bit shift.
Definition: xi2srx_hw.h:90

This macro reads the maximum number of XI2s channels available.

Parameters

  InstancePtr | is a pointer to the XI2s_Rx core instance.

Returns
  Maximum number of XI2s Channels.

Note
  C-style signature: u32 XI2s_Rx_GetMaxChannels(XI2s_Rx *InstancePtr)

Referenced by XI2s_Rx_SelfTest().

#define XI2S_RX_GINTR_EN_MASK (1 << XI2S_RX_GINTR_EN_SHIFT)

Global Interrupt Enable mask.

Referenced by I2sRxIntrExample().

#define XI2S_RX_GINTR_EN_SHIFT (31)

Global Interrupt Enable bit shift.

#define XI2s_Rx_In32 Xil_In32

Input Operations.

#define XI2S_RX_INTR_AES_BLKCMPLT_MASK (1 << XI2S_RX_INTR_AES_BLKCMPLT_SHIFT)

AES Block Complete Interrupt mask.

Referenced by I2sRxIntrExample(), and XI2s_Rx_IntrHandler().

#define XI2S_RX_INTR_AES_BLKCMPLT_SHIFT (0)

AES Block Complete Interrupt bit shift.

#define XI2S_RX_INTR_AUDOVRFLW_MASK (1 << XI2S_RX_INTR_AUDOVRFLW_SHIFT)

Audio Overflow Detected Interrupt mask.

Referenced by I2sRxIntrExample(), and XI2s_Rx_IntrHandler().

#define XI2S_RX_INTR_AUDOVRFLW_SHIFT (1)

Audio Overflow Detected Interrupt bit shift.

#define XI2S_RX_IRQCTRL_OFFSET 0x10

Interrupt Control Register.

Referenced by XI2s_Rx_IntrDisable(), XI2s_Rx_IntrEnable(), and XI2s_Rx_IntrHandler().

#define XI2S_RX_IRQSTS_OFFSET 0x14

Interrupt Status Register.

Referenced by XI2s_Rx_IntrHandler().

#define XI2s_Rx_IsXI2sMaster | ( |  | InstancePtr | ) |

Value:
((XI2s_Rx_ReadReg((InstancePtr)->Config.BaseAddress, (XI2S_RX_CORE_CFG_OFFSET))\
& XI2S_RX_REG_CFG_MSTR_MASK) ? TRUE : FALSE)
XI2S_RX_CORE_CFG_OFFSET
#define XI2S_RX_CORE_CFG_OFFSET
Core Configuration Register.
Definition: xi2srx_hw.h:62
XI2s_Rx_ReadReg
#define XI2s_Rx_ReadReg(BaseAddress, RegOffset)
This macro reads a value from a XI2s Receiver register.
Definition: xi2srx_hw.h:189
XI2S_RX_REG_CFG_MSTR_MASK
#define XI2S_RX_REG_CFG_MSTR_MASK
Is XI2S Master mask.
Definition: xi2srx_hw.h:88

This macro returns the XI2s operating mode.

Parameters

  InstancePtr | is a pointer to the XI2s_Rx core instance.

Returns
  - TRUE : is XI2s Master
  - FALSE : is XI2s Slave

Note
  C-style signature: u8 XI2s_Rx_IsXI2sMaster(XI2s_Rx *InstancePtr)

Referenced by XI2s_Rx_SelfTest().

#define XI2S_RX_LOG_ITEM_BUFFER_SIZE (256)

@ name Log Item Buffer Size

#define XI2s_Rx_Out32 Xil_Out32

Output Operations.

#define XI2s_Rx_ReadReg | ( |  | BaseAddress,
|  |  | RegOffset
| ) |  | XI2s_Rx_In32((BaseAddress) + ((u32)RegOffset))

This macro reads a value from a XI2s Receiver register.

A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.

Parameters

  BaseAddress | is the base address of the XI2s Receiver core instance.
  RegOffset | is the register offset of the register (defined at the top of this file).

Returns
  The 32-bit value of the register.

Note
  C-style signature: u32 XI2s_Rx_ReadReg(u32 BaseAddress, u32 RegOffset)

Referenced by XI2s_Rx_Enable(), XI2s_Rx_IntrDisable(), XI2s_Rx_IntrEnable(), XI2s_Rx_IntrHandler(), XI2s_Rx_Justify(), XI2s_Rx_JustifyEnable(), and XI2s_Rx_LatchAesChannelStatus().

#define XI2S_RX_REG_CFG_DWDTH_MASK (1 << XI2S_RX_REG_CFG_DWDTH_SHIFT)

XI2S Data Width mask.

#define XI2S_RX_REG_CFG_DWDTH_SHIFT (16)

XI2S Data Width bit shift.

#define XI2S_RX_REG_CFG_MSTR_MASK (1 << XI2S_RX_REG_CFG_MSTR_SHIFT)

Is XI2S Master mask.

#define XI2S_RX_REG_CFG_MSTR_SHIFT (0)

Is XI2S Master bit shift.

#define XI2S_RX_REG_CFG_NUM_CH_MASK (0xF << XI2S_RX_REG_CFG_NUM_CH_SHIFT)

Maximum number of channels mask.

#define XI2S_RX_REG_CFG_NUM_CH_SHIFT (8)

Maximum number of channels bit shift.

#define XI2S_RX_REG_CHCTRL_CHMUX_MASK (0x7 << XI2S_RX_REG_CHCTRL_CHMUX_SHIFT)

Channel MUX mask.

#define XI2S_RX_REG_CHCTRL_CHMUX_SHIFT (0)

Channel MUX bit shift.

#define XI2S_RX_REG_CTRL_EN_MASK (1 << XI2S_RX_REG_CTRL_EN_SHIFT)

Module Enable mask.

Referenced by XI2s_Rx_Enable().

#define XI2S_RX_REG_CTRL_EN_SHIFT (0)

Module Enable bit shift.

#define XI2S_RX_REG_CTRL_JFE_MASK (1 << XI2S_RX_REG_CTRL_JFE_SHIFT)

Justification Enable or Disable mask.

Referenced by XI2s_Rx_JustifyEnable().

#define XI2S_RX_REG_CTRL_JFE_SHIFT (1)

Justification Enable or Disable shift.

#define XI2S_RX_REG_CTRL_LATCH_CHSTS_MASK (1 << XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT)

Latch AES Channel Status mask.

Referenced by XI2s_Rx_LatchAesChannelStatus().

#define XI2S_RX_REG_CTRL_LATCH_CHSTS_SHIFT (16)

Latch AES Channel Status bit shift.

#define XI2S_RX_REG_CTRL_LORJF_MASK (1 << XI2S_RX_REG_CTRL_LORJF_SHIFT)

Left or Right Justification mask.

Referenced by XI2s_Rx_Justify().

#define XI2S_RX_REG_CTRL_LORJF_SHIFT (2)

Left or Right Justification shift.

#define XI2S_RX_REG_TMR_SCLKDIV_MASK (0xF << XI2S_RX_REG_TMR_SCLKDIV_SHIFT)

SClk Divider mask.

#define XI2S_RX_REG_TMR_SCLKDIV_SHIFT (0)

SClk Divider bit shift.

#define XI2S_RX_TMR_CTRL_OFFSET 0x20

XI2S Timing Control Register.

Referenced by XI2s_Rx_SetSclkOutDiv().

#define XI2s_Rx_WriteReg | ( |  | BaseAddress,
|  |  | RegOffset,
|  |  | Data
| ) |  | XI2s_Rx_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))

This macro writes a value to a XI2s Receiver register.

A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.

Parameters

  BaseAddress | is the base address of the XI2s Receiver core instance.
  RegOffset | is the register offset of the register (defined at the top of this file) to be written.
  Data | is the 32-bit value to write into the register.

Returns
  None.

Note
  C-style signature: void XI2s_Rx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XI2s_Rx_ClrAesChStatRegs(), XI2s_Rx_Enable(), XI2s_Rx_IntrDisable(), XI2s_Rx_IntrEnable(), XI2s_Rx_Justify(), XI2s_Rx_JustifyEnable(), XI2s_Rx_LatchAesChannelStatus(), XI2s_Rx_SetAesChStatus(), XI2s_Rx_SetChMux(), and XI2s_Rx_SetSclkOutDiv().

## Typedef Documentation

typedef void(* XI2s_Rx_Callback)(void *CallbackRef)

Callback function data type for handling interrupt requests from the XI2s Receiver peripheral.

The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handler is called in an interrupt context such that minimal processing should be performed.

Parameters

  CallBackRef | is a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked.

Returns
  None

Note
  None

## Enumeration Type Documentation

enum XI2s_Rx_ChannelId

These constants specify different channel ID's.

Enumerator
XI2S_RX_CHID0 | Channel 0.
XI2S_RX_CHID1 | Channel 1.
XI2S_RX_CHID2 | Channel 2.
XI2S_RX_CHID3 | Channel 3.
XI2S_RX_NUM_CHANNELS | Number of Channel ID's.

enum XI2s_Rx_ChMuxInput

This typedef specifies the input sources of the the XI2s Receiver.

Enumerator
XI2S_RX_CHMUX_DISABLED | Channel disabled.
XI2S_RX_CHMUX_XI2S_01 | XI2S Audio Channel 0 and 1.
XI2S_RX_CHMUX_XI2S_23 | XI2S Audio Channel 2 and 3.
XI2S_RX_CHMUX_XI2S_45 | XI2S Audio Channel 4 and 5.
XI2S_RX_CHMUX_XI2S_67 | XI2S Audio Channel 6 and 7.
XI2S_RX_CHMUX_WAVEGEN | Wave Generator.

enum XI2s_Rx_HandlerType

These constants specify different types of handlers and is used to differentiate interrupt requests from the XI2s Receiver peripheral.

Enumerator
XI2S_RX_HANDLER_AES_BLKCMPLT | AES Block Complete Handler.
XI2S_RX_HANDLER_AUD_OVRFLW | Audio Overflow Detected Handler.
XI2S_RX_NUM_HANDLERS | Number of handler types.

enum XI2s_Rx_Justification

This typedef specifies the justification of the the XI2s Receiver.

Enumerator
XI2S_RX_JUSTIFY_LEFT | Left Justification is enabled.
XI2S_RX_JUSTIFY_RIGHT | Right Justification is enabled.

enum XI2s_Rx_LogEvt

These constants specify different types of handlers and is used to differentiate interrupt requests from the XI2s Receiver peripheral.

Enumerator
XI2S_RX_AES_BLKCMPLT_EVT | AES Block Complete Event.
XI2S_RX_AUD_OVERFLOW_EVT | Audio Overflow Detected Event.
XI2S_RX_LOG_EVT_INVALID | Invalid Log Event.

## Function Documentation

int XI2s_Rx_CfgInitialize | ( | XI2s_Rx * | InstancePtr,
|  | XI2srx_Config * | CfgPtr,
|  | UINTPTR | EffectiveAddr
| ) |  |

This function initializes the XI2s Receiver.

This function must be called prior to using the core. Initialization of the XI2s Receiver includes setting up the instance data, and ensuring the hardware is in a quiescent state.

Parameters

  InstancePtr | is a pointer to the XI2s Receiver instance.
  CfgPtr | points to the configuration structure associated with the XI2s Receiver.
  EffectiveAddr | is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.

Returns
  - XST_SUCCESS : if successful.
  - XST_FAILURE : if version mismatched.

Note
  None.

References XI2s_Rx::Config, XI2s_Rx::IsReady, XI2s_Rx_Enable(), and XI2s_Rx_SelfTest().

Referenced by I2srx_SelfTest_Example(), I2sRxIntrExample(), and XI2s_Rx_Initialize().

void XI2s_Rx_ClrAesChStatRegs | ( | XI2s_Rx * | InstancePtr | ) |

This function clears the captured AES Channel Status bits.

This will clear all the 6 channel status registers.

Parameters

  InstancePtr | is a pointer to the XI2s_Rx core instance.

Returns
  None.

References XI2S_RX_AES_CHSTS0_OFFSET, XI2S_RX_AES_CHSTS1_OFFSET, XI2S_RX_AES_CHSTS2_OFFSET, XI2S_RX_AES_CHSTS3_OFFSET, XI2S_RX_AES_CHSTS4_OFFSET, XI2S_RX_AES_CHSTS5_OFFSET, and XI2s_Rx_WriteReg.

void XI2s_Rx_Enable | ( | XI2s_Rx * | InstancePtr,
|  | u8 | Enable
| ) |  |

This function enables/disables the XI2s Receiver.

Parameters

  InstancePtr | is a pointer to the XI2s Receiver instance.
  Enable | specifies TRUE/FALSE value to either enable or disable the XI2s Receiver.

Returns
  None.

References XI2s_Rx::Config, XI2s_Rx::IsStarted, XI2S_RX_CORE_CTRL_OFFSET, XI2s_Rx_ReadReg, XI2S_RX_REG_CTRL_EN_MASK, and XI2s_Rx_WriteReg.

Referenced by I2sRxIntrExample(), and XI2s_Rx_CfgInitialize().

int XI2s_Rx_Initialize | ( | XI2s_Rx * | InstancePtr,
|  | u16 | DeviceId
| ) |  |

Initializes a specific XI2s_Rx instance such that the driver is ready to use.

Parameters

  InstancePtr | is a pointer to the XI2s_Rx instance to be worked on.
  DeviceId | is the unique id of the device controlled by this XI2s_Rx instance. Passing in a device id associates the generic XI2s_Rx instance to a specific device, as chosen by the caller or application developer.

Returns
  - XST_SUCCESS if successful.
  - XST_DEVICE_NOT_FOUND if the device was not found in the configuration such that initialization could not be accomplished.
  - XST_INVALID_VERSION if version mismatched

References XI2s_Rx_CfgInitialize(), and XI2s_Rx_LookupConfig().

void XI2s_Rx_IntrDisable | ( | XI2s_Rx * | InstancePtr,
|  | u32 | Mask
| ) |  |

This function disables the specified interrupt of the XI2s Receiver.

Parameters

  InstancePtr | is a pointer to the XI2s Receiver instance.
  Mask | is a bit mask of the interrupts to be disabled.

Returns
  None.

See Also
  XI2s_Receiver_HW for the available interrupt masks.

References XI2s_Rx::Config, XI2S_RX_IRQCTRL_OFFSET, XI2s_Rx_ReadReg, and XI2s_Rx_WriteReg.

void XI2s_Rx_IntrEnable | ( | XI2s_Rx * | InstancePtr,
|  | u32 | Mask
| ) |  |

This function enables the specified interrupt of the XI2s Receiver.

Parameters

  InstancePtr | is a pointer to the XI2s Receiver instance.
  Mask | is a bit mask of the interrupts to be enabled.

Returns
  None.

See Also
  XI2srx_HW for the available interrupt masks.

References XI2s_Rx::Config, XI2S_RX_IRQCTRL_OFFSET, XI2s_Rx_ReadReg, and XI2s_Rx_WriteReg.

Referenced by I2sRxIntrExample().

void XI2s_Rx_IntrHandler | ( | void * | InstancePtr | ) |

This function is the interrupt handler for the XI2s Receiver driver.

This handler reads the pending interrupt from the XI2s Receiver peripheral, determines the source of the interrupts, clears the interrupts and calls callbacks accordingly.

Parameters

  InstancePtr | is a pointer to the XI2s_Rx instance.

Returns
  None.

Note
  None.

References XI2s_Rx::AudOverflowHandler, XI2s_Rx::Config, XI2s_Rx::IsReady, XI2S_RX_AES_BLKCMPLT_EVT, XI2S_RX_AUD_OVERFLOW_EVT, XI2S_RX_INTR_AES_BLKCMPLT_MASK, XI2S_RX_INTR_AUDOVRFLW_MASK, XI2S_RX_IRQCTRL_OFFSET, XI2S_RX_IRQSTS_OFFSET, XI2s_Rx_LogWrite(), and XI2s_Rx_ReadReg.

void XI2s_Rx_Justify | ( | XI2s_Rx * | InstancePtr,
|  | XI2s_Rx_Justification | Justify
| ) |  |

This function is to enable right/left justification.

Parameters

  InstancePtr | is a pointer to the XI2s Receiver instance.
  Justify | is a enum to select the left or right justfication. XI2S_RX_JUSTIFY_LEFT : Left justication XI2S_RX_JUSTIFY_RIGHT : Right justification

Returns
  None.

References XI2s_Rx::Config, XI2S_RX_CORE_CTRL_OFFSET, XI2s_Rx_ReadReg, XI2S_RX_REG_CTRL_LORJF_MASK, and XI2s_Rx_WriteReg.

void XI2s_Rx_JustifyEnable | ( | XI2s_Rx * | InstancePtr,
|  | u8 | Enable
| ) |  |

This function enables/disables the justification.

Parameters

  InstancePtr | is a pointer to the XI2s Receiver instance.
  Enable | specifies TRUE/FALSE value to either enable or disable the justification.

Returns
  None.

References XI2s_Rx::Config, XI2S_RX_CORE_CTRL_OFFSET, XI2s_Rx_ReadReg, XI2S_RX_REG_CTRL_JFE_MASK, and XI2s_Rx_WriteReg.

void XI2s_Rx_LatchAesChannelStatus | ( | XI2s_Rx * | InstancePtr | ) |

This function requests the XI2s Receiver to latch the AES Channel Status bits from the registers.

Parameters

  InstancePtr | is a pointer to the XI2s Receiver instance.

Returns
  None.

References XI2s_Rx::Config, XI2S_RX_CORE_CTRL_OFFSET, XI2s_Rx_ReadReg, XI2S_RX_REG_CTRL_LATCH_CHSTS_MASK, and XI2s_Rx_WriteReg.

void XI2s_Rx_LogDisplay | ( | XI2s_Rx * | InstancePtr | ) |

This function prints the contents of the logging buffer.

Parameters

  InstancePtr | is a pointer to the XI2s_Rx instance.

Returns
  None.

Note
  None.

References XI2s_Rx::Config, XI2srx_Config::DeviceId, XI2s_Rx_LogItem::Event, XI2S_RX_AES_BLKCMPLT_EVT, XI2S_RX_AUD_OVERFLOW_EVT, XI2S_RX_LOG_EVT_INVALID, and XI2s_Rx_LogRead().

XI2s_Rx_LogItem * XI2s_Rx_LogRead | ( | XI2s_Rx * | InstancePtr | ) |

This function returns the next item in the logging buffer.

Parameters

  InstancePtr | is a pointer to the XI2s_Rx instance.

Returns
  When the buffer is filled, the next log item is returned. When the buffer is empty, NULL is returned.

Note
  None.

References XI2s_Rx_Log::Head, XI2s_Rx_Log::Items, XI2s_Rx::Log, and XI2s_Rx_Log::Tail.

Referenced by XI2s_Rx_LogDisplay().

void XI2s_Rx_LogReset | ( | XI2s_Rx * | InstancePtr | ) |

This function clears the contents of the logging buffer.

Parameters

  InstancePtr | is a pointer to the XI2s_Rx instance.

Returns
  None.

Note
  None.

References XI2s_Rx_Log::Head, XI2s_Rx_Log::IsEnabled, XI2s_Rx::Log, and XI2s_Rx_Log::Tail.

void XI2s_Rx_LogWrite | ( | XI2s_Rx * | InstancePtr,
|  | XI2s_Rx_LogEvt | Event,
|  | u8 | Data
| ) |  |

This function writes XI2s Receiver logs into the buffer.

Parameters

  InstancePtr | is a pointer to the XI2s_Rx instance.
  Event | is the log event type.
  Data | is the log data.

Returns
  None.

Note
  Log write is done only if the log is enabled.

References XI2s_Rx_LogItem::Data, XI2s_Rx_LogItem::Event, XI2s_Rx_Log::Head, XI2s_Rx_Log::IsEnabled, XI2s_Rx_Log::Items, XI2s_Rx::Log, XI2s_Rx_Log::Tail, and XI2S_RX_LOG_EVT_INVALID.

Referenced by XI2s_Rx_IntrHandler().

XI2srx_Config * XI2s_Rx_LookupConfig | ( | u16 | DeviceId | ) |

This function returns a reference to an XI2srx_Config structure based on the core id, DeviceId.

The return value will refer to an entry in the device configuration table defined in the xi2srx_g.c file.

Parameters

  DeviceId | is the unique core ID of the XI2s Receiver core for the lookup operation.

Returns
  returns a reference to a config record in the configuration table corresponding to DeviceId, or NULL if no match is found.

Note
  None.

Referenced by I2srx_SelfTest_Example(), I2sRxIntrExample(), and XI2s_Rx_Initialize().

int XI2s_Rx_SelfTest | ( | XI2s_Rx * | InstancePtr | ) |

Runs a self-test on the driver/device.

The self-test reads the version register, data width , max channels, Master or slave configuration and verifies the values

Parameters

  InstancePtr | is a pointer to the XI2s_Rx instance.

Returns
  - XST_SUCCESS if successful i.e. if the self test passes.
  - XST_FAILURE if unsuccessful i.e. if the self test fails

Note
  None.

References XI2s_Rx_GetMaxChannels, and XI2s_Rx_IsXI2sMaster.

Referenced by XI2s_Rx_CfgInitialize().

void XI2s_Rx_SetAesChStat | ( | u32 | I2srx_SrcBuf[],
|  | u8 | I2srx_DstBuf[]
| ) |  |

This function reads the source buffer and writes to a destination buffer.

Before calling this API user application should write 192 bits i.e. 24 bytes to the array I2srx_SrcBuf.

Parameters

  I2srx_SrcBuf | is the source buffer which has 192 channel status bits.
  I2srx_DstBuf | is the destination buffer to store the 24 bytes.

Returns
  void.

< use of channel status block

< linear PCM identification

< audio signal Pre-emphasis

< lock indication

< sampling frequency

< channel mode

< user bits management

< use of auxiliary sample bits

< source word length

< indication of alignment level

< channel mode

< Channel number 0

< Channel number 1

< multi channel1 mode number

< digital audio reference signal

< reserved but undefined

< sampling frequency

< sampling frequency scaling flag

< reserved but undefined

< Alphanumeric channel origin data

< Alphanumeric channel destination data

< Local sample address code

< Time-of-day sample address code

< Reliability flags

< Cyclic redundancy check character

void XI2s_Rx_SetAesChStatus | ( | XI2s_Rx * | InstancePtr,
|  | u8 * | AesChStatusBuf
| ) |  |

This function sets the AES Channel Status bits to insert.

Parameters

  InstancePtr | is a pointer to the XI2s Receiver instance.
  AesChStatusBuf | is a pointer to a buffer containing the AES channel status bits.

Returns
  None.

References XI2s_Rx::Config, XI2S_RX_AES_CHSTS0_OFFSET, and XI2s_Rx_WriteReg.

int XI2s_Rx_SetChMux | ( | XI2s_Rx * | InstancePtr,
|  | XI2s_Rx_ChannelId | ChID,
|  | XI2s_Rx_ChMuxInput | InputSource
| ) |  |

This function sets the input source for the specified AXI-Stream channel pair.

Parameters

  InstancePtr | is a pointer to the XI2s Receiver instance.
  ChID | specifies the AXI-Stream channel pair 0 : AXI-Stream channel 0 and 1 1 : AXI-Stream channel 2 and 3 2 : AXI-Stream channel 4 and 5 3 : AXI-Stream channel 6 and 7
  InputSource | specifies the input source

Returns
  - XST_SUCCESS : if successful.
  - XST_FAILURE : if the AXI-Stream channel pair is invalid.

References XI2s_Rx::Config, XI2S_RX_CH01_OFFSET, XI2S_RX_CHMUX_WAVEGEN, XI2S_RX_CHMUX_XI2S_01, XI2S_RX_CHMUX_XI2S_23, XI2S_RX_CHMUX_XI2S_45, XI2S_RX_CHMUX_XI2S_67, XI2S_RX_NUM_CHANNELS, and XI2s_Rx_WriteReg.

Referenced by I2sRxIntrExample().

int XI2s_Rx_SetHandler | ( | XI2s_Rx * | InstancePtr,
|  | XI2s_Rx_HandlerType | HandlerType,
|  | XI2s_Rx_Callback | FuncPtr,
|  | void * | CallbackRef
| ) |  |

This function installs an asynchronous callback function for the given HandlerType:

    HandlerType                              Callback Function
    --------------------------------         ----------------------------------
    (XI2S_RX_HANDLER_AES_BLKCMPLT)            AesBlkCmpltHandler
    (XI2S_RX_HANDLER_AUD_OVERFLOW)            AudOverflowHandler

Parameters

  InstancePtr | is a pointer to the XI2s_Rx core instance.
  HandlerType | specifies the type of handler.
  FuncPtr | is a pointer to the callback function.
  CallbackRef | is a reference pointer passed on actual calling of the callback function.

Returns
  - XST_SUCCESS if callback function installed successfully.
  - XST_INVALID_PARAM when HandlerType is invalid.

Note
  Invoking this function for a handler that already has been installed replaces it with the new handler.

References XI2s_Rx::AudOverflowHandler, XI2S_RX_HANDLER_AES_BLKCMPLT, XI2S_RX_HANDLER_AUD_OVRFLW, and XI2S_RX_NUM_HANDLERS.

Referenced by I2sRxIntrExample().

u32 XI2s_Rx_SetSclkOutDiv | ( | XI2s_Rx * | InstancePtr,
|  | u32 | MClk,
|  | u32 | Fs
| ) |  |

This function calculates the SCLK Output divider value of the I2s timing generator.

Parameters

  InstancePtr | is a pointer to the I2s Receiver instance.
  MClk | is the frequency of the MClk.
  Fs | is the sampling frequency of the system. Divider value for the SCLK generation MCLK/SCLK = SCLKOUT_DIV x 2 i.e. MCLK = 384xFs, SCLK = 48xFs (2x24bits) -> SCLKOUT_DIV = MCLK/SCLK/2 = 4 Valid values are 1 through 15.

Returns
  - XST_FAILURE if SCLK Output divider is not calculated to be a positive integer.
  - XST_SUCCESS, otherwise.

References XI2s_Rx::Config, XI2srx_Config::DWidth, XI2S_RX_TMR_CTRL_OFFSET, and XI2s_Rx_WriteReg.

Referenced by I2sRxIntrExample().