config 64BIT
	bool
	default ARCH != "arm32"
	help
	  Say yes to build a 64-bit Xen
	  Say no to build a 32-bit Xen

config ARM_32
	def_bool y
	depends on !64BIT

config ARM_64
	def_bool y
	depends on 64BIT

config ARM
	def_bool y
	select HAS_ALTERNATIVE
	select HAS_ARM_HDLCD
	select HAS_DEVICE_TREE
	select HAS_PASSTHROUGH
	select HAS_PDX
	select VIDEO

config ARCH_DEFCONFIG
	string
	default "arch/arm/configs/arm32_defconfig" if ARM_32
	default "arch/arm/configs/arm64_defconfig" if ARM_64

menu "Architecture Features"

source "arch/Kconfig"

config ACPI
	bool
	prompt "ACPI (Advanced Configuration and Power Interface) Support" if EXPERT = "y"
	depends on ARM_64
	---help---

	  Advanced Configuration and Power Interface (ACPI) support for Xen is
	  an alternative to device tree on ARM64.

config GICV3
	bool "GICv3 driver"
	depends on ARM_64
	default y
	---help---

	  Driver for the ARM Generic Interrupt Controller v3.
	  If unsure, say Y

config HAS_ITS
        bool
        prompt "GICv3 ITS MSI controller support" if EXPERT = "y"
        depends on GICV3 && !NEW_VGIC

config NEW_VGIC
	bool
	prompt "Use new VGIC implementation"
	select NEEDS_LIST_SORT
	---help---

	This is an alternative implementation of the ARM GIC interrupt
	controller emulation, based on the Linux/KVM VGIC. It has a better
	design and fixes many shortcomings of the existing GIC emulation in
	Xen. It will eventually replace the existing/old VGIC.
	However at the moment it lacks support for Dom0 using the ITS for
	using MSIs.
	Say Y if you want to help testing this new code or if you experience
	problems with the standard emulation.
	At the moment this implementation is not security supported.

config SBSA_VUART_CONSOLE
	bool "Emulated SBSA UART console support"
	default y
	---help---
	  Allows a guest to use SBSA Generic UART as a console. The
	  SBSA Generic UART implements a subset of ARM PL011 UART.

endmenu

menu "ARM errata workaround via the alternative framework"
	depends on HAS_ALTERNATIVE

config ARM64_ERRATUM_827319
	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
	default y
	depends on ARM_64
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
	  master interface and an L2 cache.

	  Under certain conditions this erratum can cause a clean line eviction
	  to occur at the same time as another transaction to the same address
	  on the AMBA 5 CHI interface, which can cause data corruption if the
	  interconnect reorders the two transactions.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_824069
	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
	default y
	depends on ARM_64
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
	  to a coherent interconnect.

	  If a Cortex-A53 processor is executing a store or prefetch for
	  write instruction at the same time as a processor in another
	  cluster is executing a cache maintenance operation to the same
	  address, then this erratum might cause a clean cache line to be
	  incorrectly marked as dirty.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this option does not necessarily enable the
	  workaround, as it depends on the alternative framework, which will
	  only patch the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_819472
	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
	default y
	depends on ARM_64
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
	  present when it is connected to a coherent interconnect.

	  If the processor is executing a load and store exclusive sequence at
	  the same time as a processor in another cluster is executing a cache
	  maintenance operation to the same address, then this erratum might
	  cause data corruption.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_832075
	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
	default y
	depends on ARM_64
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 832075 on Cortex-A57 parts up to r1p2.

	  Affected Cortex-A57 parts might deadlock when exclusive load/store
	  instructions to Write-Back memory are mixed with Device loads.

	  The workaround is to promote device loads to use Load-Acquire
	  semantics.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_834220
	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
	default y
	depends on ARM_64
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 834220 on Cortex-A57 parts up to r1p2.

	  Affected Cortex-A57 parts might report a Stage 2 translation
	  fault as the result of a Stage 1 fault for load crossing a
	  page boundary when there is a permission or device memory
	  alignment fault at Stage 1 and a translation fault at Stage 2.

	  The workaround is to verify that the Stage 1 translation
	  doesn't generate a fault before handling the Stage 2 fault.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

endmenu

config HARDEN_BRANCH_PREDICTOR
	bool "Harden the branch predictor against aliasing attacks" if EXPERT
	default y
	help
	  Speculation attacks against some high-performance processors rely on
	  being able to manipulate the branch predictor for a victim context by
	  executing aliasing branches in the attacker context.  Such attacks
	  can be partially mitigated against by clearing internal branch
	  predictor state and limiting the prediction logic in some situations.

	  This config option will take CPU-specific actions to harden the
	  branch predictor against aliasing attacks and may rely on specific
	  instruction sequences or control bits being set by the system
	  firmware.

	  If unsure, say Y.

config ARM64_HARDEN_BRANCH_PREDICTOR
    def_bool y if ARM_64 && HARDEN_BRANCH_PREDICTOR

config ARM32_HARDEN_BRANCH_PREDICTOR
    def_bool y if ARM_32 && HARDEN_BRANCH_PREDICTOR

source "arch/arm/platforms/Kconfig"

source "common/Kconfig"

source "drivers/Kconfig"
