Xilinx ARM-Microblaze remoteproc driver

This driver requires specific Zynq hardware design where Microblaze is added
to the programmable logic.
Microblaze is connected with PS block via axi bus connected to PS HP port
to ensure access to PS DDR.
Communication channels are done via soft GPIO IP connected to PS block
and to Microblaze. There are also 2 gpio control signals reset and debug
which are used for reseting Microblaze.

Required properties:
- compatible : Should be "xlnx,mb_remoteproc"
- reg : Address and length of the ddr address space
- bram: Phandle to bram controller which can access Microblaze BRAM
- bram-firmware : Microblaze BRAM bootloader name
- firmware : Default firmware name which can be override by
	     "firmware" module parameter
- reset : Gpio phandle which reset Microblaze remoteproc
- debug : Gpio phandle which setup Microblaze to debug state
- ipino : Gpio phandle for Microblaze to ARM communication
- vring0 : Gpio phandle for ARM to Microblaze communication vring 0
- vring1 : Gpio phandle for ARM to Microblaze communication vring 1

Microblaze SoC can be also connected to the PS block via a axi bus.
That's why there is the option to allocate interrupts for Microblaze use only.
The driver will allocate interrupts to itself and Microblaze sw has to ensure
that interrupts are properly enabled and handled by Microblaze interrupt
controller.

Optional properties:
 - interrupts : Interrupt mapping for remoteproc
 - interrupt-parent : Phandle for the interrupt controller

Example:
test_mb: mb_remoteproc-test@800000 {
	compatible = "xlnx,mb_remoteproc";
	reg = < 0x8000000 0x8000000 >;
	bram = <&axi_bram_ctrl_0>;
	bram-firmware = "mb.bin";
	firmware = "image.elf";
	reset = <&zynq_gpio_reset 1 0>;
	debug = <&zynq_gpio_reset 0 0>;
	ipino = <&zynq_gpio_vring 0 0>;
	vring0 = <&zynq_gpio_vring 1 0>;
	vring1 = <&zynq_gpio_vring 2 0>;
} ;
