Zynq/ZynqMP EDAC driver, it does reports the DDR ECC single bit errors that are
corrected and double bit ecc errors that are detected by the DDR ECC controller.
ECC support for DDR is available in half-bus width(16 bit) configuration only.

Required properties:
- compatible: Should be "xlnx,zynq-ddrc-a05" for Zynq
	      and "xlnx,zynqmp-ddrc-2.40a""for ZynqMP
- reg: Should contain DDR controller registers location and length.
- interrupt-parent: Should be core interrupt controller
		    valid for ZynqMP DDR Controller
- interrupts: Property with a value describing the interrupt number
	      Valid for ZynqMP DDR Controller

Example:
++++++++

zynq_ddrc_0: zynq-ddrc@f8006000 {
	compatible = "xlnx,zynq-ddrc-a05";
	reg = <0xf8006000 0x1000>;
};

mc: memory-controller@fd070000 {
	compatible = "xlnx,zynqmp-ddrc-2.40a";
	reg = <0x0 0xfd070000 0x0 0x30000>;
	interrupt-parent = <&gic>;
	interrupts = <0 112 4>;
};

Zynq/ZYnqMP EDAC driver detects the DDR ECC enable state by reading the appropriate
control register.
