/* Definition for CPU ID */
#define XPAR_CPU_ID 0

/* Definitions for peripheral PS8_CORTEXR5_0 */
#define XPAR_PS8_CORTEXR5_0_CPU_CLK_FREQ_HZ 500000000


/******************************************************************/

/* Canonical definitions for peripheral PS8_CORTEXR5_0 */
#define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 500000000


/******************************************************************/

#include "xparameters_ps.h"

#define STDIN_BASEADDRESS 0xFF000000
#define STDOUT_BASEADDRESS 0xFF000000

/******************************************************************/

/* Definitions for driver CANPS */
#define XPAR_XCANPS_NUM_INSTANCES 2

/* Definitions for peripheral PS8_CAN_0 */
#define XPAR_PS8_CAN_0_DEVICE_ID 0
#define XPAR_PS8_CAN_0_BASEADDR 0xFF060000
#define XPAR_PS8_CAN_0_HIGHADDR 0xFF060FFF
#define XPAR_PS8_CAN_0_CAN_CLK_FREQ_HZ 100000000


/* Definitions for peripheral PS8_CAN_1 */
#define XPAR_PS8_CAN_1_DEVICE_ID 1
#define XPAR_PS8_CAN_1_BASEADDR 0xFF070000
#define XPAR_PS8_CAN_1_HIGHADDR 0xFF070FFF
#define XPAR_PS8_CAN_1_CAN_CLK_FREQ_HZ 100000000


/******************************************************************/

/* Canonical definitions for peripheral PS8_CAN_0 */
#define XPAR_XCANPS_0_DEVICE_ID XPAR_PS8_CAN_0_DEVICE_ID
#define XPAR_XCANPS_0_BASEADDR 0xFF060000
#define XPAR_XCANPS_0_HIGHADDR 0xFF060FFF
#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 100000000

/* Canonical definitions for peripheral PS8_CAN_1 */
#define XPAR_XCANPS_1_DEVICE_ID XPAR_PS8_CAN_1_DEVICE_ID
#define XPAR_XCANPS_1_BASEADDR 0xFF070000
#define XPAR_XCANPS_1_HIGHADDR 0xFF070FFF
#define XPAR_XCANPS_1_CAN_CLK_FREQ_HZ 100000000


/******************************************************************/

/* Definitions for driver EMACPS */
#define XPAR_XEMACPS_NUM_INSTANCES 4

/* Definitions for peripheral PS8_ETHERNET_0 */
#define XPAR_PS8_ETHERNET_0_DEVICE_ID 0
#define XPAR_PS8_ETHERNET_0_BASEADDR 0xFF0B0000
#define XPAR_PS8_ETHERNET_0_HIGHADDR 0xFF0B0FFF
#define XPAR_PS8_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000
#define XPAR_PS8_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 50000000
#define XPAR_PS8_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 50000000
#define XPAR_PS8_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 50000000
#define XPAR_PS8_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 50000000
#define XPAR_PS8_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 50000000
#define XPAR_PS8_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50000000


/* Definitions for peripheral PS8_ETHERNET_1 */
#define XPAR_PS8_ETHERNET_1_DEVICE_ID 1
#define XPAR_PS8_ETHERNET_1_BASEADDR 0xFF0C0000
#define XPAR_PS8_ETHERNET_1_HIGHADDR 0xFF0C0FFF
#define XPAR_PS8_ETHERNET_1_ENET_CLK_FREQ_HZ 125000000
#define XPAR_PS8_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 50000000
#define XPAR_PS8_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 50000000
#define XPAR_PS8_ETHERNET_1_ENET_SLCR_100MBPS_DIV0 50000000
#define XPAR_PS8_ETHERNET_1_ENET_SLCR_100MBPS_DIV1 50000000
#define XPAR_PS8_ETHERNET_1_ENET_SLCR_10MBPS_DIV0 50000000
#define XPAR_PS8_ETHERNET_1_ENET_SLCR_10MBPS_DIV1 50000000


/* Definitions for peripheral PS8_ETHERNET_2 */
#define XPAR_PS8_ETHERNET_2_DEVICE_ID 2
#define XPAR_PS8_ETHERNET_2_BASEADDR 0xFF0D0000
#define XPAR_PS8_ETHERNET_2_HIGHADDR 0xFF0D0FFF
#define XPAR_PS8_ETHERNET_2_ENET_CLK_FREQ_HZ 125000000
#define XPAR_PS8_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0 50000000
#define XPAR_PS8_ETHERNET_2_ENET_SLCR_1000MBPS_DIV1 50000000
#define XPAR_PS8_ETHERNET_2_ENET_SLCR_100MBPS_DIV0 50000000
#define XPAR_PS8_ETHERNET_2_ENET_SLCR_100MBPS_DIV1 50000000
#define XPAR_PS8_ETHERNET_2_ENET_SLCR_10MBPS_DIV0 50000000
#define XPAR_PS8_ETHERNET_2_ENET_SLCR_10MBPS_DIV1 50000000


/* Definitions for peripheral PS8_ETHERNET_3 */
#define XPAR_PS8_ETHERNET_3_DEVICE_ID 3
#define XPAR_PS8_ETHERNET_3_BASEADDR 0xFF0E0000
#define XPAR_PS8_ETHERNET_3_HIGHADDR 0xFF0E0FFF
#define XPAR_PS8_ETHERNET_3_ENET_CLK_FREQ_HZ 125000000
#define XPAR_PS8_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 50000000
#define XPAR_PS8_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 50000000
#define XPAR_PS8_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 50000000
#define XPAR_PS8_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 50000000
#define XPAR_PS8_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 50000000
#define XPAR_PS8_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 50000000


/******************************************************************/

/* Canonical definitions for peripheral PS8_ETHERNET_0 */
#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS8_ETHERNET_0_DEVICE_ID
#define XPAR_XEMACPS_0_BASEADDR 0xFF0B0000
#define XPAR_XEMACPS_0_HIGHADDR 0xFF0B0FFF
#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 50000000
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 50000000
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 50000000
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 50000000
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 50000000
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50000000

/* Canonical definitions for peripheral PS8_ETHERNET_1 */
#define XPAR_XEMACPS_1_DEVICE_ID XPAR_PS8_ETHERNET_1_DEVICE_ID
#define XPAR_XEMACPS_1_BASEADDR 0xFF0C0000
#define XPAR_XEMACPS_1_HIGHADDR 0xFF0C0FFF
#define XPAR_XEMACPS_1_ENET_CLK_FREQ_HZ 125000000
#define XPAR_XEMACPS_1_ENET_SLCR_1000Mbps_DIV0 50000000
#define XPAR_XEMACPS_1_ENET_SLCR_1000Mbps_DIV1 50000000
#define XPAR_XEMACPS_1_ENET_SLCR_100Mbps_DIV0 50000000
#define XPAR_XEMACPS_1_ENET_SLCR_100Mbps_DIV1 50000000
#define XPAR_XEMACPS_1_ENET_SLCR_10Mbps_DIV0 50000000
#define XPAR_XEMACPS_1_ENET_SLCR_10Mbps_DIV1 50000000

/* Canonical definitions for peripheral PS8_ETHERNET_2 */
#define XPAR_XEMACPS_2_DEVICE_ID XPAR_PS8_ETHERNET_2_DEVICE_ID
#define XPAR_XEMACPS_2_BASEADDR 0xFF0D0000
#define XPAR_XEMACPS_2_HIGHADDR 0xFF0D0FFF
#define XPAR_XEMACPS_2_ENET_CLK_FREQ_HZ 125000000
#define XPAR_XEMACPS_2_ENET_SLCR_1000Mbps_DIV0 50000000
#define XPAR_XEMACPS_2_ENET_SLCR_1000Mbps_DIV1 50000000
#define XPAR_XEMACPS_2_ENET_SLCR_100Mbps_DIV0 50000000
#define XPAR_XEMACPS_2_ENET_SLCR_100Mbps_DIV1 50000000
#define XPAR_XEMACPS_2_ENET_SLCR_10Mbps_DIV0 50000000
#define XPAR_XEMACPS_2_ENET_SLCR_10Mbps_DIV1 50000000

/* Canonical definitions for peripheral PS8_ETHERNET_3 */
#define XPAR_XEMACPS_3_DEVICE_ID XPAR_PS8_ETHERNET_3_DEVICE_ID
#define XPAR_XEMACPS_3_BASEADDR 0xFF0E0000
#define XPAR_XEMACPS_3_HIGHADDR 0xFF0E0FFF
#define XPAR_XEMACPS_3_ENET_CLK_FREQ_HZ 125000000
#define XPAR_XEMACPS_3_ENET_SLCR_1000Mbps_DIV0 50000000
#define XPAR_XEMACPS_3_ENET_SLCR_1000Mbps_DIV1 50000000
#define XPAR_XEMACPS_3_ENET_SLCR_100Mbps_DIV0 50000000
#define XPAR_XEMACPS_3_ENET_SLCR_100Mbps_DIV1 50000000
#define XPAR_XEMACPS_3_ENET_SLCR_10Mbps_DIV0 50000000
#define XPAR_XEMACPS_3_ENET_SLCR_10Mbps_DIV1 50000000


/******************************************************************/


/* Definitions for peripheral PS8_ADMA_0 */
#define XPAR_PS8_ADMA_0_S_AXI_BASEADDR 0xFF500000
#define XPAR_PS8_ADMA_0_S_AXI_HIGHADDR 0xFF53FFFF


/* Definitions for peripheral PS8_AFI_0 */
#define XPAR_PS8_AFI_0_S_AXI_BASEADDR 0xFE501000
#define XPAR_PS8_AFI_0_S_AXI_HIGHADDR 0xFE501FFF


/* Definitions for peripheral PS8_AFI_1 */
#define XPAR_PS8_AFI_1_S_AXI_BASEADDR 0xFE502000
#define XPAR_PS8_AFI_1_S_AXI_HIGHADDR 0xFE502FFF


/* Definitions for peripheral PS8_AFI_2 */
#define XPAR_PS8_AFI_2_S_AXI_BASEADDR 0xFE503000
#define XPAR_PS8_AFI_2_S_AXI_HIGHADDR 0xFE503FFF


/* Definitions for peripheral PS8_AFI_3 */
#define XPAR_PS8_AFI_3_S_AXI_BASEADDR 0xFE504000
#define XPAR_PS8_AFI_3_S_AXI_HIGHADDR 0xFE504FFF


/* Definitions for peripheral PS8_AFI_4 */
#define XPAR_PS8_AFI_4_S_AXI_BASEADDR 0xFE505000
#define XPAR_PS8_AFI_4_S_AXI_HIGHADDR 0xFE505FFF


/* Definitions for peripheral PS8_AFI_5 */
#define XPAR_PS8_AFI_5_S_AXI_BASEADDR 0xFE506000
#define XPAR_PS8_AFI_5_S_AXI_HIGHADDR 0xFE506FFF


/* Definitions for peripheral PS8_AFI_6 */
#define XPAR_PS8_AFI_6_S_AXI_BASEADDR 0xFE504000
#define XPAR_PS8_AFI_6_S_AXI_HIGHADDR 0xFE504FFF


/* Definitions for peripheral PS8_APM_0 */
#define XPAR_PS8_APM_0_S_AXI_BASEADDR 0xFD0B0000
#define XPAR_PS8_APM_0_S_AXI_HIGHADDR 0xFD0B0300


/* Definitions for peripheral PS8_APM_1 */
#define XPAR_PS8_APM_1_S_AXI_BASEADDR 0xFFA00000
#define XPAR_PS8_APM_1_S_AXI_HIGHADDR 0xFFA00300


/* Definitions for peripheral PS8_APM_2 */
#define XPAR_PS8_APM_2_S_AXI_BASEADDR 0xFFA10000
#define XPAR_PS8_APM_2_S_AXI_HIGHADDR 0xFFA10300


/* Definitions for peripheral PS8_APM_3 */
#define XPAR_PS8_APM_3_S_AXI_BASEADDR 0xFFA20000
#define XPAR_PS8_APM_3_S_AXI_HIGHADDR 0xFFA20300


/* Definitions for peripheral PS8_APM_4 */
#define XPAR_PS8_APM_4_S_AXI_BASEADDR 0xFFA30000
#define XPAR_PS8_APM_4_S_AXI_HIGHADDR 0xFFA30300


/* Definitions for peripheral PS8_BBRAM_0 */
#define XPAR_PS8_BBRAM_0_S_AXI_BASEADDR 0xFFCC4000
#define XPAR_PS8_BBRAM_0_S_AXI_HIGHADDR 0xFFCC4FFF


/* Definitions for peripheral PS8_CSU_RAM_0 */
#define XPAR_PS8_CSU_RAM_0_S_AXI_BASEADDR 0xFFC40000
#define XPAR_PS8_CSU_RAM_0_S_AXI_HIGHADDR 0xFFC47FFF


/* Definitions for peripheral PS8_DEV_CFG_0 */
#define XPAR_PS8_DEV_CFG_0_S_AXI_BASEADDR 0xF8007000
#define XPAR_PS8_DEV_CFG_0_S_AXI_HIGHADDR 0xF8007FFF


/* Definitions for peripheral PS8_GDMA_0 */
#define XPAR_PS8_GDMA_0_S_AXI_BASEADDR 0xFE570000
#define XPAR_PS8_GDMA_0_S_AXI_HIGHADDR 0xFE5AFFFF


/* Definitions for peripheral PS8_IOP_BUS_CONFIG_0 */
#define XPAR_PS8_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
#define XPAR_PS8_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF


/* Definitions for peripheral PS8_IOUSLCR_0 */
#define XPAR_PS8_IOUSLCR_0_S_AXI_BASEADDR 0xFF180000
#define XPAR_PS8_IOUSLCR_0_S_AXI_HIGHADDR 0xFF180FFF


/* Definitions for peripheral PS8_OCM_RAM_0 */
#define XPAR_PS8_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000
#define XPAR_PS8_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF


/* Definitions for peripheral PS8_OCM_RAM_1 */
#define XPAR_PS8_OCM_RAM_1_S_AXI_BASEADDR 0xFFFF0000
#define XPAR_PS8_OCM_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF


/* Definitions for peripheral PS8_QSPI_LINEAR_0 */
#define XPAR_PS8_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000
#define XPAR_PS8_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF


/* Definitions for peripheral PS8_R5_TCM_RAM_0 */
#define XPAR_PS8_R5_TCM_RAM_0_S_AXI_BASEADDR 0x00000000
#define XPAR_PS8_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x00020000


/* Definitions for peripheral PS8_SCUTIMER_0 */
#define XPAR_PS8_SCUTIMER_0_S_AXI_BASEADDR 0xFD3FE600
#define XPAR_PS8_SCUTIMER_0_S_AXI_HIGHADDR 0xFD3FE61F


/* Definitions for peripheral PS8_SCUWDT_0 */
#define XPAR_PS8_SCUWDT_0_S_AXI_BASEADDR 0xFD3FE620
#define XPAR_PS8_SCUWDT_0_S_AXI_HIGHADDR 0xFD3FE6FF


/******************************************************************/

/* Definitions for driver GPIOPS */
#define XPAR_XGPIOPS_NUM_INSTANCES 1

/* Definitions for peripheral PS8_GPIO_0 */
#define XPAR_PS8_GPIO_0_DEVICE_ID 0
#define XPAR_PS8_GPIO_0_BASEADDR 0xFF0A0000
#define XPAR_PS8_GPIO_0_HIGHADDR 0xFF0A0FFF


/******************************************************************/

/* Canonical definitions for peripheral PS8_GPIO_0 */
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS8_GPIO_0_DEVICE_ID
#define XPAR_XGPIOPS_0_BASEADDR 0xFF0A0000
#define XPAR_XGPIOPS_0_HIGHADDR 0xFF0A0FFF


/******************************************************************/

/* Definitions for driver IICPS */
#define XPAR_XIICPS_NUM_INSTANCES 2

/* Definitions for peripheral PS8_I2C_0 */
#define XPAR_PS8_I2C_0_DEVICE_ID 0
#define XPAR_PS8_I2C_0_BASEADDR 0xFF020000
#define XPAR_PS8_I2C_0_HIGHADDR 0xFF020FFF
#define XPAR_PS8_I2C_0_I2C_CLK_FREQ_HZ 100000000


/* Definitions for peripheral PS8_I2C_1 */
#define XPAR_PS8_I2C_1_DEVICE_ID 1
#define XPAR_PS8_I2C_1_BASEADDR 0xFF030000
#define XPAR_PS8_I2C_1_HIGHADDR 0xFF030FFF
#define XPAR_PS8_I2C_1_I2C_CLK_FREQ_HZ 100000000


/******************************************************************/

/* Canonical definitions for peripheral PS8_I2C_0 */
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS8_I2C_0_DEVICE_ID
#define XPAR_XIICPS_0_BASEADDR 0xFF020000
#define XPAR_XIICPS_0_HIGHADDR 0xFF020FFF
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 100000000

/* Canonical definitions for peripheral PS8_I2C_1 */
#define XPAR_XIICPS_1_DEVICE_ID XPAR_PS8_I2C_1_DEVICE_ID
#define XPAR_XIICPS_1_BASEADDR 0xFF030000
#define XPAR_XIICPS_1_HIGHADDR 0xFF030FFF
#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 100000000


/******************************************************************/

/* Definitions for driver NANDPS8 */
#define XPAR_XNANDPS8_NUM_INSTANCES 1

/* Definitions for peripheral PS8_NAND_0 */
#define XPAR_PS8_NAND_0_DEVICE_ID 0
#define XPAR_PS8_NAND_0_BASEADDR 0xFF100000
#define XPAR_PS8_NAND_0_HIGHADDR 0xFF100FFF


/******************************************************************/

/* Canonical definitions for peripheral PS8_NAND_0 */
#define XPAR_XNANDPS8_0_DEVICE_ID XPAR_PS8_NAND_0_DEVICE_ID
#define XPAR_XNANDPS8_0_BASEADDR 0xFF100000
#define XPAR_XNANDPS8_0_HIGHADDR 0xFF100FFF


/******************************************************************/

/* Definitions for driver QSPIPS */
#define XPAR_XQSPIPS_NUM_INSTANCES 1

/* Definitions for peripheral PS8_QSPI_0 */
#define XPAR_PS8_QSPI_0_DEVICE_ID 0
#define XPAR_PS8_QSPI_0_BASEADDR 0xFF0F0000
#define XPAR_PS8_QSPI_0_HIGHADDR 0xFF0F0FFF
#define XPAR_PS8_QSPI_0_QSPI_CLK_FREQ_HZ 300000000
#define XPAR_PS8_QSPI_0_QSPI_MODE 0


/******************************************************************/

/* Canonical definitions for peripheral PS8_QSPI_0 */
#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS8_QSPI_0_DEVICE_ID
#define XPAR_XQSPIPS_0_BASEADDR 0xFF0F0000
#define XPAR_XQSPIPS_0_HIGHADDR 0xFF0F0FFF
#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 300000000
#define XPAR_XQSPIPS_0_QSPI_MODE 0


/******************************************************************/


/***Definitions for Core_nIRQ/nFIQ interrupts ****/
/* Definitions for driver SCUGIC */
#define XPAR_XSCUGIC_NUM_INSTANCES 1

/* Definitions for peripheral PS8_SCUGIC_0 */
#define XPAR_PS8_SCUGIC_0_DEVICE_ID 0
#define XPAR_PS8_SCUGIC_0_BASEADDR 0xF9001000
#define XPAR_PS8_SCUGIC_0_HIGHADDR 0xF9001FFF
#define XPAR_PS8_SCUGIC_0_DIST_BASEADDR 0xF9000000


/******************************************************************/

/* Canonical definitions for peripheral PS8_SCUGIC_0 */
#define XPAR_SCUGIC_0_DEVICE_ID 0
#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000
#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFF
#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000


/******************************************************************/

/* Definitions for driver SDPS */
#define XPAR_XSDPS_NUM_INSTANCES 2

/* Definitions for peripheral PS8_SD_0 */
#define XPAR_PS8_SD_0_DEVICE_ID 0
#define XPAR_PS8_SD_0_BASEADDR 0xFF160000
#define XPAR_PS8_SD_0_HIGHADDR 0xFF160FFF
#define XPAR_PS8_SD_0_SDIO_CLK_FREQ_HZ 200000000


/* Definitions for peripheral PS8_SD_1 */
#define XPAR_PS8_SD_1_DEVICE_ID 1
#define XPAR_PS8_SD_1_BASEADDR 0xFF170000
#define XPAR_PS8_SD_1_HIGHADDR 0xFF170FFF
#define XPAR_PS8_SD_1_SDIO_CLK_FREQ_HZ 200000000


/******************************************************************/

/* Canonical definitions for peripheral PS8_SD_0 */
#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS8_SD_0_DEVICE_ID
#define XPAR_XSDPS_0_BASEADDR 0xFF160000
#define XPAR_XSDPS_0_HIGHADDR 0xFF160FFF
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 200000000

/* Canonical definitions for peripheral PS8_SD_1 */
#define XPAR_XSDPS_1_DEVICE_ID XPAR_PS8_SD_1_DEVICE_ID
#define XPAR_XSDPS_1_BASEADDR 0xFF170000
#define XPAR_XSDPS_1_HIGHADDR 0xFF170FFF
#define XPAR_XSDPS_1_SDIO_CLK_FREQ_HZ 200000000


/******************************************************************/

/* Definitions for driver SPIPS */
#define XPAR_XSPIPS_NUM_INSTANCES 2

/* Definitions for peripheral PS8_SPI_0 */
#define XPAR_PS8_SPI_0_DEVICE_ID 0
#define XPAR_PS8_SPI_0_BASEADDR 0xFF040000
#define XPAR_PS8_SPI_0_HIGHADDR 0xFF040FFF
#define XPAR_PS8_SPI_0_SPI_CLK_FREQ_HZ 214000000


/* Definitions for peripheral PS8_SPI_1 */
#define XPAR_PS8_SPI_1_DEVICE_ID 1
#define XPAR_PS8_SPI_1_BASEADDR 0xFF050000
#define XPAR_PS8_SPI_1_HIGHADDR 0xFF050FFF
#define XPAR_PS8_SPI_1_SPI_CLK_FREQ_HZ 214000000


/******************************************************************/

/* Canonical definitions for peripheral PS8_SPI_0 */
#define XPAR_XSPIPS_0_DEVICE_ID XPAR_PS8_SPI_0_DEVICE_ID
#define XPAR_XSPIPS_0_BASEADDR 0xFF040000
#define XPAR_XSPIPS_0_HIGHADDR 0xFF040FFF
#define XPAR_XSPIPS_0_SPI_CLK_FREQ_HZ 214000000

/* Canonical definitions for peripheral PS8_SPI_1 */
#define XPAR_XSPIPS_1_DEVICE_ID XPAR_PS8_SPI_1_DEVICE_ID
#define XPAR_XSPIPS_1_BASEADDR 0xFF050000
#define XPAR_XSPIPS_1_HIGHADDR 0xFF050FFF
#define XPAR_XSPIPS_1_SPI_CLK_FREQ_HZ 214000000


/******************************************************************/

/* Definitions for driver TTCPS */
#define XPAR_XTTCPS_NUM_INSTANCES 12

/* Definitions for peripheral PS8_TTC_0 */
#define XPAR_PS8_TTC_0_DEVICE_ID 0
#define XPAR_PS8_TTC_0_BASEADDR 0XFF110000
#define XPAR_PS8_TTC_0_TTC_CLK_FREQ_HZ 50000000
#define XPAR_PS8_TTC_0_TTC_CLK_CLKSRC 0
#define XPAR_PS8_TTC_1_DEVICE_ID 1
#define XPAR_PS8_TTC_1_BASEADDR 0XFF110004
#define XPAR_PS8_TTC_1_TTC_CLK_FREQ_HZ 50000000
#define XPAR_PS8_TTC_1_TTC_CLK_CLKSRC 0
#define XPAR_PS8_TTC_2_DEVICE_ID 2
#define XPAR_PS8_TTC_2_BASEADDR 0XFF110008
#define XPAR_PS8_TTC_2_TTC_CLK_FREQ_HZ 50000000
#define XPAR_PS8_TTC_2_TTC_CLK_CLKSRC 0


/* Definitions for peripheral PS8_TTC_1 */
#define XPAR_PS8_TTC_3_DEVICE_ID 3
#define XPAR_PS8_TTC_3_BASEADDR 0XFF120000
#define XPAR_PS8_TTC_3_TTC_CLK_FREQ_HZ 50000000
#define XPAR_PS8_TTC_3_TTC_CLK_CLKSRC 0
#define XPAR_PS8_TTC_4_DEVICE_ID 4
#define XPAR_PS8_TTC_4_BASEADDR 0XFF120004
#define XPAR_PS8_TTC_4_TTC_CLK_FREQ_HZ 50000000
#define XPAR_PS8_TTC_4_TTC_CLK_CLKSRC 0
#define XPAR_PS8_TTC_5_DEVICE_ID 5
#define XPAR_PS8_TTC_5_BASEADDR 0XFF120008
#define XPAR_PS8_TTC_5_TTC_CLK_FREQ_HZ 50000000
#define XPAR_PS8_TTC_5_TTC_CLK_CLKSRC 0


/* Definitions for peripheral PS8_TTC_2 */
#define XPAR_PS8_TTC_6_DEVICE_ID 6
#define XPAR_PS8_TTC_6_BASEADDR 0XFF130000
#define XPAR_PS8_TTC_6_TTC_CLK_FREQ_HZ 50000000
#define XPAR_PS8_TTC_6_TTC_CLK_CLKSRC 0
#define XPAR_PS8_TTC_7_DEVICE_ID 7
#define XPAR_PS8_TTC_7_BASEADDR 0XFF130004
#define XPAR_PS8_TTC_7_TTC_CLK_FREQ_HZ 50000000
#define XPAR_PS8_TTC_7_TTC_CLK_CLKSRC 0
#define XPAR_PS8_TTC_8_DEVICE_ID 8
#define XPAR_PS8_TTC_8_BASEADDR 0XFF130008
#define XPAR_PS8_TTC_8_TTC_CLK_FREQ_HZ 50000000
#define XPAR_PS8_TTC_8_TTC_CLK_CLKSRC 0


/* Definitions for peripheral PS8_TTC_3 */
#define XPAR_PS8_TTC_9_DEVICE_ID 9
#define XPAR_PS8_TTC_9_BASEADDR 0XFF140000
#define XPAR_PS8_TTC_9_TTC_CLK_FREQ_HZ 50000000
#define XPAR_PS8_TTC_9_TTC_CLK_CLKSRC 0
#define XPAR_PS8_TTC_10_DEVICE_ID 10
#define XPAR_PS8_TTC_10_BASEADDR 0XFF140004
#define XPAR_PS8_TTC_10_TTC_CLK_FREQ_HZ 50000000
#define XPAR_PS8_TTC_10_TTC_CLK_CLKSRC 0
#define XPAR_PS8_TTC_11_DEVICE_ID 11
#define XPAR_PS8_TTC_11_BASEADDR 0XFF140008
#define XPAR_PS8_TTC_11_TTC_CLK_FREQ_HZ 50000000
#define XPAR_PS8_TTC_11_TTC_CLK_CLKSRC 0


/******************************************************************/

/* Canonical definitions for peripheral PS8_TTC_0 */
#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS8_TTC_0_DEVICE_ID
#define XPAR_XTTCPS_0_BASEADDR 0xFF110000
#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 50000000
#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0

#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS8_TTC_1_DEVICE_ID
#define XPAR_XTTCPS_1_BASEADDR 0xFF110004
#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 50000000
#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0

#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS8_TTC_2_DEVICE_ID
#define XPAR_XTTCPS_2_BASEADDR 0xFF110008
#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 50000000
#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0

/* Canonical definitions for peripheral PS8_TTC_1 */
#define XPAR_XTTCPS_3_DEVICE_ID XPAR_PS8_TTC_3_DEVICE_ID
#define XPAR_XTTCPS_3_BASEADDR 0xFF120000
#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 50000000
#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0

#define XPAR_XTTCPS_4_DEVICE_ID XPAR_PS8_TTC_4_DEVICE_ID
#define XPAR_XTTCPS_4_BASEADDR 0xFF120004
#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 50000000
#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0

#define XPAR_XTTCPS_5_DEVICE_ID XPAR_PS8_TTC_5_DEVICE_ID
#define XPAR_XTTCPS_5_BASEADDR 0xFF120008
#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 50000000
#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0

/* Canonical definitions for peripheral PS8_TTC_2 */
#define XPAR_XTTCPS_6_DEVICE_ID XPAR_PS8_TTC_6_DEVICE_ID
#define XPAR_XTTCPS_6_BASEADDR 0xFF130000
#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 50000000
#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0

#define XPAR_XTTCPS_7_DEVICE_ID XPAR_PS8_TTC_7_DEVICE_ID
#define XPAR_XTTCPS_7_BASEADDR 0xFF130004
#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 50000000
#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0

#define XPAR_XTTCPS_8_DEVICE_ID XPAR_PS8_TTC_8_DEVICE_ID
#define XPAR_XTTCPS_8_BASEADDR 0xFF130008
#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 50000000
#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0

/* Canonical definitions for peripheral PS8_TTC_3 */
#define XPAR_XTTCPS_9_DEVICE_ID XPAR_PS8_TTC_9_DEVICE_ID
#define XPAR_XTTCPS_9_BASEADDR 0xFF140000
#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 50000000
#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0

#define XPAR_XTTCPS_10_DEVICE_ID XPAR_PS8_TTC_10_DEVICE_ID
#define XPAR_XTTCPS_10_BASEADDR 0xFF140004
#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 50000000
#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0

#define XPAR_XTTCPS_11_DEVICE_ID XPAR_PS8_TTC_11_DEVICE_ID
#define XPAR_XTTCPS_11_BASEADDR 0xFF140008
#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 50000000
#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0


/******************************************************************/

/* Definitions for driver UARTPS */
#define XPAR_XUARTPS_NUM_INSTANCES 2

/* Definitions for peripheral PS8_UART_0 */
#define XPAR_PS8_UART_0_DEVICE_ID 0
#define XPAR_PS8_UART_0_BASEADDR 0xFF000000
#define XPAR_PS8_UART_0_HIGHADDR 0xFF000FFF
#define XPAR_PS8_UART_0_UART_CLK_FREQ_HZ 100000000
#define XPAR_PS8_UART_0_HAS_MODEM FALSE


/* Definitions for peripheral PS8_UART_1 */
#define XPAR_PS8_UART_1_DEVICE_ID 1
#define XPAR_PS8_UART_1_BASEADDR 0xFF010000
#define XPAR_PS8_UART_1_HIGHADDR 0xFF010FFF
#define XPAR_PS8_UART_1_UART_CLK_FREQ_HZ 100000000
#define XPAR_PS8_UART_1_HAS_MODEM FALSE


/******************************************************************/

/* Canonical definitions for peripheral PS8_UART_0 */
#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS8_UART_0_DEVICE_ID
#define XPAR_XUARTPS_0_BASEADDR 0xFF000000
#define XPAR_XUARTPS_0_HIGHADDR 0xFF000FFF
#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000
#define XPAR_XUARTPS_0_HAS_MODEM FALSE

/* Canonical definitions for peripheral PS8_UART_1 */
#define XPAR_XUARTPS_1_DEVICE_ID XPAR_PS8_UART_1_DEVICE_ID
#define XPAR_XUARTPS_1_BASEADDR 0xFF010000
#define XPAR_XUARTPS_1_HIGHADDR 0xFF010FFF
#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 100000000
#define XPAR_XUARTPS_1_HAS_MODEM FALSE


/******************************************************************/

/* Definitions for driver WDTPS */
#define XPAR_XWDTPS_NUM_INSTANCES 2

/* Definitions for peripheral PS8_WDT_0 */
#define XPAR_PS8_WDT_0_DEVICE_ID 0
#define XPAR_PS8_WDT_0_BASEADDR 0xFF150000
#define XPAR_PS8_WDT_0_HIGHADDR 0xFF150FFF
#define XPAR_PS8_WDT_0_WDT_CLK_FREQ_HZ 50000000


/* Definitions for peripheral PS8_WDT_1 */
#define XPAR_PS8_WDT_1_DEVICE_ID 1
#define XPAR_PS8_WDT_1_BASEADDR 0xFD4D0000
#define XPAR_PS8_WDT_1_HIGHADDR 0xFD4D0FFF
#define XPAR_PS8_WDT_1_WDT_CLK_FREQ_HZ 50000000


/******************************************************************/

/* Canonical definitions for peripheral PS8_WDT_0 */
#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PS8_WDT_0_DEVICE_ID
#define XPAR_XWDTPS_0_BASEADDR 0xFF150000
#define XPAR_XWDTPS_0_HIGHADDR 0xFF150FFF
#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 50000000

/* Canonical definitions for peripheral PS8_WDT_1 */
#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PS8_WDT_1_DEVICE_ID
#define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000
#define XPAR_XWDTPS_1_HIGHADDR 0xFD4D0FFF
#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 50000000


/******************************************************************/

/* Xilinx FAT File System Library (XilFFs) User Settings */
#define FILE_SYSTEM_INTERFACE_SD
#define FILE_SYSTEM_INTERFACE_SD
